Commit | Line | Data |
---|---|---|
985dbe77 MH |
1 | /* |
2 | * iio/adc/ad799x.c | |
630097f7 | 3 | * Copyright (C) 2010-2011 Michael Hennerich, Analog Devices Inc. |
985dbe77 MH |
4 | * |
5 | * based on iio/adc/max1363 | |
6 | * Copyright (C) 2008-2010 Jonathan Cameron | |
7 | * | |
8 | * based on linux/drivers/i2c/chips/max123x | |
9 | * Copyright (C) 2002-2004 Stefan Eletzhofer | |
10 | * | |
11 | * based on linux/drivers/acron/char/pcf8583.c | |
12 | * Copyright (C) 2000 Russell King | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | * | |
18 | * ad799x.c | |
19 | * | |
20 | * Support for ad7991, ad7995, ad7999, ad7992, ad7993, ad7994, ad7997, | |
21 | * ad7998 and similar chips. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/interrupt.h> | |
985dbe77 MH |
26 | #include <linux/device.h> |
27 | #include <linux/kernel.h> | |
28 | #include <linux/sysfs.h> | |
985dbe77 MH |
29 | #include <linux/i2c.h> |
30 | #include <linux/regulator/consumer.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/types.h> | |
33 | #include <linux/err.h> | |
99c97852 | 34 | #include <linux/module.h> |
e1c6e2a2 | 35 | #include <linux/bitops.h> |
985dbe77 | 36 | |
06458e27 JC |
37 | #include <linux/iio/iio.h> |
38 | #include <linux/iio/sysfs.h> | |
39 | #include <linux/iio/events.h> | |
40 | #include <linux/iio/buffer.h> | |
396590b3 LPC |
41 | #include <linux/iio/trigger_consumer.h> |
42 | #include <linux/iio/triggered_buffer.h> | |
cdf38709 | 43 | |
396590b3 | 44 | #define AD799X_CHANNEL_SHIFT 4 |
e1c6e2a2 | 45 | |
396590b3 LPC |
46 | /* |
47 | * AD7991, AD7995 and AD7999 defines | |
48 | */ | |
49 | ||
50 | #define AD7991_REF_SEL 0x08 | |
51 | #define AD7991_FLTR 0x04 | |
52 | #define AD7991_BIT_TRIAL_DELAY 0x02 | |
53 | #define AD7991_SAMPLE_DELAY 0x01 | |
54 | ||
55 | /* | |
56 | * AD7992, AD7993, AD7994, AD7997 and AD7998 defines | |
57 | */ | |
58 | ||
e1c6e2a2 PM |
59 | #define AD7998_FLTR BIT(3) |
60 | #define AD7998_ALERT_EN BIT(2) | |
61 | #define AD7998_BUSY_ALERT BIT(1) | |
62 | #define AD7998_BUSY_ALERT_POL BIT(0) | |
396590b3 LPC |
63 | |
64 | #define AD7998_CONV_RES_REG 0x0 | |
65 | #define AD7998_ALERT_STAT_REG 0x1 | |
66 | #define AD7998_CONF_REG 0x2 | |
67 | #define AD7998_CYCLE_TMR_REG 0x3 | |
68 | ||
69 | #define AD7998_DATALOW_REG(x) ((x) * 3 + 0x4) | |
70 | #define AD7998_DATAHIGH_REG(x) ((x) * 3 + 0x5) | |
71 | #define AD7998_HYST_REG(x) ((x) * 3 + 0x6) | |
72 | ||
e1c6e2a2 | 73 | #define AD7998_CYC_MASK GENMASK(2, 0) |
396590b3 LPC |
74 | #define AD7998_CYC_DIS 0x0 |
75 | #define AD7998_CYC_TCONF_32 0x1 | |
76 | #define AD7998_CYC_TCONF_64 0x2 | |
77 | #define AD7998_CYC_TCONF_128 0x3 | |
78 | #define AD7998_CYC_TCONF_256 0x4 | |
79 | #define AD7998_CYC_TCONF_512 0x5 | |
80 | #define AD7998_CYC_TCONF_1024 0x6 | |
81 | #define AD7998_CYC_TCONF_2048 0x7 | |
82 | ||
83 | #define AD7998_ALERT_STAT_CLEAR 0xFF | |
84 | ||
85 | /* | |
86 | * AD7997 and AD7997 defines | |
87 | */ | |
88 | ||
e1c6e2a2 PM |
89 | #define AD7997_8_READ_SINGLE BIT(7) |
90 | #define AD7997_8_READ_SEQUENCE (BIT(6) | BIT(5) | BIT(4)) | |
396590b3 LPC |
91 | |
92 | enum { | |
93 | ad7991, | |
94 | ad7995, | |
95 | ad7999, | |
96 | ad7992, | |
97 | ad7993, | |
98 | ad7994, | |
99 | ad7997, | |
100 | ad7998 | |
101 | }; | |
102 | ||
103 | /** | |
91556c69 | 104 | * struct ad799x_chip_config - chip specific information |
396590b3 | 105 | * @channel: channel specification |
396590b3 | 106 | * @default_config: device default configuration |
a3eeb159 | 107 | * @info: pointer to iio_info struct |
396590b3 | 108 | */ |
91556c69 | 109 | struct ad799x_chip_config { |
ef0bf6f8 | 110 | const struct iio_chan_spec channel[9]; |
396590b3 LPC |
111 | u16 default_config; |
112 | const struct iio_info *info; | |
113 | }; | |
114 | ||
91556c69 PM |
115 | /** |
116 | * struct ad799x_chip_info - chip specific information | |
117 | * @num_channels: number of channels | |
118 | * @noirq_config: device configuration w/o IRQ | |
119 | * @irq_config: device configuration w/IRQ | |
120 | */ | |
121 | struct ad799x_chip_info { | |
122 | int num_channels; | |
123 | const struct ad799x_chip_config noirq_config; | |
124 | const struct ad799x_chip_config irq_config; | |
125 | }; | |
126 | ||
396590b3 LPC |
127 | struct ad799x_state { |
128 | struct i2c_client *client; | |
91556c69 | 129 | const struct ad799x_chip_config *chip_config; |
396590b3 LPC |
130 | struct regulator *reg; |
131 | struct regulator *vref; | |
132 | unsigned id; | |
133 | u16 config; | |
134 | ||
135 | u8 *rx_buf; | |
136 | unsigned int transfer_size; | |
137 | }; | |
138 | ||
89ca79af PM |
139 | static int ad799x_write_config(struct ad799x_state *st, u16 val) |
140 | { | |
141 | switch (st->id) { | |
142 | case ad7997: | |
143 | case ad7998: | |
144 | return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG, | |
145 | val); | |
146 | default: | |
147 | return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG, | |
148 | val); | |
149 | } | |
150 | } | |
151 | ||
152 | static int ad799x_read_config(struct ad799x_state *st) | |
153 | { | |
154 | switch (st->id) { | |
155 | case ad7997: | |
156 | case ad7998: | |
157 | return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG); | |
158 | default: | |
159 | return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG); | |
160 | } | |
161 | } | |
162 | ||
396590b3 LPC |
163 | /** |
164 | * ad799x_trigger_handler() bh of trigger launched polling to ring buffer | |
165 | * | |
166 | * Currently there is no option in this driver to disable the saving of | |
167 | * timestamps within the ring. | |
168 | **/ | |
169 | static irqreturn_t ad799x_trigger_handler(int irq, void *p) | |
170 | { | |
171 | struct iio_poll_func *pf = p; | |
172 | struct iio_dev *indio_dev = pf->indio_dev; | |
173 | struct ad799x_state *st = iio_priv(indio_dev); | |
174 | int b_sent; | |
175 | u8 cmd; | |
176 | ||
177 | switch (st->id) { | |
178 | case ad7991: | |
179 | case ad7995: | |
180 | case ad7999: | |
181 | cmd = st->config | | |
182 | (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT); | |
183 | break; | |
184 | case ad7992: | |
185 | case ad7993: | |
186 | case ad7994: | |
187 | cmd = (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT) | | |
188 | AD7998_CONV_RES_REG; | |
189 | break; | |
190 | case ad7997: | |
191 | case ad7998: | |
192 | cmd = AD7997_8_READ_SEQUENCE | AD7998_CONV_RES_REG; | |
193 | break; | |
194 | default: | |
195 | cmd = 0; | |
196 | } | |
197 | ||
198 | b_sent = i2c_smbus_read_i2c_block_data(st->client, | |
199 | cmd, st->transfer_size, st->rx_buf); | |
200 | if (b_sent < 0) | |
201 | goto out; | |
202 | ||
203 | iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf, | |
204 | iio_get_time_ns()); | |
205 | out: | |
206 | iio_trigger_notify_done(indio_dev->trig); | |
207 | ||
208 | return IRQ_HANDLED; | |
209 | } | |
985dbe77 | 210 | |
8235841b | 211 | static int ad799x_update_scan_mode(struct iio_dev *indio_dev, |
ae3805c3 | 212 | const unsigned long *scan_mask) |
985dbe77 | 213 | { |
ae3805c3 LPC |
214 | struct ad799x_state *st = iio_priv(indio_dev); |
215 | ||
d8dca330 LPC |
216 | kfree(st->rx_buf); |
217 | st->rx_buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL); | |
218 | if (!st->rx_buf) | |
219 | return -ENOMEM; | |
220 | ||
221 | st->transfer_size = bitmap_weight(scan_mask, indio_dev->masklength) * 2; | |
222 | ||
ae3805c3 | 223 | switch (st->id) { |
8235841b PM |
224 | case ad7992: |
225 | case ad7993: | |
226 | case ad7994: | |
ae3805c3 LPC |
227 | case ad7997: |
228 | case ad7998: | |
8235841b PM |
229 | st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT); |
230 | st->config |= (*scan_mask << AD799X_CHANNEL_SHIFT); | |
231 | return ad799x_write_config(st, st->config); | |
ae3805c3 | 232 | default: |
bd3bd432 | 233 | return 0; |
ae3805c3 | 234 | } |
985dbe77 MH |
235 | } |
236 | ||
d22fd9c5 | 237 | static int ad799x_scan_direct(struct ad799x_state *st, unsigned ch) |
985dbe77 | 238 | { |
d22fd9c5 | 239 | u8 cmd; |
985dbe77 | 240 | |
d22fd9c5 MH |
241 | switch (st->id) { |
242 | case ad7991: | |
243 | case ad7995: | |
244 | case ad7999: | |
e1c6e2a2 | 245 | cmd = st->config | (BIT(ch) << AD799X_CHANNEL_SHIFT); |
d22fd9c5 MH |
246 | break; |
247 | case ad7992: | |
248 | case ad7993: | |
249 | case ad7994: | |
e1c6e2a2 | 250 | cmd = BIT(ch) << AD799X_CHANNEL_SHIFT; |
d22fd9c5 MH |
251 | break; |
252 | case ad7997: | |
253 | case ad7998: | |
254 | cmd = (ch << AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE; | |
255 | break; | |
256 | default: | |
257 | return -EINVAL; | |
985dbe77 MH |
258 | } |
259 | ||
54154471 | 260 | return i2c_smbus_read_word_swapped(st->client, cmd); |
985dbe77 MH |
261 | } |
262 | ||
84f79ecb | 263 | static int ad799x_read_raw(struct iio_dev *indio_dev, |
d22fd9c5 MH |
264 | struct iio_chan_spec const *chan, |
265 | int *val, | |
266 | int *val2, | |
267 | long m) | |
985dbe77 | 268 | { |
d22fd9c5 | 269 | int ret; |
84f79ecb | 270 | struct ad799x_state *st = iio_priv(indio_dev); |
d22fd9c5 MH |
271 | |
272 | switch (m) { | |
b11f98ff | 273 | case IIO_CHAN_INFO_RAW: |
84f79ecb JC |
274 | mutex_lock(&indio_dev->mlock); |
275 | if (iio_buffer_enabled(indio_dev)) | |
729bbf54 | 276 | ret = -EBUSY; |
d22fd9c5 | 277 | else |
58dffaed | 278 | ret = ad799x_scan_direct(st, chan->scan_index); |
84f79ecb | 279 | mutex_unlock(&indio_dev->mlock); |
985dbe77 | 280 | |
985dbe77 | 281 | if (ret < 0) |
d22fd9c5 | 282 | return ret; |
5357ba3d | 283 | *val = (ret >> chan->scan_type.shift) & |
e1c6e2a2 | 284 | GENMASK(chan->scan_type.realbits - 1, 0); |
d22fd9c5 | 285 | return IIO_VAL_INT; |
c8a9f805 | 286 | case IIO_CHAN_INFO_SCALE: |
2deaf23b HK |
287 | ret = regulator_get_voltage(st->vref); |
288 | if (ret < 0) | |
289 | return ret; | |
290 | *val = ret / 1000; | |
b740f48a LPC |
291 | *val2 = chan->scan_type.realbits; |
292 | return IIO_VAL_FRACTIONAL_LOG2; | |
985dbe77 | 293 | } |
d22fd9c5 | 294 | return -EINVAL; |
985dbe77 | 295 | } |
24cba406 JC |
296 | static const unsigned int ad7998_frequencies[] = { |
297 | [AD7998_CYC_DIS] = 0, | |
298 | [AD7998_CYC_TCONF_32] = 15625, | |
299 | [AD7998_CYC_TCONF_64] = 7812, | |
300 | [AD7998_CYC_TCONF_128] = 3906, | |
301 | [AD7998_CYC_TCONF_512] = 976, | |
302 | [AD7998_CYC_TCONF_1024] = 488, | |
303 | [AD7998_CYC_TCONF_2048] = 244, | |
304 | }; | |
54154471 | 305 | |
985dbe77 MH |
306 | static ssize_t ad799x_read_frequency(struct device *dev, |
307 | struct device_attribute *attr, | |
308 | char *buf) | |
309 | { | |
62c51839 | 310 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
84f79ecb | 311 | struct ad799x_state *st = iio_priv(indio_dev); |
985dbe77 | 312 | |
54154471 PM |
313 | int ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG); |
314 | if (ret < 0) | |
985dbe77 MH |
315 | return ret; |
316 | ||
54154471 | 317 | return sprintf(buf, "%u\n", ad7998_frequencies[ret & AD7998_CYC_MASK]); |
985dbe77 MH |
318 | } |
319 | ||
320 | static ssize_t ad799x_write_frequency(struct device *dev, | |
321 | struct device_attribute *attr, | |
322 | const char *buf, | |
323 | size_t len) | |
324 | { | |
62c51839 | 325 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
84f79ecb | 326 | struct ad799x_state *st = iio_priv(indio_dev); |
985dbe77 MH |
327 | |
328 | long val; | |
24cba406 | 329 | int ret, i; |
985dbe77 | 330 | |
f86f8362 | 331 | ret = kstrtol(buf, 10, &val); |
985dbe77 MH |
332 | if (ret) |
333 | return ret; | |
334 | ||
84f79ecb | 335 | mutex_lock(&indio_dev->mlock); |
54154471 PM |
336 | ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG); |
337 | if (ret < 0) | |
985dbe77 MH |
338 | goto error_ret_mutex; |
339 | /* Wipe the bits clean */ | |
54154471 | 340 | ret &= ~AD7998_CYC_MASK; |
985dbe77 | 341 | |
24cba406 JC |
342 | for (i = 0; i < ARRAY_SIZE(ad7998_frequencies); i++) |
343 | if (val == ad7998_frequencies[i]) | |
344 | break; | |
345 | if (i == ARRAY_SIZE(ad7998_frequencies)) { | |
985dbe77 MH |
346 | ret = -EINVAL; |
347 | goto error_ret_mutex; | |
348 | } | |
54154471 PM |
349 | |
350 | ret = i2c_smbus_write_byte_data(st->client, AD7998_CYCLE_TMR_REG, | |
351 | ret | i); | |
352 | if (ret < 0) | |
353 | goto error_ret_mutex; | |
354 | ret = len; | |
985dbe77 MH |
355 | |
356 | error_ret_mutex: | |
84f79ecb | 357 | mutex_unlock(&indio_dev->mlock); |
985dbe77 | 358 | |
54154471 | 359 | return ret; |
985dbe77 MH |
360 | } |
361 | ||
84f79ecb | 362 | static int ad799x_read_event_config(struct iio_dev *indio_dev, |
5b9e048a LPC |
363 | const struct iio_chan_spec *chan, |
364 | enum iio_event_type type, | |
365 | enum iio_event_direction dir) | |
231c5c3b | 366 | { |
1d15330a PM |
367 | struct ad799x_state *st = iio_priv(indio_dev); |
368 | ||
369 | if (!(st->config & AD7998_ALERT_EN)) | |
370 | return 0; | |
371 | ||
372 | if ((st->config >> AD799X_CHANNEL_SHIFT) & BIT(chan->scan_index)) | |
373 | return 1; | |
374 | ||
375 | return 0; | |
231c5c3b JC |
376 | } |
377 | ||
3008d082 PM |
378 | static int ad799x_write_event_config(struct iio_dev *indio_dev, |
379 | const struct iio_chan_spec *chan, | |
380 | enum iio_event_type type, | |
381 | enum iio_event_direction dir, | |
382 | int state) | |
383 | { | |
384 | struct ad799x_state *st = iio_priv(indio_dev); | |
385 | int ret; | |
386 | ||
387 | mutex_lock(&indio_dev->mlock); | |
388 | if (iio_buffer_enabled(indio_dev)) { | |
389 | ret = -EBUSY; | |
390 | goto done; | |
391 | } | |
392 | ||
393 | if (state) | |
394 | st->config |= BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT; | |
395 | else | |
396 | st->config &= ~(BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT); | |
397 | ||
398 | if (st->config >> AD799X_CHANNEL_SHIFT) | |
399 | st->config |= AD7998_ALERT_EN; | |
400 | else | |
401 | st->config &= ~AD7998_ALERT_EN; | |
402 | ||
403 | ret = ad799x_write_config(st, st->config); | |
404 | ||
405 | done: | |
406 | mutex_unlock(&indio_dev->mlock); | |
407 | ||
408 | return ret; | |
409 | } | |
410 | ||
ba1d7961 LPC |
411 | static unsigned int ad799x_threshold_reg(const struct iio_chan_spec *chan, |
412 | enum iio_event_direction dir, | |
413 | enum iio_event_info info) | |
69582b88 | 414 | { |
ba1d7961 LPC |
415 | switch (info) { |
416 | case IIO_EV_INFO_VALUE: | |
417 | if (dir == IIO_EV_DIR_FALLING) | |
418 | return AD7998_DATALOW_REG(chan->channel); | |
419 | else | |
420 | return AD7998_DATAHIGH_REG(chan->channel); | |
421 | case IIO_EV_INFO_HYSTERESIS: | |
422 | return AD7998_HYST_REG(chan->channel); | |
423 | default: | |
424 | return -EINVAL; | |
425 | } | |
426 | ||
427 | return 0; | |
69582b88 | 428 | } |
231c5c3b JC |
429 | |
430 | static int ad799x_write_event_value(struct iio_dev *indio_dev, | |
5b9e048a LPC |
431 | const struct iio_chan_spec *chan, |
432 | enum iio_event_type type, | |
433 | enum iio_event_direction dir, | |
434 | enum iio_event_info info, | |
435 | int val, int val2) | |
231c5c3b JC |
436 | { |
437 | int ret; | |
438 | struct ad799x_state *st = iio_priv(indio_dev); | |
231c5c3b | 439 | |
e1c6e2a2 | 440 | if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0)) |
361d7950 PM |
441 | return -EINVAL; |
442 | ||
231c5c3b | 443 | mutex_lock(&indio_dev->mlock); |
54154471 PM |
444 | ret = i2c_smbus_write_word_swapped(st->client, |
445 | ad799x_threshold_reg(chan, dir, info), | |
361d7950 | 446 | val << chan->scan_type.shift); |
231c5c3b JC |
447 | mutex_unlock(&indio_dev->mlock); |
448 | ||
449 | return ret; | |
450 | } | |
451 | ||
452 | static int ad799x_read_event_value(struct iio_dev *indio_dev, | |
5b9e048a LPC |
453 | const struct iio_chan_spec *chan, |
454 | enum iio_event_type type, | |
455 | enum iio_event_direction dir, | |
456 | enum iio_event_info info, | |
457 | int *val, int *val2) | |
231c5c3b JC |
458 | { |
459 | int ret; | |
460 | struct ad799x_state *st = iio_priv(indio_dev); | |
231c5c3b JC |
461 | |
462 | mutex_lock(&indio_dev->mlock); | |
54154471 PM |
463 | ret = i2c_smbus_read_word_swapped(st->client, |
464 | ad799x_threshold_reg(chan, dir, info)); | |
231c5c3b JC |
465 | mutex_unlock(&indio_dev->mlock); |
466 | if (ret < 0) | |
467 | return ret; | |
54154471 | 468 | *val = (ret >> chan->scan_type.shift) & |
e1c6e2a2 | 469 | GENMASK(chan->scan_type.realbits - 1 , 0); |
231c5c3b | 470 | |
5b9e048a | 471 | return IIO_VAL_INT; |
231c5c3b JC |
472 | } |
473 | ||
72148f6e | 474 | static irqreturn_t ad799x_event_handler(int irq, void *private) |
985dbe77 | 475 | { |
72148f6e | 476 | struct iio_dev *indio_dev = private; |
d8aea29b | 477 | struct ad799x_state *st = iio_priv(private); |
72148f6e | 478 | int i, ret; |
985dbe77 | 479 | |
54154471 PM |
480 | ret = i2c_smbus_read_byte_data(st->client, AD7998_ALERT_STAT_REG); |
481 | if (ret <= 0) | |
f654a7e2 | 482 | goto done; |
985dbe77 | 483 | |
54154471 PM |
484 | if (i2c_smbus_write_byte_data(st->client, AD7998_ALERT_STAT_REG, |
485 | AD7998_ALERT_STAT_CLEAR) < 0) | |
f654a7e2 | 486 | goto done; |
985dbe77 | 487 | |
985dbe77 | 488 | for (i = 0; i < 8; i++) { |
e1c6e2a2 | 489 | if (ret & BIT(i)) |
5aa96188 | 490 | iio_push_event(indio_dev, |
72148f6e | 491 | i & 0x1 ? |
6835cb6b | 492 | IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, |
cdf38709 JC |
493 | (i >> 1), |
494 | IIO_EV_TYPE_THRESH, | |
495 | IIO_EV_DIR_RISING) : | |
6835cb6b | 496 | IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, |
cdf38709 JC |
497 | (i >> 1), |
498 | IIO_EV_TYPE_THRESH, | |
499 | IIO_EV_DIR_FALLING), | |
72148f6e | 500 | iio_get_time_ns()); |
985dbe77 MH |
501 | } |
502 | ||
f654a7e2 | 503 | done: |
72148f6e | 504 | return IRQ_HANDLED; |
985dbe77 MH |
505 | } |
506 | ||
985dbe77 MH |
507 | static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, |
508 | ad799x_read_frequency, | |
509 | ad799x_write_frequency); | |
510 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("15625 7812 3906 1953 976 488 244 0"); | |
511 | ||
ba1d7961 | 512 | static struct attribute *ad799x_event_attributes[] = { |
985dbe77 MH |
513 | &iio_dev_attr_sampling_frequency.dev_attr.attr, |
514 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
515 | NULL, | |
516 | }; | |
517 | ||
ba1d7961 LPC |
518 | static struct attribute_group ad799x_event_attrs_group = { |
519 | .attrs = ad799x_event_attributes, | |
8e7d9672 | 520 | .name = "events", |
985dbe77 MH |
521 | }; |
522 | ||
6fe8135f JC |
523 | static const struct iio_info ad7991_info = { |
524 | .read_raw = &ad799x_read_raw, | |
525 | .driver_module = THIS_MODULE, | |
526 | }; | |
527 | ||
91556c69 PM |
528 | static const struct iio_info ad7993_4_7_8_noirq_info = { |
529 | .read_raw = &ad799x_read_raw, | |
530 | .driver_module = THIS_MODULE, | |
8235841b | 531 | .update_scan_mode = ad799x_update_scan_mode, |
91556c69 PM |
532 | }; |
533 | ||
534 | static const struct iio_info ad7993_4_7_8_irq_info = { | |
6fe8135f | 535 | .read_raw = &ad799x_read_raw, |
ba1d7961 | 536 | .event_attrs = &ad799x_event_attrs_group, |
cb955852 | 537 | .read_event_config = &ad799x_read_event_config, |
3008d082 | 538 | .write_event_config = &ad799x_write_event_config, |
cb955852 LPC |
539 | .read_event_value = &ad799x_read_event_value, |
540 | .write_event_value = &ad799x_write_event_value, | |
6fe8135f | 541 | .driver_module = THIS_MODULE, |
8235841b | 542 | .update_scan_mode = ad799x_update_scan_mode, |
6fe8135f JC |
543 | }; |
544 | ||
5b9e048a LPC |
545 | static const struct iio_event_spec ad799x_events[] = { |
546 | { | |
547 | .type = IIO_EV_TYPE_THRESH, | |
548 | .dir = IIO_EV_DIR_RISING, | |
549 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
550 | BIT(IIO_EV_INFO_ENABLE), | |
551 | }, { | |
552 | .type = IIO_EV_TYPE_THRESH, | |
553 | .dir = IIO_EV_DIR_FALLING, | |
d180371d | 554 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | |
5b9e048a | 555 | BIT(IIO_EV_INFO_ENABLE), |
ba1d7961 LPC |
556 | }, { |
557 | .type = IIO_EV_TYPE_THRESH, | |
558 | .dir = IIO_EV_DIR_EITHER, | |
559 | .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS), | |
5b9e048a LPC |
560 | }, |
561 | }; | |
231c5c3b | 562 | |
5b9e048a | 563 | #define _AD799X_CHANNEL(_index, _realbits, _ev_spec, _num_ev_spec) { \ |
ae6d6489 LPC |
564 | .type = IIO_VOLTAGE, \ |
565 | .indexed = 1, \ | |
566 | .channel = (_index), \ | |
567 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
d00698df | 568 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ |
ae6d6489 | 569 | .scan_index = (_index), \ |
83d5f324 JC |
570 | .scan_type = { \ |
571 | .sign = 'u', \ | |
572 | .realbits = (_realbits), \ | |
573 | .storagebits = 16, \ | |
574 | .shift = 12 - (_realbits), \ | |
575 | .endianness = IIO_BE, \ | |
576 | }, \ | |
5b9e048a LPC |
577 | .event_spec = _ev_spec, \ |
578 | .num_event_specs = _num_ev_spec, \ | |
ae6d6489 LPC |
579 | } |
580 | ||
5b9e048a LPC |
581 | #define AD799X_CHANNEL(_index, _realbits) \ |
582 | _AD799X_CHANNEL(_index, _realbits, NULL, 0) | |
583 | ||
584 | #define AD799X_CHANNEL_WITH_EVENTS(_index, _realbits) \ | |
585 | _AD799X_CHANNEL(_index, _realbits, ad799x_events, \ | |
586 | ARRAY_SIZE(ad799x_events)) | |
587 | ||
985dbe77 MH |
588 | static const struct ad799x_chip_info ad799x_chip_info_tbl[] = { |
589 | [ad7991] = { | |
d22fd9c5 | 590 | .num_channels = 5, |
91556c69 PM |
591 | .noirq_config = { |
592 | .channel = { | |
593 | AD799X_CHANNEL(0, 12), | |
594 | AD799X_CHANNEL(1, 12), | |
595 | AD799X_CHANNEL(2, 12), | |
596 | AD799X_CHANNEL(3, 12), | |
597 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
598 | }, | |
599 | .info = &ad7991_info, | |
600 | }, | |
985dbe77 MH |
601 | }, |
602 | [ad7995] = { | |
d22fd9c5 | 603 | .num_channels = 5, |
91556c69 PM |
604 | .noirq_config = { |
605 | .channel = { | |
606 | AD799X_CHANNEL(0, 10), | |
607 | AD799X_CHANNEL(1, 10), | |
608 | AD799X_CHANNEL(2, 10), | |
609 | AD799X_CHANNEL(3, 10), | |
610 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
611 | }, | |
612 | .info = &ad7991_info, | |
613 | }, | |
985dbe77 MH |
614 | }, |
615 | [ad7999] = { | |
d22fd9c5 | 616 | .num_channels = 5, |
91556c69 PM |
617 | .noirq_config = { |
618 | .channel = { | |
619 | AD799X_CHANNEL(0, 8), | |
620 | AD799X_CHANNEL(1, 8), | |
621 | AD799X_CHANNEL(2, 8), | |
622 | AD799X_CHANNEL(3, 8), | |
623 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
624 | }, | |
625 | .info = &ad7991_info, | |
626 | }, | |
985dbe77 MH |
627 | }, |
628 | [ad7992] = { | |
d22fd9c5 | 629 | .num_channels = 3, |
91556c69 PM |
630 | .noirq_config = { |
631 | .channel = { | |
632 | AD799X_CHANNEL(0, 12), | |
633 | AD799X_CHANNEL(1, 12), | |
634 | IIO_CHAN_SOFT_TIMESTAMP(3), | |
635 | }, | |
636 | .info = &ad7993_4_7_8_noirq_info, | |
637 | }, | |
638 | .irq_config = { | |
639 | .channel = { | |
640 | AD799X_CHANNEL_WITH_EVENTS(0, 12), | |
641 | AD799X_CHANNEL_WITH_EVENTS(1, 12), | |
642 | IIO_CHAN_SOFT_TIMESTAMP(3), | |
643 | }, | |
0f7ddcc1 | 644 | .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT, |
91556c69 PM |
645 | .info = &ad7993_4_7_8_irq_info, |
646 | }, | |
985dbe77 MH |
647 | }, |
648 | [ad7993] = { | |
d22fd9c5 | 649 | .num_channels = 5, |
91556c69 PM |
650 | .noirq_config = { |
651 | .channel = { | |
652 | AD799X_CHANNEL(0, 10), | |
653 | AD799X_CHANNEL(1, 10), | |
654 | AD799X_CHANNEL(2, 10), | |
655 | AD799X_CHANNEL(3, 10), | |
656 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
657 | }, | |
658 | .info = &ad7993_4_7_8_noirq_info, | |
659 | }, | |
660 | .irq_config = { | |
661 | .channel = { | |
662 | AD799X_CHANNEL_WITH_EVENTS(0, 10), | |
663 | AD799X_CHANNEL_WITH_EVENTS(1, 10), | |
664 | AD799X_CHANNEL_WITH_EVENTS(2, 10), | |
665 | AD799X_CHANNEL_WITH_EVENTS(3, 10), | |
666 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
667 | }, | |
0f7ddcc1 | 668 | .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT, |
91556c69 PM |
669 | .info = &ad7993_4_7_8_irq_info, |
670 | }, | |
985dbe77 MH |
671 | }, |
672 | [ad7994] = { | |
d22fd9c5 | 673 | .num_channels = 5, |
91556c69 PM |
674 | .noirq_config = { |
675 | .channel = { | |
676 | AD799X_CHANNEL(0, 12), | |
677 | AD799X_CHANNEL(1, 12), | |
678 | AD799X_CHANNEL(2, 12), | |
679 | AD799X_CHANNEL(3, 12), | |
680 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
681 | }, | |
682 | .info = &ad7993_4_7_8_noirq_info, | |
683 | }, | |
684 | .irq_config = { | |
685 | .channel = { | |
686 | AD799X_CHANNEL_WITH_EVENTS(0, 12), | |
687 | AD799X_CHANNEL_WITH_EVENTS(1, 12), | |
688 | AD799X_CHANNEL_WITH_EVENTS(2, 12), | |
689 | AD799X_CHANNEL_WITH_EVENTS(3, 12), | |
690 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
691 | }, | |
0f7ddcc1 | 692 | .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT, |
91556c69 PM |
693 | .info = &ad7993_4_7_8_irq_info, |
694 | }, | |
985dbe77 MH |
695 | }, |
696 | [ad7997] = { | |
d22fd9c5 | 697 | .num_channels = 9, |
91556c69 PM |
698 | .noirq_config = { |
699 | .channel = { | |
700 | AD799X_CHANNEL(0, 10), | |
701 | AD799X_CHANNEL(1, 10), | |
702 | AD799X_CHANNEL(2, 10), | |
703 | AD799X_CHANNEL(3, 10), | |
704 | AD799X_CHANNEL(4, 10), | |
705 | AD799X_CHANNEL(5, 10), | |
706 | AD799X_CHANNEL(6, 10), | |
707 | AD799X_CHANNEL(7, 10), | |
708 | IIO_CHAN_SOFT_TIMESTAMP(8), | |
709 | }, | |
710 | .info = &ad7993_4_7_8_noirq_info, | |
711 | }, | |
712 | .irq_config = { | |
713 | .channel = { | |
714 | AD799X_CHANNEL_WITH_EVENTS(0, 10), | |
715 | AD799X_CHANNEL_WITH_EVENTS(1, 10), | |
716 | AD799X_CHANNEL_WITH_EVENTS(2, 10), | |
717 | AD799X_CHANNEL_WITH_EVENTS(3, 10), | |
718 | AD799X_CHANNEL(4, 10), | |
719 | AD799X_CHANNEL(5, 10), | |
720 | AD799X_CHANNEL(6, 10), | |
721 | AD799X_CHANNEL(7, 10), | |
722 | IIO_CHAN_SOFT_TIMESTAMP(8), | |
723 | }, | |
0f7ddcc1 | 724 | .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT, |
91556c69 PM |
725 | .info = &ad7993_4_7_8_irq_info, |
726 | }, | |
985dbe77 MH |
727 | }, |
728 | [ad7998] = { | |
d22fd9c5 | 729 | .num_channels = 9, |
91556c69 PM |
730 | .noirq_config = { |
731 | .channel = { | |
732 | AD799X_CHANNEL(0, 12), | |
733 | AD799X_CHANNEL(1, 12), | |
734 | AD799X_CHANNEL(2, 12), | |
735 | AD799X_CHANNEL(3, 12), | |
736 | AD799X_CHANNEL(4, 12), | |
737 | AD799X_CHANNEL(5, 12), | |
738 | AD799X_CHANNEL(6, 12), | |
739 | AD799X_CHANNEL(7, 12), | |
740 | IIO_CHAN_SOFT_TIMESTAMP(8), | |
741 | }, | |
742 | .info = &ad7993_4_7_8_noirq_info, | |
743 | }, | |
744 | .irq_config = { | |
745 | .channel = { | |
746 | AD799X_CHANNEL_WITH_EVENTS(0, 12), | |
747 | AD799X_CHANNEL_WITH_EVENTS(1, 12), | |
748 | AD799X_CHANNEL_WITH_EVENTS(2, 12), | |
749 | AD799X_CHANNEL_WITH_EVENTS(3, 12), | |
750 | AD799X_CHANNEL(4, 12), | |
751 | AD799X_CHANNEL(5, 12), | |
752 | AD799X_CHANNEL(6, 12), | |
753 | AD799X_CHANNEL(7, 12), | |
754 | IIO_CHAN_SOFT_TIMESTAMP(8), | |
755 | }, | |
0f7ddcc1 | 756 | .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT, |
91556c69 PM |
757 | .info = &ad7993_4_7_8_irq_info, |
758 | }, | |
985dbe77 MH |
759 | }, |
760 | }; | |
761 | ||
4ae1c61f | 762 | static int ad799x_probe(struct i2c_client *client, |
985dbe77 MH |
763 | const struct i2c_device_id *id) |
764 | { | |
26d25ae3 | 765 | int ret; |
1bf7ac76 | 766 | struct ad799x_state *st; |
6a88fa48 | 767 | struct iio_dev *indio_dev; |
91556c69 PM |
768 | const struct ad799x_chip_info *chip_info = |
769 | &ad799x_chip_info_tbl[id->driver_data]; | |
1bf7ac76 | 770 | |
6a88fa48 | 771 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); |
1bf7ac76 MH |
772 | if (indio_dev == NULL) |
773 | return -ENOMEM; | |
985dbe77 | 774 | |
1bf7ac76 | 775 | st = iio_priv(indio_dev); |
985dbe77 | 776 | /* this is only used for device removal purposes */ |
1bf7ac76 | 777 | i2c_set_clientdata(client, indio_dev); |
985dbe77 | 778 | |
985dbe77 | 779 | st->id = id->driver_data; |
91556c69 PM |
780 | if (client->irq > 0 && chip_info->irq_config.info) |
781 | st->chip_config = &chip_info->irq_config; | |
782 | else | |
783 | st->chip_config = &chip_info->noirq_config; | |
985dbe77 MH |
784 | |
785 | /* TODO: Add pdata options for filtering and bit delay */ | |
786 | ||
6a88fa48 | 787 | st->reg = devm_regulator_get(&client->dev, "vcc"); |
2deaf23b HK |
788 | if (IS_ERR(st->reg)) |
789 | return PTR_ERR(st->reg); | |
790 | ret = regulator_enable(st->reg); | |
791 | if (ret) | |
792 | return ret; | |
793 | st->vref = devm_regulator_get(&client->dev, "vref"); | |
794 | if (IS_ERR(st->vref)) { | |
795 | ret = PTR_ERR(st->vref); | |
796 | goto error_disable_reg; | |
985dbe77 | 797 | } |
2deaf23b HK |
798 | ret = regulator_enable(st->vref); |
799 | if (ret) | |
800 | goto error_disable_reg; | |
801 | ||
985dbe77 MH |
802 | st->client = client; |
803 | ||
1bf7ac76 MH |
804 | indio_dev->dev.parent = &client->dev; |
805 | indio_dev->name = id->name; | |
91556c69 | 806 | indio_dev->info = st->chip_config->info; |
6fe8135f | 807 | |
1bf7ac76 | 808 | indio_dev->modes = INDIO_DIRECT_MODE; |
91556c69 PM |
809 | indio_dev->channels = st->chip_config->channel; |
810 | indio_dev->num_channels = chip_info->num_channels; | |
1bf7ac76 | 811 | |
0f7ddcc1 PM |
812 | ret = ad799x_write_config(st, st->chip_config->default_config); |
813 | if (ret < 0) | |
814 | goto error_disable_reg; | |
815 | ret = ad799x_read_config(st); | |
816 | if (ret < 0) | |
817 | goto error_disable_reg; | |
818 | st->config = ret; | |
819 | ||
396590b3 LPC |
820 | ret = iio_triggered_buffer_setup(indio_dev, NULL, |
821 | &ad799x_trigger_handler, NULL); | |
985dbe77 | 822 | if (ret) |
82a5803c | 823 | goto error_disable_vref; |
985dbe77 | 824 | |
6fe8135f | 825 | if (client->irq > 0) { |
cc7c0f7e HK |
826 | ret = devm_request_threaded_irq(&client->dev, |
827 | client->irq, | |
828 | NULL, | |
829 | ad799x_event_handler, | |
830 | IRQF_TRIGGER_FALLING | | |
831 | IRQF_ONESHOT, | |
832 | client->name, | |
833 | indio_dev); | |
985dbe77 MH |
834 | if (ret) |
835 | goto error_cleanup_ring; | |
985dbe77 | 836 | } |
26d25ae3 JC |
837 | ret = iio_device_register(indio_dev); |
838 | if (ret) | |
cc7c0f7e | 839 | goto error_cleanup_ring; |
985dbe77 MH |
840 | |
841 | return 0; | |
1bf7ac76 | 842 | |
985dbe77 | 843 | error_cleanup_ring: |
396590b3 | 844 | iio_triggered_buffer_cleanup(indio_dev); |
82a5803c DC |
845 | error_disable_vref: |
846 | regulator_disable(st->vref); | |
985dbe77 | 847 | error_disable_reg: |
82a5803c | 848 | regulator_disable(st->reg); |
1bf7ac76 | 849 | |
985dbe77 MH |
850 | return ret; |
851 | } | |
852 | ||
447d4f29 | 853 | static int ad799x_remove(struct i2c_client *client) |
985dbe77 | 854 | { |
1bf7ac76 MH |
855 | struct iio_dev *indio_dev = i2c_get_clientdata(client); |
856 | struct ad799x_state *st = iio_priv(indio_dev); | |
985dbe77 | 857 | |
d2fffd6c | 858 | iio_device_unregister(indio_dev); |
985dbe77 | 859 | |
396590b3 | 860 | iio_triggered_buffer_cleanup(indio_dev); |
82a5803c DC |
861 | regulator_disable(st->vref); |
862 | regulator_disable(st->reg); | |
d8dca330 | 863 | kfree(st->rx_buf); |
985dbe77 MH |
864 | |
865 | return 0; | |
866 | } | |
867 | ||
868 | static const struct i2c_device_id ad799x_id[] = { | |
869 | { "ad7991", ad7991 }, | |
870 | { "ad7995", ad7995 }, | |
871 | { "ad7999", ad7999 }, | |
872 | { "ad7992", ad7992 }, | |
873 | { "ad7993", ad7993 }, | |
874 | { "ad7994", ad7994 }, | |
875 | { "ad7997", ad7997 }, | |
876 | { "ad7998", ad7998 }, | |
877 | {} | |
878 | }; | |
879 | ||
880 | MODULE_DEVICE_TABLE(i2c, ad799x_id); | |
881 | ||
882 | static struct i2c_driver ad799x_driver = { | |
883 | .driver = { | |
884 | .name = "ad799x", | |
885 | }, | |
886 | .probe = ad799x_probe, | |
e543acf0 | 887 | .remove = ad799x_remove, |
985dbe77 MH |
888 | .id_table = ad799x_id, |
889 | }; | |
6e5af184 | 890 | module_i2c_driver(ad799x_driver); |
985dbe77 MH |
891 | |
892 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
893 | MODULE_DESCRIPTION("Analog Devices AD799x ADC"); | |
894 | MODULE_LICENSE("GPL v2"); |