Commit | Line | Data |
---|---|---|
c2f37c8d MH |
1 | /* |
2 | * AD5686R, AD5685R, AD5684R Digital to analog converters driver | |
3 | * | |
4 | * Copyright 2011 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2. | |
7 | */ | |
8 | ||
9 | #include <linux/interrupt.h> | |
c2f37c8d MH |
10 | #include <linux/fs.h> |
11 | #include <linux/device.h> | |
99c97852 | 12 | #include <linux/module.h> |
c2f37c8d MH |
13 | #include <linux/kernel.h> |
14 | #include <linux/spi/spi.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/sysfs.h> | |
17 | #include <linux/regulator/consumer.h> | |
18 | ||
06458e27 JC |
19 | #include <linux/iio/iio.h> |
20 | #include <linux/iio/sysfs.h> | |
c2f37c8d MH |
21 | |
22 | #define AD5686_DAC_CHANNELS 4 | |
23 | ||
24 | #define AD5686_ADDR(x) ((x) << 16) | |
25 | #define AD5686_CMD(x) ((x) << 20) | |
26 | ||
a45186c0 | 27 | #define AD5686_ADDR_DAC(chan) (0x1 << (chan)) |
c2f37c8d MH |
28 | #define AD5686_ADDR_ALL_DAC 0xF |
29 | ||
30 | #define AD5686_CMD_NOOP 0x0 | |
31 | #define AD5686_CMD_WRITE_INPUT_N 0x1 | |
32 | #define AD5686_CMD_UPDATE_DAC_N 0x2 | |
33 | #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3 | |
34 | #define AD5686_CMD_POWERDOWN_DAC 0x4 | |
35 | #define AD5686_CMD_LDAC_MASK 0x5 | |
36 | #define AD5686_CMD_RESET 0x6 | |
37 | #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7 | |
38 | #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8 | |
39 | #define AD5686_CMD_READBACK_ENABLE 0x9 | |
40 | ||
41 | #define AD5686_LDAC_PWRDN_NONE 0x0 | |
42 | #define AD5686_LDAC_PWRDN_1K 0x1 | |
43 | #define AD5686_LDAC_PWRDN_100K 0x2 | |
44 | #define AD5686_LDAC_PWRDN_3STATE 0x3 | |
45 | ||
46 | /** | |
47 | * struct ad5686_chip_info - chip specific information | |
48 | * @int_vref_mv: AD5620/40/60: the internal reference voltage | |
49 | * @channel: channel specification | |
50 | */ | |
51 | ||
52 | struct ad5686_chip_info { | |
53 | u16 int_vref_mv; | |
54 | struct iio_chan_spec channel[AD5686_DAC_CHANNELS]; | |
55 | }; | |
56 | ||
57 | /** | |
58 | * struct ad5446_state - driver instance specific data | |
59 | * @spi: spi_device | |
60 | * @chip_info: chip model specific constants, available modes etc | |
61 | * @reg: supply regulator | |
62 | * @vref_mv: actual reference voltage used | |
63 | * @pwr_down_mask: power down mask | |
64 | * @pwr_down_mode: current power down mode | |
65 | * @data: spi transfer buffers | |
66 | */ | |
67 | ||
68 | struct ad5686_state { | |
69 | struct spi_device *spi; | |
70 | const struct ad5686_chip_info *chip_info; | |
71 | struct regulator *reg; | |
72 | unsigned short vref_mv; | |
73 | unsigned pwr_down_mask; | |
74 | unsigned pwr_down_mode; | |
75 | /* | |
76 | * DMA (thus cache coherency maintenance) requires the | |
77 | * transfer buffers to live in their own cache lines. | |
78 | */ | |
79 | ||
80 | union { | |
81 | u32 d32; | |
82 | u8 d8[4]; | |
83 | } data[3] ____cacheline_aligned; | |
84 | }; | |
85 | ||
86 | /** | |
87 | * ad5686_supported_device_ids: | |
88 | */ | |
89 | ||
90 | enum ad5686_supported_device_ids { | |
91 | ID_AD5684, | |
92 | ID_AD5685, | |
93 | ID_AD5686, | |
94 | }; | |
c2f37c8d MH |
95 | static int ad5686_spi_write(struct ad5686_state *st, |
96 | u8 cmd, u8 addr, u16 val, u8 shift) | |
97 | { | |
98 | val <<= shift; | |
99 | ||
100 | st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) | | |
101 | AD5686_ADDR(addr) | | |
102 | val); | |
103 | ||
104 | return spi_write(st->spi, &st->data[0].d8[1], 3); | |
105 | } | |
106 | ||
107 | static int ad5686_spi_read(struct ad5686_state *st, u8 addr) | |
108 | { | |
109 | struct spi_transfer t[] = { | |
110 | { | |
111 | .tx_buf = &st->data[0].d8[1], | |
112 | .len = 3, | |
113 | .cs_change = 1, | |
114 | }, { | |
115 | .tx_buf = &st->data[1].d8[1], | |
116 | .rx_buf = &st->data[2].d8[1], | |
117 | .len = 3, | |
118 | }, | |
119 | }; | |
c2f37c8d MH |
120 | int ret; |
121 | ||
c2f37c8d MH |
122 | st->data[0].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_READBACK_ENABLE) | |
123 | AD5686_ADDR(addr)); | |
124 | st->data[1].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_NOOP)); | |
125 | ||
14543a00 | 126 | ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); |
c2f37c8d MH |
127 | if (ret < 0) |
128 | return ret; | |
129 | ||
130 | return be32_to_cpu(st->data[2].d32); | |
131 | } | |
132 | ||
fe4586a8 LPC |
133 | static const char * const ad5686_powerdown_modes[] = { |
134 | "1kohm_to_gnd", | |
135 | "100kohm_to_gnd", | |
136 | "three_state" | |
137 | }; | |
138 | ||
139 | static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev, | |
140 | const struct iio_chan_spec *chan) | |
c2f37c8d | 141 | { |
c2f37c8d | 142 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d | 143 | |
fe4586a8 | 144 | return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1; |
c2f37c8d MH |
145 | } |
146 | ||
fe4586a8 LPC |
147 | static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev, |
148 | const struct iio_chan_spec *chan, unsigned int mode) | |
c2f37c8d | 149 | { |
c2f37c8d | 150 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d | 151 | |
fe4586a8 LPC |
152 | st->pwr_down_mode &= ~(0x3 << (chan->channel * 2)); |
153 | st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2)); | |
c2f37c8d | 154 | |
fe4586a8 | 155 | return 0; |
c2f37c8d MH |
156 | } |
157 | ||
fe4586a8 LPC |
158 | static const struct iio_enum ad5686_powerdown_mode_enum = { |
159 | .items = ad5686_powerdown_modes, | |
160 | .num_items = ARRAY_SIZE(ad5686_powerdown_modes), | |
161 | .get = ad5686_get_powerdown_mode, | |
162 | .set = ad5686_set_powerdown_mode, | |
163 | }; | |
164 | ||
165 | static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev, | |
166 | uintptr_t private, const struct iio_chan_spec *chan, char *buf) | |
c2f37c8d | 167 | { |
c2f37c8d | 168 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d MH |
169 | |
170 | return sprintf(buf, "%d\n", !!(st->pwr_down_mask & | |
fe4586a8 | 171 | (0x3 << (chan->channel * 2)))); |
c2f37c8d MH |
172 | } |
173 | ||
fe4586a8 LPC |
174 | static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev, |
175 | uintptr_t private, const struct iio_chan_spec *chan, const char *buf, | |
176 | size_t len) | |
c2f37c8d MH |
177 | { |
178 | bool readin; | |
179 | int ret; | |
c2f37c8d | 180 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d MH |
181 | |
182 | ret = strtobool(buf, &readin); | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
7737fa6d | 186 | if (readin) |
fe4586a8 | 187 | st->pwr_down_mask |= (0x3 << (chan->channel * 2)); |
c2f37c8d | 188 | else |
fe4586a8 | 189 | st->pwr_down_mask &= ~(0x3 << (chan->channel * 2)); |
c2f37c8d MH |
190 | |
191 | ret = ad5686_spi_write(st, AD5686_CMD_POWERDOWN_DAC, 0, | |
192 | st->pwr_down_mask & st->pwr_down_mode, 0); | |
193 | ||
194 | return ret ? ret : len; | |
195 | } | |
196 | ||
c2f37c8d MH |
197 | static int ad5686_read_raw(struct iio_dev *indio_dev, |
198 | struct iio_chan_spec const *chan, | |
199 | int *val, | |
200 | int *val2, | |
201 | long m) | |
202 | { | |
203 | struct ad5686_state *st = iio_priv(indio_dev); | |
204 | unsigned long scale_uv; | |
205 | int ret; | |
206 | ||
207 | switch (m) { | |
09f4eb40 | 208 | case IIO_CHAN_INFO_RAW: |
c2f37c8d MH |
209 | mutex_lock(&indio_dev->mlock); |
210 | ret = ad5686_spi_read(st, chan->address); | |
211 | mutex_unlock(&indio_dev->mlock); | |
212 | if (ret < 0) | |
213 | return ret; | |
214 | *val = ret; | |
215 | return IIO_VAL_INT; | |
216 | break; | |
c8a9f805 | 217 | case IIO_CHAN_INFO_SCALE: |
c2f37c8d MH |
218 | scale_uv = (st->vref_mv * 100000) |
219 | >> (chan->scan_type.realbits); | |
220 | *val = scale_uv / 100000; | |
221 | *val2 = (scale_uv % 100000) * 10; | |
222 | return IIO_VAL_INT_PLUS_MICRO; | |
223 | ||
224 | } | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
228 | static int ad5686_write_raw(struct iio_dev *indio_dev, | |
229 | struct iio_chan_spec const *chan, | |
230 | int val, | |
231 | int val2, | |
232 | long mask) | |
233 | { | |
234 | struct ad5686_state *st = iio_priv(indio_dev); | |
235 | int ret; | |
236 | ||
237 | switch (mask) { | |
09f4eb40 | 238 | case IIO_CHAN_INFO_RAW: |
cd8eca6f | 239 | if (val > (1 << chan->scan_type.realbits) || val < 0) |
c2f37c8d MH |
240 | return -EINVAL; |
241 | ||
242 | mutex_lock(&indio_dev->mlock); | |
243 | ret = ad5686_spi_write(st, | |
244 | AD5686_CMD_WRITE_INPUT_N_UPDATE_N, | |
245 | chan->address, | |
246 | val, | |
247 | chan->scan_type.shift); | |
248 | mutex_unlock(&indio_dev->mlock); | |
249 | break; | |
250 | default: | |
251 | ret = -EINVAL; | |
252 | } | |
253 | ||
254 | return ret; | |
255 | } | |
256 | ||
257 | static const struct iio_info ad5686_info = { | |
258 | .read_raw = ad5686_read_raw, | |
259 | .write_raw = ad5686_write_raw, | |
c2f37c8d MH |
260 | .driver_module = THIS_MODULE, |
261 | }; | |
262 | ||
fe4586a8 LPC |
263 | static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { |
264 | { | |
265 | .name = "powerdown", | |
266 | .read = ad5686_read_dac_powerdown, | |
267 | .write = ad5686_write_dac_powerdown, | |
268 | }, | |
269 | IIO_ENUM("powerdown_mode", false, &ad5686_powerdown_mode_enum), | |
270 | IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum), | |
271 | { }, | |
272 | }; | |
273 | ||
274 | #define AD5868_CHANNEL(chan, bits, shift) { \ | |
275 | .type = IIO_VOLTAGE, \ | |
276 | .indexed = 1, \ | |
277 | .output = 1, \ | |
278 | .channel = chan, \ | |
d87a1d78 JC |
279 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
280 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ | |
281 | .address = AD5686_ADDR_DAC(chan), \ | |
fe4586a8 LPC |
282 | .scan_type = IIO_ST('u', bits, 16, shift), \ |
283 | .ext_info = ad5686_ext_info, \ | |
284 | } | |
285 | ||
286 | static const struct ad5686_chip_info ad5686_chip_info_tbl[] = { | |
287 | [ID_AD5684] = { | |
288 | .channel[0] = AD5868_CHANNEL(0, 12, 4), | |
289 | .channel[1] = AD5868_CHANNEL(1, 12, 4), | |
290 | .channel[2] = AD5868_CHANNEL(2, 12, 4), | |
291 | .channel[3] = AD5868_CHANNEL(3, 12, 4), | |
292 | .int_vref_mv = 2500, | |
293 | }, | |
294 | [ID_AD5685] = { | |
295 | .channel[0] = AD5868_CHANNEL(0, 14, 2), | |
296 | .channel[1] = AD5868_CHANNEL(1, 14, 2), | |
297 | .channel[2] = AD5868_CHANNEL(2, 14, 2), | |
298 | .channel[3] = AD5868_CHANNEL(3, 14, 2), | |
299 | .int_vref_mv = 2500, | |
300 | }, | |
301 | [ID_AD5686] = { | |
302 | .channel[0] = AD5868_CHANNEL(0, 16, 0), | |
303 | .channel[1] = AD5868_CHANNEL(1, 16, 0), | |
304 | .channel[2] = AD5868_CHANNEL(2, 16, 0), | |
305 | .channel[3] = AD5868_CHANNEL(3, 16, 0), | |
306 | .int_vref_mv = 2500, | |
307 | }, | |
308 | }; | |
309 | ||
310 | ||
fc52692c | 311 | static int ad5686_probe(struct spi_device *spi) |
c2f37c8d MH |
312 | { |
313 | struct ad5686_state *st; | |
314 | struct iio_dev *indio_dev; | |
315 | int ret, regdone = 0, voltage_uv = 0; | |
316 | ||
edf3fd41 | 317 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
c2f37c8d MH |
318 | if (indio_dev == NULL) |
319 | return -ENOMEM; | |
320 | ||
321 | st = iio_priv(indio_dev); | |
322 | spi_set_drvdata(spi, indio_dev); | |
323 | ||
edf3fd41 | 324 | st->reg = devm_regulator_get(&spi->dev, "vcc"); |
c2f37c8d MH |
325 | if (!IS_ERR(st->reg)) { |
326 | ret = regulator_enable(st->reg); | |
327 | if (ret) | |
edf3fd41 | 328 | return ret; |
c2f37c8d | 329 | |
359570ad AL |
330 | ret = regulator_get_voltage(st->reg); |
331 | if (ret < 0) | |
332 | goto error_disable_reg; | |
333 | ||
334 | voltage_uv = ret; | |
c2f37c8d MH |
335 | } |
336 | ||
337 | st->chip_info = | |
338 | &ad5686_chip_info_tbl[spi_get_device_id(spi)->driver_data]; | |
339 | ||
340 | if (voltage_uv) | |
341 | st->vref_mv = voltage_uv / 1000; | |
342 | else | |
343 | st->vref_mv = st->chip_info->int_vref_mv; | |
344 | ||
345 | st->spi = spi; | |
346 | ||
fe4586a8 LPC |
347 | /* Set all the power down mode for all channels to 1K pulldown */ |
348 | st->pwr_down_mode = 0x55; | |
349 | ||
c2f37c8d MH |
350 | indio_dev->dev.parent = &spi->dev; |
351 | indio_dev->name = spi_get_device_id(spi)->name; | |
352 | indio_dev->info = &ad5686_info; | |
353 | indio_dev->modes = INDIO_DIRECT_MODE; | |
354 | indio_dev->channels = st->chip_info->channel; | |
355 | indio_dev->num_channels = AD5686_DAC_CHANNELS; | |
356 | ||
c2f37c8d MH |
357 | regdone = 1; |
358 | ret = ad5686_spi_write(st, AD5686_CMD_INTERNAL_REFER_SETUP, 0, | |
359 | !!voltage_uv, 0); | |
360 | if (ret) | |
361 | goto error_disable_reg; | |
362 | ||
26d25ae3 JC |
363 | ret = iio_device_register(indio_dev); |
364 | if (ret) | |
365 | goto error_disable_reg; | |
366 | ||
c2f37c8d MH |
367 | return 0; |
368 | ||
369 | error_disable_reg: | |
370 | if (!IS_ERR(st->reg)) | |
371 | regulator_disable(st->reg); | |
c2f37c8d MH |
372 | return ret; |
373 | } | |
374 | ||
fc52692c | 375 | static int ad5686_remove(struct spi_device *spi) |
c2f37c8d MH |
376 | { |
377 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
378 | struct ad5686_state *st = iio_priv(indio_dev); | |
c2f37c8d | 379 | |
d2fffd6c | 380 | iio_device_unregister(indio_dev); |
edf3fd41 | 381 | if (!IS_ERR(st->reg)) |
26a54797 | 382 | regulator_disable(st->reg); |
c2f37c8d MH |
383 | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static const struct spi_device_id ad5686_id[] = { | |
388 | {"ad5684", ID_AD5684}, | |
389 | {"ad5685", ID_AD5685}, | |
390 | {"ad5686", ID_AD5686}, | |
391 | {} | |
392 | }; | |
55e4390c | 393 | MODULE_DEVICE_TABLE(spi, ad5686_id); |
c2f37c8d MH |
394 | |
395 | static struct spi_driver ad5686_driver = { | |
396 | .driver = { | |
397 | .name = "ad5686", | |
398 | .owner = THIS_MODULE, | |
399 | }, | |
400 | .probe = ad5686_probe, | |
fc52692c | 401 | .remove = ad5686_remove, |
c2f37c8d MH |
402 | .id_table = ad5686_id, |
403 | }; | |
ae6ae6fe | 404 | module_spi_driver(ad5686_driver); |
c2f37c8d MH |
405 | |
406 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
407 | MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC"); | |
408 | MODULE_LICENSE("GPL v2"); |