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77241056 | 1 | /* |
05d6ac1d | 2 | * Copyright(c) 2015, 2016 Intel Corporation. |
77241056 MM |
3 | * |
4 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
5 | * redistributing this file, you may do so under either license. | |
6 | * | |
7 | * GPL LICENSE SUMMARY | |
8 | * | |
77241056 MM |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * BSD LICENSE | |
19 | * | |
77241056 MM |
20 | * Redistribution and use in source and binary forms, with or without |
21 | * modification, are permitted provided that the following conditions | |
22 | * are met: | |
23 | * | |
24 | * - Redistributions of source code must retain the above copyright | |
25 | * notice, this list of conditions and the following disclaimer. | |
26 | * - Redistributions in binary form must reproduce the above copyright | |
27 | * notice, this list of conditions and the following disclaimer in | |
28 | * the documentation and/or other materials provided with the | |
29 | * distribution. | |
30 | * - Neither the name of Intel Corporation nor the names of its | |
31 | * contributors may be used to endorse or promote products derived | |
32 | * from this software without specific prior written permission. | |
33 | * | |
34 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
35 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
37 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
38 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
39 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
40 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
41 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
42 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
43 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
44 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
45 | * | |
46 | */ | |
47 | ||
48 | #include <linux/pci.h> | |
49 | #include <linux/io.h> | |
50 | #include <linux/delay.h> | |
51 | #include <linux/vmalloc.h> | |
52 | #include <linux/aer.h> | |
53 | #include <linux/module.h> | |
54 | ||
55 | #include "hfi.h" | |
56 | #include "chip_registers.h" | |
affa48de | 57 | #include "aspm.h" |
77241056 MM |
58 | |
59 | /* link speed vector for Gen3 speed - not in Linux headers */ | |
60 | #define GEN1_SPEED_VECTOR 0x1 | |
61 | #define GEN2_SPEED_VECTOR 0x2 | |
62 | #define GEN3_SPEED_VECTOR 0x3 | |
63 | ||
64 | /* | |
65 | * This file contains PCIe utility routines. | |
66 | */ | |
67 | ||
68 | /* | |
69 | * Code to adjust PCIe capabilities. | |
70 | */ | |
71 | static void tune_pcie_caps(struct hfi1_devdata *); | |
72 | ||
73 | /* | |
74 | * Do all the common PCIe setup and initialization. | |
75 | * devdata is not yet allocated, and is not allocated until after this | |
76 | * routine returns success. Therefore dd_dev_err() can't be used for error | |
77 | * printing. | |
78 | */ | |
79 | int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) | |
80 | { | |
81 | int ret; | |
82 | ||
83 | ret = pci_enable_device(pdev); | |
84 | if (ret) { | |
85 | /* | |
86 | * This can happen (in theory) iff: | |
87 | * We did a chip reset, and then failed to reprogram the | |
88 | * BAR, or the chip reset due to an internal error. We then | |
89 | * unloaded the driver and reloaded it. | |
90 | * | |
91 | * Both reset cases set the BAR back to initial state. For | |
92 | * the latter case, the AER sticky error bit at offset 0x718 | |
93 | * should be set, but the Linux kernel doesn't yet know | |
94 | * about that, it appears. If the original BAR was retained | |
95 | * in the kernel data structures, this may be OK. | |
96 | */ | |
97 | hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", | |
98 | -ret); | |
99 | goto done; | |
100 | } | |
101 | ||
102 | ret = pci_request_regions(pdev, DRIVER_NAME); | |
103 | if (ret) { | |
104 | hfi1_early_err(&pdev->dev, | |
105 | "pci_request_regions fails: err %d\n", -ret); | |
106 | goto bail; | |
107 | } | |
108 | ||
109 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
110 | if (ret) { | |
111 | /* | |
112 | * If the 64 bit setup fails, try 32 bit. Some systems | |
113 | * do not setup 64 bit maps on systems with 2GB or less | |
114 | * memory installed. | |
115 | */ | |
116 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
117 | if (ret) { | |
118 | hfi1_early_err(&pdev->dev, | |
119 | "Unable to set DMA mask: %d\n", ret); | |
120 | goto bail; | |
121 | } | |
122 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
e490974e | 123 | } else { |
77241056 | 124 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
e490974e | 125 | } |
77241056 MM |
126 | if (ret) { |
127 | hfi1_early_err(&pdev->dev, | |
128 | "Unable to set DMA consistent mask: %d\n", ret); | |
129 | goto bail; | |
130 | } | |
131 | ||
132 | pci_set_master(pdev); | |
0096765b | 133 | (void)pci_enable_pcie_error_reporting(pdev); |
77241056 MM |
134 | goto done; |
135 | ||
136 | bail: | |
137 | hfi1_pcie_cleanup(pdev); | |
138 | done: | |
139 | return ret; | |
140 | } | |
141 | ||
142 | /* | |
143 | * Clean what was done in hfi1_pcie_init() | |
144 | */ | |
145 | void hfi1_pcie_cleanup(struct pci_dev *pdev) | |
146 | { | |
147 | pci_disable_device(pdev); | |
148 | /* | |
149 | * Release regions should be called after the disable. OK to | |
150 | * call if request regions has not been called or failed. | |
151 | */ | |
152 | pci_release_regions(pdev); | |
153 | } | |
154 | ||
155 | /* | |
156 | * Do remaining PCIe setup, once dd is allocated, and save away | |
157 | * fields required to re-initialize after a chip reset, or for | |
158 | * various other purposes | |
159 | */ | |
160 | int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev, | |
161 | const struct pci_device_id *ent) | |
162 | { | |
163 | unsigned long len; | |
164 | resource_size_t addr; | |
165 | ||
166 | dd->pcidev = pdev; | |
167 | pci_set_drvdata(pdev, dd); | |
168 | ||
169 | addr = pci_resource_start(pdev, 0); | |
170 | len = pci_resource_len(pdev, 0); | |
171 | ||
172 | /* | |
173 | * The TXE PIO buffers are at the tail end of the chip space. | |
174 | * Cut them off and map them separately. | |
175 | */ | |
176 | ||
177 | /* sanity check vs expectations */ | |
178 | if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { | |
179 | dd_dev_err(dd, "chip PIO range does not match\n"); | |
180 | return -EINVAL; | |
181 | } | |
182 | ||
183 | dd->kregbase = ioremap_nocache(addr, TXE_PIO_SEND); | |
184 | if (!dd->kregbase) | |
185 | return -ENOMEM; | |
186 | ||
187 | dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); | |
188 | if (!dd->piobase) { | |
189 | iounmap(dd->kregbase); | |
190 | return -ENOMEM; | |
191 | } | |
192 | ||
193 | dd->flags |= HFI1_PRESENT; /* now register routines work */ | |
194 | ||
195 | dd->kregend = dd->kregbase + TXE_PIO_SEND; | |
196 | dd->physaddr = addr; /* used for io_remap, etc. */ | |
197 | ||
198 | /* | |
199 | * Re-map the chip's RcvArray as write-combining to allow us | |
200 | * to write an entire cacheline worth of entries in one shot. | |
201 | * If this re-map fails, just continue - the RcvArray programming | |
202 | * function will handle both cases. | |
203 | */ | |
204 | dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); | |
205 | dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, | |
206 | dd->chip_rcv_array_count * 8); | |
207 | dd_dev_info(dd, "WC Remapped RcvArray: %p\n", dd->rcvarray_wc); | |
208 | /* | |
209 | * Save BARs and command to rewrite after device reset. | |
210 | */ | |
211 | dd->pcibar0 = addr; | |
212 | dd->pcibar1 = addr >> 32; | |
213 | pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); | |
214 | pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); | |
215 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl); | |
216 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, &dd->pcie_lnkctl); | |
217 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, | |
17fb4f29 | 218 | &dd->pcie_devctl2); |
77241056 | 219 | pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); |
17fb4f29 | 220 | pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, &dd->pci_lnkctl3); |
77241056 MM |
221 | pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2); |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | /* | |
227 | * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior | |
228 | * to releasing the dd memory. | |
229 | * Void because all of the core pcie cleanup functions are void. | |
230 | */ | |
231 | void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) | |
232 | { | |
50e5dcbe | 233 | u64 __iomem *base = (void __iomem *)dd->kregbase; |
77241056 MM |
234 | |
235 | dd->flags &= ~HFI1_PRESENT; | |
236 | dd->kregbase = NULL; | |
237 | iounmap(base); | |
238 | if (dd->rcvarray_wc) | |
239 | iounmap(dd->rcvarray_wc); | |
240 | if (dd->piobase) | |
241 | iounmap(dd->piobase); | |
77241056 MM |
242 | } |
243 | ||
244 | /* | |
245 | * Do a Function Level Reset (FLR) on the device. | |
246 | * Based on static function drivers/pci/pci.c:pcie_flr(). | |
247 | */ | |
248 | void hfi1_pcie_flr(struct hfi1_devdata *dd) | |
249 | { | |
250 | int i; | |
251 | u16 status; | |
252 | ||
253 | /* no need to check for the capability - we know the device has it */ | |
254 | ||
255 | /* wait for Transaction Pending bit to clear, at most a few ms */ | |
256 | for (i = 0; i < 4; i++) { | |
257 | if (i) | |
258 | msleep((1 << (i - 1)) * 100); | |
259 | ||
260 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVSTA, &status); | |
261 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
262 | goto clear; | |
263 | } | |
264 | ||
265 | dd_dev_err(dd, "Transaction Pending bit is not clearing, proceeding with reset anyway\n"); | |
266 | ||
267 | clear: | |
268 | pcie_capability_set_word(dd->pcidev, PCI_EXP_DEVCTL, | |
17fb4f29 | 269 | PCI_EXP_DEVCTL_BCR_FLR); |
77241056 MM |
270 | /* PCIe spec requires the function to be back within 100ms */ |
271 | msleep(100); | |
272 | } | |
273 | ||
274 | static void msix_setup(struct hfi1_devdata *dd, int pos, u32 *msixcnt, | |
275 | struct hfi1_msix_entry *hfi1_msix_entry) | |
276 | { | |
277 | int ret; | |
278 | int nvec = *msixcnt; | |
279 | struct msix_entry *msix_entry; | |
280 | int i; | |
281 | ||
4d114fdd JJ |
282 | /* |
283 | * We can't pass hfi1_msix_entry array to msix_setup | |
77241056 | 284 | * so use a dummy msix_entry array and copy the allocated |
4d114fdd JJ |
285 | * irq back to the hfi1_msix_entry array. |
286 | */ | |
77241056 MM |
287 | msix_entry = kmalloc_array(nvec, sizeof(*msix_entry), GFP_KERNEL); |
288 | if (!msix_entry) { | |
289 | ret = -ENOMEM; | |
290 | goto do_intx; | |
291 | } | |
292 | ||
293 | for (i = 0; i < nvec; i++) | |
294 | msix_entry[i] = hfi1_msix_entry[i].msix; | |
295 | ||
296 | ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec); | |
297 | if (ret < 0) | |
298 | goto free_msix_entry; | |
299 | nvec = ret; | |
300 | ||
301 | for (i = 0; i < nvec; i++) | |
302 | hfi1_msix_entry[i].msix = msix_entry[i]; | |
303 | ||
304 | kfree(msix_entry); | |
305 | *msixcnt = nvec; | |
306 | return; | |
307 | ||
308 | free_msix_entry: | |
309 | kfree(msix_entry); | |
310 | ||
311 | do_intx: | |
312 | dd_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, falling back to INTx\n", | |
313 | nvec, ret); | |
314 | *msixcnt = 0; | |
315 | hfi1_enable_intx(dd->pcidev); | |
77241056 MM |
316 | } |
317 | ||
318 | /* return the PCIe link speed from the given link status */ | |
319 | static u32 extract_speed(u16 linkstat) | |
320 | { | |
321 | u32 speed; | |
322 | ||
323 | switch (linkstat & PCI_EXP_LNKSTA_CLS) { | |
324 | default: /* not defined, assume Gen1 */ | |
325 | case PCI_EXP_LNKSTA_CLS_2_5GB: | |
326 | speed = 2500; /* Gen 1, 2.5GHz */ | |
327 | break; | |
328 | case PCI_EXP_LNKSTA_CLS_5_0GB: | |
329 | speed = 5000; /* Gen 2, 5GHz */ | |
330 | break; | |
331 | case GEN3_SPEED_VECTOR: | |
332 | speed = 8000; /* Gen 3, 8GHz */ | |
333 | break; | |
334 | } | |
335 | return speed; | |
336 | } | |
337 | ||
338 | /* return the PCIe link speed from the given link status */ | |
339 | static u32 extract_width(u16 linkstat) | |
340 | { | |
341 | return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; | |
342 | } | |
343 | ||
344 | /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ | |
345 | static void update_lbus_info(struct hfi1_devdata *dd) | |
346 | { | |
347 | u16 linkstat; | |
348 | ||
349 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); | |
350 | dd->lbus_width = extract_width(linkstat); | |
351 | dd->lbus_speed = extract_speed(linkstat); | |
352 | snprintf(dd->lbus_info, sizeof(dd->lbus_info), | |
353 | "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); | |
354 | } | |
355 | ||
356 | /* | |
357 | * Read in the current PCIe link width and speed. Find if the link is | |
358 | * Gen3 capable. | |
359 | */ | |
360 | int pcie_speeds(struct hfi1_devdata *dd) | |
361 | { | |
362 | u32 linkcap; | |
bf400235 | 363 | struct pci_dev *parent = dd->pcidev->bus->self; |
77241056 MM |
364 | |
365 | if (!pci_is_pcie(dd->pcidev)) { | |
366 | dd_dev_err(dd, "Can't find PCI Express capability!\n"); | |
367 | return -EINVAL; | |
368 | } | |
369 | ||
370 | /* find if our max speed is Gen3 and parent supports Gen3 speeds */ | |
371 | dd->link_gen3_capable = 1; | |
372 | ||
373 | pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); | |
374 | if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) { | |
375 | dd_dev_info(dd, | |
17fb4f29 JJ |
376 | "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", |
377 | linkcap & PCI_EXP_LNKCAP_SLS); | |
77241056 MM |
378 | dd->link_gen3_capable = 0; |
379 | } | |
380 | ||
381 | /* | |
382 | * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed | |
383 | */ | |
bf400235 | 384 | if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { |
77241056 MM |
385 | dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); |
386 | dd->link_gen3_capable = 0; | |
387 | } | |
388 | ||
389 | /* obtain the link width and current speed */ | |
390 | update_lbus_info(dd); | |
391 | ||
82ab09e1 | 392 | dd_dev_info(dd, "%s\n", dd->lbus_info); |
77241056 MM |
393 | |
394 | return 0; | |
395 | } | |
396 | ||
397 | /* | |
398 | * Returns in *nent: | |
399 | * - actual number of interrupts allocated | |
400 | * - 0 if fell back to INTx. | |
401 | */ | |
402 | void request_msix(struct hfi1_devdata *dd, u32 *nent, | |
403 | struct hfi1_msix_entry *entry) | |
404 | { | |
405 | int pos; | |
406 | ||
407 | pos = dd->pcidev->msix_cap; | |
408 | if (*nent && pos) { | |
409 | msix_setup(dd, pos, nent, entry); | |
410 | /* did it, either MSI-X or INTx */ | |
411 | } else { | |
412 | *nent = 0; | |
413 | hfi1_enable_intx(dd->pcidev); | |
414 | } | |
415 | ||
416 | tune_pcie_caps(dd); | |
417 | } | |
418 | ||
77241056 MM |
419 | void hfi1_enable_intx(struct pci_dev *pdev) |
420 | { | |
421 | /* first, turn on INTx */ | |
422 | pci_intx(pdev, 1); | |
423 | /* then turn off MSI-X */ | |
424 | pci_disable_msix(pdev); | |
425 | } | |
426 | ||
427 | /* restore command and BARs after a reset has wiped them out */ | |
428 | void restore_pci_variables(struct hfi1_devdata *dd) | |
429 | { | |
430 | pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); | |
17fb4f29 JJ |
431 | pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, dd->pcibar0); |
432 | pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, dd->pcibar1); | |
433 | pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); | |
77241056 MM |
434 | pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, dd->pcie_devctl); |
435 | pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, dd->pcie_lnkctl); | |
436 | pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, | |
17fb4f29 | 437 | dd->pcie_devctl2); |
77241056 | 438 | pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); |
17fb4f29 | 439 | pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, dd->pci_lnkctl3); |
77241056 MM |
440 | pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2); |
441 | } | |
442 | ||
77241056 MM |
443 | /* |
444 | * BIOS may not set PCIe bus-utilization parameters for best performance. | |
445 | * Check and optionally adjust them to maximize our throughput. | |
446 | */ | |
447 | static int hfi1_pcie_caps; | |
448 | module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); | |
449 | MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); | |
450 | ||
affa48de AD |
451 | uint aspm_mode = ASPM_MODE_DISABLED; |
452 | module_param_named(aspm, aspm_mode, uint, S_IRUGO); | |
453 | MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); | |
454 | ||
77241056 MM |
455 | static void tune_pcie_caps(struct hfi1_devdata *dd) |
456 | { | |
457 | struct pci_dev *parent; | |
458 | u16 rc_mpss, rc_mps, ep_mpss, ep_mps; | |
bf70a775 | 459 | u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; |
77241056 | 460 | |
bf70a775 VM |
461 | /* |
462 | * Turn on extended tags in DevCtl in case the BIOS has turned it off | |
463 | * to improve WFR SDMA bandwidth | |
464 | */ | |
465 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); | |
466 | if (!(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { | |
467 | dd_dev_info(dd, "Enabling PCIe extended tags\n"); | |
468 | ectl |= PCI_EXP_DEVCTL_EXT_TAG; | |
469 | pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl); | |
470 | } | |
77241056 MM |
471 | /* Find out supported and configured values for parent (root) */ |
472 | parent = dd->pcidev->bus->self; | |
bf400235 KW |
473 | /* |
474 | * The driver cannot perform the tuning if it does not have | |
475 | * access to the upstream component. | |
476 | */ | |
477 | if (!parent) | |
478 | return; | |
77241056 MM |
479 | if (!pci_is_root_bus(parent->bus)) { |
480 | dd_dev_info(dd, "Parent not root\n"); | |
481 | return; | |
482 | } | |
483 | ||
484 | if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) | |
485 | return; | |
486 | rc_mpss = parent->pcie_mpss; | |
487 | rc_mps = ffs(pcie_get_mps(parent)) - 8; | |
488 | /* Find out supported and configured values for endpoint (us) */ | |
489 | ep_mpss = dd->pcidev->pcie_mpss; | |
490 | ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; | |
491 | ||
492 | /* Find max payload supported by root, endpoint */ | |
493 | if (rc_mpss > ep_mpss) | |
494 | rc_mpss = ep_mpss; | |
495 | ||
496 | /* If Supported greater than limit in module param, limit it */ | |
497 | if (rc_mpss > (hfi1_pcie_caps & 7)) | |
498 | rc_mpss = hfi1_pcie_caps & 7; | |
499 | /* If less than (allowed, supported), bump root payload */ | |
500 | if (rc_mpss > rc_mps) { | |
501 | rc_mps = rc_mpss; | |
502 | pcie_set_mps(parent, 128 << rc_mps); | |
503 | } | |
504 | /* If less than (allowed, supported), bump endpoint payload */ | |
505 | if (rc_mpss > ep_mps) { | |
506 | ep_mps = rc_mpss; | |
507 | pcie_set_mps(dd->pcidev, 128 << ep_mps); | |
508 | } | |
509 | ||
510 | /* | |
511 | * Now the Read Request size. | |
512 | * No field for max supported, but PCIe spec limits it to 4096, | |
513 | * which is code '5' (log2(4096) - 7) | |
514 | */ | |
515 | max_mrrs = 5; | |
516 | if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) | |
517 | max_mrrs = (hfi1_pcie_caps >> 4) & 7; | |
518 | ||
519 | max_mrrs = 128 << max_mrrs; | |
520 | rc_mrrs = pcie_get_readrq(parent); | |
521 | ep_mrrs = pcie_get_readrq(dd->pcidev); | |
522 | ||
523 | if (max_mrrs > rc_mrrs) { | |
524 | rc_mrrs = max_mrrs; | |
525 | pcie_set_readrq(parent, rc_mrrs); | |
526 | } | |
527 | if (max_mrrs > ep_mrrs) { | |
528 | ep_mrrs = max_mrrs; | |
529 | pcie_set_readrq(dd->pcidev, ep_mrrs); | |
530 | } | |
531 | } | |
f4d507cd | 532 | |
77241056 MM |
533 | /* End of PCIe capability tuning */ |
534 | ||
535 | /* | |
536 | * From here through hfi1_pci_err_handler definition is invoked via | |
537 | * PCI error infrastructure, registered via pci | |
538 | */ | |
539 | static pci_ers_result_t | |
540 | pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
541 | { | |
542 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
543 | pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; | |
544 | ||
545 | switch (state) { | |
546 | case pci_channel_io_normal: | |
547 | dd_dev_info(dd, "State Normal, ignoring\n"); | |
548 | break; | |
549 | ||
550 | case pci_channel_io_frozen: | |
551 | dd_dev_info(dd, "State Frozen, requesting reset\n"); | |
552 | pci_disable_device(pdev); | |
553 | ret = PCI_ERS_RESULT_NEED_RESET; | |
554 | break; | |
555 | ||
556 | case pci_channel_io_perm_failure: | |
557 | if (dd) { | |
558 | dd_dev_info(dd, "State Permanent Failure, disabling\n"); | |
559 | /* no more register accesses! */ | |
560 | dd->flags &= ~HFI1_PRESENT; | |
561 | hfi1_disable_after_error(dd); | |
562 | } | |
563 | /* else early, or other problem */ | |
564 | ret = PCI_ERS_RESULT_DISCONNECT; | |
565 | break; | |
566 | ||
567 | default: /* shouldn't happen */ | |
568 | dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", | |
569 | state); | |
570 | break; | |
571 | } | |
572 | return ret; | |
573 | } | |
574 | ||
575 | static pci_ers_result_t | |
576 | pci_mmio_enabled(struct pci_dev *pdev) | |
577 | { | |
578 | u64 words = 0U; | |
579 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
580 | pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; | |
581 | ||
582 | if (dd && dd->pport) { | |
583 | words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); | |
584 | if (words == ~0ULL) | |
585 | ret = PCI_ERS_RESULT_NEED_RESET; | |
586 | dd_dev_info(dd, | |
587 | "HFI1 mmio_enabled function called, read wordscntr %Lx, returning %d\n", | |
588 | words, ret); | |
589 | } | |
590 | return ret; | |
591 | } | |
592 | ||
593 | static pci_ers_result_t | |
594 | pci_slot_reset(struct pci_dev *pdev) | |
595 | { | |
596 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
597 | ||
598 | dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); | |
599 | return PCI_ERS_RESULT_CAN_RECOVER; | |
600 | } | |
601 | ||
602 | static pci_ers_result_t | |
603 | pci_link_reset(struct pci_dev *pdev) | |
604 | { | |
605 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
606 | ||
607 | dd_dev_info(dd, "HFI1 link_reset function called, ignored\n"); | |
608 | return PCI_ERS_RESULT_CAN_RECOVER; | |
609 | } | |
610 | ||
611 | static void | |
612 | pci_resume(struct pci_dev *pdev) | |
613 | { | |
614 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
615 | ||
616 | dd_dev_info(dd, "HFI1 resume function called\n"); | |
617 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
618 | /* | |
619 | * Running jobs will fail, since it's asynchronous | |
620 | * unlike sysfs-requested reset. Better than | |
621 | * doing nothing. | |
622 | */ | |
623 | hfi1_init(dd, 1); /* same as re-init after reset */ | |
624 | } | |
625 | ||
626 | const struct pci_error_handlers hfi1_pci_err_handler = { | |
627 | .error_detected = pci_error_detected, | |
628 | .mmio_enabled = pci_mmio_enabled, | |
629 | .link_reset = pci_link_reset, | |
630 | .slot_reset = pci_slot_reset, | |
631 | .resume = pci_resume, | |
632 | }; | |
633 | ||
634 | /*============================================================================*/ | |
635 | /* PCIe Gen3 support */ | |
636 | ||
637 | /* | |
638 | * This code is separated out because it is expected to be removed in the | |
639 | * final shipping product. If not, then it will be revisited and items | |
640 | * will be moved to more standard locations. | |
641 | */ | |
642 | ||
643 | /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ | |
644 | #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ | |
645 | #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ | |
646 | #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ | |
647 | ||
648 | /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ | |
649 | #define DL_ERR_NONE 0x0 /* no error */ | |
650 | #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ | |
651 | /* or response data */ | |
652 | #define DL_ERR_DISABLED 0x2 /* hfi disabled */ | |
653 | #define DL_ERR_SECURITY 0x3 /* security check failed */ | |
654 | #define DL_ERR_SBUS 0x4 /* SBus status error */ | |
655 | #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ | |
656 | ||
657 | /* gasket block secondary bus reset delay */ | |
658 | #define SBR_DELAY_US 200000 /* 200ms */ | |
659 | ||
660 | /* mask for PCIe capability register lnkctl2 target link speed */ | |
661 | #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf | |
662 | ||
663 | static uint pcie_target = 3; | |
664 | module_param(pcie_target, uint, S_IRUGO); | |
665 | MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); | |
666 | ||
667 | static uint pcie_force; | |
668 | module_param(pcie_force, uint, S_IRUGO); | |
669 | MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); | |
670 | ||
671 | static uint pcie_retry = 5; | |
672 | module_param(pcie_retry, uint, S_IRUGO); | |
673 | MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); | |
674 | ||
675 | #define UNSET_PSET 255 | |
676 | #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ | |
677 | #define DEFAULT_MCP_PSET 4 /* MCP HFI */ | |
678 | static uint pcie_pset = UNSET_PSET; | |
679 | module_param(pcie_pset, uint, S_IRUGO); | |
680 | MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); | |
681 | ||
c3f8de0b DL |
682 | static uint pcie_ctle = 1; /* discrete on, integrated off */ |
683 | module_param(pcie_ctle, uint, S_IRUGO); | |
684 | MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); | |
685 | ||
77241056 MM |
686 | /* equalization columns */ |
687 | #define PREC 0 | |
688 | #define ATTN 1 | |
689 | #define POST 2 | |
690 | ||
691 | /* discrete silicon preliminary equalization values */ | |
692 | static const u8 discrete_preliminary_eq[11][3] = { | |
693 | /* prec attn post */ | |
694 | { 0x00, 0x00, 0x12 }, /* p0 */ | |
695 | { 0x00, 0x00, 0x0c }, /* p1 */ | |
696 | { 0x00, 0x00, 0x0f }, /* p2 */ | |
697 | { 0x00, 0x00, 0x09 }, /* p3 */ | |
698 | { 0x00, 0x00, 0x00 }, /* p4 */ | |
699 | { 0x06, 0x00, 0x00 }, /* p5 */ | |
700 | { 0x09, 0x00, 0x00 }, /* p6 */ | |
701 | { 0x06, 0x00, 0x0f }, /* p7 */ | |
702 | { 0x09, 0x00, 0x09 }, /* p8 */ | |
703 | { 0x0c, 0x00, 0x00 }, /* p9 */ | |
704 | { 0x00, 0x00, 0x18 }, /* p10 */ | |
705 | }; | |
706 | ||
707 | /* integrated silicon preliminary equalization values */ | |
708 | static const u8 integrated_preliminary_eq[11][3] = { | |
709 | /* prec attn post */ | |
710 | { 0x00, 0x1e, 0x07 }, /* p0 */ | |
711 | { 0x00, 0x1e, 0x05 }, /* p1 */ | |
712 | { 0x00, 0x1e, 0x06 }, /* p2 */ | |
713 | { 0x00, 0x1e, 0x04 }, /* p3 */ | |
714 | { 0x00, 0x1e, 0x00 }, /* p4 */ | |
715 | { 0x03, 0x1e, 0x00 }, /* p5 */ | |
716 | { 0x04, 0x1e, 0x00 }, /* p6 */ | |
717 | { 0x03, 0x1e, 0x06 }, /* p7 */ | |
718 | { 0x03, 0x1e, 0x04 }, /* p8 */ | |
719 | { 0x05, 0x1e, 0x00 }, /* p9 */ | |
720 | { 0x00, 0x1e, 0x0a }, /* p10 */ | |
721 | }; | |
722 | ||
c3f8de0b DL |
723 | static const u8 discrete_ctle_tunings[11][4] = { |
724 | /* DC LF HF BW */ | |
725 | { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ | |
726 | { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ | |
727 | { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ | |
728 | { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ | |
729 | { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ | |
730 | { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ | |
731 | { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ | |
732 | { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ | |
733 | { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ | |
734 | { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ | |
735 | { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ | |
736 | }; | |
737 | ||
738 | static const u8 integrated_ctle_tunings[11][4] = { | |
739 | /* DC LF HF BW */ | |
740 | { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ | |
741 | { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ | |
742 | { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ | |
743 | { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ | |
744 | { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ | |
745 | { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ | |
746 | { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ | |
747 | { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ | |
748 | { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ | |
749 | { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ | |
750 | { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ | |
751 | }; | |
752 | ||
77241056 MM |
753 | /* helper to format the value to write to hardware */ |
754 | #define eq_value(pre, curr, post) \ | |
755 | ((((u32)(pre)) << \ | |
756 | PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ | |
757 | | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ | |
758 | | (((u32)(post)) << \ | |
759 | PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) | |
760 | ||
761 | /* | |
762 | * Load the given EQ preset table into the PCIe hardware. | |
763 | */ | |
764 | static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, | |
765 | u8 div) | |
766 | { | |
767 | struct pci_dev *pdev = dd->pcidev; | |
768 | u32 hit_error = 0; | |
769 | u32 violation; | |
770 | u32 i; | |
771 | u8 c_minus1, c0, c_plus1; | |
772 | ||
773 | for (i = 0; i < 11; i++) { | |
774 | /* set index */ | |
775 | pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); | |
776 | /* write the value */ | |
777 | c_minus1 = eq[i][PREC] / div; | |
778 | c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); | |
779 | c_plus1 = eq[i][POST] / div; | |
780 | pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, | |
17fb4f29 | 781 | eq_value(c_minus1, c0, c_plus1)); |
77241056 MM |
782 | /* check if these coefficients violate EQ rules */ |
783 | pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL105, | |
17fb4f29 | 784 | &violation); |
77241056 MM |
785 | if (violation |
786 | & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ | |
787 | if (hit_error == 0) { | |
788 | dd_dev_err(dd, | |
17fb4f29 | 789 | "Gen3 EQ Table Coefficient rule violations\n"); |
77241056 MM |
790 | dd_dev_err(dd, " prec attn post\n"); |
791 | } | |
792 | dd_dev_err(dd, " p%02d: %02x %02x %02x\n", | |
17fb4f29 JJ |
793 | i, (u32)eq[i][0], (u32)eq[i][1], |
794 | (u32)eq[i][2]); | |
77241056 | 795 | dd_dev_err(dd, " %02x %02x %02x\n", |
17fb4f29 | 796 | (u32)c_minus1, (u32)c0, (u32)c_plus1); |
77241056 MM |
797 | hit_error = 1; |
798 | } | |
799 | } | |
800 | if (hit_error) | |
801 | return -EINVAL; | |
802 | return 0; | |
803 | } | |
804 | ||
805 | /* | |
806 | * Steps to be done after the PCIe firmware is downloaded and | |
807 | * before the SBR for the Pcie Gen3. | |
576531fd | 808 | * The SBus resource is already being held. |
77241056 MM |
809 | */ |
810 | static void pcie_post_steps(struct hfi1_devdata *dd) | |
811 | { | |
812 | int i; | |
813 | ||
814 | set_sbus_fast_mode(dd); | |
815 | /* | |
816 | * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. | |
817 | * This avoids a spurious framing error that can otherwise be | |
818 | * generated by the MAC layer. | |
819 | * | |
820 | * Use individual addresses since no broadcast is set up. | |
821 | */ | |
822 | for (i = 0; i < NUM_PCIE_SERDES; i++) { | |
823 | sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], | |
824 | 0x03, WRITE_SBUS_RECEIVER, 0x00022132); | |
825 | } | |
826 | ||
827 | clear_sbus_fast_mode(dd); | |
828 | } | |
829 | ||
830 | /* | |
831 | * Trigger a secondary bus reset (SBR) on ourselves using our parent. | |
832 | * | |
833 | * Based on pci_parent_bus_reset() which is not exported by the | |
834 | * kernel core. | |
835 | */ | |
836 | static int trigger_sbr(struct hfi1_devdata *dd) | |
837 | { | |
838 | struct pci_dev *dev = dd->pcidev; | |
839 | struct pci_dev *pdev; | |
840 | ||
841 | /* need a parent */ | |
842 | if (!dev->bus->self) { | |
843 | dd_dev_err(dd, "%s: no parent device\n", __func__); | |
844 | return -ENOTTY; | |
845 | } | |
846 | ||
847 | /* should not be anyone else on the bus */ | |
848 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
849 | if (pdev != dev) { | |
850 | dd_dev_err(dd, | |
17fb4f29 JJ |
851 | "%s: another device is on the same bus\n", |
852 | __func__); | |
77241056 MM |
853 | return -ENOTTY; |
854 | } | |
855 | ||
856 | /* | |
857 | * A secondary bus reset (SBR) issues a hot reset to our device. | |
858 | * The following routine does a 1s wait after the reset is dropped | |
859 | * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - | |
860 | * Conventional Reset, paragraph 3, line 35 also says that a 1s | |
861 | * delay after a reset is required. Per spec requirements, | |
862 | * the link is either working or not after that point. | |
863 | */ | |
864 | pci_reset_bridge_secondary_bus(dev->bus->self); | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
869 | /* | |
870 | * Write the given gasket interrupt register. | |
871 | */ | |
872 | static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, | |
873 | u16 code, u16 data) | |
874 | { | |
875 | write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), | |
17fb4f29 JJ |
876 | (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | |
877 | ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); | |
77241056 MM |
878 | } |
879 | ||
880 | /* | |
881 | * Tell the gasket logic how to react to the reset. | |
882 | */ | |
883 | static void arm_gasket_logic(struct hfi1_devdata *dd) | |
884 | { | |
885 | u64 reg; | |
886 | ||
17fb4f29 JJ |
887 | reg = (((u64)1 << dd->hfi1_id) << |
888 | ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | | |
889 | ((u64)pcie_serdes_broadcast[dd->hfi1_id] << | |
890 | ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | | |
891 | ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | | |
892 | ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << | |
893 | ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); | |
77241056 MM |
894 | write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); |
895 | /* read back to push the write */ | |
896 | read_csr(dd, ASIC_PCIE_SD_HOST_CMD); | |
897 | } | |
898 | ||
14d88ec5 DL |
899 | /* |
900 | * CCE_PCIE_CTRL long name helpers | |
901 | * We redefine these shorter macros to use in the code while leaving | |
902 | * chip_registers.h to be autogenerated from the hardware spec. | |
903 | */ | |
904 | #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK | |
905 | #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT | |
906 | #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK | |
907 | #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT | |
908 | #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT | |
909 | #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT | |
910 | #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK | |
911 | #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT | |
912 | #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK | |
913 | #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT | |
914 | ||
915 | /* | |
916 | * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). | |
917 | */ | |
918 | static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) | |
919 | { | |
920 | u64 pcie_ctrl; | |
921 | u64 xmt_margin; | |
922 | u64 xmt_margin_oe; | |
923 | u64 lane_delay; | |
924 | u64 lane_bundle; | |
925 | ||
926 | pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); | |
927 | ||
928 | /* | |
929 | * For Discrete, use full-swing. | |
930 | * - PCIe TX defaults to full-swing. | |
931 | * Leave this register as default. | |
932 | * For Integrated, use half-swing | |
933 | * - Copy xmt_margin and xmt_margin_oe | |
934 | * from Gen1/Gen2 to Gen3. | |
935 | */ | |
936 | if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ | |
937 | /* extract initial fields */ | |
938 | xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) | |
939 | & MARGIN_GEN1_GEN2_MASK; | |
940 | xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) | |
941 | & MARGIN_G1_G2_OVERWRITE_MASK; | |
942 | lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; | |
943 | lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) | |
944 | & LANE_BUNDLE_MASK; | |
945 | ||
946 | /* | |
947 | * For A0, EFUSE values are not set. Override with the | |
948 | * correct values. | |
949 | */ | |
950 | if (is_ax(dd)) { | |
951 | /* | |
952 | * xmt_margin and OverwiteEnabel should be the | |
953 | * same for Gen1/Gen2 and Gen3 | |
954 | */ | |
955 | xmt_margin = 0x5; | |
956 | xmt_margin_oe = 0x1; | |
957 | lane_delay = 0xF; /* Delay 240ns. */ | |
958 | lane_bundle = 0x0; /* Set to 1 lane. */ | |
959 | } | |
960 | ||
961 | /* overwrite existing values */ | |
962 | pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) | |
963 | | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) | |
964 | | (xmt_margin << MARGIN_SHIFT) | |
965 | | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) | |
966 | | (lane_delay << LANE_DELAY_SHIFT) | |
967 | | (lane_bundle << LANE_BUNDLE_SHIFT); | |
968 | ||
969 | write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); | |
970 | } | |
971 | ||
972 | dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", | |
973 | fname, pcie_ctrl); | |
974 | } | |
975 | ||
77241056 MM |
976 | /* |
977 | * Do all the steps needed to transition the PCIe link to Gen3 speed. | |
978 | */ | |
979 | int do_pcie_gen3_transition(struct hfi1_devdata *dd) | |
980 | { | |
bf400235 | 981 | struct pci_dev *parent = dd->pcidev->bus->self; |
77241056 MM |
982 | u64 fw_ctrl; |
983 | u64 reg, therm; | |
984 | u32 reg32, fs, lf; | |
985 | u32 status, err; | |
986 | int ret; | |
987 | int do_retry, retry_count = 0; | |
c3f8de0b | 988 | int intnum = 0; |
77241056 MM |
989 | uint default_pset; |
990 | u16 target_vector, target_speed; | |
affa48de | 991 | u16 lnkctl2, vendor; |
77241056 MM |
992 | u8 div; |
993 | const u8 (*eq)[3]; | |
c3f8de0b DL |
994 | const u8 (*ctle_tunings)[4]; |
995 | uint static_ctle_mode; | |
77241056 MM |
996 | int return_error = 0; |
997 | ||
998 | /* PCIe Gen3 is for the ASIC only */ | |
999 | if (dd->icode != ICODE_RTL_SILICON) | |
1000 | return 0; | |
1001 | ||
1002 | if (pcie_target == 1) { /* target Gen1 */ | |
1003 | target_vector = GEN1_SPEED_VECTOR; | |
1004 | target_speed = 2500; | |
1005 | } else if (pcie_target == 2) { /* target Gen2 */ | |
1006 | target_vector = GEN2_SPEED_VECTOR; | |
1007 | target_speed = 5000; | |
1008 | } else if (pcie_target == 3) { /* target Gen3 */ | |
1009 | target_vector = GEN3_SPEED_VECTOR; | |
1010 | target_speed = 8000; | |
1011 | } else { | |
1012 | /* off or invalid target - skip */ | |
1013 | dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); | |
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | /* if already at target speed, done (unless forced) */ | |
1018 | if (dd->lbus_speed == target_speed) { | |
1019 | dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, | |
17fb4f29 JJ |
1020 | pcie_target, |
1021 | pcie_force ? "re-doing anyway" : "skipping"); | |
77241056 MM |
1022 | if (!pcie_force) |
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | /* | |
bf400235 KW |
1027 | * The driver cannot do the transition if it has no access to the |
1028 | * upstream component | |
77241056 | 1029 | */ |
bf400235 KW |
1030 | if (!parent) { |
1031 | dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", | |
1032 | __func__); | |
1033 | return 0; | |
1034 | } | |
77241056 MM |
1035 | |
1036 | /* | |
1037 | * Do the Gen3 transition. Steps are those of the PCIe Gen3 | |
1038 | * recipe. | |
1039 | */ | |
1040 | ||
1041 | /* step 1: pcie link working in gen1/gen2 */ | |
1042 | ||
1043 | /* step 2: if either side is not capable of Gen3, done */ | |
1044 | if (pcie_target == 3 && !dd->link_gen3_capable) { | |
1045 | dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); | |
1046 | ret = -ENOSYS; | |
1047 | goto done_no_mutex; | |
1048 | } | |
1049 | ||
576531fd DL |
1050 | /* hold the SBus resource across the firmware download and SBR */ |
1051 | ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); | |
1052 | if (ret) { | |
1053 | dd_dev_err(dd, "%s: unable to acquire SBus resource\n", | |
1054 | __func__); | |
77241056 | 1055 | return ret; |
576531fd | 1056 | } |
77241056 MM |
1057 | |
1058 | /* make sure thermal polling is not causing interrupts */ | |
1059 | therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); | |
1060 | if (therm) { | |
1061 | write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); | |
1062 | msleep(100); | |
1063 | dd_dev_info(dd, "%s: Disabled therm polling\n", | |
1064 | __func__); | |
1065 | } | |
1066 | ||
c91b4a12 | 1067 | retry: |
65fcf557 | 1068 | /* the SBus download will reset the spico for thermal */ |
c91b4a12 | 1069 | |
77241056 MM |
1070 | /* step 3: download SBus Master firmware */ |
1071 | /* step 4: download PCIe Gen3 SerDes firmware */ | |
77241056 MM |
1072 | dd_dev_info(dd, "%s: downloading firmware\n", __func__); |
1073 | ret = load_pcie_firmware(dd); | |
6b14e0ea DL |
1074 | if (ret) { |
1075 | /* do not proceed if the firmware cannot be downloaded */ | |
1076 | return_error = 1; | |
77241056 | 1077 | goto done; |
6b14e0ea | 1078 | } |
77241056 MM |
1079 | |
1080 | /* step 5: set up device parameter settings */ | |
1081 | dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); | |
1082 | ||
1083 | /* | |
1084 | * PcieCfgSpcie1 - Link Control 3 | |
1085 | * Leave at reset value. No need to set PerfEq - link equalization | |
1086 | * will be performed automatically after the SBR when the target | |
1087 | * speed is 8GT/s. | |
1088 | */ | |
1089 | ||
1090 | /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ | |
1091 | pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); | |
1092 | ||
1093 | /* step 5a: Set Synopsys Port Logic registers */ | |
1094 | ||
1095 | /* | |
1096 | * PcieCfgRegPl2 - Port Force Link | |
1097 | * | |
1098 | * Set the low power field to 0x10 to avoid unnecessary power | |
1099 | * management messages. All other fields are zero. | |
1100 | */ | |
1101 | reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; | |
1102 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); | |
1103 | ||
1104 | /* | |
1105 | * PcieCfgRegPl100 - Gen3 Control | |
1106 | * | |
1107 | * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl | |
80e4898e | 1108 | * turn on PcieCfgRegPl100.EqEieosCnt |
77241056 MM |
1109 | * Everything else zero. |
1110 | */ | |
1111 | reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; | |
1112 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); | |
1113 | ||
1114 | /* | |
1115 | * PcieCfgRegPl101 - Gen3 EQ FS and LF | |
1116 | * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping | |
1117 | * PcieCfgRegPl103 - Gen3 EQ Preset Index | |
1118 | * PcieCfgRegPl105 - Gen3 EQ Status | |
1119 | * | |
1120 | * Give initial EQ settings. | |
1121 | */ | |
1122 | if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ | |
1123 | /* 1000mV, FS=24, LF = 8 */ | |
1124 | fs = 24; | |
1125 | lf = 8; | |
1126 | div = 3; | |
1127 | eq = discrete_preliminary_eq; | |
1128 | default_pset = DEFAULT_DISCRETE_PSET; | |
c3f8de0b DL |
1129 | ctle_tunings = discrete_ctle_tunings; |
1130 | /* bit 0 - discrete on/off */ | |
1131 | static_ctle_mode = pcie_ctle & 0x1; | |
77241056 MM |
1132 | } else { |
1133 | /* 400mV, FS=29, LF = 9 */ | |
1134 | fs = 29; | |
1135 | lf = 9; | |
1136 | div = 1; | |
1137 | eq = integrated_preliminary_eq; | |
1138 | default_pset = DEFAULT_MCP_PSET; | |
c3f8de0b DL |
1139 | ctle_tunings = integrated_ctle_tunings; |
1140 | /* bit 1 - integrated on/off */ | |
1141 | static_ctle_mode = (pcie_ctle >> 1) & 0x1; | |
77241056 MM |
1142 | } |
1143 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, | |
17fb4f29 JJ |
1144 | (fs << |
1145 | PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | | |
1146 | (lf << | |
1147 | PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); | |
77241056 MM |
1148 | ret = load_eq_table(dd, eq, fs, div); |
1149 | if (ret) | |
1150 | goto done; | |
1151 | ||
1152 | /* | |
1153 | * PcieCfgRegPl106 - Gen3 EQ Control | |
1154 | * | |
1155 | * Set Gen3EqPsetReqVec, leave other fields 0. | |
1156 | */ | |
1157 | if (pcie_pset == UNSET_PSET) | |
1158 | pcie_pset = default_pset; | |
1159 | if (pcie_pset > 10) { /* valid range is 0-10, inclusive */ | |
1160 | dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", | |
17fb4f29 | 1161 | __func__, pcie_pset, default_pset); |
77241056 MM |
1162 | pcie_pset = default_pset; |
1163 | } | |
1164 | dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset); | |
1165 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, | |
17fb4f29 JJ |
1166 | ((1 << pcie_pset) << |
1167 | PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | | |
1168 | PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | | |
1169 | PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); | |
77241056 MM |
1170 | |
1171 | /* | |
1172 | * step 5b: Do post firmware download steps via SBus | |
1173 | */ | |
1174 | dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); | |
1175 | pcie_post_steps(dd); | |
1176 | ||
1177 | /* | |
1178 | * step 5c: Program gasket interrupts | |
1179 | */ | |
1180 | /* set the Rx Bit Rate to REFCLK ratio */ | |
c3f8de0b | 1181 | write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); |
77241056 | 1182 | /* disable pCal for PCIe Gen3 RX equalization */ |
c3f8de0b DL |
1183 | /* select adaptive or static CTLE */ |
1184 | write_gasket_interrupt(dd, intnum++, 0x0026, | |
1185 | 0x5b01 | (static_ctle_mode << 3)); | |
77241056 MM |
1186 | /* |
1187 | * Enable iCal for PCIe Gen3 RX equalization, and set which | |
1188 | * evaluation of RX_EQ_EVAL will launch the iCal procedure. | |
1189 | */ | |
c3f8de0b DL |
1190 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); |
1191 | ||
1192 | if (static_ctle_mode) { | |
1193 | /* apply static CTLE tunings */ | |
1194 | u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; | |
1195 | ||
1196 | pcie_dc = ctle_tunings[pcie_pset][0]; | |
1197 | pcie_lf = ctle_tunings[pcie_pset][1]; | |
1198 | pcie_hf = ctle_tunings[pcie_pset][2]; | |
1199 | pcie_bw = ctle_tunings[pcie_pset][3]; | |
1200 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); | |
1201 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); | |
1202 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); | |
1203 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); | |
1204 | } | |
1205 | ||
77241056 | 1206 | /* terminate list */ |
c3f8de0b | 1207 | write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); |
77241056 MM |
1208 | |
1209 | /* | |
1210 | * step 5d: program XMT margin | |
77241056 | 1211 | */ |
14d88ec5 | 1212 | write_xmt_margin(dd, __func__); |
77241056 | 1213 | |
affa48de AD |
1214 | /* |
1215 | * step 5e: disable active state power management (ASPM). It | |
1216 | * will be enabled if required later | |
1217 | */ | |
77241056 | 1218 | dd_dev_info(dd, "%s: clearing ASPM\n", __func__); |
affa48de | 1219 | aspm_hw_disable_l1(dd); |
77241056 MM |
1220 | |
1221 | /* | |
1222 | * step 5f: clear DirectSpeedChange | |
1223 | * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the | |
1224 | * change in the speed target from starting before we are ready. | |
1225 | * This field defaults to 0 and we are not changing it, so nothing | |
1226 | * needs to be done. | |
1227 | */ | |
1228 | ||
1229 | /* step 5g: Set target link speed */ | |
1230 | /* | |
1231 | * Set target link speed to be target on both device and parent. | |
1232 | * On setting the parent: Some system BIOSs "helpfully" set the | |
1233 | * parent target speed to Gen2 to match the ASIC's initial speed. | |
1234 | * We can set the target Gen3 because we have already checked | |
1235 | * that it is Gen3 capable earlier. | |
1236 | */ | |
1237 | dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); | |
77241056 MM |
1238 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); |
1239 | dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, | |
17fb4f29 | 1240 | (u32)lnkctl2); |
77241056 MM |
1241 | /* only write to parent if target is not as high as ours */ |
1242 | if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) { | |
1243 | lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; | |
1244 | lnkctl2 |= target_vector; | |
1245 | dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, | |
17fb4f29 | 1246 | (u32)lnkctl2); |
77241056 MM |
1247 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL2, lnkctl2); |
1248 | } else { | |
1249 | dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); | |
1250 | } | |
1251 | ||
1252 | dd_dev_info(dd, "%s: setting target link speed\n", __func__); | |
1253 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); | |
1254 | dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, | |
17fb4f29 | 1255 | (u32)lnkctl2); |
77241056 MM |
1256 | lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; |
1257 | lnkctl2 |= target_vector; | |
1258 | dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, | |
17fb4f29 | 1259 | (u32)lnkctl2); |
77241056 MM |
1260 | pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); |
1261 | ||
1262 | /* step 5h: arm gasket logic */ | |
1263 | /* hold DC in reset across the SBR */ | |
1264 | write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); | |
50e5dcbe | 1265 | (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ |
77241056 MM |
1266 | /* save firmware control across the SBR */ |
1267 | fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); | |
1268 | ||
1269 | dd_dev_info(dd, "%s: arming gasket logic\n", __func__); | |
1270 | arm_gasket_logic(dd); | |
1271 | ||
1272 | /* | |
1273 | * step 6: quiesce PCIe link | |
1274 | * The chip has already been reset, so there will be no traffic | |
1275 | * from the chip. Linux has no easy way to enforce that it will | |
1276 | * not try to access the device, so we just need to hope it doesn't | |
1277 | * do it while we are doing the reset. | |
1278 | */ | |
1279 | ||
1280 | /* | |
1281 | * step 7: initiate the secondary bus reset (SBR) | |
1282 | * step 8: hardware brings the links back up | |
1283 | * step 9: wait for link speed transition to be complete | |
1284 | */ | |
1285 | dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); | |
1286 | ret = trigger_sbr(dd); | |
1287 | if (ret) | |
1288 | goto done; | |
1289 | ||
1290 | /* step 10: decide what to do next */ | |
1291 | ||
1292 | /* check if we can read PCI space */ | |
1293 | ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); | |
1294 | if (ret) { | |
1295 | dd_dev_info(dd, | |
17fb4f29 JJ |
1296 | "%s: read of VendorID failed after SBR, err %d\n", |
1297 | __func__, ret); | |
77241056 MM |
1298 | return_error = 1; |
1299 | goto done; | |
1300 | } | |
1301 | if (vendor == 0xffff) { | |
1302 | dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); | |
1303 | return_error = 1; | |
1304 | ret = -EIO; | |
1305 | goto done; | |
1306 | } | |
1307 | ||
1308 | /* restore PCI space registers we know were reset */ | |
1309 | dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); | |
1310 | restore_pci_variables(dd); | |
1311 | /* restore firmware control */ | |
1312 | write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); | |
1313 | ||
1314 | /* | |
1315 | * Check the gasket block status. | |
1316 | * | |
1317 | * This is the first CSR read after the SBR. If the read returns | |
1318 | * all 1s (fails), the link did not make it back. | |
1319 | * | |
1320 | * Once we're sure we can read and write, clear the DC reset after | |
1321 | * the SBR. Then check for any per-lane errors. Then look over | |
1322 | * the status. | |
1323 | */ | |
1324 | reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); | |
1325 | dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); | |
1326 | if (reg == ~0ull) { /* PCIe read failed/timeout */ | |
1327 | dd_dev_err(dd, "SBR failed - unable to read from device\n"); | |
1328 | return_error = 1; | |
1329 | ret = -ENOSYS; | |
1330 | goto done; | |
1331 | } | |
1332 | ||
1333 | /* clear the DC reset */ | |
1334 | write_csr(dd, CCE_DC_CTRL, 0); | |
abfc4459 | 1335 | |
77241056 | 1336 | /* Set the LED off */ |
773d0451 | 1337 | setextled(dd, 0); |
77241056 MM |
1338 | |
1339 | /* check for any per-lane errors */ | |
1340 | pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); | |
1341 | dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); | |
1342 | ||
1343 | /* extract status, look for our HFI */ | |
1344 | status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) | |
1345 | & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; | |
1346 | if ((status & (1 << dd->hfi1_id)) == 0) { | |
1347 | dd_dev_err(dd, | |
17fb4f29 JJ |
1348 | "%s: gasket status 0x%x, expecting 0x%x\n", |
1349 | __func__, status, 1 << dd->hfi1_id); | |
77241056 MM |
1350 | ret = -EIO; |
1351 | goto done; | |
1352 | } | |
1353 | ||
1354 | /* extract error */ | |
1355 | err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) | |
1356 | & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; | |
1357 | if (err) { | |
1358 | dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); | |
1359 | ret = -EIO; | |
1360 | goto done; | |
1361 | } | |
1362 | ||
1363 | /* update our link information cache */ | |
1364 | update_lbus_info(dd); | |
1365 | dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, | |
17fb4f29 | 1366 | dd->lbus_info); |
77241056 MM |
1367 | |
1368 | if (dd->lbus_speed != target_speed) { /* not target */ | |
1369 | /* maybe retry */ | |
1370 | do_retry = retry_count < pcie_retry; | |
1371 | dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", | |
17fb4f29 | 1372 | pcie_target, do_retry ? ", retrying" : ""); |
77241056 MM |
1373 | retry_count++; |
1374 | if (do_retry) { | |
1375 | msleep(100); /* allow time to settle */ | |
1376 | goto retry; | |
1377 | } | |
1378 | ret = -EIO; | |
1379 | } | |
1380 | ||
1381 | done: | |
1382 | if (therm) { | |
1383 | write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); | |
1384 | msleep(100); | |
1385 | dd_dev_info(dd, "%s: Re-enable therm polling\n", | |
1386 | __func__); | |
1387 | } | |
576531fd | 1388 | release_chip_resource(dd, CR_SBUS); |
77241056 MM |
1389 | done_no_mutex: |
1390 | /* return no error if it is OK to be at current speed */ | |
1391 | if (ret && !return_error) { | |
1392 | dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); | |
1393 | ret = 0; | |
1394 | } | |
1395 | ||
1396 | dd_dev_info(dd, "%s: done\n", __func__); | |
1397 | return ret; | |
1398 | } |