Commit | Line | Data |
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7bb206e3 | 1 | /* |
759d5768 | 2 | * Copyright (c) 2006 QLogic, Inc. All rights reserved. |
7bb206e3 BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/spinlock.h> | |
35 | #include <linux/idr.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/vmalloc.h> | |
40 | ||
41 | #include "ipath_kernel.h" | |
b1c1b6a3 | 42 | #include "ipath_verbs.h" |
27b678dd | 43 | #include "ipath_common.h" |
7bb206e3 BS |
44 | |
45 | static void ipath_update_pio_bufs(struct ipath_devdata *); | |
46 | ||
47 | const char *ipath_get_unit_name(int unit) | |
48 | { | |
49 | static char iname[16]; | |
50 | snprintf(iname, sizeof iname, "infinipath%u", unit); | |
51 | return iname; | |
52 | } | |
53 | ||
759d5768 | 54 | #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: " |
7bb206e3 BS |
55 | #define PFX IPATH_DRV_NAME ": " |
56 | ||
57 | /* | |
58 | * The size has to be longer than this string, so we can append | |
59 | * board/chip information to it in the init code. | |
60 | */ | |
b55f4f06 | 61 | const char ib_ipath_version[] = IPATH_IDSTR "\n"; |
7bb206e3 BS |
62 | |
63 | static struct idr unit_table; | |
64 | DEFINE_SPINLOCK(ipath_devs_lock); | |
65 | LIST_HEAD(ipath_dev_list); | |
66 | ||
0fd41363 | 67 | wait_queue_head_t ipath_state_wait; |
7bb206e3 BS |
68 | |
69 | unsigned ipath_debug = __IPATH_INFO; | |
70 | ||
71 | module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO); | |
72 | MODULE_PARM_DESC(debug, "mask for debug prints"); | |
73 | EXPORT_SYMBOL_GPL(ipath_debug); | |
74 | ||
75 | MODULE_LICENSE("GPL"); | |
759d5768 BS |
76 | MODULE_AUTHOR("QLogic <support@pathscale.com>"); |
77 | MODULE_DESCRIPTION("QLogic InfiniPath driver"); | |
7bb206e3 BS |
78 | |
79 | const char *ipath_ibcstatus_str[] = { | |
80 | "Disabled", | |
81 | "LinkUp", | |
82 | "PollActive", | |
83 | "PollQuiet", | |
84 | "SleepDelay", | |
85 | "SleepQuiet", | |
86 | "LState6", /* unused */ | |
87 | "LState7", /* unused */ | |
88 | "CfgDebounce", | |
89 | "CfgRcvfCfg", | |
90 | "CfgWaitRmt", | |
91 | "CfgIdle", | |
92 | "RecovRetrain", | |
93 | "LState0xD", /* unused */ | |
94 | "RecovWaitRmt", | |
95 | "RecovIdle", | |
96 | }; | |
97 | ||
7bb206e3 BS |
98 | static void __devexit ipath_remove_one(struct pci_dev *); |
99 | static int __devinit ipath_init_one(struct pci_dev *, | |
100 | const struct pci_device_id *); | |
101 | ||
102 | /* Only needed for registration, nothing else needs this info */ | |
103 | #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 | |
104 | #define PCI_DEVICE_ID_INFINIPATH_HT 0xd | |
105 | #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10 | |
106 | ||
107 | static const struct pci_device_id ipath_pci_tbl[] = { | |
6f4bb3d8 RD |
108 | { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) }, |
109 | { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) }, | |
110 | { 0, } | |
7bb206e3 BS |
111 | }; |
112 | ||
113 | MODULE_DEVICE_TABLE(pci, ipath_pci_tbl); | |
114 | ||
115 | static struct pci_driver ipath_driver = { | |
116 | .name = IPATH_DRV_NAME, | |
117 | .probe = ipath_init_one, | |
118 | .remove = __devexit_p(ipath_remove_one), | |
119 | .id_table = ipath_pci_tbl, | |
120 | }; | |
121 | ||
7bb206e3 BS |
122 | |
123 | static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev, | |
124 | u32 *bar0, u32 *bar1) | |
125 | { | |
126 | int ret; | |
127 | ||
128 | ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); | |
129 | if (ret) | |
130 | ipath_dev_err(dd, "failed to read bar0 before enable: " | |
131 | "error %d\n", -ret); | |
132 | ||
133 | ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1); | |
134 | if (ret) | |
135 | ipath_dev_err(dd, "failed to read bar1 before enable: " | |
136 | "error %d\n", -ret); | |
137 | ||
138 | ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1); | |
139 | } | |
140 | ||
141 | static void ipath_free_devdata(struct pci_dev *pdev, | |
142 | struct ipath_devdata *dd) | |
143 | { | |
144 | unsigned long flags; | |
145 | ||
146 | pci_set_drvdata(pdev, NULL); | |
147 | ||
148 | if (dd->ipath_unit != -1) { | |
149 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
150 | idr_remove(&unit_table, dd->ipath_unit); | |
151 | list_del(&dd->ipath_list); | |
152 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
153 | } | |
06993ca6 | 154 | vfree(dd); |
7bb206e3 BS |
155 | } |
156 | ||
157 | static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev) | |
158 | { | |
159 | unsigned long flags; | |
160 | struct ipath_devdata *dd; | |
7bb206e3 BS |
161 | int ret; |
162 | ||
163 | if (!idr_pre_get(&unit_table, GFP_KERNEL)) { | |
164 | dd = ERR_PTR(-ENOMEM); | |
165 | goto bail; | |
166 | } | |
167 | ||
06993ca6 | 168 | dd = vmalloc(sizeof(*dd)); |
7bb206e3 BS |
169 | if (!dd) { |
170 | dd = ERR_PTR(-ENOMEM); | |
171 | goto bail; | |
172 | } | |
06993ca6 | 173 | memset(dd, 0, sizeof(*dd)); |
7bb206e3 BS |
174 | dd->ipath_unit = -1; |
175 | ||
176 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
177 | ||
178 | ret = idr_get_new(&unit_table, dd, &dd->ipath_unit); | |
179 | if (ret < 0) { | |
180 | printk(KERN_ERR IPATH_DRV_NAME | |
181 | ": Could not allocate unit ID: error %d\n", -ret); | |
182 | ipath_free_devdata(pdev, dd); | |
183 | dd = ERR_PTR(ret); | |
184 | goto bail_unlock; | |
185 | } | |
186 | ||
187 | dd->pcidev = pdev; | |
188 | pci_set_drvdata(pdev, dd); | |
189 | ||
190 | list_add(&dd->ipath_list, &ipath_dev_list); | |
191 | ||
192 | bail_unlock: | |
193 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
194 | ||
195 | bail: | |
196 | return dd; | |
197 | } | |
198 | ||
199 | static inline struct ipath_devdata *__ipath_lookup(int unit) | |
200 | { | |
201 | return idr_find(&unit_table, unit); | |
202 | } | |
203 | ||
204 | struct ipath_devdata *ipath_lookup(int unit) | |
205 | { | |
206 | struct ipath_devdata *dd; | |
207 | unsigned long flags; | |
208 | ||
209 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
210 | dd = __ipath_lookup(unit); | |
211 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
212 | ||
213 | return dd; | |
214 | } | |
215 | ||
216 | int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp) | |
217 | { | |
218 | int nunits, npresent, nup; | |
219 | struct ipath_devdata *dd; | |
220 | unsigned long flags; | |
221 | u32 maxports; | |
222 | ||
223 | nunits = npresent = nup = maxports = 0; | |
224 | ||
225 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
226 | ||
227 | list_for_each_entry(dd, &ipath_dev_list, ipath_list) { | |
228 | nunits++; | |
229 | if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase) | |
230 | npresent++; | |
231 | if (dd->ipath_lid && | |
232 | !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN | |
233 | | IPATH_LINKUNK))) | |
234 | nup++; | |
235 | if (dd->ipath_cfgports > maxports) | |
236 | maxports = dd->ipath_cfgports; | |
237 | } | |
238 | ||
239 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
240 | ||
241 | if (npresentp) | |
242 | *npresentp = npresent; | |
243 | if (nupp) | |
244 | *nupp = nup; | |
245 | if (maxportsp) | |
246 | *maxportsp = maxports; | |
247 | ||
248 | return nunits; | |
249 | } | |
250 | ||
7bb206e3 BS |
251 | /* |
252 | * These next two routines are placeholders in case we don't have per-arch | |
253 | * code for controlling write combining. If explicit control of write | |
254 | * combining is not available, performance will probably be awful. | |
255 | */ | |
256 | ||
257 | int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd) | |
258 | { | |
259 | return -EOPNOTSUPP; | |
260 | } | |
261 | ||
262 | void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd) | |
263 | { | |
264 | } | |
265 | ||
266 | static int __devinit ipath_init_one(struct pci_dev *pdev, | |
267 | const struct pci_device_id *ent) | |
268 | { | |
269 | int ret, len, j; | |
270 | struct ipath_devdata *dd; | |
271 | unsigned long long addr; | |
272 | u32 bar0 = 0, bar1 = 0; | |
273 | u8 rev; | |
274 | ||
7bb206e3 BS |
275 | dd = ipath_alloc_devdata(pdev); |
276 | if (IS_ERR(dd)) { | |
277 | ret = PTR_ERR(dd); | |
278 | printk(KERN_ERR IPATH_DRV_NAME | |
279 | ": Could not allocate devdata: error %d\n", -ret); | |
f37bda92 | 280 | goto bail; |
7bb206e3 BS |
281 | } |
282 | ||
283 | ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit); | |
284 | ||
285 | read_bars(dd, pdev, &bar0, &bar1); | |
286 | ||
287 | ret = pci_enable_device(pdev); | |
288 | if (ret) { | |
289 | /* This can happen iff: | |
290 | * | |
291 | * We did a chip reset, and then failed to reprogram the | |
292 | * BAR, or the chip reset due to an internal error. We then | |
293 | * unloaded the driver and reloaded it. | |
294 | * | |
295 | * Both reset cases set the BAR back to initial state. For | |
296 | * the latter case, the AER sticky error bit at offset 0x718 | |
297 | * should be set, but the Linux kernel doesn't yet know | |
298 | * about that, it appears. If the original BAR was retained | |
299 | * in the kernel data structures, this may be OK. | |
300 | */ | |
301 | ipath_dev_err(dd, "enable unit %d failed: error %d\n", | |
302 | dd->ipath_unit, -ret); | |
303 | goto bail_devdata; | |
304 | } | |
305 | addr = pci_resource_start(pdev, 0); | |
306 | len = pci_resource_len(pdev, 0); | |
51f65ebc | 307 | ipath_cdbg(VERBOSE, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x " |
7bb206e3 BS |
308 | "driver_data %lx\n", addr, len, pdev->irq, ent->vendor, |
309 | ent->device, ent->driver_data); | |
310 | ||
311 | read_bars(dd, pdev, &bar0, &bar1); | |
312 | ||
313 | if (!bar1 && !(bar0 & ~0xf)) { | |
314 | if (addr) { | |
315 | dev_info(&pdev->dev, "BAR is 0 (probable RESET), " | |
316 | "rewriting as %llx\n", addr); | |
317 | ret = pci_write_config_dword( | |
318 | pdev, PCI_BASE_ADDRESS_0, addr); | |
319 | if (ret) { | |
320 | ipath_dev_err(dd, "rewrite of BAR0 " | |
321 | "failed: err %d\n", -ret); | |
322 | goto bail_disable; | |
323 | } | |
324 | ret = pci_write_config_dword( | |
325 | pdev, PCI_BASE_ADDRESS_1, addr >> 32); | |
326 | if (ret) { | |
327 | ipath_dev_err(dd, "rewrite of BAR1 " | |
328 | "failed: err %d\n", -ret); | |
329 | goto bail_disable; | |
330 | } | |
331 | } else { | |
332 | ipath_dev_err(dd, "BAR is 0 (probable RESET), " | |
333 | "not usable until reboot\n"); | |
334 | ret = -ENODEV; | |
335 | goto bail_disable; | |
336 | } | |
337 | } | |
338 | ||
339 | ret = pci_request_regions(pdev, IPATH_DRV_NAME); | |
340 | if (ret) { | |
341 | dev_info(&pdev->dev, "pci_request_regions unit %u fails: " | |
342 | "err %d\n", dd->ipath_unit, -ret); | |
343 | goto bail_disable; | |
344 | } | |
345 | ||
346 | ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
347 | if (ret) { | |
68dd43a1 BS |
348 | /* |
349 | * if the 64 bit setup fails, try 32 bit. Some systems | |
350 | * do not setup 64 bit maps on systems with 2GB or less | |
351 | * memory installed. | |
352 | */ | |
353 | ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
354 | if (ret) { | |
b1d8865a BS |
355 | dev_info(&pdev->dev, |
356 | "Unable to set DMA mask for unit %u: %d\n", | |
357 | dd->ipath_unit, ret); | |
68dd43a1 BS |
358 | goto bail_regions; |
359 | } | |
b1d8865a | 360 | else { |
68dd43a1 | 361 | ipath_dbg("No 64bit DMA mask, used 32 bit mask\n"); |
b1d8865a BS |
362 | ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
363 | if (ret) | |
364 | dev_info(&pdev->dev, | |
365 | "Unable to set DMA consistent mask " | |
366 | "for unit %u: %d\n", | |
367 | dd->ipath_unit, ret); | |
368 | ||
369 | } | |
370 | } | |
371 | else { | |
372 | ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
373 | if (ret) | |
374 | dev_info(&pdev->dev, | |
375 | "Unable to set DMA consistent mask " | |
376 | "for unit %u: %d\n", | |
377 | dd->ipath_unit, ret); | |
7bb206e3 BS |
378 | } |
379 | ||
380 | pci_set_master(pdev); | |
381 | ||
382 | /* | |
383 | * Save BARs to rewrite after device reset. Save all 64 bits of | |
384 | * BAR, just in case. | |
385 | */ | |
386 | dd->ipath_pcibar0 = addr; | |
387 | dd->ipath_pcibar1 = addr >> 32; | |
388 | dd->ipath_deviceid = ent->device; /* save for later use */ | |
389 | dd->ipath_vendorid = ent->vendor; | |
390 | ||
391 | /* setup the chip-specific functions, as early as possible. */ | |
392 | switch (ent->device) { | |
e757bef2 | 393 | #ifdef CONFIG_HT_IRQ |
7bb206e3 | 394 | case PCI_DEVICE_ID_INFINIPATH_HT: |
525d0ca1 | 395 | ipath_init_iba6110_funcs(dd); |
7bb206e3 | 396 | break; |
e757bef2 BS |
397 | #endif |
398 | #ifdef CONFIG_PCI_MSI | |
7bb206e3 | 399 | case PCI_DEVICE_ID_INFINIPATH_PE800: |
525d0ca1 | 400 | ipath_init_iba6120_funcs(dd); |
7bb206e3 | 401 | break; |
e757bef2 | 402 | #endif |
7bb206e3 | 403 | default: |
759d5768 | 404 | ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, " |
7bb206e3 BS |
405 | "failing\n", ent->device); |
406 | return -ENODEV; | |
407 | } | |
408 | ||
409 | for (j = 0; j < 6; j++) { | |
410 | if (!pdev->resource[j].start) | |
411 | continue; | |
e29419ff GKH |
412 | ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n", |
413 | j, (unsigned long long)pdev->resource[j].start, | |
414 | (unsigned long long)pdev->resource[j].end, | |
415 | (unsigned long long)pci_resource_len(pdev, j)); | |
7bb206e3 BS |
416 | } |
417 | ||
418 | if (!addr) { | |
419 | ipath_dev_err(dd, "No valid address in BAR 0!\n"); | |
420 | ret = -ENODEV; | |
421 | goto bail_regions; | |
422 | } | |
423 | ||
424 | dd->ipath_deviceid = ent->device; /* save for later use */ | |
425 | dd->ipath_vendorid = ent->vendor; | |
426 | ||
427 | ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
428 | if (ret) { | |
429 | ipath_dev_err(dd, "Failed to read PCI revision ID unit " | |
430 | "%u: err %d\n", dd->ipath_unit, -ret); | |
431 | goto bail_regions; /* shouldn't ever happen */ | |
432 | } | |
433 | dd->ipath_pcirev = rev; | |
434 | ||
eb9dc6f4 BS |
435 | #if defined(__powerpc__) |
436 | /* There isn't a generic way to specify writethrough mappings */ | |
437 | dd->ipath_kregbase = __ioremap(addr, len, | |
438 | (_PAGE_NO_CACHE|_PAGE_WRITETHRU)); | |
439 | #else | |
7bb206e3 | 440 | dd->ipath_kregbase = ioremap_nocache(addr, len); |
eb9dc6f4 | 441 | #endif |
7bb206e3 BS |
442 | |
443 | if (!dd->ipath_kregbase) { | |
444 | ipath_dbg("Unable to map io addr %llx to kvirt, failing\n", | |
445 | addr); | |
446 | ret = -ENOMEM; | |
447 | goto bail_iounmap; | |
448 | } | |
449 | dd->ipath_kregend = (u64 __iomem *) | |
450 | ((void __iomem *)dd->ipath_kregbase + len); | |
451 | dd->ipath_physaddr = addr; /* used for io_remap, etc. */ | |
452 | /* for user mmap */ | |
b35f004d BS |
453 | ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n", |
454 | addr, dd->ipath_kregbase); | |
7bb206e3 BS |
455 | |
456 | /* | |
457 | * clear ipath_flags here instead of in ipath_init_chip as it is set | |
458 | * by ipath_setup_htconfig. | |
459 | */ | |
460 | dd->ipath_flags = 0; | |
fba75200 BS |
461 | dd->ipath_lli_counter = 0; |
462 | dd->ipath_lli_errors = 0; | |
7bb206e3 BS |
463 | |
464 | if (dd->ipath_f_bus(dd, pdev)) | |
465 | ipath_dev_err(dd, "Failed to setup config space; " | |
466 | "continuing anyway\n"); | |
467 | ||
468 | /* | |
dace1453 | 469 | * set up our interrupt handler; IRQF_SHARED probably not needed, |
7bb206e3 BS |
470 | * since MSI interrupts shouldn't be shared but won't hurt for now. |
471 | * check 0 irq after we return from chip-specific bus setup, since | |
472 | * that can affect this due to setup | |
473 | */ | |
51f65ebc | 474 | if (!dd->ipath_irq) |
7bb206e3 BS |
475 | ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't " |
476 | "work\n"); | |
477 | else { | |
51f65ebc | 478 | ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED, |
7bb206e3 BS |
479 | IPATH_DRV_NAME, dd); |
480 | if (ret) { | |
481 | ipath_dev_err(dd, "Couldn't setup irq handler, " | |
51f65ebc | 482 | "irq=%d: %d\n", dd->ipath_irq, ret); |
7bb206e3 BS |
483 | goto bail_iounmap; |
484 | } | |
485 | } | |
486 | ||
487 | ret = ipath_init_chip(dd, 0); /* do the chip-specific init */ | |
488 | if (ret) | |
489 | goto bail_iounmap; | |
490 | ||
491 | ret = ipath_enable_wc(dd); | |
492 | ||
493 | if (ret) { | |
494 | ipath_dev_err(dd, "Write combining not enabled " | |
495 | "(err %d): performance may be poor\n", | |
496 | -ret); | |
497 | ret = 0; | |
498 | } | |
499 | ||
500 | ipath_device_create_group(&pdev->dev, dd); | |
501 | ipathfs_add_device(dd); | |
502 | ipath_user_add(dd); | |
a2acb2ff | 503 | ipath_diag_add(dd); |
b1c1b6a3 | 504 | ipath_register_ib_device(dd); |
7bb206e3 BS |
505 | |
506 | goto bail; | |
507 | ||
508 | bail_iounmap: | |
509 | iounmap((volatile void __iomem *) dd->ipath_kregbase); | |
510 | ||
511 | bail_regions: | |
512 | pci_release_regions(pdev); | |
513 | ||
514 | bail_disable: | |
515 | pci_disable_device(pdev); | |
516 | ||
517 | bail_devdata: | |
518 | ipath_free_devdata(pdev, dd); | |
519 | ||
7bb206e3 BS |
520 | bail: |
521 | return ret; | |
522 | } | |
523 | ||
7227aac4 | 524 | static void __devexit cleanup_device(struct ipath_devdata *dd) |
7bb206e3 | 525 | { |
7227aac4 | 526 | int port; |
7bb206e3 | 527 | |
7227aac4 | 528 | ipath_shutdown_device(dd); |
7bb206e3 | 529 | |
7227aac4 BS |
530 | if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) { |
531 | /* can't do anything more with chip; needs re-init */ | |
532 | *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT; | |
533 | if (dd->ipath_kregbase) { | |
534 | /* | |
535 | * if we haven't already cleaned up before these are | |
536 | * to ensure any register reads/writes "fail" until | |
537 | * re-init | |
538 | */ | |
539 | dd->ipath_kregbase = NULL; | |
540 | dd->ipath_uregbase = 0; | |
541 | dd->ipath_sregbase = 0; | |
542 | dd->ipath_cregbase = 0; | |
543 | dd->ipath_kregsize = 0; | |
544 | } | |
545 | ipath_disable_wc(dd); | |
546 | } | |
c78f6415 | 547 | |
7227aac4 BS |
548 | if (dd->ipath_pioavailregs_dma) { |
549 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
550 | (void *) dd->ipath_pioavailregs_dma, | |
551 | dd->ipath_pioavailregs_phys); | |
552 | dd->ipath_pioavailregs_dma = NULL; | |
553 | } | |
554 | if (dd->ipath_dummy_hdrq) { | |
555 | dma_free_coherent(&dd->pcidev->dev, | |
556 | dd->ipath_pd[0]->port_rcvhdrq_size, | |
557 | dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys); | |
558 | dd->ipath_dummy_hdrq = NULL; | |
559 | } | |
560 | ||
561 | if (dd->ipath_pageshadow) { | |
562 | struct page **tmpp = dd->ipath_pageshadow; | |
563 | dma_addr_t *tmpd = dd->ipath_physshadow; | |
564 | int i, cnt = 0; | |
565 | ||
566 | ipath_cdbg(VERBOSE, "Unlocking any expTID pages still " | |
567 | "locked\n"); | |
568 | for (port = 0; port < dd->ipath_cfgports; port++) { | |
569 | int port_tidbase = port * dd->ipath_rcvtidcnt; | |
570 | int maxtid = port_tidbase + dd->ipath_rcvtidcnt; | |
571 | for (i = port_tidbase; i < maxtid; i++) { | |
572 | if (!tmpp[i]) | |
573 | continue; | |
574 | pci_unmap_page(dd->pcidev, tmpd[i], | |
575 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
576 | ipath_release_user_pages(&tmpp[i], 1); | |
577 | tmpp[i] = NULL; | |
578 | cnt++; | |
579 | } | |
580 | } | |
581 | if (cnt) { | |
582 | ipath_stats.sps_pageunlocks += cnt; | |
583 | ipath_cdbg(VERBOSE, "There were still %u expTID " | |
584 | "entries locked\n", cnt); | |
585 | } | |
586 | if (ipath_stats.sps_pagelocks || | |
587 | ipath_stats.sps_pageunlocks) | |
588 | ipath_cdbg(VERBOSE, "%llu pages locked, %llu " | |
589 | "unlocked via ipath_m{un}lock\n", | |
590 | (unsigned long long) | |
591 | ipath_stats.sps_pagelocks, | |
592 | (unsigned long long) | |
593 | ipath_stats.sps_pageunlocks); | |
594 | ||
595 | ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n", | |
596 | dd->ipath_pageshadow); | |
597 | vfree(dd->ipath_pageshadow); | |
598 | dd->ipath_pageshadow = NULL; | |
c78f6415 BS |
599 | } |
600 | ||
7227aac4 BS |
601 | /* |
602 | * free any resources still in use (usually just kernel ports) | |
603 | * at unload; we do for portcnt, not cfgports, because cfgports | |
604 | * could have changed while we were loaded. | |
605 | */ | |
606 | for (port = 0; port < dd->ipath_portcnt; port++) { | |
607 | struct ipath_portdata *pd = dd->ipath_pd[port]; | |
608 | dd->ipath_pd[port] = NULL; | |
609 | ipath_free_pddata(dd, pd); | |
610 | } | |
611 | kfree(dd->ipath_pd); | |
612 | /* | |
613 | * debuggability, in case some cleanup path tries to use it | |
614 | * after this | |
615 | */ | |
616 | dd->ipath_pd = NULL; | |
617 | } | |
618 | ||
619 | static void __devexit ipath_remove_one(struct pci_dev *pdev) | |
620 | { | |
621 | struct ipath_devdata *dd = pci_get_drvdata(pdev); | |
622 | ||
623 | ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd); | |
624 | ||
625 | if (dd->verbs_dev) | |
626 | ipath_unregister_ib_device(dd->verbs_dev); | |
627 | ||
a2acb2ff BS |
628 | ipath_diag_remove(dd); |
629 | ipath_user_remove(dd); | |
7bb206e3 BS |
630 | ipathfs_remove_device(dd); |
631 | ipath_device_remove_group(&pdev->dev, dd); | |
7227aac4 | 632 | |
7bb206e3 BS |
633 | ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, " |
634 | "unit %u\n", dd, (u32) dd->ipath_unit); | |
7227aac4 BS |
635 | |
636 | cleanup_device(dd); | |
637 | ||
638 | /* | |
639 | * turn off rcv, send, and interrupts for all ports, all drivers | |
640 | * should also hard reset the chip here? | |
641 | * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs | |
642 | * for all versions of the driver, if they were allocated | |
643 | */ | |
51f65ebc BS |
644 | if (dd->ipath_irq) { |
645 | ipath_cdbg(VERBOSE, "unit %u free irq %d\n", | |
646 | dd->ipath_unit, dd->ipath_irq); | |
647 | dd->ipath_f_free_irq(dd); | |
7227aac4 BS |
648 | } else |
649 | ipath_dbg("irq is 0, not doing free_irq " | |
650 | "for unit %u\n", dd->ipath_unit); | |
651 | /* | |
652 | * we check for NULL here, because it's outside | |
653 | * the kregbase check, and we need to call it | |
654 | * after the free_irq. Thus it's possible that | |
655 | * the function pointers were never initialized. | |
656 | */ | |
657 | if (dd->ipath_f_cleanup) | |
658 | /* clean up chip-specific stuff */ | |
659 | dd->ipath_f_cleanup(dd); | |
660 | ||
661 | ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase); | |
662 | iounmap((volatile void __iomem *) dd->ipath_kregbase); | |
7bb206e3 BS |
663 | pci_release_regions(pdev); |
664 | ipath_cdbg(VERBOSE, "calling pci_disable_device\n"); | |
665 | pci_disable_device(pdev); | |
666 | ||
667 | ipath_free_devdata(pdev, dd); | |
7bb206e3 BS |
668 | } |
669 | ||
670 | /* general driver use */ | |
671 | DEFINE_MUTEX(ipath_mutex); | |
672 | ||
673 | static DEFINE_SPINLOCK(ipath_pioavail_lock); | |
674 | ||
675 | /** | |
676 | * ipath_disarm_piobufs - cancel a range of PIO buffers | |
677 | * @dd: the infinipath device | |
678 | * @first: the first PIO buffer to cancel | |
679 | * @cnt: the number of PIO buffers to cancel | |
680 | * | |
681 | * cancel a range of PIO buffers, used when they might be armed, but | |
682 | * not triggered. Used at init to ensure buffer state, and also user | |
683 | * process close, in case it died while writing to a PIO buffer | |
684 | * Also after errors. | |
685 | */ | |
686 | void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first, | |
687 | unsigned cnt) | |
688 | { | |
689 | unsigned i, last = first + cnt; | |
690 | u64 sendctrl, sendorig; | |
691 | ||
692 | ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first); | |
693 | sendorig = dd->ipath_sendctrl | INFINIPATH_S_DISARM; | |
694 | for (i = first; i < last; i++) { | |
695 | sendctrl = sendorig | | |
696 | (i << INFINIPATH_S_DISARMPIOBUF_SHIFT); | |
697 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
698 | sendctrl); | |
699 | } | |
700 | ||
701 | /* | |
702 | * Write it again with current value, in case ipath_sendctrl changed | |
703 | * while we were looping; no critical bits that would require | |
704 | * locking. | |
705 | * | |
706 | * Write a 0, and then the original value, reading scratch in | |
707 | * between. This seems to avoid a chip timing race that causes | |
708 | * pioavail updates to memory to stop. | |
709 | */ | |
710 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
711 | 0); | |
712 | sendorig = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
713 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
714 | dd->ipath_sendctrl); | |
715 | } | |
716 | ||
717 | /** | |
718 | * ipath_wait_linkstate - wait for an IB link state change to occur | |
719 | * @dd: the infinipath device | |
720 | * @state: the state to wait for | |
721 | * @msecs: the number of milliseconds to wait | |
722 | * | |
723 | * wait up to msecs milliseconds for IB link state change to occur for | |
724 | * now, take the easy polling route. Currently used only by | |
34b2aafe | 725 | * ipath_set_linkstate. Returns 0 if state reached, otherwise |
7bb206e3 BS |
726 | * -ETIMEDOUT state can have multiple states set, for any of several |
727 | * transitions. | |
728 | */ | |
34b2aafe BS |
729 | static int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, |
730 | int msecs) | |
7bb206e3 | 731 | { |
0fd41363 BS |
732 | dd->ipath_state_wanted = state; |
733 | wait_event_interruptible_timeout(ipath_state_wait, | |
7bb206e3 BS |
734 | (dd->ipath_flags & state), |
735 | msecs_to_jiffies(msecs)); | |
0fd41363 | 736 | dd->ipath_state_wanted = 0; |
7bb206e3 BS |
737 | |
738 | if (!(dd->ipath_flags & state)) { | |
739 | u64 val; | |
0fd41363 BS |
740 | ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u" |
741 | " ms\n", | |
7bb206e3 BS |
742 | /* test INIT ahead of DOWN, both can be set */ |
743 | (state & IPATH_LINKINIT) ? "INIT" : | |
744 | ((state & IPATH_LINKDOWN) ? "DOWN" : | |
745 | ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")), | |
746 | msecs); | |
747 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); | |
748 | ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n", | |
749 | (unsigned long long) ipath_read_kreg64( | |
750 | dd, dd->ipath_kregs->kr_ibcctrl), | |
751 | (unsigned long long) val, | |
752 | ipath_ibcstatus_str[val & 0xf]); | |
753 | } | |
754 | return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT; | |
755 | } | |
756 | ||
757 | void ipath_decode_err(char *buf, size_t blen, ipath_err_t err) | |
758 | { | |
759 | *buf = '\0'; | |
760 | if (err & INFINIPATH_E_RHDRLEN) | |
761 | strlcat(buf, "rhdrlen ", blen); | |
762 | if (err & INFINIPATH_E_RBADTID) | |
763 | strlcat(buf, "rbadtid ", blen); | |
764 | if (err & INFINIPATH_E_RBADVERSION) | |
765 | strlcat(buf, "rbadversion ", blen); | |
766 | if (err & INFINIPATH_E_RHDR) | |
767 | strlcat(buf, "rhdr ", blen); | |
768 | if (err & INFINIPATH_E_RLONGPKTLEN) | |
769 | strlcat(buf, "rlongpktlen ", blen); | |
770 | if (err & INFINIPATH_E_RSHORTPKTLEN) | |
771 | strlcat(buf, "rshortpktlen ", blen); | |
772 | if (err & INFINIPATH_E_RMAXPKTLEN) | |
773 | strlcat(buf, "rmaxpktlen ", blen); | |
774 | if (err & INFINIPATH_E_RMINPKTLEN) | |
775 | strlcat(buf, "rminpktlen ", blen); | |
776 | if (err & INFINIPATH_E_RFORMATERR) | |
777 | strlcat(buf, "rformaterr ", blen); | |
778 | if (err & INFINIPATH_E_RUNSUPVL) | |
779 | strlcat(buf, "runsupvl ", blen); | |
780 | if (err & INFINIPATH_E_RUNEXPCHAR) | |
781 | strlcat(buf, "runexpchar ", blen); | |
782 | if (err & INFINIPATH_E_RIBFLOW) | |
783 | strlcat(buf, "ribflow ", blen); | |
784 | if (err & INFINIPATH_E_REBP) | |
785 | strlcat(buf, "EBP ", blen); | |
786 | if (err & INFINIPATH_E_SUNDERRUN) | |
787 | strlcat(buf, "sunderrun ", blen); | |
788 | if (err & INFINIPATH_E_SPIOARMLAUNCH) | |
789 | strlcat(buf, "spioarmlaunch ", blen); | |
790 | if (err & INFINIPATH_E_SUNEXPERRPKTNUM) | |
791 | strlcat(buf, "sunexperrpktnum ", blen); | |
792 | if (err & INFINIPATH_E_SDROPPEDDATAPKT) | |
793 | strlcat(buf, "sdroppeddatapkt ", blen); | |
794 | if (err & INFINIPATH_E_SDROPPEDSMPPKT) | |
795 | strlcat(buf, "sdroppedsmppkt ", blen); | |
796 | if (err & INFINIPATH_E_SMAXPKTLEN) | |
797 | strlcat(buf, "smaxpktlen ", blen); | |
798 | if (err & INFINIPATH_E_SMINPKTLEN) | |
799 | strlcat(buf, "sminpktlen ", blen); | |
800 | if (err & INFINIPATH_E_SUNSUPVL) | |
801 | strlcat(buf, "sunsupVL ", blen); | |
802 | if (err & INFINIPATH_E_SPKTLEN) | |
803 | strlcat(buf, "spktlen ", blen); | |
804 | if (err & INFINIPATH_E_INVALIDADDR) | |
805 | strlcat(buf, "invalidaddr ", blen); | |
806 | if (err & INFINIPATH_E_RICRC) | |
807 | strlcat(buf, "CRC ", blen); | |
808 | if (err & INFINIPATH_E_RVCRC) | |
809 | strlcat(buf, "VCRC ", blen); | |
810 | if (err & INFINIPATH_E_RRCVEGRFULL) | |
811 | strlcat(buf, "rcvegrfull ", blen); | |
812 | if (err & INFINIPATH_E_RRCVHDRFULL) | |
813 | strlcat(buf, "rcvhdrfull ", blen); | |
814 | if (err & INFINIPATH_E_IBSTATUSCHANGED) | |
815 | strlcat(buf, "ibcstatuschg ", blen); | |
816 | if (err & INFINIPATH_E_RIBLOSTLINK) | |
817 | strlcat(buf, "riblostlink ", blen); | |
818 | if (err & INFINIPATH_E_HARDWARE) | |
819 | strlcat(buf, "hardware ", blen); | |
820 | if (err & INFINIPATH_E_RESET) | |
821 | strlcat(buf, "reset ", blen); | |
822 | } | |
823 | ||
824 | /** | |
825 | * get_rhf_errstring - decode RHF errors | |
826 | * @err: the err number | |
827 | * @msg: the output buffer | |
828 | * @len: the length of the output buffer | |
829 | * | |
830 | * only used one place now, may want more later | |
831 | */ | |
832 | static void get_rhf_errstring(u32 err, char *msg, size_t len) | |
833 | { | |
834 | /* if no errors, and so don't need to check what's first */ | |
835 | *msg = '\0'; | |
836 | ||
837 | if (err & INFINIPATH_RHF_H_ICRCERR) | |
838 | strlcat(msg, "icrcerr ", len); | |
839 | if (err & INFINIPATH_RHF_H_VCRCERR) | |
840 | strlcat(msg, "vcrcerr ", len); | |
841 | if (err & INFINIPATH_RHF_H_PARITYERR) | |
842 | strlcat(msg, "parityerr ", len); | |
843 | if (err & INFINIPATH_RHF_H_LENERR) | |
844 | strlcat(msg, "lenerr ", len); | |
845 | if (err & INFINIPATH_RHF_H_MTUERR) | |
846 | strlcat(msg, "mtuerr ", len); | |
847 | if (err & INFINIPATH_RHF_H_IHDRERR) | |
848 | /* infinipath hdr checksum error */ | |
849 | strlcat(msg, "ipathhdrerr ", len); | |
850 | if (err & INFINIPATH_RHF_H_TIDERR) | |
851 | strlcat(msg, "tiderr ", len); | |
852 | if (err & INFINIPATH_RHF_H_MKERR) | |
853 | /* bad port, offset, etc. */ | |
854 | strlcat(msg, "invalid ipathhdr ", len); | |
855 | if (err & INFINIPATH_RHF_H_IBERR) | |
856 | strlcat(msg, "iberr ", len); | |
857 | if (err & INFINIPATH_RHF_L_SWA) | |
858 | strlcat(msg, "swA ", len); | |
859 | if (err & INFINIPATH_RHF_L_SWB) | |
860 | strlcat(msg, "swB ", len); | |
861 | } | |
862 | ||
863 | /** | |
864 | * ipath_get_egrbuf - get an eager buffer | |
865 | * @dd: the infinipath device | |
866 | * @bufnum: the eager buffer to get | |
867 | * @err: unused | |
868 | * | |
869 | * must only be called if ipath_pd[port] is known to be allocated | |
870 | */ | |
871 | static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum, | |
872 | int err) | |
873 | { | |
1fd3b40f BS |
874 | return dd->ipath_port0_skbinfo ? |
875 | (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL; | |
7bb206e3 BS |
876 | } |
877 | ||
878 | /** | |
879 | * ipath_alloc_skb - allocate an skb and buffer with possible constraints | |
880 | * @dd: the infinipath device | |
881 | * @gfp_mask: the sk_buff SFP mask | |
882 | */ | |
883 | struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, | |
884 | gfp_t gfp_mask) | |
885 | { | |
886 | struct sk_buff *skb; | |
887 | u32 len; | |
888 | ||
889 | /* | |
890 | * Only fully supported way to handle this is to allocate lots | |
891 | * extra, align as needed, and then do skb_reserve(). That wastes | |
892 | * a lot of memory... I'll have to hack this into infinipath_copy | |
893 | * also. | |
894 | */ | |
895 | ||
896 | /* | |
1fd3b40f BS |
897 | * We need 2 extra bytes for ipath_ether data sent in the |
898 | * key header. In order to keep everything dword aligned, | |
899 | * we'll reserve 4 bytes. | |
7bb206e3 | 900 | */ |
1fd3b40f BS |
901 | len = dd->ipath_ibmaxlen + 4; |
902 | ||
7bb206e3 | 903 | if (dd->ipath_flags & IPATH_4BYTE_TID) { |
1fd3b40f | 904 | /* We need a 2KB multiple alignment, and there is no way |
7bb206e3 BS |
905 | * to do it except to allocate extra and then skb_reserve |
906 | * enough to bring it up to the right alignment. | |
907 | */ | |
1fd3b40f | 908 | len += 2047; |
7bb206e3 | 909 | } |
1fd3b40f | 910 | |
7bb206e3 BS |
911 | skb = __dev_alloc_skb(len, gfp_mask); |
912 | if (!skb) { | |
913 | ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n", | |
914 | len); | |
915 | goto bail; | |
916 | } | |
1fd3b40f BS |
917 | |
918 | skb_reserve(skb, 4); | |
919 | ||
7bb206e3 | 920 | if (dd->ipath_flags & IPATH_4BYTE_TID) { |
1fd3b40f | 921 | u32 una = (unsigned long)skb->data & 2047; |
7bb206e3 | 922 | if (una) |
1fd3b40f BS |
923 | skb_reserve(skb, 2048 - una); |
924 | } | |
7bb206e3 BS |
925 | |
926 | bail: | |
927 | return skb; | |
928 | } | |
929 | ||
3d37b9e2 RC |
930 | static void ipath_rcv_hdrerr(struct ipath_devdata *dd, |
931 | u32 eflags, | |
932 | u32 l, | |
933 | u32 etail, | |
934 | u64 *rc) | |
935 | { | |
936 | char emsg[128]; | |
937 | struct ipath_message_header *hdr; | |
938 | ||
939 | get_rhf_errstring(eflags, emsg, sizeof emsg); | |
940 | hdr = (struct ipath_message_header *)&rc[1]; | |
941 | ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u " | |
942 | "tlen=%x opcode=%x egridx=%x: %s\n", | |
943 | eflags, l, | |
944 | ipath_hdrget_rcv_type((__le32 *) rc), | |
945 | ipath_hdrget_length_in_bytes((__le32 *) rc), | |
946 | be32_to_cpu(hdr->bth[0]) >> 24, | |
947 | etail, emsg); | |
948 | ||
949 | /* Count local link integrity errors. */ | |
950 | if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) { | |
951 | u8 n = (dd->ipath_ibcctrl >> | |
952 | INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) & | |
953 | INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK; | |
954 | ||
955 | if (++dd->ipath_lli_counter > n) { | |
956 | dd->ipath_lli_counter = 0; | |
957 | dd->ipath_lli_errors++; | |
958 | } | |
959 | } | |
960 | } | |
961 | ||
7bb206e3 BS |
962 | /* |
963 | * ipath_kreceive - receive a packet | |
964 | * @dd: the infinipath device | |
965 | * | |
966 | * called from interrupt handler for errors or receive interrupt | |
967 | */ | |
968 | void ipath_kreceive(struct ipath_devdata *dd) | |
969 | { | |
970 | u64 *rc; | |
971 | void *ebuf; | |
972 | const u32 rsize = dd->ipath_rcvhdrentsize; /* words */ | |
973 | const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */ | |
974 | u32 etail = -1, l, hdrqtail; | |
27b678dd | 975 | struct ipath_message_header *hdr; |
57abad25 | 976 | u32 eflags, i, etype, tlen, pkttot = 0, updegr=0, reloop=0; |
7bb206e3 | 977 | static u64 totcalls; /* stats, may eventually remove */ |
7bb206e3 BS |
978 | |
979 | if (!dd->ipath_hdrqtailptr) { | |
980 | ipath_dev_err(dd, | |
981 | "hdrqtailptr not set, can't do receives\n"); | |
982 | goto bail; | |
983 | } | |
984 | ||
985 | /* There is already a thread processing this queue. */ | |
986 | if (test_and_set_bit(0, &dd->ipath_rcv_pending)) | |
987 | goto bail; | |
988 | ||
f5f99929 | 989 | l = dd->ipath_port0head; |
57abad25 BS |
990 | hdrqtail = (u32) le64_to_cpu(*dd->ipath_hdrqtailptr); |
991 | if (l == hdrqtail) | |
7bb206e3 BS |
992 | goto done; |
993 | ||
57abad25 | 994 | reloop: |
f5f99929 | 995 | for (i = 0; l != hdrqtail; i++) { |
7bb206e3 BS |
996 | u32 qp; |
997 | u8 *bthbytes; | |
998 | ||
999 | rc = (u64 *) (dd->ipath_pd[0]->port_rcvhdrq + (l << 2)); | |
27b678dd | 1000 | hdr = (struct ipath_message_header *)&rc[1]; |
7bb206e3 BS |
1001 | /* |
1002 | * could make a network order version of IPATH_KD_QP, and | |
1003 | * do the obvious shift before masking to speed this up. | |
1004 | */ | |
1005 | qp = ntohl(hdr->bth[1]) & 0xffffff; | |
1006 | bthbytes = (u8 *) hdr->bth; | |
1007 | ||
27b678dd BS |
1008 | eflags = ipath_hdrget_err_flags((__le32 *) rc); |
1009 | etype = ipath_hdrget_rcv_type((__le32 *) rc); | |
7bb206e3 | 1010 | /* total length */ |
27b678dd | 1011 | tlen = ipath_hdrget_length_in_bytes((__le32 *) rc); |
7bb206e3 BS |
1012 | ebuf = NULL; |
1013 | if (etype != RCVHQ_RCV_TYPE_EXPECTED) { | |
1014 | /* | |
1015 | * it turns out that the chips uses an eager buffer | |
1016 | * for all non-expected packets, whether it "needs" | |
1017 | * one or not. So always get the index, but don't | |
1018 | * set ebuf (so we try to copy data) unless the | |
1019 | * length requires it. | |
1020 | */ | |
27b678dd | 1021 | etail = ipath_hdrget_index((__le32 *) rc); |
7bb206e3 BS |
1022 | if (tlen > sizeof(*hdr) || |
1023 | etype == RCVHQ_RCV_TYPE_NON_KD) | |
1024 | ebuf = ipath_get_egrbuf(dd, etail, 0); | |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * both tiderr and ipathhdrerr are set for all plain IB | |
1029 | * packets; only ipathhdrerr should be set. | |
1030 | */ | |
1031 | ||
1032 | if (etype != RCVHQ_RCV_TYPE_NON_KD && etype != | |
27b678dd | 1033 | RCVHQ_RCV_TYPE_ERROR && ipath_hdrget_ipath_ver( |
7bb206e3 BS |
1034 | hdr->iph.ver_port_tid_offset) != |
1035 | IPS_PROTO_VERSION) { | |
1036 | ipath_cdbg(PKT, "Bad InfiniPath protocol version " | |
1037 | "%x\n", etype); | |
1038 | } | |
1039 | ||
3d37b9e2 RC |
1040 | if (unlikely(eflags)) |
1041 | ipath_rcv_hdrerr(dd, eflags, l, etail, rc); | |
1042 | else if (etype == RCVHQ_RCV_TYPE_NON_KD) { | |
34b2aafe BS |
1043 | ipath_ib_rcv(dd->verbs_dev, rc + 1, ebuf, tlen); |
1044 | if (dd->ipath_lli_counter) | |
1045 | dd->ipath_lli_counter--; | |
1046 | ipath_cdbg(PKT, "typ %x, opcode %x (eager, " | |
1047 | "qp=%x), len %x; ignored\n", | |
1048 | etype, bthbytes[0], qp, tlen); | |
7bb206e3 | 1049 | } |
34b2aafe BS |
1050 | else if (etype == RCVHQ_RCV_TYPE_EAGER) |
1051 | ipath_cdbg(PKT, "typ %x, opcode %x (eager, " | |
1052 | "qp=%x), len %x; ignored\n", | |
1053 | etype, bthbytes[0], qp, tlen); | |
7bb206e3 BS |
1054 | else if (etype == RCVHQ_RCV_TYPE_EXPECTED) |
1055 | ipath_dbg("Bug: Expected TID, opcode %x; ignored\n", | |
1056 | be32_to_cpu(hdr->bth[0]) & 0xff); | |
3d37b9e2 | 1057 | else { |
7bb206e3 BS |
1058 | /* |
1059 | * error packet, type of error unknown. | |
1060 | * Probably type 3, but we don't know, so don't | |
1061 | * even try to print the opcode, etc. | |
1062 | */ | |
1063 | ipath_dbg("Error Pkt, but no eflags! egrbuf %x, " | |
1064 | "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; " | |
1065 | "hdr %llx %llx %llx %llx %llx\n", | |
1066 | etail, tlen, (unsigned long) rc, l, | |
1067 | (unsigned long long) rc[0], | |
1068 | (unsigned long long) rc[1], | |
1069 | (unsigned long long) rc[2], | |
1070 | (unsigned long long) rc[3], | |
1071 | (unsigned long long) rc[4], | |
1072 | (unsigned long long) rc[5]); | |
1073 | } | |
1074 | l += rsize; | |
1075 | if (l >= maxcnt) | |
1076 | l = 0; | |
f5f99929 BS |
1077 | if (etype != RCVHQ_RCV_TYPE_EXPECTED) |
1078 | updegr = 1; | |
7bb206e3 | 1079 | /* |
f5f99929 BS |
1080 | * update head regs on last packet, and every 16 packets. |
1081 | * Reduce bus traffic, while still trying to prevent | |
1082 | * rcvhdrq overflows, for when the queue is nearly full | |
7bb206e3 | 1083 | */ |
f5f99929 BS |
1084 | if (l == hdrqtail || (i && !(i&0xf))) { |
1085 | u64 lval; | |
525d0ca1 BS |
1086 | if (l == hdrqtail) |
1087 | /* request IBA6120 interrupt only on last */ | |
f5f99929 BS |
1088 | lval = dd->ipath_rhdrhead_intr_off | l; |
1089 | else | |
1090 | lval = l; | |
1091 | (void)ipath_write_ureg(dd, ur_rcvhdrhead, lval, 0); | |
1092 | if (updegr) { | |
1093 | (void)ipath_write_ureg(dd, ur_rcvegrindexhead, | |
1094 | etail, 0); | |
1095 | updegr = 0; | |
1096 | } | |
1097 | } | |
7bb206e3 BS |
1098 | } |
1099 | ||
57abad25 | 1100 | if (!dd->ipath_rhdrhead_intr_off && !reloop) { |
525d0ca1 | 1101 | /* IBA6110 workaround; we can have a race clearing chip |
57abad25 BS |
1102 | * interrupt with another interrupt about to be delivered, |
1103 | * and can clear it before it is delivered on the GPIO | |
1104 | * workaround. By doing the extra check here for the | |
1105 | * in-memory tail register updating while we were doing | |
1106 | * earlier packets, we "almost" guarantee we have covered | |
1107 | * that case. | |
1108 | */ | |
1109 | u32 hqtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr); | |
1110 | if (hqtail != hdrqtail) { | |
1111 | hdrqtail = hqtail; | |
1112 | reloop = 1; /* loop 1 extra time at most */ | |
1113 | goto reloop; | |
1114 | } | |
1115 | } | |
1116 | ||
7bb206e3 BS |
1117 | pkttot += i; |
1118 | ||
1119 | dd->ipath_port0head = l; | |
1120 | ||
7bb206e3 BS |
1121 | if (pkttot > ipath_stats.sps_maxpkts_call) |
1122 | ipath_stats.sps_maxpkts_call = pkttot; | |
1123 | ipath_stats.sps_port0pkts += pkttot; | |
1124 | ipath_stats.sps_avgpkts_call = | |
1125 | ipath_stats.sps_port0pkts / ++totcalls; | |
1126 | ||
1127 | done: | |
1128 | clear_bit(0, &dd->ipath_rcv_pending); | |
1129 | smp_mb__after_clear_bit(); | |
1130 | ||
1131 | bail:; | |
1132 | } | |
1133 | ||
1134 | /** | |
1135 | * ipath_update_pio_bufs - update shadow copy of the PIO availability map | |
1136 | * @dd: the infinipath device | |
1137 | * | |
1138 | * called whenever our local copy indicates we have run out of send buffers | |
1139 | * NOTE: This can be called from interrupt context by some code | |
1140 | * and from non-interrupt context by ipath_getpiobuf(). | |
1141 | */ | |
1142 | ||
1143 | static void ipath_update_pio_bufs(struct ipath_devdata *dd) | |
1144 | { | |
1145 | unsigned long flags; | |
1146 | int i; | |
1147 | const unsigned piobregs = (unsigned)dd->ipath_pioavregs; | |
1148 | ||
1149 | /* If the generation (check) bits have changed, then we update the | |
1150 | * busy bit for the corresponding PIO buffer. This algorithm will | |
1151 | * modify positions to the value they already have in some cases | |
1152 | * (i.e., no change), but it's faster than changing only the bits | |
1153 | * that have changed. | |
1154 | * | |
1155 | * We would like to do this atomicly, to avoid spinlocks in the | |
1156 | * critical send path, but that's not really possible, given the | |
1157 | * type of changes, and that this routine could be called on | |
1158 | * multiple cpu's simultaneously, so we lock in this routine only, | |
1159 | * to avoid conflicting updates; all we change is the shadow, and | |
1160 | * it's a single 64 bit memory location, so by definition the update | |
1161 | * is atomic in terms of what other cpu's can see in testing the | |
1162 | * bits. The spin_lock overhead isn't too bad, since it only | |
1163 | * happens when all buffers are in use, so only cpu overhead, not | |
1164 | * latency or bandwidth is affected. | |
1165 | */ | |
1166 | #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL | |
1167 | if (!dd->ipath_pioavailregs_dma) { | |
1168 | ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n"); | |
1169 | return; | |
1170 | } | |
1171 | if (ipath_debug & __IPATH_VERBDBG) { | |
1172 | /* only if packet debug and verbose */ | |
1173 | volatile __le64 *dma = dd->ipath_pioavailregs_dma; | |
1174 | unsigned long *shadow = dd->ipath_pioavailshadow; | |
1175 | ||
1176 | ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, " | |
1177 | "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx " | |
1178 | "s3=%lx\n", | |
1179 | (unsigned long long) le64_to_cpu(dma[0]), | |
1180 | shadow[0], | |
1181 | (unsigned long long) le64_to_cpu(dma[1]), | |
1182 | shadow[1], | |
1183 | (unsigned long long) le64_to_cpu(dma[2]), | |
1184 | shadow[2], | |
1185 | (unsigned long long) le64_to_cpu(dma[3]), | |
1186 | shadow[3]); | |
1187 | if (piobregs > 4) | |
1188 | ipath_cdbg( | |
1189 | PKT, "2nd group, dma4=%llx shad4=%lx, " | |
1190 | "d5=%llx s5=%lx, d6=%llx s6=%lx, " | |
1191 | "d7=%llx s7=%lx\n", | |
1192 | (unsigned long long) le64_to_cpu(dma[4]), | |
1193 | shadow[4], | |
1194 | (unsigned long long) le64_to_cpu(dma[5]), | |
1195 | shadow[5], | |
1196 | (unsigned long long) le64_to_cpu(dma[6]), | |
1197 | shadow[6], | |
1198 | (unsigned long long) le64_to_cpu(dma[7]), | |
1199 | shadow[7]); | |
1200 | } | |
1201 | spin_lock_irqsave(&ipath_pioavail_lock, flags); | |
1202 | for (i = 0; i < piobregs; i++) { | |
1203 | u64 pchbusy, pchg, piov, pnew; | |
1204 | /* | |
1205 | * Chip Errata: bug 6641; even and odd qwords>3 are swapped | |
1206 | */ | |
1207 | if (i > 3) { | |
1208 | if (i & 1) | |
1209 | piov = le64_to_cpu( | |
1210 | dd->ipath_pioavailregs_dma[i - 1]); | |
1211 | else | |
1212 | piov = le64_to_cpu( | |
1213 | dd->ipath_pioavailregs_dma[i + 1]); | |
1214 | } else | |
1215 | piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]); | |
1216 | pchg = _IPATH_ALL_CHECKBITS & | |
1217 | ~(dd->ipath_pioavailshadow[i] ^ piov); | |
1218 | pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT; | |
1219 | if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) { | |
1220 | pnew = dd->ipath_pioavailshadow[i] & ~pchbusy; | |
1221 | pnew |= piov & pchbusy; | |
1222 | dd->ipath_pioavailshadow[i] = pnew; | |
1223 | } | |
1224 | } | |
1225 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * ipath_setrcvhdrsize - set the receive header size | |
1230 | * @dd: the infinipath device | |
1231 | * @rhdrsize: the receive header size | |
1232 | * | |
1233 | * called from user init code, and also layered driver init | |
1234 | */ | |
1235 | int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize) | |
1236 | { | |
1237 | int ret = 0; | |
1238 | ||
1239 | if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) { | |
1240 | if (dd->ipath_rcvhdrsize != rhdrsize) { | |
1241 | dev_info(&dd->pcidev->dev, | |
1242 | "Error: can't set protocol header " | |
1243 | "size %u, already %u\n", | |
1244 | rhdrsize, dd->ipath_rcvhdrsize); | |
1245 | ret = -EAGAIN; | |
1246 | } else | |
1247 | ipath_cdbg(VERBOSE, "Reuse same protocol header " | |
1248 | "size %u\n", dd->ipath_rcvhdrsize); | |
1249 | } else if (rhdrsize > (dd->ipath_rcvhdrentsize - | |
1250 | (sizeof(u64) / sizeof(u32)))) { | |
1251 | ipath_dbg("Error: can't set protocol header size %u " | |
1252 | "(> max %u)\n", rhdrsize, | |
1253 | dd->ipath_rcvhdrentsize - | |
1254 | (u32) (sizeof(u64) / sizeof(u32))); | |
1255 | ret = -EOVERFLOW; | |
1256 | } else { | |
1257 | dd->ipath_flags |= IPATH_RCVHDRSZ_SET; | |
1258 | dd->ipath_rcvhdrsize = rhdrsize; | |
1259 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize, | |
1260 | dd->ipath_rcvhdrsize); | |
1261 | ipath_cdbg(VERBOSE, "Set protocol header size to %u\n", | |
1262 | dd->ipath_rcvhdrsize); | |
1263 | } | |
1264 | return ret; | |
1265 | } | |
1266 | ||
1267 | /** | |
1268 | * ipath_getpiobuf - find an available pio buffer | |
1269 | * @dd: the infinipath device | |
1270 | * @pbufnum: the buffer number is placed here | |
1271 | * | |
1272 | * do appropriate marking as busy, etc. | |
1273 | * returns buffer number if one found (>=0), negative number is error. | |
0fd41363 | 1274 | * Used by ipath_layer_send |
7bb206e3 BS |
1275 | */ |
1276 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 * pbufnum) | |
1277 | { | |
1278 | int i, j, starti, updated = 0; | |
1279 | unsigned piobcnt, iter; | |
1280 | unsigned long flags; | |
1281 | unsigned long *shadow = dd->ipath_pioavailshadow; | |
1282 | u32 __iomem *buf; | |
1283 | ||
1284 | piobcnt = (unsigned)(dd->ipath_piobcnt2k | |
1285 | + dd->ipath_piobcnt4k); | |
1286 | starti = dd->ipath_lastport_piobuf; | |
1287 | iter = piobcnt - starti; | |
1288 | if (dd->ipath_upd_pio_shadow) { | |
1289 | /* | |
1290 | * Minor optimization. If we had no buffers on last call, | |
1291 | * start out by doing the update; continue and do scan even | |
1292 | * if no buffers were updated, to be paranoid | |
1293 | */ | |
1294 | ipath_update_pio_bufs(dd); | |
1295 | /* we scanned here, don't do it at end of scan */ | |
1296 | updated = 1; | |
1297 | i = starti; | |
1298 | } else | |
1299 | i = dd->ipath_lastpioindex; | |
1300 | ||
1301 | rescan: | |
1302 | /* | |
1303 | * while test_and_set_bit() is atomic, we do that and then the | |
1304 | * change_bit(), and the pair is not. See if this is the cause | |
1305 | * of the remaining armlaunch errors. | |
1306 | */ | |
1307 | spin_lock_irqsave(&ipath_pioavail_lock, flags); | |
1308 | for (j = 0; j < iter; j++, i++) { | |
1309 | if (i >= piobcnt) | |
1310 | i = starti; | |
1311 | /* | |
1312 | * To avoid bus lock overhead, we first find a candidate | |
1313 | * buffer, then do the test and set, and continue if that | |
1314 | * fails. | |
1315 | */ | |
1316 | if (test_bit((2 * i) + 1, shadow) || | |
1317 | test_and_set_bit((2 * i) + 1, shadow)) | |
1318 | continue; | |
1319 | /* flip generation bit */ | |
1320 | change_bit(2 * i, shadow); | |
1321 | break; | |
1322 | } | |
1323 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); | |
1324 | ||
1325 | if (j == iter) { | |
1326 | volatile __le64 *dma = dd->ipath_pioavailregs_dma; | |
1327 | ||
1328 | /* | |
1329 | * first time through; shadow exhausted, but may be real | |
1330 | * buffers available, so go see; if any updated, rescan | |
1331 | * (once) | |
1332 | */ | |
1333 | if (!updated) { | |
1334 | ipath_update_pio_bufs(dd); | |
1335 | updated = 1; | |
1336 | i = starti; | |
1337 | goto rescan; | |
1338 | } | |
1339 | dd->ipath_upd_pio_shadow = 1; | |
1340 | /* | |
1341 | * not atomic, but if we lose one once in a while, that's OK | |
1342 | */ | |
1343 | ipath_stats.sps_nopiobufs++; | |
1344 | if (!(++dd->ipath_consec_nopiobuf % 100000)) { | |
1345 | ipath_dbg( | |
1346 | "%u pio sends with no bufavail; dmacopy: " | |
1347 | "%llx %llx %llx %llx; shadow: " | |
1348 | "%lx %lx %lx %lx\n", | |
1349 | dd->ipath_consec_nopiobuf, | |
1350 | (unsigned long long) le64_to_cpu(dma[0]), | |
1351 | (unsigned long long) le64_to_cpu(dma[1]), | |
1352 | (unsigned long long) le64_to_cpu(dma[2]), | |
1353 | (unsigned long long) le64_to_cpu(dma[3]), | |
1354 | shadow[0], shadow[1], shadow[2], | |
1355 | shadow[3]); | |
1356 | /* | |
1357 | * 4 buffers per byte, 4 registers above, cover rest | |
1358 | * below | |
1359 | */ | |
1360 | if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > | |
1361 | (sizeof(shadow[0]) * 4 * 4)) | |
1362 | ipath_dbg("2nd group: dmacopy: %llx %llx " | |
1363 | "%llx %llx; shadow: %lx %lx " | |
1364 | "%lx %lx\n", | |
1365 | (unsigned long long) | |
1366 | le64_to_cpu(dma[4]), | |
1367 | (unsigned long long) | |
1368 | le64_to_cpu(dma[5]), | |
1369 | (unsigned long long) | |
1370 | le64_to_cpu(dma[6]), | |
1371 | (unsigned long long) | |
1372 | le64_to_cpu(dma[7]), | |
1373 | shadow[4], shadow[5], | |
1374 | shadow[6], shadow[7]); | |
1375 | } | |
1376 | buf = NULL; | |
1377 | goto bail; | |
1378 | } | |
1379 | ||
7bb206e3 BS |
1380 | /* |
1381 | * set next starting place. Since it's just an optimization, | |
1382 | * it doesn't matter who wins on this, so no locking | |
1383 | */ | |
1384 | dd->ipath_lastpioindex = i + 1; | |
1385 | if (dd->ipath_upd_pio_shadow) | |
1386 | dd->ipath_upd_pio_shadow = 0; | |
1387 | if (dd->ipath_consec_nopiobuf) | |
1388 | dd->ipath_consec_nopiobuf = 0; | |
1389 | if (i < dd->ipath_piobcnt2k) | |
1390 | buf = (u32 __iomem *) (dd->ipath_pio2kbase + | |
1391 | i * dd->ipath_palign); | |
1392 | else | |
1393 | buf = (u32 __iomem *) | |
1394 | (dd->ipath_pio4kbase + | |
1395 | (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign); | |
1396 | ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n", | |
1397 | i, (i < dd->ipath_piobcnt2k) ? 2 : 4, buf); | |
1398 | if (pbufnum) | |
1399 | *pbufnum = i; | |
1400 | ||
1401 | bail: | |
1402 | return buf; | |
1403 | } | |
1404 | ||
1405 | /** | |
1406 | * ipath_create_rcvhdrq - create a receive header queue | |
1407 | * @dd: the infinipath device | |
1408 | * @pd: the port data | |
1409 | * | |
f37bda92 BS |
1410 | * this must be contiguous memory (from an i/o perspective), and must be |
1411 | * DMA'able (which means for some systems, it will go through an IOMMU, | |
1412 | * or be forced into a low address range). | |
7bb206e3 BS |
1413 | */ |
1414 | int ipath_create_rcvhdrq(struct ipath_devdata *dd, | |
1415 | struct ipath_portdata *pd) | |
1416 | { | |
f37bda92 | 1417 | int ret = 0; |
7bb206e3 | 1418 | |
7bb206e3 | 1419 | if (!pd->port_rcvhdrq) { |
f37bda92 | 1420 | dma_addr_t phys_hdrqtail; |
7bb206e3 | 1421 | gfp_t gfp_flags = GFP_USER | __GFP_COMP; |
f37bda92 BS |
1422 | int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize * |
1423 | sizeof(u32), PAGE_SIZE); | |
7bb206e3 BS |
1424 | |
1425 | pd->port_rcvhdrq = dma_alloc_coherent( | |
1426 | &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys, | |
1427 | gfp_flags); | |
1428 | ||
1429 | if (!pd->port_rcvhdrq) { | |
1430 | ipath_dev_err(dd, "attempt to allocate %d bytes " | |
1431 | "for port %u rcvhdrq failed\n", | |
1432 | amt, pd->port_port); | |
1433 | ret = -ENOMEM; | |
1434 | goto bail; | |
1435 | } | |
f37bda92 BS |
1436 | pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent( |
1437 | &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, GFP_KERNEL); | |
1438 | if (!pd->port_rcvhdrtail_kvaddr) { | |
1439 | ipath_dev_err(dd, "attempt to allocate 1 page " | |
1440 | "for port %u rcvhdrqtailaddr failed\n", | |
1441 | pd->port_port); | |
1442 | ret = -ENOMEM; | |
221e3198 BS |
1443 | dma_free_coherent(&dd->pcidev->dev, amt, |
1444 | pd->port_rcvhdrq, pd->port_rcvhdrq_phys); | |
1445 | pd->port_rcvhdrq = NULL; | |
f37bda92 BS |
1446 | goto bail; |
1447 | } | |
1448 | pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail; | |
7bb206e3 BS |
1449 | |
1450 | pd->port_rcvhdrq_size = amt; | |
1451 | ||
1452 | ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu " | |
1453 | "for port %u rcvhdr Q\n", | |
1454 | amt >> PAGE_SHIFT, pd->port_rcvhdrq, | |
1455 | (unsigned long) pd->port_rcvhdrq_phys, | |
1456 | (unsigned long) pd->port_rcvhdrq_size, | |
1457 | pd->port_port); | |
f37bda92 BS |
1458 | |
1459 | ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx physical\n", | |
1460 | pd->port_port, | |
1461 | (unsigned long long) phys_hdrqtail); | |
7bb206e3 | 1462 | } |
f37bda92 BS |
1463 | else |
1464 | ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; " | |
1465 | "hdrtailaddr@%p %llx physical\n", | |
1466 | pd->port_port, pd->port_rcvhdrq, | |
1fd3b40f BS |
1467 | (unsigned long long) pd->port_rcvhdrq_phys, |
1468 | pd->port_rcvhdrtail_kvaddr, (unsigned long long) | |
1469 | pd->port_rcvhdrqtailaddr_phys); | |
f37bda92 BS |
1470 | |
1471 | /* clear for security and sanity on each use */ | |
1472 | memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size); | |
076fafcd | 1473 | memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE); |
7bb206e3 BS |
1474 | |
1475 | /* | |
1476 | * tell chip each time we init it, even if we are re-using previous | |
f37bda92 | 1477 | * memory (we zero the register at process close) |
7bb206e3 | 1478 | */ |
f37bda92 BS |
1479 | ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr, |
1480 | pd->port_port, pd->port_rcvhdrqtailaddr_phys); | |
7bb206e3 BS |
1481 | ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr, |
1482 | pd->port_port, pd->port_rcvhdrq_phys); | |
1483 | ||
1484 | ret = 0; | |
1485 | bail: | |
1486 | return ret; | |
1487 | } | |
1488 | ||
1489 | int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id, | |
1490 | u64 bits_to_wait_for, u64 * valp) | |
1491 | { | |
1492 | unsigned long timeout; | |
1493 | u64 lastval, val; | |
1494 | int ret; | |
1495 | ||
1496 | lastval = ipath_read_kreg64(dd, reg_id); | |
1497 | /* wait a ridiculously long time */ | |
1498 | timeout = jiffies + msecs_to_jiffies(5); | |
1499 | do { | |
1500 | val = ipath_read_kreg64(dd, reg_id); | |
1501 | /* set so they have something, even on failures. */ | |
1502 | *valp = val; | |
1503 | if ((val & bits_to_wait_for) == bits_to_wait_for) { | |
1504 | ret = 0; | |
1505 | break; | |
1506 | } | |
1507 | if (val != lastval) | |
1508 | ipath_cdbg(VERBOSE, "Changed from %llx to %llx, " | |
1509 | "waiting for %llx bits\n", | |
1510 | (unsigned long long) lastval, | |
1511 | (unsigned long long) val, | |
1512 | (unsigned long long) bits_to_wait_for); | |
1513 | cond_resched(); | |
1514 | if (time_after(jiffies, timeout)) { | |
1515 | ipath_dbg("Didn't get bits %llx in register 0x%x, " | |
1516 | "got %llx\n", | |
1517 | (unsigned long long) bits_to_wait_for, | |
1518 | reg_id, (unsigned long long) *valp); | |
1519 | ret = -ENODEV; | |
1520 | break; | |
1521 | } | |
1522 | } while (1); | |
1523 | ||
1524 | return ret; | |
1525 | } | |
1526 | ||
1527 | /** | |
1528 | * ipath_waitfor_mdio_cmdready - wait for last command to complete | |
1529 | * @dd: the infinipath device | |
1530 | * | |
1531 | * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go | |
1532 | * away indicating the last command has completed. It doesn't return data | |
1533 | */ | |
1534 | int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd) | |
1535 | { | |
1536 | unsigned long timeout; | |
1537 | u64 val; | |
1538 | int ret; | |
1539 | ||
1540 | /* wait a ridiculously long time */ | |
1541 | timeout = jiffies + msecs_to_jiffies(5); | |
1542 | do { | |
1543 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio); | |
1544 | if (!(val & IPATH_MDIO_CMDVALID)) { | |
1545 | ret = 0; | |
1546 | break; | |
1547 | } | |
1548 | cond_resched(); | |
1549 | if (time_after(jiffies, timeout)) { | |
1550 | ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n", | |
1551 | (unsigned long long) val); | |
1552 | ret = -ENODEV; | |
1553 | break; | |
1554 | } | |
1555 | } while (1); | |
1556 | ||
1557 | return ret; | |
1558 | } | |
1559 | ||
34b2aafe | 1560 | static void ipath_set_ib_lstate(struct ipath_devdata *dd, int which) |
7bb206e3 BS |
1561 | { |
1562 | static const char *what[4] = { | |
1563 | [0] = "DOWN", | |
1564 | [INFINIPATH_IBCC_LINKCMD_INIT] = "INIT", | |
1565 | [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED", | |
1566 | [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE" | |
1567 | }; | |
f37bda92 BS |
1568 | int linkcmd = (which >> INFINIPATH_IBCC_LINKCMD_SHIFT) & |
1569 | INFINIPATH_IBCC_LINKCMD_MASK; | |
1570 | ||
0fd41363 | 1571 | ipath_cdbg(VERBOSE, "Trying to move unit %u to %s, current ltstate " |
7bb206e3 | 1572 | "is %s\n", dd->ipath_unit, |
f37bda92 | 1573 | what[linkcmd], |
7bb206e3 BS |
1574 | ipath_ibcstatus_str[ |
1575 | (ipath_read_kreg64 | |
1576 | (dd, dd->ipath_kregs->kr_ibcstatus) >> | |
1577 | INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & | |
1578 | INFINIPATH_IBCS_LINKTRAININGSTATE_MASK]); | |
f37bda92 | 1579 | /* flush all queued sends when going to DOWN or INIT, to be sure that |
0fd41363 | 1580 | * they don't block MAD packets */ |
f37bda92 BS |
1581 | if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT) { |
1582 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
1583 | INFINIPATH_S_ABORT); | |
1584 | ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf, | |
1585 | (unsigned)(dd->ipath_piobcnt2k + | |
1586 | dd->ipath_piobcnt4k) - | |
1587 | dd->ipath_lastport_piobuf); | |
1588 | } | |
7bb206e3 BS |
1589 | |
1590 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
1591 | dd->ipath_ibcctrl | which); | |
1592 | } | |
1593 | ||
34b2aafe BS |
1594 | int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate) |
1595 | { | |
1596 | u32 lstate; | |
1597 | int ret; | |
1598 | ||
1599 | switch (newstate) { | |
1600 | case IPATH_IB_LINKDOWN: | |
1601 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_POLL << | |
1602 | INFINIPATH_IBCC_LINKINITCMD_SHIFT); | |
1603 | /* don't wait */ | |
1604 | ret = 0; | |
1605 | goto bail; | |
1606 | ||
1607 | case IPATH_IB_LINKDOWN_SLEEP: | |
1608 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_SLEEP << | |
1609 | INFINIPATH_IBCC_LINKINITCMD_SHIFT); | |
1610 | /* don't wait */ | |
1611 | ret = 0; | |
1612 | goto bail; | |
1613 | ||
1614 | case IPATH_IB_LINKDOWN_DISABLE: | |
1615 | ipath_set_ib_lstate(dd, | |
1616 | INFINIPATH_IBCC_LINKINITCMD_DISABLE << | |
1617 | INFINIPATH_IBCC_LINKINITCMD_SHIFT); | |
1618 | /* don't wait */ | |
1619 | ret = 0; | |
1620 | goto bail; | |
1621 | ||
1622 | case IPATH_IB_LINKINIT: | |
1623 | if (dd->ipath_flags & IPATH_LINKINIT) { | |
1624 | ret = 0; | |
1625 | goto bail; | |
1626 | } | |
1627 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_INIT << | |
1628 | INFINIPATH_IBCC_LINKCMD_SHIFT); | |
1629 | lstate = IPATH_LINKINIT; | |
1630 | break; | |
1631 | ||
1632 | case IPATH_IB_LINKARM: | |
1633 | if (dd->ipath_flags & IPATH_LINKARMED) { | |
1634 | ret = 0; | |
1635 | goto bail; | |
1636 | } | |
1637 | if (!(dd->ipath_flags & | |
1638 | (IPATH_LINKINIT | IPATH_LINKACTIVE))) { | |
1639 | ret = -EINVAL; | |
1640 | goto bail; | |
1641 | } | |
1642 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED << | |
1643 | INFINIPATH_IBCC_LINKCMD_SHIFT); | |
1644 | /* | |
1645 | * Since the port can transition to ACTIVE by receiving | |
1646 | * a non VL 15 packet, wait for either state. | |
1647 | */ | |
1648 | lstate = IPATH_LINKARMED | IPATH_LINKACTIVE; | |
1649 | break; | |
1650 | ||
1651 | case IPATH_IB_LINKACTIVE: | |
1652 | if (dd->ipath_flags & IPATH_LINKACTIVE) { | |
1653 | ret = 0; | |
1654 | goto bail; | |
1655 | } | |
1656 | if (!(dd->ipath_flags & IPATH_LINKARMED)) { | |
1657 | ret = -EINVAL; | |
1658 | goto bail; | |
1659 | } | |
1660 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE << | |
1661 | INFINIPATH_IBCC_LINKCMD_SHIFT); | |
1662 | lstate = IPATH_LINKACTIVE; | |
1663 | break; | |
1664 | ||
946db67f BS |
1665 | case IPATH_IB_LINK_LOOPBACK: |
1666 | dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n"); | |
1667 | dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK; | |
1668 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
1669 | dd->ipath_ibcctrl); | |
1670 | ret = 0; | |
1671 | goto bail; // no state change to wait for | |
1672 | ||
1673 | case IPATH_IB_LINK_EXTERNAL: | |
1674 | dev_info(&dd->pcidev->dev, "Disabling IB local loopback (normal)\n"); | |
1675 | dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK; | |
1676 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
1677 | dd->ipath_ibcctrl); | |
1678 | ret = 0; | |
1679 | goto bail; // no state change to wait for | |
1680 | ||
34b2aafe BS |
1681 | default: |
1682 | ipath_dbg("Invalid linkstate 0x%x requested\n", newstate); | |
1683 | ret = -EINVAL; | |
1684 | goto bail; | |
1685 | } | |
1686 | ret = ipath_wait_linkstate(dd, lstate, 2000); | |
1687 | ||
1688 | bail: | |
1689 | return ret; | |
1690 | } | |
1691 | ||
1692 | /** | |
1693 | * ipath_set_mtu - set the MTU | |
1694 | * @dd: the infinipath device | |
1695 | * @arg: the new MTU | |
1696 | * | |
1697 | * we can handle "any" incoming size, the issue here is whether we | |
1698 | * need to restrict our outgoing size. For now, we don't do any | |
1699 | * sanity checking on this, and we don't deal with what happens to | |
1700 | * programs that are already running when the size changes. | |
1701 | * NOTE: changing the MTU will usually cause the IBC to go back to | |
1702 | * link initialize (IPATH_IBSTATE_INIT) state... | |
1703 | */ | |
1704 | int ipath_set_mtu(struct ipath_devdata *dd, u16 arg) | |
1705 | { | |
1706 | u32 piosize; | |
1707 | int changed = 0; | |
1708 | int ret; | |
1709 | ||
1710 | /* | |
1711 | * mtu is IB data payload max. It's the largest power of 2 less | |
1712 | * than piosize (or even larger, since it only really controls the | |
1713 | * largest we can receive; we can send the max of the mtu and | |
1714 | * piosize). We check that it's one of the valid IB sizes. | |
1715 | */ | |
1716 | if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 && | |
1717 | arg != 4096) { | |
1718 | ipath_dbg("Trying to set invalid mtu %u, failing\n", arg); | |
1719 | ret = -EINVAL; | |
1720 | goto bail; | |
1721 | } | |
1722 | if (dd->ipath_ibmtu == arg) { | |
1723 | ret = 0; /* same as current */ | |
1724 | goto bail; | |
1725 | } | |
1726 | ||
1727 | piosize = dd->ipath_ibmaxlen; | |
1728 | dd->ipath_ibmtu = arg; | |
1729 | ||
1730 | if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) { | |
1731 | /* Only if it's not the initial value (or reset to it) */ | |
1732 | if (piosize != dd->ipath_init_ibmaxlen) { | |
1733 | dd->ipath_ibmaxlen = piosize; | |
1734 | changed = 1; | |
1735 | } | |
1736 | } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) { | |
1737 | piosize = arg + IPATH_PIO_MAXIBHDR; | |
1738 | ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x " | |
1739 | "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize, | |
1740 | arg); | |
1741 | dd->ipath_ibmaxlen = piosize; | |
1742 | changed = 1; | |
1743 | } | |
1744 | ||
1745 | if (changed) { | |
1746 | /* | |
1747 | * set the IBC maxpktlength to the size of our pio | |
1748 | * buffers in words | |
1749 | */ | |
1750 | u64 ibc = dd->ipath_ibcctrl; | |
1751 | ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK << | |
1752 | INFINIPATH_IBCC_MAXPKTLEN_SHIFT); | |
1753 | ||
1754 | piosize = piosize - 2 * sizeof(u32); /* ignore pbc */ | |
1755 | dd->ipath_ibmaxlen = piosize; | |
1756 | piosize /= sizeof(u32); /* in words */ | |
1757 | /* | |
1758 | * for ICRC, which we only send in diag test pkt mode, and | |
1759 | * we don't need to worry about that for mtu | |
1760 | */ | |
1761 | piosize += 1; | |
1762 | ||
1763 | ibc |= piosize << INFINIPATH_IBCC_MAXPKTLEN_SHIFT; | |
1764 | dd->ipath_ibcctrl = ibc; | |
1765 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, | |
1766 | dd->ipath_ibcctrl); | |
1767 | dd->ipath_f_tidtemplate(dd); | |
1768 | } | |
1769 | ||
1770 | ret = 0; | |
1771 | ||
1772 | bail: | |
1773 | return ret; | |
1774 | } | |
1775 | ||
1776 | int ipath_set_lid(struct ipath_devdata *dd, u32 arg, u8 lmc) | |
1777 | { | |
1778 | dd->ipath_lid = arg; | |
1779 | dd->ipath_lmc = lmc; | |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
7bb206e3 BS |
1784 | /** |
1785 | * ipath_read_kreg64_port - read a device's per-port 64-bit kernel register | |
1786 | * @dd: the infinipath device | |
1787 | * @regno: the register number to read | |
1788 | * @port: the port containing the register | |
1789 | * | |
1790 | * Registers that vary with the chip implementation constants (port) | |
1791 | * use this routine. | |
1792 | */ | |
1793 | u64 ipath_read_kreg64_port(const struct ipath_devdata *dd, ipath_kreg regno, | |
1794 | unsigned port) | |
1795 | { | |
1796 | u16 where; | |
1797 | ||
1798 | if (port < dd->ipath_portcnt && | |
1799 | (regno == dd->ipath_kregs->kr_rcvhdraddr || | |
1800 | regno == dd->ipath_kregs->kr_rcvhdrtailaddr)) | |
1801 | where = regno + port; | |
1802 | else | |
1803 | where = -1; | |
1804 | ||
1805 | return ipath_read_kreg64(dd, where); | |
1806 | } | |
1807 | ||
1808 | /** | |
1809 | * ipath_write_kreg_port - write a device's per-port 64-bit kernel register | |
1810 | * @dd: the infinipath device | |
1811 | * @regno: the register number to write | |
1812 | * @port: the port containing the register | |
1813 | * @value: the value to write | |
1814 | * | |
1815 | * Registers that vary with the chip implementation constants (port) | |
1816 | * use this routine. | |
1817 | */ | |
1818 | void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno, | |
1819 | unsigned port, u64 value) | |
1820 | { | |
1821 | u16 where; | |
1822 | ||
1823 | if (port < dd->ipath_portcnt && | |
1824 | (regno == dd->ipath_kregs->kr_rcvhdraddr || | |
1825 | regno == dd->ipath_kregs->kr_rcvhdrtailaddr)) | |
1826 | where = regno + port; | |
1827 | else | |
1828 | where = -1; | |
1829 | ||
1830 | ipath_write_kreg(dd, where, value); | |
1831 | } | |
1832 | ||
1833 | /** | |
1834 | * ipath_shutdown_device - shut down a device | |
1835 | * @dd: the infinipath device | |
1836 | * | |
1837 | * This is called to make the device quiet when we are about to | |
1838 | * unload the driver, and also when the device is administratively | |
1839 | * disabled. It does not free any data structures. | |
1840 | * Everything it does has to be setup again by ipath_init_chip(dd,1) | |
1841 | */ | |
1842 | void ipath_shutdown_device(struct ipath_devdata *dd) | |
1843 | { | |
7bb206e3 BS |
1844 | ipath_dbg("Shutting down the device\n"); |
1845 | ||
1846 | dd->ipath_flags |= IPATH_LINKUNK; | |
1847 | dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN | | |
1848 | IPATH_LINKINIT | IPATH_LINKARMED | | |
1849 | IPATH_LINKACTIVE); | |
1850 | *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF | | |
1851 | IPATH_STATUS_IB_READY); | |
1852 | ||
1853 | /* mask interrupts, but not errors */ | |
1854 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); | |
1855 | ||
1856 | dd->ipath_rcvctrl = 0; | |
1857 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, | |
1858 | dd->ipath_rcvctrl); | |
1859 | ||
1860 | /* | |
1861 | * gracefully stop all sends allowing any in progress to trickle out | |
1862 | * first. | |
1863 | */ | |
1864 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0ULL); | |
1865 | /* flush it */ | |
44f8e3f3 | 1866 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
7bb206e3 BS |
1867 | /* |
1868 | * enough for anything that's going to trickle out to have actually | |
1869 | * done so. | |
1870 | */ | |
1871 | udelay(5); | |
1872 | ||
1873 | /* | |
1874 | * abort any armed or launched PIO buffers that didn't go. (self | |
1875 | * clearing). Will cause any packet currently being transmitted to | |
1876 | * go out with an EBP, and may also cause a short packet error on | |
1877 | * the receiver. | |
1878 | */ | |
1879 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
1880 | INFINIPATH_S_ABORT); | |
1881 | ||
1882 | ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_DISABLE << | |
1883 | INFINIPATH_IBCC_LINKINITCMD_SHIFT); | |
1884 | ||
7bb206e3 BS |
1885 | /* disable IBC */ |
1886 | dd->ipath_control &= ~INFINIPATH_C_LINKENABLE; | |
1887 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
a40f55fc | 1888 | dd->ipath_control | INFINIPATH_C_FREEZEMODE); |
7bb206e3 BS |
1889 | |
1890 | /* | |
1891 | * clear SerdesEnable and turn the leds off; do this here because | |
1892 | * we are unloading, so don't count on interrupts to move along | |
1893 | * Turn the LEDs off explictly for the same reason. | |
1894 | */ | |
1895 | dd->ipath_f_quiet_serdes(dd); | |
1896 | dd->ipath_f_setextled(dd, 0, 0); | |
1897 | ||
1898 | if (dd->ipath_stats_timer_active) { | |
1899 | del_timer_sync(&dd->ipath_stats_timer); | |
1900 | dd->ipath_stats_timer_active = 0; | |
1901 | } | |
1902 | ||
1903 | /* | |
1904 | * clear all interrupts and errors, so that the next time the driver | |
1905 | * is loaded or device is enabled, we know that whatever is set | |
1906 | * happened while we were unloaded | |
1907 | */ | |
1908 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
1909 | ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED); | |
1910 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL); | |
1911 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL); | |
1912 | } | |
1913 | ||
1914 | /** | |
1915 | * ipath_free_pddata - free a port's allocated data | |
1916 | * @dd: the infinipath device | |
f37bda92 | 1917 | * @pd: the portdata structure |
7bb206e3 | 1918 | * |
f37bda92 BS |
1919 | * free up any allocated data for a port |
1920 | * This should not touch anything that would affect a simultaneous | |
1921 | * re-allocation of port data, because it is called after ipath_mutex | |
1922 | * is released (and can be called from reinit as well). | |
1923 | * It should never change any chip state, or global driver state. | |
1924 | * (The only exception to global state is freeing the port0 port0_skbs.) | |
7bb206e3 | 1925 | */ |
f37bda92 | 1926 | void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd) |
7bb206e3 | 1927 | { |
7bb206e3 BS |
1928 | if (!pd) |
1929 | return; | |
f37bda92 BS |
1930 | |
1931 | if (pd->port_rcvhdrq) { | |
7bb206e3 BS |
1932 | ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p " |
1933 | "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq, | |
1934 | (unsigned long) pd->port_rcvhdrq_size); | |
1935 | dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size, | |
1936 | pd->port_rcvhdrq, pd->port_rcvhdrq_phys); | |
1937 | pd->port_rcvhdrq = NULL; | |
f37bda92 BS |
1938 | if (pd->port_rcvhdrtail_kvaddr) { |
1939 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
076fafcd | 1940 | pd->port_rcvhdrtail_kvaddr, |
f37bda92 BS |
1941 | pd->port_rcvhdrqtailaddr_phys); |
1942 | pd->port_rcvhdrtail_kvaddr = NULL; | |
1943 | } | |
7bb206e3 | 1944 | } |
f37bda92 BS |
1945 | if (pd->port_port && pd->port_rcvegrbuf) { |
1946 | unsigned e; | |
1947 | ||
1948 | for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) { | |
1949 | void *base = pd->port_rcvegrbuf[e]; | |
1950 | size_t size = pd->port_rcvegrbuf_size; | |
1951 | ||
1952 | ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), " | |
1953 | "chunk %u/%u\n", base, | |
1954 | (unsigned long) size, | |
1955 | e, pd->port_rcvegrbuf_chunks); | |
1956 | dma_free_coherent(&dd->pcidev->dev, size, | |
1957 | base, pd->port_rcvegrbuf_phys[e]); | |
7bb206e3 | 1958 | } |
9929b0fb | 1959 | kfree(pd->port_rcvegrbuf); |
f37bda92 | 1960 | pd->port_rcvegrbuf = NULL; |
9929b0fb | 1961 | kfree(pd->port_rcvegrbuf_phys); |
f37bda92 | 1962 | pd->port_rcvegrbuf_phys = NULL; |
7bb206e3 | 1963 | pd->port_rcvegrbuf_chunks = 0; |
1fd3b40f | 1964 | } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) { |
7bb206e3 | 1965 | unsigned e; |
1fd3b40f | 1966 | struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo; |
7bb206e3 | 1967 | |
1fd3b40f BS |
1968 | dd->ipath_port0_skbinfo = NULL; |
1969 | ipath_cdbg(VERBOSE, "free closed port %d " | |
1970 | "ipath_port0_skbinfo @ %p\n", pd->port_port, | |
1971 | skbinfo); | |
7bb206e3 | 1972 | for (e = 0; e < dd->ipath_rcvegrcnt; e++) |
1fd3b40f BS |
1973 | if (skbinfo[e].skb) { |
1974 | pci_unmap_single(dd->pcidev, skbinfo[e].phys, | |
1975 | dd->ipath_ibmaxlen, | |
1976 | PCI_DMA_FROMDEVICE); | |
1977 | dev_kfree_skb(skbinfo[e].skb); | |
1978 | } | |
1979 | vfree(skbinfo); | |
7bb206e3 | 1980 | } |
f37bda92 | 1981 | kfree(pd->port_tid_pg_list); |
9929b0fb BS |
1982 | vfree(pd->subport_uregbase); |
1983 | vfree(pd->subport_rcvegrbuf); | |
1984 | vfree(pd->subport_rcvhdr_base); | |
f37bda92 | 1985 | kfree(pd); |
7bb206e3 BS |
1986 | } |
1987 | ||
ac2ae4c9 | 1988 | static int __init infinipath_init(void) |
7bb206e3 BS |
1989 | { |
1990 | int ret; | |
1991 | ||
39c0d0b9 BS |
1992 | if (ipath_debug & __IPATH_DBG) |
1993 | printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version); | |
7bb206e3 BS |
1994 | |
1995 | /* | |
1996 | * These must be called before the driver is registered with | |
1997 | * the PCI subsystem. | |
1998 | */ | |
1999 | idr_init(&unit_table); | |
2000 | if (!idr_pre_get(&unit_table, GFP_KERNEL)) { | |
2001 | ret = -ENOMEM; | |
2002 | goto bail; | |
2003 | } | |
2004 | ||
2005 | ret = pci_register_driver(&ipath_driver); | |
2006 | if (ret < 0) { | |
2007 | printk(KERN_ERR IPATH_DRV_NAME | |
2008 | ": Unable to register driver: error %d\n", -ret); | |
2009 | goto bail_unit; | |
2010 | } | |
2011 | ||
2012 | ret = ipath_driver_create_group(&ipath_driver.driver); | |
2013 | if (ret < 0) { | |
2014 | printk(KERN_ERR IPATH_DRV_NAME ": Unable to create driver " | |
2015 | "sysfs entries: error %d\n", -ret); | |
2016 | goto bail_pci; | |
2017 | } | |
2018 | ||
2019 | ret = ipath_init_ipathfs(); | |
2020 | if (ret < 0) { | |
2021 | printk(KERN_ERR IPATH_DRV_NAME ": Unable to create " | |
2022 | "ipathfs: error %d\n", -ret); | |
2023 | goto bail_group; | |
2024 | } | |
2025 | ||
2026 | goto bail; | |
2027 | ||
2028 | bail_group: | |
2029 | ipath_driver_remove_group(&ipath_driver.driver); | |
2030 | ||
2031 | bail_pci: | |
2032 | pci_unregister_driver(&ipath_driver); | |
2033 | ||
2034 | bail_unit: | |
2035 | idr_destroy(&unit_table); | |
2036 | ||
2037 | bail: | |
2038 | return ret; | |
2039 | } | |
2040 | ||
7bb206e3 BS |
2041 | static void __exit infinipath_cleanup(void) |
2042 | { | |
7bb206e3 BS |
2043 | ipath_exit_ipathfs(); |
2044 | ||
2045 | ipath_driver_remove_group(&ipath_driver.driver); | |
2046 | ||
7bb206e3 BS |
2047 | ipath_cdbg(VERBOSE, "Unregistering pci driver\n"); |
2048 | pci_unregister_driver(&ipath_driver); | |
2049 | ||
2050 | idr_destroy(&unit_table); | |
2051 | } | |
2052 | ||
2053 | /** | |
2054 | * ipath_reset_device - reset the chip if possible | |
2055 | * @unit: the device to reset | |
2056 | * | |
2057 | * Whether or not reset is successful, we attempt to re-initialize the chip | |
2058 | * (that is, much like a driver unload/reload). We clear the INITTED flag | |
2059 | * so that the various entry points will fail until we reinitialize. For | |
2060 | * now, we only allow this if no user ports are open that use chip resources | |
2061 | */ | |
2062 | int ipath_reset_device(int unit) | |
2063 | { | |
2064 | int ret, i; | |
2065 | struct ipath_devdata *dd = ipath_lookup(unit); | |
2066 | ||
2067 | if (!dd) { | |
2068 | ret = -ENODEV; | |
2069 | goto bail; | |
2070 | } | |
2071 | ||
2072 | dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit); | |
2073 | ||
2074 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) { | |
2075 | dev_info(&dd->pcidev->dev, "Invalid unit number %u or " | |
2076 | "not initialized or not present\n", unit); | |
2077 | ret = -ENXIO; | |
2078 | goto bail; | |
2079 | } | |
2080 | ||
2081 | if (dd->ipath_pd) | |
23e86a45 | 2082 | for (i = 1; i < dd->ipath_cfgports; i++) { |
7bb206e3 BS |
2083 | if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) { |
2084 | ipath_dbg("unit %u port %d is in use " | |
2085 | "(PID %u cmd %s), can't reset\n", | |
2086 | unit, i, | |
2087 | dd->ipath_pd[i]->port_pid, | |
2088 | dd->ipath_pd[i]->port_comm); | |
2089 | ret = -EBUSY; | |
2090 | goto bail; | |
2091 | } | |
2092 | } | |
2093 | ||
2094 | dd->ipath_flags &= ~IPATH_INITTED; | |
2095 | ret = dd->ipath_f_reset(dd); | |
2096 | if (ret != 1) | |
2097 | ipath_dbg("reset was not successful\n"); | |
2098 | ipath_dbg("Trying to reinitialize unit %u after reset attempt\n", | |
2099 | unit); | |
2100 | ret = ipath_init_chip(dd, 1); | |
2101 | if (ret) | |
2102 | ipath_dev_err(dd, "Reinitialize unit %u after " | |
2103 | "reset failed with %d\n", unit, ret); | |
2104 | else | |
2105 | dev_info(&dd->pcidev->dev, "Reinitialized unit %u after " | |
2106 | "resetting\n", unit); | |
2107 | ||
2108 | bail: | |
2109 | return ret; | |
2110 | } | |
2111 | ||
30fc5c31 BS |
2112 | int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv) |
2113 | { | |
2114 | u64 val; | |
2115 | if ( new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK ) { | |
2116 | return -1; | |
2117 | } | |
2118 | if ( dd->ipath_rx_pol_inv != new_pol_inv ) { | |
2119 | dd->ipath_rx_pol_inv = new_pol_inv; | |
2120 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); | |
2121 | val &= ~(INFINIPATH_XGXS_RX_POL_MASK << | |
3cd96564 RD |
2122 | INFINIPATH_XGXS_RX_POL_SHIFT); |
2123 | val |= ((u64)dd->ipath_rx_pol_inv) << | |
2124 | INFINIPATH_XGXS_RX_POL_SHIFT; | |
30fc5c31 BS |
2125 | ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); |
2126 | } | |
2127 | return 0; | |
2128 | } | |
7bb206e3 BS |
2129 | module_init(infinipath_init); |
2130 | module_exit(infinipath_cleanup); |