[deliverable/linux.git] / drivers / infiniband / hw / nes / nes.h

/*
 * Copyright (c) 2006 - 2011 Intel Corporation.  All rights reserved.
 * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __NES_H
#define __NES_H

#include <linux/netdevice.h>
#include <linux/inetdevice.h>
#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/crc32c.h>

#include <rdma/ib_smi.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_pack.h>
#include <rdma/rdma_cm.h>
#include <rdma/iw_cm.h>

#define NES_SEND_FIRST_WRITE

#define QUEUE_DISCONNECTS

#define DRV_NAME    "iw_nes"
#define DRV_VERSION "1.5.0.1"
#define PFX         DRV_NAME ": "

/*
 * NetEffect PCI vendor id and NE010 PCI device id.
 */
#ifndef PCI_VENDOR_ID_NETEFFECT	/* not in pci.ids yet */
#define PCI_VENDOR_ID_NETEFFECT          0x1678
#define PCI_DEVICE_ID_NETEFFECT_NE020    0x0100
#define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110
#endif

#define NE020_REV   4
#define NE020_REV1  5

#define BAR_0       0
#define BAR_1       2

#define RX_BUF_SIZE             (1536 + 8)
#define NES_REG0_SIZE           (4 * 1024)
#define NES_TX_TIMEOUT          (6*HZ)
#define NES_FIRST_QPN           64
#define NES_SW_CONTEXT_ALIGN    1024

#define NES_NIC_MAX_NICS        16
#define NES_MAX_ARP_TABLE_SIZE  4096

#define NES_NIC_CEQ_SIZE        8
/* NICs will be on a separate CQ */
#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)

#define NES_MAX_PORT_COUNT 4

#define MAX_DPC_ITERATIONS               128

#define NES_DRV_OPT_ENABLE_MPA_VER_0     0x00000001
#define NES_DRV_OPT_DISABLE_MPA_CRC      0x00000002
#define NES_DRV_OPT_DISABLE_FIRST_WRITE  0x00000004
#define NES_DRV_OPT_DISABLE_INTF         0x00000008
#define NES_DRV_OPT_ENABLE_MSI           0x00000010
#define NES_DRV_OPT_DUAL_LOGICAL_PORT    0x00000020
#define NES_DRV_OPT_SUPRESS_OPTION_BC    0x00000040
#define NES_DRV_OPT_NO_INLINE_DATA       0x00000080
#define NES_DRV_OPT_DISABLE_INT_MOD      0x00000100
#define NES_DRV_OPT_DISABLE_VIRT_WQ      0x00000200
#define NES_DRV_OPT_ENABLE_PAU           0x00000400

#define NES_AEQ_EVENT_TIMEOUT         2500
#define NES_DISCONNECT_EVENT_TIMEOUT  2000

/* debug levels */
/* must match userspace */
#define NES_DBG_HW          0x00000001
#define NES_DBG_INIT        0x00000002
#define NES_DBG_ISR         0x00000004
#define NES_DBG_PHY         0x00000008
#define NES_DBG_NETDEV      0x00000010
#define NES_DBG_CM          0x00000020
#define NES_DBG_CM1         0x00000040
#define NES_DBG_NIC_RX      0x00000080
#define NES_DBG_NIC_TX      0x00000100
#define NES_DBG_CQP         0x00000200
#define NES_DBG_MMAP        0x00000400
#define NES_DBG_MR          0x00000800
#define NES_DBG_PD          0x00001000
#define NES_DBG_CQ          0x00002000
#define NES_DBG_QP          0x00004000
#define NES_DBG_MOD_QP      0x00008000
#define NES_DBG_AEQ         0x00010000
#define NES_DBG_IW_RX       0x00020000
#define NES_DBG_IW_TX       0x00040000
#define NES_DBG_SHUTDOWN    0x00080000
#define NES_DBG_PAU         0x00100000
#define NES_DBG_RSVD1       0x10000000
#define NES_DBG_RSVD2       0x20000000
#define NES_DBG_RSVD3       0x40000000
#define NES_DBG_RSVD4       0x80000000
#define NES_DBG_ALL         0xffffffff

#ifdef CONFIG_INFINIBAND_NES_DEBUG
#define nes_debug(level, fmt, args...) \
do { \
	if (level & nes_debug_level) \
		printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
} while (0)

#define assert(expr) \
do { \
	if (!(expr)) { \
		printk(KERN_ERR PFX "Assertion failed! %s, %s, %s, line %d\n", \
			   #expr, __FILE__, __func__, __LINE__); \
	} \
} while (0)

#define NES_EVENT_TIMEOUT   1200000
#else
#define nes_debug(level, fmt, args...)
#define assert(expr)          do {} while (0)

#define NES_EVENT_TIMEOUT   100000
#endif

#include "nes_hw.h"
#include "nes_verbs.h"
#include "nes_context.h"
#include "nes_user.h"
#include "nes_cm.h"
#include "nes_mgt.h"

extern int max_mtu;
#define max_frame_len (max_mtu+ETH_HLEN)
extern int interrupt_mod_interval;
extern int nes_if_count;
extern int mpa_version;
extern int disable_mpa_crc;
extern unsigned int nes_drv_opt;
extern unsigned int nes_debug_level;
extern unsigned int wqm_quanta;
extern struct list_head nes_adapter_list;

extern atomic_t cm_connects;
extern atomic_t cm_accepts;
extern atomic_t cm_disconnects;
extern atomic_t cm_closes;
extern atomic_t cm_connecteds;
extern atomic_t cm_connect_reqs;
extern atomic_t cm_rejects;
extern atomic_t mod_qp_timouts;
extern atomic_t qps_created;
extern atomic_t qps_destroyed;
extern atomic_t sw_qps_destroyed;
extern u32 mh_detected;
extern u32 mh_pauses_sent;
extern u32 cm_packets_sent;
extern u32 cm_packets_bounced;
extern u32 cm_packets_created;
extern u32 cm_packets_received;
extern u32 cm_packets_dropped;
extern u32 cm_packets_retrans;
extern atomic_t cm_listens_created;
extern atomic_t cm_listens_destroyed;
extern u32 cm_backlog_drops;
extern atomic_t cm_loopbacks;
extern atomic_t cm_nodes_created;
extern atomic_t cm_nodes_destroyed;
extern atomic_t cm_accel_dropped_pkts;
extern atomic_t cm_resets_recvd;
extern atomic_t pau_qps_created;
extern atomic_t pau_qps_destroyed;

extern u32 int_mod_timer_init;
extern u32 int_mod_cq_depth_256;
extern u32 int_mod_cq_depth_128;
extern u32 int_mod_cq_depth_32;
extern u32 int_mod_cq_depth_24;
extern u32 int_mod_cq_depth_16;
extern u32 int_mod_cq_depth_4;
extern u32 int_mod_cq_depth_1;

struct nes_device {
	struct nes_adapter	   *nesadapter;
	void __iomem           *regs;
	void __iomem           *index_reg;
	struct pci_dev         *pcidev;
	struct net_device      *netdev[NES_NIC_MAX_NICS];
	u64                    link_status_interrupts;
	struct tasklet_struct  dpc_tasklet;
	spinlock_t             indexed_regs_lock;
	unsigned long          csr_start;
	unsigned long          doorbell_region;
	unsigned long          doorbell_start;
	unsigned long          mac_tx_errors;
	unsigned long          mac_pause_frames_sent;
	unsigned long          mac_pause_frames_received;
	unsigned long          mac_rx_errors;
	unsigned long          mac_rx_crc_errors;
	unsigned long          mac_rx_symbol_err_frames;
	unsigned long          mac_rx_jabber_frames;
	unsigned long          mac_rx_oversized_frames;
	unsigned long          mac_rx_short_frames;
	unsigned long          port_rx_discards;
	unsigned long          port_tx_discards;
	unsigned int           mac_index;
	unsigned int           nes_stack_start;

	/* Control Structures */
	void                   *cqp_vbase;
	dma_addr_t             cqp_pbase;
	u32                    cqp_mem_size;
	u8                     ceq_index;
	u8                     nic_ceq_index;
	struct nes_hw_cqp      cqp;
	struct nes_hw_cq       ccq;
	struct list_head       cqp_avail_reqs;
	struct list_head       cqp_pending_reqs;
	struct nes_cqp_request *nes_cqp_requests;

	u32                    int_req;
	u32                    int_stat;
	u32                    timer_int_req;
	u32                    timer_only_int_count;
	u32                    intf_int_req;
	u32                    last_mac_tx_pauses;
	u32                    last_used_chunks_tx;
	struct list_head       list;

	u16                    base_doorbell_index;
	u16                    currcq_count;
	u16                    deepcq_count;
	u8                     iw_status;
	u8                     msi_enabled;
	u8                     netdev_count;
	u8                     napi_isr_ran;
	u8                     disable_rx_flow_control;
	u8                     disable_tx_flow_control;

	struct delayed_work    work;
	u8                     link_recheck;
};

/* Receive skb private area - must fit in skb->cb area */
struct nes_rskb_cb {
	u64                    busaddr;
	u32                    maplen;
	u32                    seqnum;
	u8                     *data_start;
	struct nes_qp          *nesqp;
};

static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
{
	u32 crc_value;
	crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));

	/*
	 * With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
	 * state in cpu order"), behavior of crc32c changes on
	 * big-endian platforms.  Our algorithm expects the previous
	 * behavior; otherwise we have RDMA connection establishment
	 * issue on big-endian.
	 */
	return cpu_to_le32(crc_value);
}

static inline void
set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
{
	wqe_words[index]     = cpu_to_le32((u32) value);
	wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
}

static inline void
set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
{
	wqe_words[index] = cpu_to_le32(value);
}

static inline void
nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
{
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX]       = 0;
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX]      = 0;
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX]   = 0;
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX]  = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX]       = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX]       = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX]        = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX]       = 0;
}

static inline void
nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head)
{
	u32 value;
	value = ((u32)((unsigned long) nesqp)) | head;
	set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
			(u32)(upper_32_bits((unsigned long)(nesqp))));
	set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
}

/* Read from memory-mapped device */
static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
{
	unsigned long flags;
	void __iomem *addr = nesdev->index_reg;
	u32 value;

	spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);

	writel(reg_index, addr);
	value = readl((void __iomem *)addr + 4);

	spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
	return value;
}

static inline u32 nes_read32(const void __iomem *addr)
{
	return readl(addr);
}

static inline u16 nes_read16(const void __iomem *addr)
{
	return readw(addr);
}

static inline u8 nes_read8(const void __iomem *addr)
{
	return readb(addr);
}

/* Write to memory-mapped device */
static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
{
	unsigned long flags;
	void __iomem *addr = nesdev->index_reg;

	spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);

	writel(reg_index, addr);
	writel(val, (void __iomem *)addr + 4);

	spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
}

static inline void nes_write32(void __iomem *addr, u32 val)
{
	writel(val, addr);
}

static inline void nes_write16(void __iomem *addr, u16 val)
{
	writew(val, addr);
}

static inline void nes_write8(void __iomem *addr, u8 val)
{
	writeb(val, addr);
}

enum nes_resource {
	NES_RESOURCE_MW = 1,
	NES_RESOURCE_FAST_MR,
	NES_RESOURCE_PHYS_MR,
	NES_RESOURCE_USER_MR,
	NES_RESOURCE_PD,
	NES_RESOURCE_QP,
	NES_RESOURCE_CQ,
	NES_RESOURCE_ARP
};

static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
		unsigned long *resource_array, u32 max_resources,
		u32 *req_resource_num, u32 *next, enum nes_resource resource_type)
{
	unsigned long flags;
	u32 resource_num;

	spin_lock_irqsave(&nesadapter->resource_lock, flags);

	resource_num = find_next_zero_bit(resource_array, max_resources, *next);
	if (resource_num >= max_resources) {
		resource_num = find_first_zero_bit(resource_array, max_resources);
		if (resource_num >= max_resources) {
			printk(KERN_ERR PFX "%s: No available resources [type=%u].\n", __func__, resource_type);
			spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
			return -EMFILE;
		}
	}
	set_bit(resource_num, resource_array);
	*next = resource_num+1;
	if (*next == max_resources) {
		*next = 0;
	}
	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
	*req_resource_num = resource_num;

	return 0;
}

static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
		unsigned long *resource_array, u32 resource_num)
{
	unsigned long flags;
	int bit_is_set;

	spin_lock_irqsave(&nesadapter->resource_lock, flags);

	bit_is_set = test_bit(resource_num, resource_array);
	nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
			resource_num, (bit_is_set ? "": " not"));
	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);

	return bit_is_set;
}

static inline void nes_free_resource(struct nes_adapter *nesadapter,
		unsigned long *resource_array, u32 resource_num)
{
	unsigned long flags;

	spin_lock_irqsave(&nesadapter->resource_lock, flags);
	clear_bit(resource_num, resource_array);
	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
}

static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev)
{
	return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
}

static inline struct nes_pd *to_nespd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct nes_pd, ibpd);
}

static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext)
{
	return container_of(ibucontext, struct nes_ucontext, ibucontext);
}

static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct nes_mr, ibmr);
}

static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr)
{
	return container_of(ibfmr, struct nes_mr, ibfmr);
}

static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw)
{
	return container_of(ibmw, struct nes_mr, ibmw);
}

static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr)
{
	return container_of(nesmr, struct nes_fmr, nesmr);
}

static inline struct nes_cq *to_nescq(struct ib_cq *ibcq)
{
	return container_of(ibcq, struct nes_cq, ibcq);
}

static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct nes_qp, ibqp);
}


/* nes.c */
void nes_add_ref(struct ib_qp *);
void nes_rem_ref(struct ib_qp *);
struct ib_qp *nes_get_qp(struct ib_device *, int);


/* nes_hw.c */
struct nes_adapter *nes_init_adapter(struct nes_device *, u8);
void  nes_nic_init_timer_defaults(struct nes_device *, u8);
void nes_destroy_adapter(struct nes_adapter *);
int nes_init_cqp(struct nes_device *);
int nes_init_phy(struct nes_device *);
int nes_init_nic_qp(struct nes_device *, struct net_device *);
void nes_destroy_nic_qp(struct nes_vnic *);
int nes_napi_isr(struct nes_device *);
void nes_dpc(unsigned long);
void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *);
void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
int nes_destroy_cqp(struct nes_device *);
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
void nes_recheck_link_status(struct work_struct *work);
void nes_terminate_timeout(unsigned long context);

/* nes_nic.c */
struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
void nes_netdev_destroy(struct net_device *);
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);

/* nes_cm.c */
void *nes_cm_create(struct net_device *);
int nes_cm_recv(struct sk_buff *, struct net_device *);
void nes_update_arp(unsigned char *, u32, u32, u16, u16);
void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32);
void nes_sock_release(struct nes_qp *, unsigned long *);
void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32);
int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
int nes_cm_disconn(struct nes_qp *);
void nes_cm_disconn_worker(void *);

/* nes_verbs.c */
int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32, u32);
int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
struct nes_ib_device *nes_init_ofa_device(struct net_device *);
void  nes_port_ibevent(struct nes_vnic *nesvnic);
void nes_destroy_ofa_device(struct nes_ib_device *);
int nes_register_ofa_device(struct nes_ib_device *);

/* nes_util.c */
int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *);
void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *);
void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
struct nes_cqp_request *nes_get_cqp_request(struct nes_device *);
void nes_free_cqp_request(struct nes_device *nesdev,
			  struct nes_cqp_request *cqp_request);
void nes_put_cqp_request(struct nes_device *nesdev,
			 struct nes_cqp_request *cqp_request);
void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
int nes_arp_table(struct nes_device *, u32, u8 *, u32);
void nes_mh_fix(unsigned long);
void nes_clc(unsigned long);
void nes_dump_mem(unsigned int, void *, int);
u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);

#endif	/* __NES_H */
Commit	Line	Data
3c2d774c	1	/*
c5488c57	2	* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
3c2d774c GS	3	* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
	34	#ifndef __NES_H
	35	#define __NES_H
	36
	37	#include <linux/netdevice.h>
	38	#include <linux/inetdevice.h>
	39	#include <linux/spinlock.h>
	40	#include <linux/kernel.h>
	41	#include <linux/delay.h>
	42	#include <linux/pci.h>
	43	#include <linux/dma-mapping.h>
	44	#include <linux/workqueue.h>
	45	#include <linux/slab.h>
3c2d774c GS	46	#include <asm/io.h>
	47	#include <linux/crc32c.h>
	48
	49	#include <rdma/ib_smi.h>
	50	#include <rdma/ib_verbs.h>
	51	#include <rdma/ib_pack.h>
	52	#include <rdma/rdma_cm.h>
	53	#include <rdma/iw_cm.h>
	54
	55	#define NES_SEND_FIRST_WRITE
	56
	57	#define QUEUE_DISCONNECTS
	58
3c2d774c	59	#define DRV_NAME "iw_nes"
cf9fd75c	60	#define DRV_VERSION "1.5.0.1"
3c2d774c GS	61	#define PFX DRV_NAME ": "
	62
	63	/*
	64	* NetEffect PCI vendor id and NE010 PCI device id.
	65	*/
	66	#ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */
09124e19 CT	67	#define PCI_VENDOR_ID_NETEFFECT 0x1678
	68	#define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100
	69	#define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110
3c2d774c GS	70	#endif
	71
	72	#define NE020_REV 4
	73	#define NE020_REV1 5
	74
	75	#define BAR_0 0
	76	#define BAR_1 2
	77
	78	#define RX_BUF_SIZE (1536 + 8)
	79	#define NES_REG0_SIZE (4 * 1024)
	80	#define NES_TX_TIMEOUT (6*HZ)
	81	#define NES_FIRST_QPN 64
	82	#define NES_SW_CONTEXT_ALIGN 1024
	83
	84	#define NES_NIC_MAX_NICS 16
	85	#define NES_MAX_ARP_TABLE_SIZE 4096
	86
	87	#define NES_NIC_CEQ_SIZE 8
	88	/* NICs will be on a separate CQ */
	89	#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
	90
	91	#define NES_MAX_PORT_COUNT 4
	92
	93	#define MAX_DPC_ITERATIONS 128
	94
3c2d774c GS	95	#define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
	96	#define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002
	97	#define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
	98	#define NES_DRV_OPT_DISABLE_INTF 0x00000008
	99	#define NES_DRV_OPT_ENABLE_MSI 0x00000010
	100	#define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
	101	#define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040
	102	#define NES_DRV_OPT_NO_INLINE_DATA 0x00000080
	103	#define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100
	104	#define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
0f0bee8b	105	#define NES_DRV_OPT_ENABLE_PAU 0x00000400
3c2d774c GS	106
	107	#define NES_AEQ_EVENT_TIMEOUT 2500
	108	#define NES_DISCONNECT_EVENT_TIMEOUT 2000
	109
	110	/* debug levels */
	111	/* must match userspace */
	112	#define NES_DBG_HW 0x00000001
	113	#define NES_DBG_INIT 0x00000002
	114	#define NES_DBG_ISR 0x00000004
	115	#define NES_DBG_PHY 0x00000008
	116	#define NES_DBG_NETDEV 0x00000010
	117	#define NES_DBG_CM 0x00000020
	118	#define NES_DBG_CM1 0x00000040
	119	#define NES_DBG_NIC_RX 0x00000080
	120	#define NES_DBG_NIC_TX 0x00000100
	121	#define NES_DBG_CQP 0x00000200
	122	#define NES_DBG_MMAP 0x00000400
	123	#define NES_DBG_MR 0x00000800
	124	#define NES_DBG_PD 0x00001000
	125	#define NES_DBG_CQ 0x00002000
	126	#define NES_DBG_QP 0x00004000
	127	#define NES_DBG_MOD_QP 0x00008000
	128	#define NES_DBG_AEQ 0x00010000
	129	#define NES_DBG_IW_RX 0x00020000
	130	#define NES_DBG_IW_TX 0x00040000
	131	#define NES_DBG_SHUTDOWN 0x00080000
0f0bee8b	132	#define NES_DBG_PAU 0x00100000
3c2d774c GS	133	#define NES_DBG_RSVD1 0x10000000
	134	#define NES_DBG_RSVD2 0x20000000
	135	#define NES_DBG_RSVD3 0x40000000
	136	#define NES_DBG_RSVD4 0x80000000
	137	#define NES_DBG_ALL 0xffffffff
	138
	139	#ifdef CONFIG_INFINIBAND_NES_DEBUG
	140	#define nes_debug(level, fmt, args...) \
6098d107	141	do { \
3c2d774c	142	if (level & nes_debug_level) \
6098d107 CT	143	printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
	144	} while (0)
	145
	146	#define assert(expr) \
	147	do { \
	148	if (!(expr)) { \
	149	printk(KERN_ERR PFX "Assertion failed! %s, %s, %s, line %d\n", \
	150	#expr, __FILE__, __func__, __LINE__); \
	151	} \
	152	} while (0)
3c2d774c GS	153
	154	#define NES_EVENT_TIMEOUT 1200000
	155	#else
	156	#define nes_debug(level, fmt, args...)
	157	#define assert(expr) do {} while (0)
	158
	159	#define NES_EVENT_TIMEOUT 100000
	160	#endif
	161
	162	#include "nes_hw.h"
	163	#include "nes_verbs.h"
	164	#include "nes_context.h"
	165	#include "nes_user.h"
	166	#include "nes_cm.h"
0f0bee8b	167	#include "nes_mgt.h"
3c2d774c GS	168
3c2d774c GS	169	extern int max_mtu;
3c2d774c GS	170	#define max_frame_len (max_mtu+ETH_HLEN)
	171	extern int interrupt_mod_interval;
	172	extern int nes_if_count;
	173	extern int mpa_version;
	174	extern int disable_mpa_crc;
3c2d774c GS	175	extern unsigned int nes_drv_opt;
3c2d774c GS	176	extern unsigned int nes_debug_level;
2b537c28	177	extern unsigned int wqm_quanta;
3c2d774c	178	extern struct list_head nes_adapter_list;
3c2d774c GS	179
	180	extern atomic_t cm_connects;
	181	extern atomic_t cm_accepts;
	182	extern atomic_t cm_disconnects;
	183	extern atomic_t cm_closes;
	184	extern atomic_t cm_connecteds;
	185	extern atomic_t cm_connect_reqs;
	186	extern atomic_t cm_rejects;
	187	extern atomic_t mod_qp_timouts;
	188	extern atomic_t qps_created;
	189	extern atomic_t qps_destroyed;
	190	extern atomic_t sw_qps_destroyed;
	191	extern u32 mh_detected;
	192	extern u32 mh_pauses_sent;
	193	extern u32 cm_packets_sent;
	194	extern u32 cm_packets_bounced;
	195	extern u32 cm_packets_created;
	196	extern u32 cm_packets_received;
	197	extern u32 cm_packets_dropped;
	198	extern u32 cm_packets_retrans;
6e10d2e4 FL	199	extern atomic_t cm_listens_created;
6e10d2e4 FL	200	extern atomic_t cm_listens_destroyed;
3c2d774c GS	201	extern u32 cm_backlog_drops;
	202	extern atomic_t cm_loopbacks;
	203	extern atomic_t cm_nodes_created;
	204	extern atomic_t cm_nodes_destroyed;
	205	extern atomic_t cm_accel_dropped_pkts;
	206	extern atomic_t cm_resets_recvd;
0f0bee8b FL	207	extern atomic_t pau_qps_created;
0f0bee8b FL	208	extern atomic_t pau_qps_destroyed;
3c2d774c	209
3c2d774c GS	210	extern u32 int_mod_timer_init;
	211	extern u32 int_mod_cq_depth_256;
	212	extern u32 int_mod_cq_depth_128;
	213	extern u32 int_mod_cq_depth_32;
	214	extern u32 int_mod_cq_depth_24;
	215	extern u32 int_mod_cq_depth_16;
	216	extern u32 int_mod_cq_depth_4;
	217	extern u32 int_mod_cq_depth_1;
	218
3c2d774c GS	219	struct nes_device {
	220	struct nes_adapter *nesadapter;
	221	void __iomem *regs;
	222	void __iomem *index_reg;
	223	struct pci_dev *pcidev;
	224	struct net_device *netdev[NES_NIC_MAX_NICS];
	225	u64 link_status_interrupts;
	226	struct tasklet_struct dpc_tasklet;
	227	spinlock_t indexed_regs_lock;
	228	unsigned long csr_start;
	229	unsigned long doorbell_region;
	230	unsigned long doorbell_start;
	231	unsigned long mac_tx_errors;
	232	unsigned long mac_pause_frames_sent;
	233	unsigned long mac_pause_frames_received;
	234	unsigned long mac_rx_errors;
	235	unsigned long mac_rx_crc_errors;
	236	unsigned long mac_rx_symbol_err_frames;
	237	unsigned long mac_rx_jabber_frames;
	238	unsigned long mac_rx_oversized_frames;
	239	unsigned long mac_rx_short_frames;
	240	unsigned long port_rx_discards;
	241	unsigned long port_tx_discards;
	242	unsigned int mac_index;
	243	unsigned int nes_stack_start;
	244
	245	/* Control Structures */
	246	void *cqp_vbase;
	247	dma_addr_t cqp_pbase;
	248	u32 cqp_mem_size;
	249	u8 ceq_index;
	250	u8 nic_ceq_index;
	251	struct nes_hw_cqp cqp;
	252	struct nes_hw_cq ccq;
	253	struct list_head cqp_avail_reqs;
	254	struct list_head cqp_pending_reqs;
	255	struct nes_cqp_request *nes_cqp_requests;
	256
	257	u32 int_req;
	258	u32 int_stat;
	259	u32 timer_int_req;
	260	u32 timer_only_int_count;
	261	u32 intf_int_req;
	262	u32 last_mac_tx_pauses;
	263	u32 last_used_chunks_tx;
	264	struct list_head list;
	265
	266	u16 base_doorbell_index;
	267	u16 currcq_count;
	268	u16 deepcq_count;
cd6860eb	269	u8 iw_status;
3c2d774c GS	270	u8 msi_enabled;
	271	u8 netdev_count;
	272	u8 napi_isr_ran;
	273	u8 disable_rx_flow_control;
	274	u8 disable_tx_flow_control;
5f61b2c6 MS	275
	276	struct delayed_work work;
	277	u8 link_recheck;
3c2d774c GS	278	};
3c2d774c GS	279
0f0bee8b FL	280	/* Receive skb private area - must fit in skb->cb area */
	281	struct nes_rskb_cb {
	282	u64 busaddr;
	283	u32 maplen;
	284	u32 seqnum;
	285	u8 *data_start;
	286	struct nes_qp *nesqp;
	287	};
3c2d774c	288
30da7cff FL	289	static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
	290	{
	291	u32 crc_value;
	292	crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
	293
	294	/*
	295	* With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
	296	* state in cpu order"), behavior of crc32c changes on
	297	* big-endian platforms. Our algorithm expects the previous
	298	* behavior; otherwise we have RDMA connection establishment
	299	* issue on big-endian.
	300	*/
	301	return cpu_to_le32(crc_value);
	302	}
	303
3c2d774c GS	304	static inline void
	305	set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
	306	{
7a5efb62 DW	307	wqe_words[index] = cpu_to_le32((u32) value);
7a5efb62 DW	308	wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
3c2d774c GS	309	}
	310
	311	static inline void
	312	set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
	313	{
	314	wqe_words[index] = cpu_to_le32(value);
	315	}
	316
	317	static inline void
	318	nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe cqp_wqe, struct nes_device nesdev)
	319	{
0f0bee8b FL	320	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = 0;
0f0bee8b FL	321	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
3c2d774c GS	322	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
	323	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
	324	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
	325	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0;
	326	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0;
	327	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0;
	328	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0;
	329	}
	330
	331	static inline void
	332	nes_fill_init_qp_wqe(struct nes_hw_qp_wqe wqe, struct nes_qp nesqp, u32 head)
	333	{
	334	u32 value;
	335	value = ((u32)((unsigned long) nesqp)) \| head;
	336	set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
	337	(u32)(upper_32_bits((unsigned long)(nesqp))));
	338	set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
	339	}
	340
	341	/* Read from memory-mapped device */
	342	static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
	343	{
	344	unsigned long flags;
	345	void __iomem *addr = nesdev->index_reg;
	346	u32 value;
	347
	348	spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
	349
	350	writel(reg_index, addr);
	351	value = readl((void __iomem *)addr + 4);
	352
	353	spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
	354	return value;
	355	}
	356
	357	static inline u32 nes_read32(const void __iomem *addr)
	358	{
	359	return readl(addr);
	360	}
	361
	362	static inline u16 nes_read16(const void __iomem *addr)
	363	{
	364	return readw(addr);
	365	}
	366
	367	static inline u8 nes_read8(const void __iomem *addr)
	368	{
	369	return readb(addr);
	370	}
	371
	372	/* Write to memory-mapped device */
	373	static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
	374	{
	375	unsigned long flags;
	376	void __iomem *addr = nesdev->index_reg;
	377
	378	spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
	379
	380	writel(reg_index, addr);
	381	writel(val, (void __iomem *)addr + 4);
	382
	383	spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
	384	}
	385
386	static inline void nes_write32(void __iomem *addr, u32 val)
387	{
388	writel(val, addr);
389	}
390
391	static inline void nes_write16(void __iomem *addr, u16 val)
392	{
393	writew(val, addr);
394	}
395
396	static inline void nes_write8(void __iomem *addr, u8 val)
397	{
398	writeb(val, addr);
399	}
400
81821644 TN	401	enum nes_resource {
	402	NES_RESOURCE_MW = 1,
	403	NES_RESOURCE_FAST_MR,
	404	NES_RESOURCE_PHYS_MR,
	405	NES_RESOURCE_USER_MR,
	406	NES_RESOURCE_PD,
	407	NES_RESOURCE_QP,
	408	NES_RESOURCE_CQ,
	409	NES_RESOURCE_ARP
	410	};
3c2d774c GS	411
	412	static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
	413	unsigned long *resource_array, u32 max_resources,
81821644	414	u32 req_resource_num, u32 next, enum nes_resource resource_type)
3c2d774c GS	415	{
	416	unsigned long flags;
	417	u32 resource_num;
	418
	419	spin_lock_irqsave(&nesadapter->resource_lock, flags);
	420
	421	resource_num = find_next_zero_bit(resource_array, max_resources, *next);
	422	if (resource_num >= max_resources) {
	423	resource_num = find_first_zero_bit(resource_array, max_resources);
	424	if (resource_num >= max_resources) {
81821644	425	printk(KERN_ERR PFX "%s: No available resources [type=%u].\n", __func__, resource_type);
3c2d774c GS	426	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
	427	return -EMFILE;
	428	}
	429	}
	430	set_bit(resource_num, resource_array);
	431	*next = resource_num+1;
	432	if (*next == max_resources) {
	433	*next = 0;
	434	}
	435	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
	436	*req_resource_num = resource_num;
	437
	438	return 0;
	439	}
	440
	441	static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
	442	unsigned long *resource_array, u32 resource_num)
	443	{
	444	unsigned long flags;
	445	int bit_is_set;
	446
	447	spin_lock_irqsave(&nesadapter->resource_lock, flags);
	448
	449	bit_is_set = test_bit(resource_num, resource_array);
	450	nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
	451	resource_num, (bit_is_set ? "": " not"));
	452	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
	453
	454	return bit_is_set;
	455	}
	456
	457	static inline void nes_free_resource(struct nes_adapter *nesadapter,
	458	unsigned long *resource_array, u32 resource_num)
	459	{
	460	unsigned long flags;
	461
	462	spin_lock_irqsave(&nesadapter->resource_lock, flags);
	463	clear_bit(resource_num, resource_array);
	464	spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
	465	}
	466
	467	static inline struct nes_vnic to_nesvnic(struct ib_device ibdev)
	468	{
	469	return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
	470	}
	471
	472	static inline struct nes_pd to_nespd(struct ib_pd ibpd)
	473	{
	474	return container_of(ibpd, struct nes_pd, ibpd);
	475	}
	476
	477	static inline struct nes_ucontext to_nesucontext(struct ib_ucontext ibucontext)
	478	{
	479	return container_of(ibucontext, struct nes_ucontext, ibucontext);
	480	}
	481
	482	static inline struct nes_mr to_nesmr(struct ib_mr ibmr)
	483	{
	484	return container_of(ibmr, struct nes_mr, ibmr);
	485	}
	486
	487	static inline struct nes_mr to_nesmr_from_ibfmr(struct ib_fmr ibfmr)
	488	{
	489	return container_of(ibfmr, struct nes_mr, ibfmr);
490	}
491
492	static inline struct nes_mr to_nesmw(struct ib_mw ibmw)
493	{
494	return container_of(ibmw, struct nes_mr, ibmw);
495	}
496
497	static inline struct nes_fmr to_nesfmr(struct nes_mr nesmr)
498	{
499	return container_of(nesmr, struct nes_fmr, nesmr);
500	}
501
502	static inline struct nes_cq to_nescq(struct ib_cq ibcq)
503	{
504	return container_of(ibcq, struct nes_cq, ibcq);
505	}
506
507	static inline struct nes_qp to_nesqp(struct ib_qp ibqp)
508	{
509	return container_of(ibqp, struct nes_qp, ibqp);
510	}
511
512
513
514	/* nes.c */
515	void nes_add_ref(struct ib_qp *);
516	void nes_rem_ref(struct ib_qp *);
517	struct ib_qp nes_get_qp(struct ib_device , int);
518
519
520	/* nes_hw.c */
521	struct nes_adapter nes_init_adapter(struct nes_device , u8);
522	void nes_nic_init_timer_defaults(struct nes_device *, u8);
3c2d774c GS	523	void nes_destroy_adapter(struct nes_adapter *);
	524	int nes_init_cqp(struct nes_device *);
	525	int nes_init_phy(struct nes_device *);
	526	int nes_init_nic_qp(struct nes_device , struct net_device );
	527	void nes_destroy_nic_qp(struct nes_vnic *);
	528	int nes_napi_isr(struct nes_device *);
	529	void nes_dpc(unsigned long);
3c2d774c	530	void nes_nic_ce_handler(struct nes_device , struct nes_hw_nic_cq );
3c2d774c GS	531	void nes_iwarp_ce_handler(struct nes_device , struct nes_hw_cq );
	532	int nes_destroy_cqp(struct nes_device *);
	533	int nes_nic_cm_xmit(struct sk_buff , struct net_device );
5f61b2c6	534	void nes_recheck_link_status(struct work_struct *work);
7bfcfa51	535	void nes_terminate_timeout(unsigned long context);
3c2d774c GS	536
3c2d774c GS	537	/* nes_nic.c */
3c2d774c GS	538	struct net_device nes_netdev_init(struct nes_device , void __iomem *);
	539	void nes_netdev_destroy(struct net_device *);
	540	int nes_nic_cm_xmit(struct sk_buff , struct net_device );
	541
	542	/* nes_cm.c */
	543	void nes_cm_create(struct net_device );
	544	int nes_cm_recv(struct sk_buff , struct net_device );
	545	void nes_update_arp(unsigned char *, u32, u32, u16, u16);
	546	void nes_manage_arp_cache(struct net_device , unsigned char , u32, u32);
	547	void nes_sock_release(struct nes_qp , unsigned long );
3c2d774c GS	548	void flush_wqes(struct nes_device nesdev, struct nes_qp , u32, u32);
	549	int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
	550	int nes_cm_disconn(struct nes_qp *);
	551	void nes_cm_disconn_worker(void *);
	552
	553	/* nes_verbs.c */
8b1c9dc4	554	int nes_hw_modify_qp(struct nes_device , struct nes_qp , u32, u32, u32);
3c2d774c GS	555	int nes_modify_qp(struct ib_qp , struct ib_qp_attr , int, struct ib_udata *);
3c2d774c GS	556	struct nes_ib_device nes_init_ofa_device(struct net_device );
cd6860eb	557	void nes_port_ibevent(struct nes_vnic *nesvnic);
3c2d774c GS	558	void nes_destroy_ofa_device(struct nes_ib_device *);
3c2d774c GS	559	int nes_register_ofa_device(struct nes_ib_device *);
3c2d774c GS	560
	561	/* nes_util.c */
	562	int nes_read_eeprom_values(struct nes_device , struct nes_adapter );
	563	void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
	564	void nes_read_1G_phy_reg(struct nes_device , u8, u8, u16 );
0e1de5d6 ES	565	void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
0e1de5d6 ES	566	void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
3c2d774c	567	struct nes_cqp_request nes_get_cqp_request(struct nes_device );
1ff66e8c RD	568	void nes_free_cqp_request(struct nes_device *nesdev,
	569	struct nes_cqp_request *cqp_request);
	570	void nes_put_cqp_request(struct nes_device *nesdev,
	571	struct nes_cqp_request *cqp_request);
8294f297	572	void nes_post_cqp_request(struct nes_device , struct nes_cqp_request );
3c2d774c GS	573	int nes_arp_table(struct nes_device , u32, u8 , u32);
	574	void nes_mh_fix(unsigned long);
	575	void nes_clc(unsigned long);
	576	void nes_dump_mem(unsigned int, void *, int);
	577	u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
	578
	579	#endif /* __NES_H */