Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
7e044e05 | 13 | #include <linux/types.h> |
1da177e4 LT |
14 | #include <linux/delay.h> |
15 | #include <linux/module.h> | |
1da177e4 LT |
16 | #include <linux/interrupt.h> |
17 | #include <linux/ioport.h> | |
1da177e4 LT |
18 | #include <linux/init.h> |
19 | #include <linux/serio.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/rcupdate.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
553a05b8 | 23 | #include <linux/i8042.h> |
1da177e4 LT |
24 | |
25 | #include <asm/io.h> | |
26 | ||
27 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
28 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
29 | MODULE_LICENSE("GPL"); | |
30 | ||
386b3849 | 31 | static bool i8042_nokbd; |
945ef0d4 DT |
32 | module_param_named(nokbd, i8042_nokbd, bool, 0); |
33 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
34 | ||
386b3849 | 35 | static bool i8042_noaux; |
1da177e4 LT |
36 | module_param_named(noaux, i8042_noaux, bool, 0); |
37 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
38 | ||
386b3849 | 39 | static bool i8042_nomux; |
1da177e4 LT |
40 | module_param_named(nomux, i8042_nomux, bool, 0); |
41 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); | |
42 | ||
386b3849 | 43 | static bool i8042_unlock; |
1da177e4 LT |
44 | module_param_named(unlock, i8042_unlock, bool, 0); |
45 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
46 | ||
386b3849 | 47 | static bool i8042_reset; |
1da177e4 LT |
48 | module_param_named(reset, i8042_reset, bool, 0); |
49 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
50 | ||
386b3849 | 51 | static bool i8042_direct; |
1da177e4 LT |
52 | module_param_named(direct, i8042_direct, bool, 0); |
53 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
54 | ||
386b3849 | 55 | static bool i8042_dumbkbd; |
1da177e4 LT |
56 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); |
57 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
58 | ||
386b3849 | 59 | static bool i8042_noloop; |
1da177e4 LT |
60 | module_param_named(noloop, i8042_noloop, bool, 0); |
61 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
62 | ||
63 | static unsigned int i8042_blink_frequency = 500; | |
64 | module_param_named(panicblink, i8042_blink_frequency, uint, 0600); | |
65 | MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); | |
66 | ||
8987fec0 | 67 | #ifdef CONFIG_X86 |
386b3849 | 68 | static bool i8042_dritek; |
8987fec0 CC |
69 | module_param_named(dritek, i8042_dritek, bool, 0); |
70 | MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); | |
71 | #endif | |
72 | ||
1da177e4 | 73 | #ifdef CONFIG_PNP |
386b3849 | 74 | static bool i8042_nopnp; |
1da177e4 LT |
75 | module_param_named(nopnp, i8042_nopnp, bool, 0); |
76 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
77 | #endif | |
78 | ||
79 | #define DEBUG | |
80 | #ifdef DEBUG | |
386b3849 | 81 | static bool i8042_debug; |
1da177e4 LT |
82 | module_param_named(debug, i8042_debug, bool, 0600); |
83 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
84 | #endif | |
85 | ||
1c7827ae DT |
86 | static bool i8042_bypass_aux_irq_test; |
87 | ||
1da177e4 LT |
88 | #include "i8042.h" |
89 | ||
181d683d DT |
90 | /* |
91 | * i8042_lock protects serialization between i8042_command and | |
92 | * the interrupt handler. | |
93 | */ | |
1da177e4 LT |
94 | static DEFINE_SPINLOCK(i8042_lock); |
95 | ||
181d683d DT |
96 | /* |
97 | * Writers to AUX and KBD ports as well as users issuing i8042_command | |
98 | * directly should acquire i8042_mutex (by means of calling | |
99 | * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that | |
100 | * they do not disturb each other (unfortunately in many i8042 | |
101 | * implementations write to one of the ports will immediately abort | |
102 | * command that is being processed by another port). | |
103 | */ | |
104 | static DEFINE_MUTEX(i8042_mutex); | |
105 | ||
1da177e4 LT |
106 | struct i8042_port { |
107 | struct serio *serio; | |
108 | int irq; | |
386b3849 | 109 | bool exists; |
1da177e4 | 110 | signed char mux; |
1da177e4 LT |
111 | }; |
112 | ||
113 | #define I8042_KBD_PORT_NO 0 | |
114 | #define I8042_AUX_PORT_NO 1 | |
115 | #define I8042_MUX_PORT_NO 2 | |
116 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
117 | |
118 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
119 | |
120 | static unsigned char i8042_initial_ctr; | |
121 | static unsigned char i8042_ctr; | |
386b3849 DT |
122 | static bool i8042_mux_present; |
123 | static bool i8042_kbd_irq_registered; | |
124 | static bool i8042_aux_irq_registered; | |
817e6ba3 | 125 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 LT |
126 | static struct platform_device *i8042_platform_device; |
127 | ||
7d12e780 | 128 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
1da177e4 | 129 | |
181d683d DT |
130 | void i8042_lock_chip(void) |
131 | { | |
132 | mutex_lock(&i8042_mutex); | |
133 | } | |
134 | EXPORT_SYMBOL(i8042_lock_chip); | |
135 | ||
136 | void i8042_unlock_chip(void) | |
137 | { | |
138 | mutex_unlock(&i8042_mutex); | |
139 | } | |
140 | EXPORT_SYMBOL(i8042_unlock_chip); | |
141 | ||
1da177e4 LT |
142 | /* |
143 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
144 | * be ready for reading values from it / writing values to it. | |
145 | * Called always with i8042_lock held. | |
146 | */ | |
147 | ||
148 | static int i8042_wait_read(void) | |
149 | { | |
150 | int i = 0; | |
de9ce703 | 151 | |
1da177e4 LT |
152 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
153 | udelay(50); | |
154 | i++; | |
155 | } | |
156 | return -(i == I8042_CTL_TIMEOUT); | |
157 | } | |
158 | ||
159 | static int i8042_wait_write(void) | |
160 | { | |
161 | int i = 0; | |
de9ce703 | 162 | |
1da177e4 LT |
163 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
164 | udelay(50); | |
165 | i++; | |
166 | } | |
167 | return -(i == I8042_CTL_TIMEOUT); | |
168 | } | |
169 | ||
170 | /* | |
171 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
172 | * of the i8042 down the toilet. | |
173 | */ | |
174 | ||
175 | static int i8042_flush(void) | |
176 | { | |
177 | unsigned long flags; | |
178 | unsigned char data, str; | |
179 | int i = 0; | |
180 | ||
181 | spin_lock_irqsave(&i8042_lock, flags); | |
182 | ||
183 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
184 | udelay(50); | |
185 | data = i8042_read_data(); | |
186 | i++; | |
187 | dbg("%02x <- i8042 (flush, %s)", data, | |
188 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
189 | } | |
190 | ||
191 | spin_unlock_irqrestore(&i8042_lock, flags); | |
192 | ||
193 | return i; | |
194 | } | |
195 | ||
196 | /* | |
197 | * i8042_command() executes a command on the i8042. It also sends the input | |
198 | * parameter(s) of the commands to it, and receives the output value(s). The | |
199 | * parameters are to be stored in the param array, and the output is placed | |
200 | * into the same array. The number of the parameters and output values is | |
201 | * encoded in bits 8-11 of the command number. | |
202 | */ | |
203 | ||
de9ce703 | 204 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 205 | { |
de9ce703 | 206 | int i, error; |
1da177e4 LT |
207 | |
208 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
209 | return -1; | |
210 | ||
de9ce703 DT |
211 | error = i8042_wait_write(); |
212 | if (error) | |
213 | return error; | |
463a4f76 DT |
214 | |
215 | dbg("%02x -> i8042 (command)", command & 0xff); | |
216 | i8042_write_command(command & 0xff); | |
217 | ||
218 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 DT |
219 | error = i8042_wait_write(); |
220 | if (error) | |
221 | return error; | |
463a4f76 DT |
222 | dbg("%02x -> i8042 (parameter)", param[i]); |
223 | i8042_write_data(param[i]); | |
1da177e4 LT |
224 | } |
225 | ||
463a4f76 | 226 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
227 | error = i8042_wait_read(); |
228 | if (error) { | |
229 | dbg(" -- i8042 (timeout)"); | |
230 | return error; | |
231 | } | |
1da177e4 | 232 | |
463a4f76 DT |
233 | if (command == I8042_CMD_AUX_LOOP && |
234 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
de9ce703 DT |
235 | dbg(" -- i8042 (auxerr)"); |
236 | return -1; | |
1da177e4 LT |
237 | } |
238 | ||
463a4f76 DT |
239 | param[i] = i8042_read_data(); |
240 | dbg("%02x <- i8042 (return)", param[i]); | |
241 | } | |
1da177e4 | 242 | |
de9ce703 DT |
243 | return 0; |
244 | } | |
1da177e4 | 245 | |
553a05b8 | 246 | int i8042_command(unsigned char *param, int command) |
de9ce703 DT |
247 | { |
248 | unsigned long flags; | |
249 | int retval; | |
250 | ||
251 | spin_lock_irqsave(&i8042_lock, flags); | |
252 | retval = __i8042_command(param, command); | |
463a4f76 | 253 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 254 | |
1da177e4 LT |
255 | return retval; |
256 | } | |
553a05b8 | 257 | EXPORT_SYMBOL(i8042_command); |
1da177e4 LT |
258 | |
259 | /* | |
260 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
261 | */ | |
262 | ||
263 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
264 | { | |
265 | unsigned long flags; | |
266 | int retval = 0; | |
267 | ||
268 | spin_lock_irqsave(&i8042_lock, flags); | |
269 | ||
de9ce703 | 270 | if (!(retval = i8042_wait_write())) { |
1da177e4 LT |
271 | dbg("%02x -> i8042 (kbd-data)", c); |
272 | i8042_write_data(c); | |
273 | } | |
274 | ||
275 | spin_unlock_irqrestore(&i8042_lock, flags); | |
276 | ||
277 | return retval; | |
278 | } | |
279 | ||
280 | /* | |
281 | * i8042_aux_write() sends a byte out through the aux interface. | |
282 | */ | |
283 | ||
284 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
285 | { | |
286 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 287 | |
f4e3c711 DT |
288 | return i8042_command(&c, port->mux == -1 ? |
289 | I8042_CMD_AUX_SEND : | |
290 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
291 | } |
292 | ||
5ddbc77c DT |
293 | |
294 | /* | |
295 | * i8042_aux_close attempts to clear AUX or KBD port state by disabling | |
296 | * and then re-enabling it. | |
297 | */ | |
298 | ||
299 | static void i8042_port_close(struct serio *serio) | |
300 | { | |
301 | int irq_bit; | |
302 | int disable_bit; | |
303 | const char *port_name; | |
304 | ||
305 | if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { | |
306 | irq_bit = I8042_CTR_AUXINT; | |
307 | disable_bit = I8042_CTR_AUXDIS; | |
308 | port_name = "AUX"; | |
309 | } else { | |
310 | irq_bit = I8042_CTR_KBDINT; | |
311 | disable_bit = I8042_CTR_KBDDIS; | |
312 | port_name = "KBD"; | |
313 | } | |
314 | ||
315 | i8042_ctr &= ~irq_bit; | |
316 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
317 | printk(KERN_WARNING | |
318 | "i8042.c: Can't write CTR while closing %s port.\n", | |
319 | port_name); | |
320 | ||
321 | udelay(50); | |
322 | ||
323 | i8042_ctr &= ~disable_bit; | |
324 | i8042_ctr |= irq_bit; | |
325 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
326 | printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", | |
327 | port_name); | |
328 | ||
329 | /* | |
330 | * See if there is any data appeared while we were messing with | |
331 | * port state. | |
332 | */ | |
333 | i8042_interrupt(0, NULL); | |
334 | } | |
335 | ||
1da177e4 LT |
336 | /* |
337 | * i8042_start() is called by serio core when port is about to finish | |
338 | * registering. It will mark port as existing so i8042_interrupt can | |
339 | * start sending data through it. | |
340 | */ | |
341 | static int i8042_start(struct serio *serio) | |
342 | { | |
343 | struct i8042_port *port = serio->port_data; | |
344 | ||
386b3849 | 345 | port->exists = true; |
1da177e4 LT |
346 | mb(); |
347 | return 0; | |
348 | } | |
349 | ||
350 | /* | |
351 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
352 | * will not try to send data to the port that is about to go away. | |
353 | * The function is called by serio core as part of unregister procedure. | |
354 | */ | |
355 | static void i8042_stop(struct serio *serio) | |
356 | { | |
357 | struct i8042_port *port = serio->port_data; | |
358 | ||
386b3849 | 359 | port->exists = false; |
a8399c51 DT |
360 | |
361 | /* | |
362 | * We synchronize with both AUX and KBD IRQs because there is | |
363 | * a (very unlikely) chance that AUX IRQ is raised for KBD port | |
364 | * and vice versa. | |
365 | */ | |
366 | synchronize_irq(I8042_AUX_IRQ); | |
367 | synchronize_irq(I8042_KBD_IRQ); | |
1da177e4 LT |
368 | port->serio = NULL; |
369 | } | |
370 | ||
371 | /* | |
372 | * i8042_interrupt() is the most important function in this driver - | |
373 | * it handles the interrupts from the i8042, and sends incoming bytes | |
374 | * to the upper layers. | |
375 | */ | |
376 | ||
7d12e780 | 377 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
378 | { |
379 | struct i8042_port *port; | |
380 | unsigned long flags; | |
381 | unsigned char str, data; | |
382 | unsigned int dfl; | |
383 | unsigned int port_no; | |
817e6ba3 | 384 | int ret = 1; |
1da177e4 | 385 | |
1da177e4 LT |
386 | spin_lock_irqsave(&i8042_lock, flags); |
387 | str = i8042_read_status(); | |
388 | if (unlikely(~str & I8042_STR_OBF)) { | |
389 | spin_unlock_irqrestore(&i8042_lock, flags); | |
390 | if (irq) dbg("Interrupt %d, without any data", irq); | |
391 | ret = 0; | |
392 | goto out; | |
393 | } | |
394 | data = i8042_read_data(); | |
395 | spin_unlock_irqrestore(&i8042_lock, flags); | |
396 | ||
397 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
398 | static unsigned long last_transmit; | |
399 | static unsigned char last_str; | |
400 | ||
401 | dfl = 0; | |
402 | if (str & I8042_STR_MUXERR) { | |
403 | dbg("MUX error, status is %02x, data is %02x", str, data); | |
1da177e4 LT |
404 | /* |
405 | * When MUXERR condition is signalled the data register can only contain | |
406 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
407 | * it is not always the case. Some KBCs also report 0xfc when there is |
408 | * nothing connected to the port while others sometimes get confused which | |
409 | * port the data came from and signal error leaving the data intact. They | |
410 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
411 | * to legacy mode yet, when we see one we'll add proper handling). | |
412 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
413 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
414 | * was transmitted (if transmission happened not too long ago). |
415 | */ | |
a216a4b6 DT |
416 | |
417 | switch (data) { | |
418 | default: | |
1da177e4 LT |
419 | if (time_before(jiffies, last_transmit + HZ/10)) { |
420 | str = last_str; | |
421 | break; | |
422 | } | |
423 | /* fall through - report timeout */ | |
a216a4b6 | 424 | case 0xfc: |
1da177e4 LT |
425 | case 0xfd: |
426 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
427 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
428 | } | |
429 | } | |
430 | ||
431 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
432 | last_str = str; | |
433 | last_transmit = jiffies; | |
434 | } else { | |
435 | ||
436 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
437 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
438 | ||
439 | port_no = (str & I8042_STR_AUXDATA) ? | |
440 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
441 | } | |
442 | ||
443 | port = &i8042_ports[port_no]; | |
444 | ||
de9ce703 DT |
445 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", |
446 | data, port_no, irq, | |
1da177e4 LT |
447 | dfl & SERIO_PARITY ? ", bad parity" : "", |
448 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
449 | ||
817e6ba3 DT |
450 | if (unlikely(i8042_suppress_kbd_ack)) |
451 | if (port_no == I8042_KBD_PORT_NO && | |
452 | (data == 0xfa || data == 0xfe)) { | |
19f3c3e3 | 453 | i8042_suppress_kbd_ack--; |
817e6ba3 DT |
454 | goto out; |
455 | } | |
456 | ||
1da177e4 | 457 | if (likely(port->exists)) |
7d12e780 | 458 | serio_interrupt(port->serio, data, dfl); |
1da177e4 | 459 | |
0854e52d | 460 | out: |
1da177e4 LT |
461 | return IRQ_RETVAL(ret); |
462 | } | |
463 | ||
de9ce703 | 464 | /* |
5ddbc77c | 465 | * i8042_enable_kbd_port enables keyboard port on chip |
de9ce703 DT |
466 | */ |
467 | ||
468 | static int i8042_enable_kbd_port(void) | |
469 | { | |
470 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
471 | i8042_ctr |= I8042_CTR_KBDINT; | |
472 | ||
473 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
474 | i8042_ctr &= ~I8042_CTR_KBDINT; |
475 | i8042_ctr |= I8042_CTR_KBDDIS; | |
de9ce703 DT |
476 | printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); |
477 | return -EIO; | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | /* | |
484 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
485 | */ | |
486 | ||
487 | static int i8042_enable_aux_port(void) | |
488 | { | |
489 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
490 | i8042_ctr |= I8042_CTR_AUXINT; | |
491 | ||
492 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
493 | i8042_ctr &= ~I8042_CTR_AUXINT; |
494 | i8042_ctr |= I8042_CTR_AUXDIS; | |
de9ce703 DT |
495 | printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); |
496 | return -EIO; | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | /* | |
503 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
504 | * the controller has been switched into Multiplexed mode | |
505 | */ | |
506 | ||
507 | static int i8042_enable_mux_ports(void) | |
508 | { | |
509 | unsigned char param; | |
510 | int i; | |
511 | ||
512 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
513 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
514 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
515 | } | |
516 | ||
517 | return i8042_enable_aux_port(); | |
518 | } | |
519 | ||
1da177e4 | 520 | /* |
386b3849 DT |
521 | * i8042_set_mux_mode checks whether the controller has an |
522 | * active multiplexor and puts the chip into Multiplexed (true) | |
523 | * or Legacy (false) mode. | |
1da177e4 LT |
524 | */ |
525 | ||
386b3849 | 526 | static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) |
1da177e4 LT |
527 | { |
528 | ||
386b3849 | 529 | unsigned char param, val; |
1da177e4 LT |
530 | /* |
531 | * Get rid of bytes in the queue. | |
532 | */ | |
533 | ||
534 | i8042_flush(); | |
535 | ||
536 | /* | |
537 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 538 | * mouse interface, the last should be version. |
1da177e4 LT |
539 | */ |
540 | ||
386b3849 DT |
541 | param = val = 0xf0; |
542 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
543 | return -1; | |
544 | param = val = multiplex ? 0x56 : 0xf6; | |
545 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
1da177e4 | 546 | return -1; |
386b3849 DT |
547 | param = val = multiplex ? 0xa4 : 0xa5; |
548 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) | |
1da177e4 | 549 | return -1; |
386b3849 DT |
550 | |
551 | /* | |
552 | * Workaround for interference with USB Legacy emulation | |
553 | * that causes a v10.12 MUX to be found. | |
554 | */ | |
555 | if (param == 0xac) | |
1da177e4 LT |
556 | return -1; |
557 | ||
558 | if (mux_version) | |
463a4f76 | 559 | *mux_version = param; |
1da177e4 LT |
560 | |
561 | return 0; | |
562 | } | |
563 | ||
1da177e4 | 564 | /* |
de9ce703 DT |
565 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
566 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
567 | * LCS/Telegraphics. | |
1da177e4 LT |
568 | */ |
569 | ||
f8113416 | 570 | static int __init i8042_check_mux(void) |
1da177e4 | 571 | { |
de9ce703 DT |
572 | unsigned char mux_version; |
573 | ||
386b3849 | 574 | if (i8042_set_mux_mode(true, &mux_version)) |
de9ce703 DT |
575 | return -1; |
576 | ||
577 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | |
578 | (mux_version >> 4) & 0xf, mux_version & 0xf); | |
1da177e4 | 579 | |
de9ce703 DT |
580 | /* |
581 | * Disable all muxed ports by disabling AUX. | |
582 | */ | |
1da177e4 LT |
583 | i8042_ctr |= I8042_CTR_AUXDIS; |
584 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
585 | ||
586 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
587 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | |
de9ce703 | 588 | return -EIO; |
1da177e4 LT |
589 | } |
590 | ||
386b3849 | 591 | i8042_mux_present = true; |
1da177e4 LT |
592 | |
593 | return 0; | |
594 | } | |
595 | ||
1da177e4 | 596 | /* |
de9ce703 | 597 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 598 | */ |
f8113416 DT |
599 | static struct completion i8042_aux_irq_delivered __initdata; |
600 | static bool i8042_irq_being_tested __initdata; | |
1da177e4 | 601 | |
f8113416 | 602 | static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 603 | { |
de9ce703 DT |
604 | unsigned long flags; |
605 | unsigned char str, data; | |
e3758b2a | 606 | int ret = 0; |
1da177e4 | 607 | |
de9ce703 DT |
608 | spin_lock_irqsave(&i8042_lock, flags); |
609 | str = i8042_read_status(); | |
610 | if (str & I8042_STR_OBF) { | |
611 | data = i8042_read_data(); | |
d3d2dfe2 DT |
612 | dbg("%02x <- i8042 (aux_test_irq, %s)", |
613 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
de9ce703 DT |
614 | if (i8042_irq_being_tested && |
615 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
616 | complete(&i8042_aux_irq_delivered); | |
e3758b2a | 617 | ret = 1; |
de9ce703 DT |
618 | } |
619 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 620 | |
e3758b2a | 621 | return IRQ_RETVAL(ret); |
1da177e4 LT |
622 | } |
623 | ||
d2ada559 RS |
624 | /* |
625 | * i8042_toggle_aux - enables or disables AUX port on i8042 via command and | |
626 | * verifies success by readinng CTR. Used when testing for presence of AUX | |
627 | * port. | |
628 | */ | |
f8113416 | 629 | static int __init i8042_toggle_aux(bool on) |
d2ada559 RS |
630 | { |
631 | unsigned char param; | |
632 | int i; | |
633 | ||
634 | if (i8042_command(¶m, | |
635 | on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) | |
636 | return -1; | |
637 | ||
638 | /* some chips need some time to set the I8042_CTR_AUXDIS bit */ | |
639 | for (i = 0; i < 100; i++) { | |
640 | udelay(50); | |
641 | ||
642 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) | |
643 | return -1; | |
644 | ||
645 | if (!(param & I8042_CTR_AUXDIS) == on) | |
646 | return 0; | |
647 | } | |
648 | ||
649 | return -1; | |
650 | } | |
1da177e4 LT |
651 | |
652 | /* | |
653 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
654 | * the presence of an AUX interface. | |
655 | */ | |
656 | ||
f8113416 | 657 | static int __init i8042_check_aux(void) |
1da177e4 | 658 | { |
de9ce703 | 659 | int retval = -1; |
386b3849 DT |
660 | bool irq_registered = false; |
661 | bool aux_loop_broken = false; | |
de9ce703 | 662 | unsigned long flags; |
1da177e4 | 663 | unsigned char param; |
1da177e4 LT |
664 | |
665 | /* | |
666 | * Get rid of bytes in the queue. | |
667 | */ | |
668 | ||
669 | i8042_flush(); | |
670 | ||
671 | /* | |
672 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
673 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
674 | * though it has an AUX port. | |
675 | */ | |
676 | ||
677 | param = 0x5a; | |
3ca5de6d DT |
678 | retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); |
679 | if (retval || param != 0x5a) { | |
1da177e4 LT |
680 | |
681 | /* | |
682 | * External connection test - filters out AT-soldered PS/2 i8042's | |
683 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
684 | * 0xfa - no error on some notebooks which ignore the spec | |
685 | * Because it's common for chipsets to return error on perfectly functioning | |
686 | * AUX ports, we test for this only when the LOOP command failed. | |
687 | */ | |
688 | ||
de9ce703 DT |
689 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
690 | (param && param != 0xfa && param != 0xff)) | |
691 | return -1; | |
1e4865f8 | 692 | |
3ca5de6d DT |
693 | /* |
694 | * If AUX_LOOP completed without error but returned unexpected data | |
695 | * mark it as broken | |
696 | */ | |
697 | if (!retval) | |
386b3849 | 698 | aux_loop_broken = true; |
1da177e4 LT |
699 | } |
700 | ||
701 | /* | |
702 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
703 | */ | |
704 | ||
386b3849 | 705 | if (i8042_toggle_aux(false)) { |
1da177e4 LT |
706 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
707 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | |
708 | } | |
709 | ||
386b3849 | 710 | if (i8042_toggle_aux(true)) |
1da177e4 LT |
711 | return -1; |
712 | ||
713 | /* | |
de9ce703 DT |
714 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
715 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
716 | */ |
717 | ||
1c7827ae | 718 | if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { |
de9ce703 DT |
719 | /* |
720 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
721 | * is working and hope we are right. | |
722 | */ | |
723 | retval = 0; | |
724 | goto out; | |
725 | } | |
1da177e4 | 726 | |
de9ce703 DT |
727 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
728 | "i8042", i8042_platform_device)) | |
729 | goto out; | |
1da177e4 | 730 | |
386b3849 | 731 | irq_registered = true; |
de9ce703 DT |
732 | |
733 | if (i8042_enable_aux_port()) | |
734 | goto out; | |
735 | ||
736 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 737 | |
de9ce703 | 738 | init_completion(&i8042_aux_irq_delivered); |
386b3849 | 739 | i8042_irq_being_tested = true; |
de9ce703 DT |
740 | |
741 | param = 0xa5; | |
742 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
743 | ||
744 | spin_unlock_irqrestore(&i8042_lock, flags); | |
745 | ||
746 | if (retval) | |
747 | goto out; | |
1da177e4 | 748 | |
de9ce703 DT |
749 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
750 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 751 | /* |
de9ce703 DT |
752 | * AUX IRQ was never delivered so we need to flush the controller to |
753 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 754 | */ |
d3d2dfe2 | 755 | dbg(" -- i8042 (aux irq test timeout)"); |
de9ce703 DT |
756 | i8042_flush(); |
757 | retval = -1; | |
758 | } | |
1da177e4 | 759 | |
de9ce703 | 760 | out: |
1da177e4 | 761 | |
de9ce703 DT |
762 | /* |
763 | * Disable the interface. | |
764 | */ | |
1da177e4 | 765 | |
de9ce703 DT |
766 | i8042_ctr |= I8042_CTR_AUXDIS; |
767 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 768 | |
de9ce703 DT |
769 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
770 | retval = -1; | |
1da177e4 | 771 | |
de9ce703 DT |
772 | if (irq_registered) |
773 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 774 | |
de9ce703 DT |
775 | return retval; |
776 | } | |
1da177e4 | 777 | |
de9ce703 | 778 | static int i8042_controller_check(void) |
1da177e4 | 779 | { |
de9ce703 DT |
780 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
781 | printk(KERN_ERR "i8042.c: No controller found.\n"); | |
782 | return -ENODEV; | |
783 | } | |
784 | ||
785 | return 0; | |
1da177e4 LT |
786 | } |
787 | ||
de9ce703 | 788 | static int i8042_controller_selftest(void) |
2673c836 VP |
789 | { |
790 | unsigned char param; | |
5ea2fc64 | 791 | int i = 0; |
2673c836 VP |
792 | |
793 | if (!i8042_reset) | |
794 | return 0; | |
795 | ||
5ea2fc64 AV |
796 | /* |
797 | * We try this 5 times; on some really fragile systems this does not | |
798 | * take the first time... | |
799 | */ | |
800 | do { | |
801 | ||
802 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
803 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | |
804 | return -ENODEV; | |
805 | } | |
806 | ||
807 | if (param == I8042_RET_CTL_TEST) | |
808 | return 0; | |
2673c836 | 809 | |
2673c836 | 810 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", |
5ea2fc64 AV |
811 | param, I8042_RET_CTL_TEST); |
812 | msleep(50); | |
813 | } while (i++ < 5); | |
2673c836 | 814 | |
5ea2fc64 AV |
815 | #ifdef CONFIG_X86 |
816 | /* | |
817 | * On x86, we don't fail entire i8042 initialization if controller | |
818 | * reset fails in hopes that keyboard port will still be functional | |
819 | * and user will still get a working keyboard. This is especially | |
820 | * important on netbooks. On other arches we trust hardware more. | |
821 | */ | |
822 | printk(KERN_INFO | |
823 | "i8042: giving up on controller selftest, continuing anyway...\n"); | |
2673c836 | 824 | return 0; |
5ea2fc64 AV |
825 | #else |
826 | return -EIO; | |
827 | #endif | |
2673c836 | 828 | } |
1da177e4 LT |
829 | |
830 | /* | |
831 | * i8042_controller init initializes the i8042 controller, and, | |
832 | * most importantly, sets it into non-xlated mode if that's | |
833 | * desired. | |
834 | */ | |
835 | ||
836 | static int i8042_controller_init(void) | |
837 | { | |
838 | unsigned long flags; | |
839 | ||
1da177e4 LT |
840 | /* |
841 | * Save the CTR for restoral on unload / reboot. | |
842 | */ | |
843 | ||
844 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { | |
845 | printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); | |
de9ce703 | 846 | return -EIO; |
1da177e4 LT |
847 | } |
848 | ||
849 | i8042_initial_ctr = i8042_ctr; | |
850 | ||
851 | /* | |
852 | * Disable the keyboard interface and interrupt. | |
853 | */ | |
854 | ||
855 | i8042_ctr |= I8042_CTR_KBDDIS; | |
856 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
857 | ||
858 | /* | |
859 | * Handle keylock. | |
860 | */ | |
861 | ||
862 | spin_lock_irqsave(&i8042_lock, flags); | |
863 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
864 | if (i8042_unlock) | |
865 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
82dd9eff | 866 | else |
1da177e4 LT |
867 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); |
868 | } | |
869 | spin_unlock_irqrestore(&i8042_lock, flags); | |
870 | ||
871 | /* | |
872 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
873 | * bother enabling translating and be happy. | |
874 | */ | |
875 | ||
876 | if (~i8042_ctr & I8042_CTR_XLATE) | |
386b3849 | 877 | i8042_direct = true; |
1da177e4 LT |
878 | |
879 | /* | |
880 | * Set nontranslated mode for the kbd interface if requested by an option. | |
881 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
882 | * interface is. We don't do this by default, since it can confuse notebook | |
883 | * BIOSes. | |
884 | */ | |
885 | ||
886 | if (i8042_direct) | |
887 | i8042_ctr &= ~I8042_CTR_XLATE; | |
888 | ||
889 | /* | |
890 | * Write CTR back. | |
891 | */ | |
892 | ||
893 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
894 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | |
de9ce703 | 895 | return -EIO; |
1da177e4 LT |
896 | } |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | ||
902 | /* | |
de9ce703 | 903 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 904 | */ |
de9ce703 | 905 | |
1da177e4 LT |
906 | static void i8042_controller_reset(void) |
907 | { | |
de9ce703 | 908 | i8042_flush(); |
1da177e4 | 909 | |
8d04ddb6 DT |
910 | /* |
911 | * Disable both KBD and AUX interfaces so they don't get in the way | |
912 | */ | |
913 | ||
914 | i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; | |
915 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | |
916 | ||
5ddbc77c DT |
917 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) |
918 | printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); | |
919 | ||
1da177e4 LT |
920 | /* |
921 | * Disable MUX mode if present. | |
922 | */ | |
923 | ||
924 | if (i8042_mux_present) | |
386b3849 | 925 | i8042_set_mux_mode(false, NULL); |
1da177e4 LT |
926 | |
927 | /* | |
de9ce703 | 928 | * Reset the controller if requested. |
1da177e4 LT |
929 | */ |
930 | ||
de9ce703 | 931 | i8042_controller_selftest(); |
1da177e4 | 932 | |
de9ce703 DT |
933 | /* |
934 | * Restore the original control register setting. | |
935 | */ | |
936 | ||
937 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
1da177e4 LT |
938 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); |
939 | } | |
940 | ||
941 | ||
1da177e4 LT |
942 | /* |
943 | * i8042_panic_blink() will flash the keyboard LEDs and is called when | |
944 | * kernel panics. Flashing LEDs is useful for users running X who may | |
945 | * not see the console and will help distingushing panics from "real" | |
946 | * lockups. | |
947 | * | |
948 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
949 | * waiting for KBC to free up even if KBD interrupt is off | |
950 | */ | |
951 | ||
952 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
953 | ||
954 | static long i8042_panic_blink(long count) | |
955 | { | |
956 | long delay = 0; | |
957 | static long last_blink; | |
958 | static char led; | |
959 | ||
960 | /* | |
961 | * We expect frequency to be about 1/2s. KDB uses about 1s. | |
962 | * Make sure they are different. | |
963 | */ | |
964 | if (!i8042_blink_frequency) | |
965 | return 0; | |
966 | if (count - last_blink < i8042_blink_frequency) | |
967 | return 0; | |
968 | ||
969 | led ^= 0x01 | 0x04; | |
970 | while (i8042_read_status() & I8042_STR_IBF) | |
971 | DELAY; | |
19f3c3e3 DT |
972 | dbg("%02x -> i8042 (panic blink)", 0xed); |
973 | i8042_suppress_kbd_ack = 2; | |
1da177e4 LT |
974 | i8042_write_data(0xed); /* set leds */ |
975 | DELAY; | |
976 | while (i8042_read_status() & I8042_STR_IBF) | |
977 | DELAY; | |
978 | DELAY; | |
19f3c3e3 | 979 | dbg("%02x -> i8042 (panic blink)", led); |
1da177e4 LT |
980 | i8042_write_data(led); |
981 | DELAY; | |
982 | last_blink = count; | |
983 | return delay; | |
984 | } | |
985 | ||
986 | #undef DELAY | |
987 | ||
d35895db BP |
988 | #ifdef CONFIG_X86 |
989 | static void i8042_dritek_enable(void) | |
990 | { | |
991 | char param = 0x90; | |
992 | int error; | |
993 | ||
994 | error = i8042_command(¶m, 0x1059); | |
995 | if (error) | |
996 | printk(KERN_WARNING | |
997 | "Failed to enable DRITEK extension: %d\n", | |
998 | error); | |
999 | } | |
1000 | #endif | |
1001 | ||
82dd9eff | 1002 | #ifdef CONFIG_PM |
7e044e05 | 1003 | |
1da177e4 | 1004 | /* |
ebd7768d DT |
1005 | * Here we try to restore the original BIOS settings to avoid |
1006 | * upsetting it. | |
1da177e4 LT |
1007 | */ |
1008 | ||
ebd7768d | 1009 | static int i8042_pm_reset(struct device *dev) |
1da177e4 | 1010 | { |
ebd7768d | 1011 | i8042_controller_reset(); |
1da177e4 LT |
1012 | |
1013 | return 0; | |
1014 | } | |
1015 | ||
1da177e4 | 1016 | /* |
ebd7768d DT |
1017 | * Here we try to reset everything back to a state we had |
1018 | * before suspending. | |
1da177e4 LT |
1019 | */ |
1020 | ||
ebd7768d | 1021 | static int i8042_pm_restore(struct device *dev) |
1da177e4 | 1022 | { |
de9ce703 | 1023 | int error; |
1da177e4 | 1024 | |
de9ce703 DT |
1025 | error = i8042_controller_check(); |
1026 | if (error) | |
1027 | return error; | |
2673c836 | 1028 | |
de9ce703 DT |
1029 | error = i8042_controller_selftest(); |
1030 | if (error) | |
1031 | return error; | |
1da177e4 LT |
1032 | |
1033 | /* | |
82dd9eff | 1034 | * Restore original CTR value and disable all ports |
1da177e4 LT |
1035 | */ |
1036 | ||
82dd9eff DT |
1037 | i8042_ctr = i8042_initial_ctr; |
1038 | if (i8042_direct) | |
1039 | i8042_ctr &= ~I8042_CTR_XLATE; | |
de9ce703 DT |
1040 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
1041 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
1042 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
2f6a77d5 JK |
1043 | printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); |
1044 | msleep(50); | |
1045 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
1046 | printk(KERN_ERR "i8042: CTR write retry failed\n"); | |
1047 | return -EIO; | |
1048 | } | |
de9ce703 | 1049 | } |
1da177e4 | 1050 | |
d35895db BP |
1051 | |
1052 | #ifdef CONFIG_X86 | |
1053 | if (i8042_dritek) | |
1054 | i8042_dritek_enable(); | |
1055 | #endif | |
1056 | ||
de9ce703 | 1057 | if (i8042_mux_present) { |
386b3849 | 1058 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
de9ce703 DT |
1059 | printk(KERN_WARNING |
1060 | "i8042: failed to resume active multiplexor, " | |
1061 | "mouse won't work.\n"); | |
1062 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) | |
1063 | i8042_enable_aux_port(); | |
1da177e4 | 1064 | |
de9ce703 DT |
1065 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
1066 | i8042_enable_kbd_port(); | |
1067 | ||
7d12e780 | 1068 | i8042_interrupt(0, NULL); |
1da177e4 LT |
1069 | |
1070 | return 0; | |
1da177e4 | 1071 | } |
ebd7768d DT |
1072 | |
1073 | static const struct dev_pm_ops i8042_pm_ops = { | |
1074 | .suspend = i8042_pm_reset, | |
1075 | .resume = i8042_pm_restore, | |
1076 | .poweroff = i8042_pm_reset, | |
1077 | .restore = i8042_pm_restore, | |
1078 | }; | |
1079 | ||
82dd9eff | 1080 | #endif /* CONFIG_PM */ |
1da177e4 LT |
1081 | |
1082 | /* | |
1083 | * We need to reset the 8042 back to original mode on system shutdown, | |
1084 | * because otherwise BIOSes will be confused. | |
1085 | */ | |
1086 | ||
3ae5eaec | 1087 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 | 1088 | { |
82dd9eff | 1089 | i8042_controller_reset(); |
1da177e4 LT |
1090 | } |
1091 | ||
f8113416 | 1092 | static int __init i8042_create_kbd_port(void) |
1da177e4 LT |
1093 | { |
1094 | struct serio *serio; | |
1095 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
1096 | ||
d39969de | 1097 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1098 | if (!serio) |
1099 | return -ENOMEM; | |
1100 | ||
1101 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
1102 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
1103 | serio->start = i8042_start; |
1104 | serio->stop = i8042_stop; | |
5ddbc77c | 1105 | serio->close = i8042_port_close; |
0854e52d DT |
1106 | serio->port_data = port; |
1107 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 1108 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d DT |
1109 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
1110 | ||
1111 | port->serio = serio; | |
de9ce703 | 1112 | port->irq = I8042_KBD_IRQ; |
0854e52d | 1113 | |
de9ce703 | 1114 | return 0; |
1da177e4 LT |
1115 | } |
1116 | ||
f8113416 | 1117 | static int __init i8042_create_aux_port(int idx) |
1da177e4 LT |
1118 | { |
1119 | struct serio *serio; | |
de9ce703 DT |
1120 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
1121 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 1122 | |
d39969de | 1123 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1124 | if (!serio) |
1125 | return -ENOMEM; | |
1126 | ||
1127 | serio->id.type = SERIO_8042; | |
1128 | serio->write = i8042_aux_write; | |
0854e52d DT |
1129 | serio->start = i8042_start; |
1130 | serio->stop = i8042_stop; | |
1131 | serio->port_data = port; | |
1132 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
1133 | if (idx < 0) { |
1134 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
1135 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
5ddbc77c | 1136 | serio->close = i8042_port_close; |
de9ce703 DT |
1137 | } else { |
1138 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
1139 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
1140 | } | |
0854e52d DT |
1141 | |
1142 | port->serio = serio; | |
de9ce703 DT |
1143 | port->mux = idx; |
1144 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 1145 | |
de9ce703 | 1146 | return 0; |
1da177e4 LT |
1147 | } |
1148 | ||
f8113416 | 1149 | static void __init i8042_free_kbd_port(void) |
1da177e4 | 1150 | { |
de9ce703 DT |
1151 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
1152 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
1153 | } | |
1da177e4 | 1154 | |
f8113416 | 1155 | static void __init i8042_free_aux_ports(void) |
de9ce703 DT |
1156 | { |
1157 | int i; | |
0854e52d | 1158 | |
de9ce703 DT |
1159 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
1160 | kfree(i8042_ports[i].serio); | |
1161 | i8042_ports[i].serio = NULL; | |
1162 | } | |
1163 | } | |
0854e52d | 1164 | |
f8113416 | 1165 | static void __init i8042_register_ports(void) |
de9ce703 DT |
1166 | { |
1167 | int i; | |
0854e52d | 1168 | |
de9ce703 DT |
1169 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1170 | if (i8042_ports[i].serio) { | |
1171 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", | |
1172 | i8042_ports[i].serio->name, | |
1173 | (unsigned long) I8042_DATA_REG, | |
1174 | (unsigned long) I8042_COMMAND_REG, | |
1175 | i8042_ports[i].irq); | |
1176 | serio_register_port(i8042_ports[i].serio); | |
1177 | } | |
1178 | } | |
1da177e4 LT |
1179 | } |
1180 | ||
7a1904c3 | 1181 | static void __devexit i8042_unregister_ports(void) |
1da177e4 | 1182 | { |
de9ce703 | 1183 | int i; |
1da177e4 | 1184 | |
de9ce703 DT |
1185 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1186 | if (i8042_ports[i].serio) { | |
1187 | serio_unregister_port(i8042_ports[i].serio); | |
1188 | i8042_ports[i].serio = NULL; | |
1189 | } | |
1190 | } | |
1191 | } | |
1192 | ||
181d683d DT |
1193 | /* |
1194 | * Checks whether port belongs to i8042 controller. | |
1195 | */ | |
1196 | bool i8042_check_port_owner(const struct serio *port) | |
1197 | { | |
1198 | int i; | |
1199 | ||
1200 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1201 | if (i8042_ports[i].serio == port) | |
1202 | return true; | |
1203 | ||
1204 | return false; | |
1205 | } | |
1206 | EXPORT_SYMBOL(i8042_check_port_owner); | |
1207 | ||
de9ce703 DT |
1208 | static void i8042_free_irqs(void) |
1209 | { | |
1210 | if (i8042_aux_irq_registered) | |
1211 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1212 | if (i8042_kbd_irq_registered) | |
1213 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1214 | ||
386b3849 | 1215 | i8042_aux_irq_registered = i8042_kbd_irq_registered = false; |
de9ce703 DT |
1216 | } |
1217 | ||
f8113416 | 1218 | static int __init i8042_setup_aux(void) |
de9ce703 DT |
1219 | { |
1220 | int (*aux_enable)(void); | |
1221 | int error; | |
1222 | int i; | |
1da177e4 | 1223 | |
de9ce703 | 1224 | if (i8042_check_aux()) |
87fd6318 | 1225 | return -ENODEV; |
1da177e4 | 1226 | |
de9ce703 DT |
1227 | if (i8042_nomux || i8042_check_mux()) { |
1228 | error = i8042_create_aux_port(-1); | |
1229 | if (error) | |
1230 | goto err_free_ports; | |
1231 | aux_enable = i8042_enable_aux_port; | |
1232 | } else { | |
1233 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1234 | error = i8042_create_aux_port(i); | |
1235 | if (error) | |
1236 | goto err_free_ports; | |
0854e52d | 1237 | } |
de9ce703 | 1238 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1239 | } |
1240 | ||
de9ce703 DT |
1241 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1242 | "i8042", i8042_platform_device); | |
1243 | if (error) | |
1244 | goto err_free_ports; | |
945ef0d4 | 1245 | |
de9ce703 DT |
1246 | if (aux_enable()) |
1247 | goto err_free_irq; | |
1da177e4 | 1248 | |
386b3849 | 1249 | i8042_aux_irq_registered = true; |
1da177e4 | 1250 | return 0; |
0854e52d | 1251 | |
de9ce703 DT |
1252 | err_free_irq: |
1253 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1254 | err_free_ports: | |
1255 | i8042_free_aux_ports(); | |
1256 | return error; | |
1257 | } | |
0854e52d | 1258 | |
f8113416 | 1259 | static int __init i8042_setup_kbd(void) |
de9ce703 DT |
1260 | { |
1261 | int error; | |
1262 | ||
1263 | error = i8042_create_kbd_port(); | |
1264 | if (error) | |
1265 | return error; | |
1266 | ||
1267 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1268 | "i8042", i8042_platform_device); | |
1269 | if (error) | |
1270 | goto err_free_port; | |
1271 | ||
1272 | error = i8042_enable_kbd_port(); | |
1273 | if (error) | |
1274 | goto err_free_irq; | |
1275 | ||
386b3849 | 1276 | i8042_kbd_irq_registered = true; |
de9ce703 DT |
1277 | return 0; |
1278 | ||
1279 | err_free_irq: | |
1280 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1281 | err_free_port: | |
1282 | i8042_free_kbd_port(); | |
1283 | return error; | |
1da177e4 LT |
1284 | } |
1285 | ||
f8113416 | 1286 | static int __init i8042_probe(struct platform_device *dev) |
1da177e4 | 1287 | { |
de9ce703 | 1288 | int error; |
1da177e4 | 1289 | |
de9ce703 DT |
1290 | error = i8042_controller_selftest(); |
1291 | if (error) | |
1292 | return error; | |
1da177e4 | 1293 | |
de9ce703 DT |
1294 | error = i8042_controller_init(); |
1295 | if (error) | |
1296 | return error; | |
1297 | ||
d35895db BP |
1298 | #ifdef CONFIG_X86 |
1299 | if (i8042_dritek) | |
1300 | i8042_dritek_enable(); | |
1301 | #endif | |
1302 | ||
de9ce703 DT |
1303 | if (!i8042_noaux) { |
1304 | error = i8042_setup_aux(); | |
1305 | if (error && error != -ENODEV && error != -EBUSY) | |
1306 | goto out_fail; | |
1307 | } | |
1308 | ||
1309 | if (!i8042_nokbd) { | |
1310 | error = i8042_setup_kbd(); | |
1311 | if (error) | |
1312 | goto out_fail; | |
1313 | } | |
de9ce703 DT |
1314 | /* |
1315 | * Ok, everything is ready, let's register all serio ports | |
1316 | */ | |
1317 | i8042_register_ports(); | |
1318 | ||
1319 | return 0; | |
1320 | ||
1321 | out_fail: | |
1322 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1323 | i8042_free_irqs(); | |
1324 | i8042_controller_reset(); | |
1325 | ||
1326 | return error; | |
1327 | } | |
1328 | ||
1329 | static int __devexit i8042_remove(struct platform_device *dev) | |
1330 | { | |
1331 | i8042_unregister_ports(); | |
1332 | i8042_free_irqs(); | |
1333 | i8042_controller_reset(); | |
1da177e4 | 1334 | |
87fd6318 DT |
1335 | return 0; |
1336 | } | |
1337 | ||
1338 | static struct platform_driver i8042_driver = { | |
1339 | .driver = { | |
1340 | .name = "i8042", | |
1341 | .owner = THIS_MODULE, | |
ebd7768d DT |
1342 | #ifdef CONFIG_PM |
1343 | .pm = &i8042_pm_ops, | |
1344 | #endif | |
87fd6318 | 1345 | }, |
87fd6318 | 1346 | .remove = __devexit_p(i8042_remove), |
82dd9eff | 1347 | .shutdown = i8042_shutdown, |
87fd6318 DT |
1348 | }; |
1349 | ||
1350 | static int __init i8042_init(void) | |
1351 | { | |
1352 | int err; | |
1353 | ||
1354 | dbg_init(); | |
1355 | ||
1356 | err = i8042_platform_init(); | |
1357 | if (err) | |
1358 | return err; | |
1359 | ||
de9ce703 DT |
1360 | err = i8042_controller_check(); |
1361 | if (err) | |
1362 | goto err_platform_exit; | |
87fd6318 | 1363 | |
87fd6318 DT |
1364 | i8042_platform_device = platform_device_alloc("i8042", -1); |
1365 | if (!i8042_platform_device) { | |
1366 | err = -ENOMEM; | |
f8113416 | 1367 | goto err_platform_exit; |
87fd6318 DT |
1368 | } |
1369 | ||
1370 | err = platform_device_add(i8042_platform_device); | |
1371 | if (err) | |
1372 | goto err_free_device; | |
1373 | ||
f8113416 DT |
1374 | err = platform_driver_probe(&i8042_driver, i8042_probe); |
1375 | if (err) | |
1376 | goto err_del_device; | |
1377 | ||
de9ce703 DT |
1378 | panic_blink = i8042_panic_blink; |
1379 | ||
87fd6318 DT |
1380 | return 0; |
1381 | ||
f8113416 DT |
1382 | err_del_device: |
1383 | platform_device_del(i8042_platform_device); | |
87fd6318 DT |
1384 | err_free_device: |
1385 | platform_device_put(i8042_platform_device); | |
87fd6318 DT |
1386 | err_platform_exit: |
1387 | i8042_platform_exit(); | |
1388 | ||
1389 | return err; | |
1390 | } | |
1391 | ||
1392 | static void __exit i8042_exit(void) | |
1393 | { | |
3ae5eaec | 1394 | platform_driver_unregister(&i8042_driver); |
f8113416 | 1395 | platform_device_unregister(i8042_platform_device); |
1da177e4 LT |
1396 | i8042_platform_exit(); |
1397 | ||
1398 | panic_blink = NULL; | |
1399 | } | |
1400 | ||
1401 | module_init(i8042_init); | |
1402 | module_exit(i8042_exit); |