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1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/config.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/serio.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/rcupdate.h> | |
23 | ||
24 | #include <asm/io.h> | |
25 | ||
26 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
27 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
28 | MODULE_LICENSE("GPL"); | |
29 | ||
30 | static unsigned int i8042_noaux; | |
31 | module_param_named(noaux, i8042_noaux, bool, 0); | |
32 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
33 | ||
34 | static unsigned int i8042_nomux; | |
35 | module_param_named(nomux, i8042_nomux, bool, 0); | |
36 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); | |
37 | ||
38 | static unsigned int i8042_unlock; | |
39 | module_param_named(unlock, i8042_unlock, bool, 0); | |
40 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
41 | ||
42 | static unsigned int i8042_reset; | |
43 | module_param_named(reset, i8042_reset, bool, 0); | |
44 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
45 | ||
46 | static unsigned int i8042_direct; | |
47 | module_param_named(direct, i8042_direct, bool, 0); | |
48 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
49 | ||
50 | static unsigned int i8042_dumbkbd; | |
51 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); | |
52 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
53 | ||
54 | static unsigned int i8042_noloop; | |
55 | module_param_named(noloop, i8042_noloop, bool, 0); | |
56 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
57 | ||
58 | static unsigned int i8042_blink_frequency = 500; | |
59 | module_param_named(panicblink, i8042_blink_frequency, uint, 0600); | |
60 | MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); | |
61 | ||
62 | #ifdef CONFIG_PNP | |
63 | static int i8042_nopnp; | |
64 | module_param_named(nopnp, i8042_nopnp, bool, 0); | |
65 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
66 | #endif | |
67 | ||
68 | #define DEBUG | |
69 | #ifdef DEBUG | |
70 | static int i8042_debug; | |
71 | module_param_named(debug, i8042_debug, bool, 0600); | |
72 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
73 | #endif | |
74 | ||
75 | __obsolete_setup("i8042_noaux"); | |
76 | __obsolete_setup("i8042_nomux"); | |
77 | __obsolete_setup("i8042_unlock"); | |
78 | __obsolete_setup("i8042_reset"); | |
79 | __obsolete_setup("i8042_direct"); | |
80 | __obsolete_setup("i8042_dumbkbd"); | |
81 | ||
82 | #include "i8042.h" | |
83 | ||
84 | static DEFINE_SPINLOCK(i8042_lock); | |
85 | ||
86 | struct i8042_port { | |
87 | struct serio *serio; | |
88 | int irq; | |
89 | unsigned char disable; | |
90 | unsigned char irqen; | |
91 | unsigned char exists; | |
92 | signed char mux; | |
93 | char name[8]; | |
94 | }; | |
95 | ||
96 | #define I8042_KBD_PORT_NO 0 | |
97 | #define I8042_AUX_PORT_NO 1 | |
98 | #define I8042_MUX_PORT_NO 2 | |
99 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
100 | static struct i8042_port i8042_ports[I8042_NUM_PORTS] = { | |
101 | { | |
102 | .disable = I8042_CTR_KBDDIS, | |
103 | .irqen = I8042_CTR_KBDINT, | |
104 | .mux = -1, | |
105 | .name = "KBD", | |
106 | }, | |
107 | { | |
108 | .disable = I8042_CTR_AUXDIS, | |
109 | .irqen = I8042_CTR_AUXINT, | |
110 | .mux = -1, | |
111 | .name = "AUX", | |
112 | } | |
113 | }; | |
114 | ||
115 | static unsigned char i8042_initial_ctr; | |
116 | static unsigned char i8042_ctr; | |
117 | static unsigned char i8042_mux_open; | |
118 | static unsigned char i8042_mux_present; | |
119 | static struct timer_list i8042_timer; | |
120 | static struct platform_device *i8042_platform_device; | |
121 | ||
122 | ||
123 | /* | |
124 | * Shared IRQ's require a device pointer, but this driver doesn't support | |
125 | * multiple devices | |
126 | */ | |
127 | #define i8042_request_irq_cookie (&i8042_timer) | |
128 | ||
129 | static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs); | |
130 | ||
131 | /* | |
132 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
133 | * be ready for reading values from it / writing values to it. | |
134 | * Called always with i8042_lock held. | |
135 | */ | |
136 | ||
137 | static int i8042_wait_read(void) | |
138 | { | |
139 | int i = 0; | |
140 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { | |
141 | udelay(50); | |
142 | i++; | |
143 | } | |
144 | return -(i == I8042_CTL_TIMEOUT); | |
145 | } | |
146 | ||
147 | static int i8042_wait_write(void) | |
148 | { | |
149 | int i = 0; | |
150 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { | |
151 | udelay(50); | |
152 | i++; | |
153 | } | |
154 | return -(i == I8042_CTL_TIMEOUT); | |
155 | } | |
156 | ||
157 | /* | |
158 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
159 | * of the i8042 down the toilet. | |
160 | */ | |
161 | ||
162 | static int i8042_flush(void) | |
163 | { | |
164 | unsigned long flags; | |
165 | unsigned char data, str; | |
166 | int i = 0; | |
167 | ||
168 | spin_lock_irqsave(&i8042_lock, flags); | |
169 | ||
170 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
171 | udelay(50); | |
172 | data = i8042_read_data(); | |
173 | i++; | |
174 | dbg("%02x <- i8042 (flush, %s)", data, | |
175 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
176 | } | |
177 | ||
178 | spin_unlock_irqrestore(&i8042_lock, flags); | |
179 | ||
180 | return i; | |
181 | } | |
182 | ||
183 | /* | |
184 | * i8042_command() executes a command on the i8042. It also sends the input | |
185 | * parameter(s) of the commands to it, and receives the output value(s). The | |
186 | * parameters are to be stored in the param array, and the output is placed | |
187 | * into the same array. The number of the parameters and output values is | |
188 | * encoded in bits 8-11 of the command number. | |
189 | */ | |
190 | ||
191 | static int i8042_command(unsigned char *param, int command) | |
192 | { | |
193 | unsigned long flags; | |
194 | int retval = 0, i = 0; | |
195 | ||
196 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
197 | return -1; | |
198 | ||
199 | spin_lock_irqsave(&i8042_lock, flags); | |
200 | ||
201 | retval = i8042_wait_write(); | |
202 | if (!retval) { | |
203 | dbg("%02x -> i8042 (command)", command & 0xff); | |
204 | i8042_write_command(command & 0xff); | |
205 | } | |
206 | ||
207 | if (!retval) | |
208 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
209 | if ((retval = i8042_wait_write())) break; | |
210 | dbg("%02x -> i8042 (parameter)", param[i]); | |
211 | i8042_write_data(param[i]); | |
212 | } | |
213 | ||
214 | if (!retval) | |
215 | for (i = 0; i < ((command >> 8) & 0xf); i++) { | |
216 | if ((retval = i8042_wait_read())) break; | |
217 | if (i8042_read_status() & I8042_STR_AUXDATA) | |
218 | param[i] = ~i8042_read_data(); | |
219 | else | |
220 | param[i] = i8042_read_data(); | |
221 | dbg("%02x <- i8042 (return)", param[i]); | |
222 | } | |
223 | ||
224 | spin_unlock_irqrestore(&i8042_lock, flags); | |
225 | ||
226 | if (retval) | |
227 | dbg(" -- i8042 (timeout)"); | |
228 | ||
229 | return retval; | |
230 | } | |
231 | ||
232 | /* | |
233 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
234 | */ | |
235 | ||
236 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
237 | { | |
238 | unsigned long flags; | |
239 | int retval = 0; | |
240 | ||
241 | spin_lock_irqsave(&i8042_lock, flags); | |
242 | ||
243 | if(!(retval = i8042_wait_write())) { | |
244 | dbg("%02x -> i8042 (kbd-data)", c); | |
245 | i8042_write_data(c); | |
246 | } | |
247 | ||
248 | spin_unlock_irqrestore(&i8042_lock, flags); | |
249 | ||
250 | return retval; | |
251 | } | |
252 | ||
253 | /* | |
254 | * i8042_aux_write() sends a byte out through the aux interface. | |
255 | */ | |
256 | ||
257 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
258 | { | |
259 | struct i8042_port *port = serio->port_data; | |
260 | int retval; | |
261 | ||
262 | /* | |
263 | * Send the byte out. | |
264 | */ | |
265 | ||
266 | if (port->mux == -1) | |
267 | retval = i8042_command(&c, I8042_CMD_AUX_SEND); | |
268 | else | |
269 | retval = i8042_command(&c, I8042_CMD_MUX_SEND + port->mux); | |
270 | ||
271 | /* | |
272 | * Make sure the interrupt happens and the character is received even | |
273 | * in the case the IRQ isn't wired, so that we can receive further | |
274 | * characters later. | |
275 | */ | |
276 | ||
277 | i8042_interrupt(0, NULL, NULL); | |
278 | return retval; | |
279 | } | |
280 | ||
281 | /* | |
282 | * i8042_activate_port() enables port on a chip. | |
283 | */ | |
284 | ||
285 | static int i8042_activate_port(struct i8042_port *port) | |
286 | { | |
287 | if (!port->serio) | |
288 | return -1; | |
289 | ||
290 | i8042_flush(); | |
291 | ||
292 | /* | |
293 | * Enable port again here because it is disabled if we are | |
294 | * resuming (normally it is enabled already). | |
295 | */ | |
296 | i8042_ctr &= ~port->disable; | |
297 | ||
298 | i8042_ctr |= port->irqen; | |
299 | ||
300 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
301 | i8042_ctr &= ~port->irqen; | |
302 | return -1; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | ||
309 | /* | |
310 | * i8042_open() is called when a port is open by the higher layer. | |
311 | * It allocates the interrupt and calls i8042_enable_port. | |
312 | */ | |
313 | ||
314 | static int i8042_open(struct serio *serio) | |
315 | { | |
316 | struct i8042_port *port = serio->port_data; | |
317 | ||
318 | if (port->mux != -1) | |
319 | if (i8042_mux_open++) | |
320 | return 0; | |
321 | ||
322 | if (request_irq(port->irq, i8042_interrupt, | |
323 | SA_SHIRQ, "i8042", i8042_request_irq_cookie)) { | |
324 | printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", port->irq, port->name); | |
325 | goto irq_fail; | |
326 | } | |
327 | ||
328 | if (i8042_activate_port(port)) { | |
329 | printk(KERN_ERR "i8042.c: Can't activate %s, unregistering the port\n", port->name); | |
330 | goto activate_fail; | |
331 | } | |
332 | ||
333 | i8042_interrupt(0, NULL, NULL); | |
334 | ||
335 | return 0; | |
336 | ||
337 | activate_fail: | |
338 | free_irq(port->irq, i8042_request_irq_cookie); | |
339 | ||
340 | irq_fail: | |
341 | serio_unregister_port_delayed(serio); | |
342 | ||
343 | return -1; | |
344 | } | |
345 | ||
346 | /* | |
347 | * i8042_close() frees the interrupt, so that it can possibly be used | |
348 | * by another driver. We never know - if the user doesn't have a mouse, | |
349 | * the BIOS could have used the AUX interrupt for PCI. | |
350 | */ | |
351 | ||
352 | static void i8042_close(struct serio *serio) | |
353 | { | |
354 | struct i8042_port *port = serio->port_data; | |
355 | ||
356 | if (port->mux != -1) | |
357 | if (--i8042_mux_open) | |
358 | return; | |
359 | ||
360 | i8042_ctr &= ~port->irqen; | |
361 | ||
362 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
363 | printk(KERN_WARNING "i8042.c: Can't write CTR while closing %s.\n", port->name); | |
364 | /* | |
365 | * We still want to continue and free IRQ so if more data keeps coming in | |
366 | * kernel will just ignore the irq. | |
367 | */ | |
368 | } | |
369 | ||
370 | free_irq(port->irq, i8042_request_irq_cookie); | |
371 | ||
372 | i8042_flush(); | |
373 | } | |
374 | ||
375 | /* | |
376 | * i8042_start() is called by serio core when port is about to finish | |
377 | * registering. It will mark port as existing so i8042_interrupt can | |
378 | * start sending data through it. | |
379 | */ | |
380 | static int i8042_start(struct serio *serio) | |
381 | { | |
382 | struct i8042_port *port = serio->port_data; | |
383 | ||
384 | port->exists = 1; | |
385 | mb(); | |
386 | return 0; | |
387 | } | |
388 | ||
389 | /* | |
390 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
391 | * will not try to send data to the port that is about to go away. | |
392 | * The function is called by serio core as part of unregister procedure. | |
393 | */ | |
394 | static void i8042_stop(struct serio *serio) | |
395 | { | |
396 | struct i8042_port *port = serio->port_data; | |
397 | ||
398 | port->exists = 0; | |
b2b18660 | 399 | synchronize_sched(); |
1da177e4 LT |
400 | port->serio = NULL; |
401 | } | |
402 | ||
403 | /* | |
404 | * i8042_interrupt() is the most important function in this driver - | |
405 | * it handles the interrupts from the i8042, and sends incoming bytes | |
406 | * to the upper layers. | |
407 | */ | |
408 | ||
409 | static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
410 | { | |
411 | struct i8042_port *port; | |
412 | unsigned long flags; | |
413 | unsigned char str, data; | |
414 | unsigned int dfl; | |
415 | unsigned int port_no; | |
416 | int ret; | |
417 | ||
418 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
419 | ||
420 | spin_lock_irqsave(&i8042_lock, flags); | |
421 | str = i8042_read_status(); | |
422 | if (unlikely(~str & I8042_STR_OBF)) { | |
423 | spin_unlock_irqrestore(&i8042_lock, flags); | |
424 | if (irq) dbg("Interrupt %d, without any data", irq); | |
425 | ret = 0; | |
426 | goto out; | |
427 | } | |
428 | data = i8042_read_data(); | |
429 | spin_unlock_irqrestore(&i8042_lock, flags); | |
430 | ||
431 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
432 | static unsigned long last_transmit; | |
433 | static unsigned char last_str; | |
434 | ||
435 | dfl = 0; | |
436 | if (str & I8042_STR_MUXERR) { | |
437 | dbg("MUX error, status is %02x, data is %02x", str, data); | |
438 | switch (data) { | |
439 | default: | |
440 | /* | |
441 | * When MUXERR condition is signalled the data register can only contain | |
442 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
443 | * it is not always the case. Some KBC just get confused which port the | |
444 | * data came from and signal error leaving the data intact. They _do not_ | |
445 | * revert to legacy mode (actually I've never seen KBC reverting to legacy | |
446 | * mode yet, when we see one we'll add proper handling). | |
447 | * Anyway, we will assume that the data came from the same serio last byte | |
448 | * was transmitted (if transmission happened not too long ago). | |
449 | */ | |
450 | if (time_before(jiffies, last_transmit + HZ/10)) { | |
451 | str = last_str; | |
452 | break; | |
453 | } | |
454 | /* fall through - report timeout */ | |
455 | case 0xfd: | |
456 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
457 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
458 | } | |
459 | } | |
460 | ||
461 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
462 | last_str = str; | |
463 | last_transmit = jiffies; | |
464 | } else { | |
465 | ||
466 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
467 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
468 | ||
469 | port_no = (str & I8042_STR_AUXDATA) ? | |
470 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
471 | } | |
472 | ||
473 | port = &i8042_ports[port_no]; | |
474 | ||
475 | dbg("%02x <- i8042 (interrupt, %s, %d%s%s)", | |
476 | data, port->name, irq, | |
477 | dfl & SERIO_PARITY ? ", bad parity" : "", | |
478 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
479 | ||
480 | if (likely(port->exists)) | |
481 | serio_interrupt(port->serio, data, dfl, regs); | |
482 | ||
483 | ret = 1; | |
484 | out: | |
485 | return IRQ_RETVAL(ret); | |
486 | } | |
487 | ||
488 | /* | |
489 | * i8042_set_mux_mode checks whether the controller has an active | |
490 | * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode. | |
491 | */ | |
492 | ||
493 | static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version) | |
494 | { | |
495 | ||
496 | unsigned char param; | |
497 | /* | |
498 | * Get rid of bytes in the queue. | |
499 | */ | |
500 | ||
501 | i8042_flush(); | |
502 | ||
503 | /* | |
504 | * Internal loopback test - send three bytes, they should come back from the | |
505 | * mouse interface, the last should be version. Note that we negate mouseport | |
506 | * command responses for the i8042_check_aux() routine. | |
507 | */ | |
508 | ||
509 | param = 0xf0; | |
510 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x0f) | |
511 | return -1; | |
512 | param = mode ? 0x56 : 0xf6; | |
513 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0xa9 : 0x09)) | |
514 | return -1; | |
515 | param = mode ? 0xa4 : 0xa5; | |
516 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0x5b : 0x5a)) | |
517 | return -1; | |
518 | ||
519 | if (mux_version) | |
520 | *mux_version = ~param; | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | ||
526 | /* | |
527 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
528 | * the controller has been switched into Multiplexed mode | |
529 | */ | |
530 | ||
531 | static int i8042_enable_mux_ports(void) | |
532 | { | |
533 | unsigned char param; | |
534 | int i; | |
535 | /* | |
536 | * Disable all muxed ports by disabling AUX. | |
537 | */ | |
538 | ||
539 | i8042_ctr |= I8042_CTR_AUXDIS; | |
540 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
541 | ||
542 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
543 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | |
544 | return -1; | |
545 | } | |
546 | ||
547 | /* | |
548 | * Enable all muxed ports. | |
549 | */ | |
550 | ||
551 | for (i = 0; i < 4; i++) { | |
552 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
553 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | ||
560 | /* | |
561 | * i8042_check_mux() checks whether the controller supports the PS/2 Active | |
562 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
563 | * LCS/Telegraphics. | |
564 | */ | |
565 | ||
566 | static int __init i8042_check_mux(void) | |
567 | { | |
568 | unsigned char mux_version; | |
569 | ||
570 | if (i8042_set_mux_mode(1, &mux_version)) | |
571 | return -1; | |
572 | ||
573 | /* Workaround for interference with USB Legacy emulation */ | |
574 | /* that causes a v10.12 MUX to be found. */ | |
575 | if (mux_version == 0xAC) | |
576 | return -1; | |
577 | ||
578 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | |
579 | (mux_version >> 4) & 0xf, mux_version & 0xf); | |
580 | ||
581 | if (i8042_enable_mux_ports()) | |
582 | return -1; | |
583 | ||
584 | i8042_mux_present = 1; | |
585 | return 0; | |
586 | } | |
587 | ||
588 | ||
589 | /* | |
590 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
591 | * the presence of an AUX interface. | |
592 | */ | |
593 | ||
594 | static int __init i8042_check_aux(void) | |
595 | { | |
596 | unsigned char param; | |
597 | static int i8042_check_aux_cookie; | |
598 | ||
599 | /* | |
600 | * Check if AUX irq is available. If it isn't, then there is no point | |
601 | * in trying to detect AUX presence. | |
602 | */ | |
603 | ||
604 | if (request_irq(i8042_ports[I8042_AUX_PORT_NO].irq, i8042_interrupt, | |
605 | SA_SHIRQ, "i8042", &i8042_check_aux_cookie)) | |
606 | return -1; | |
607 | free_irq(i8042_ports[I8042_AUX_PORT_NO].irq, &i8042_check_aux_cookie); | |
608 | ||
609 | /* | |
610 | * Get rid of bytes in the queue. | |
611 | */ | |
612 | ||
613 | i8042_flush(); | |
614 | ||
615 | /* | |
616 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
617 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
618 | * though it has an AUX port. | |
619 | */ | |
620 | ||
621 | param = 0x5a; | |
622 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xa5) { | |
623 | ||
624 | /* | |
625 | * External connection test - filters out AT-soldered PS/2 i8042's | |
626 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
627 | * 0xfa - no error on some notebooks which ignore the spec | |
628 | * Because it's common for chipsets to return error on perfectly functioning | |
629 | * AUX ports, we test for this only when the LOOP command failed. | |
630 | */ | |
631 | ||
632 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) | |
633 | || (param && param != 0xfa && param != 0xff)) | |
634 | return -1; | |
635 | } | |
636 | ||
637 | /* | |
638 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
639 | */ | |
640 | ||
641 | if (i8042_command(¶m, I8042_CMD_AUX_DISABLE)) | |
642 | return -1; | |
643 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) { | |
644 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); | |
645 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | |
646 | } | |
647 | ||
648 | if (i8042_command(¶m, I8042_CMD_AUX_ENABLE)) | |
649 | return -1; | |
650 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS)) | |
651 | return -1; | |
652 | ||
653 | /* | |
654 | * Disable the interface. | |
655 | */ | |
656 | ||
657 | i8042_ctr |= I8042_CTR_AUXDIS; | |
658 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
659 | ||
660 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
661 | return -1; | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
666 | ||
667 | /* | |
668 | * i8042_port_register() marks the device as existing, | |
669 | * registers it, and reports to the user. | |
670 | */ | |
671 | ||
672 | static int __init i8042_port_register(struct i8042_port *port) | |
673 | { | |
674 | i8042_ctr &= ~port->disable; | |
675 | ||
676 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
677 | printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n"); | |
678 | kfree(port->serio); | |
679 | port->serio = NULL; | |
680 | i8042_ctr |= port->disable; | |
681 | return -1; | |
682 | } | |
683 | ||
684 | printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n", | |
685 | port->name, | |
686 | (unsigned long) I8042_DATA_REG, | |
687 | (unsigned long) I8042_COMMAND_REG, | |
688 | port->irq); | |
689 | ||
690 | serio_register_port(port->serio); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
695 | ||
696 | static void i8042_timer_func(unsigned long data) | |
697 | { | |
698 | i8042_interrupt(0, NULL, NULL); | |
699 | } | |
700 | ||
2673c836 VP |
701 | static int i8042_ctl_test(void) |
702 | { | |
703 | unsigned char param; | |
704 | ||
705 | if (!i8042_reset) | |
706 | return 0; | |
707 | ||
708 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
709 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | |
710 | return -1; | |
711 | } | |
712 | ||
713 | if (param != I8042_RET_CTL_TEST) { | |
714 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | |
715 | param, I8042_RET_CTL_TEST); | |
716 | return -1; | |
717 | } | |
718 | ||
719 | return 0; | |
720 | } | |
1da177e4 LT |
721 | |
722 | /* | |
723 | * i8042_controller init initializes the i8042 controller, and, | |
724 | * most importantly, sets it into non-xlated mode if that's | |
725 | * desired. | |
726 | */ | |
727 | ||
728 | static int i8042_controller_init(void) | |
729 | { | |
730 | unsigned long flags; | |
731 | ||
732 | /* | |
733 | * Test the i8042. We need to know if it thinks it's working correctly | |
734 | * before doing anything else. | |
735 | */ | |
736 | ||
737 | if (i8042_flush() == I8042_BUFFER_SIZE) { | |
738 | printk(KERN_ERR "i8042.c: No controller found.\n"); | |
739 | return -1; | |
740 | } | |
741 | ||
2673c836 VP |
742 | if (i8042_ctl_test()) |
743 | return -1; | |
1da177e4 LT |
744 | |
745 | /* | |
746 | * Save the CTR for restoral on unload / reboot. | |
747 | */ | |
748 | ||
749 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { | |
750 | printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); | |
751 | return -1; | |
752 | } | |
753 | ||
754 | i8042_initial_ctr = i8042_ctr; | |
755 | ||
756 | /* | |
757 | * Disable the keyboard interface and interrupt. | |
758 | */ | |
759 | ||
760 | i8042_ctr |= I8042_CTR_KBDDIS; | |
761 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
762 | ||
763 | /* | |
764 | * Handle keylock. | |
765 | */ | |
766 | ||
767 | spin_lock_irqsave(&i8042_lock, flags); | |
768 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
769 | if (i8042_unlock) | |
770 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
771 | else | |
772 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); | |
773 | } | |
774 | spin_unlock_irqrestore(&i8042_lock, flags); | |
775 | ||
776 | /* | |
777 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
778 | * bother enabling translating and be happy. | |
779 | */ | |
780 | ||
781 | if (~i8042_ctr & I8042_CTR_XLATE) | |
782 | i8042_direct = 1; | |
783 | ||
784 | /* | |
785 | * Set nontranslated mode for the kbd interface if requested by an option. | |
786 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
787 | * interface is. We don't do this by default, since it can confuse notebook | |
788 | * BIOSes. | |
789 | */ | |
790 | ||
791 | if (i8042_direct) | |
792 | i8042_ctr &= ~I8042_CTR_XLATE; | |
793 | ||
794 | /* | |
795 | * Write CTR back. | |
796 | */ | |
797 | ||
798 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
799 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | |
800 | return -1; | |
801 | } | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | ||
807 | /* | |
808 | * Reset the controller. | |
809 | */ | |
810 | static void i8042_controller_reset(void) | |
811 | { | |
1da177e4 LT |
812 | /* |
813 | * Reset the controller if requested. | |
814 | */ | |
815 | ||
2673c836 | 816 | i8042_ctl_test(); |
1da177e4 LT |
817 | |
818 | /* | |
819 | * Disable MUX mode if present. | |
820 | */ | |
821 | ||
822 | if (i8042_mux_present) | |
823 | i8042_set_mux_mode(0, NULL); | |
824 | ||
825 | /* | |
826 | * Restore the original control register setting. | |
827 | */ | |
828 | ||
829 | i8042_ctr = i8042_initial_ctr; | |
830 | ||
831 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
832 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); | |
833 | } | |
834 | ||
835 | ||
836 | /* | |
837 | * Here we try to reset everything back to a state in which the BIOS will be | |
838 | * able to talk to the hardware when rebooting. | |
839 | */ | |
840 | ||
841 | static void i8042_controller_cleanup(void) | |
842 | { | |
843 | int i; | |
844 | ||
845 | i8042_flush(); | |
846 | ||
847 | /* | |
848 | * Reset anything that is connected to the ports. | |
849 | */ | |
850 | ||
851 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
852 | if (i8042_ports[i].exists) | |
853 | serio_cleanup(i8042_ports[i].serio); | |
854 | ||
855 | i8042_controller_reset(); | |
856 | } | |
857 | ||
858 | ||
859 | /* | |
860 | * i8042_panic_blink() will flash the keyboard LEDs and is called when | |
861 | * kernel panics. Flashing LEDs is useful for users running X who may | |
862 | * not see the console and will help distingushing panics from "real" | |
863 | * lockups. | |
864 | * | |
865 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
866 | * waiting for KBC to free up even if KBD interrupt is off | |
867 | */ | |
868 | ||
869 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
870 | ||
871 | static long i8042_panic_blink(long count) | |
872 | { | |
873 | long delay = 0; | |
874 | static long last_blink; | |
875 | static char led; | |
876 | ||
877 | /* | |
878 | * We expect frequency to be about 1/2s. KDB uses about 1s. | |
879 | * Make sure they are different. | |
880 | */ | |
881 | if (!i8042_blink_frequency) | |
882 | return 0; | |
883 | if (count - last_blink < i8042_blink_frequency) | |
884 | return 0; | |
885 | ||
886 | led ^= 0x01 | 0x04; | |
887 | while (i8042_read_status() & I8042_STR_IBF) | |
888 | DELAY; | |
889 | i8042_write_data(0xed); /* set leds */ | |
890 | DELAY; | |
891 | while (i8042_read_status() & I8042_STR_IBF) | |
892 | DELAY; | |
893 | DELAY; | |
894 | i8042_write_data(led); | |
895 | DELAY; | |
896 | last_blink = count; | |
897 | return delay; | |
898 | } | |
899 | ||
900 | #undef DELAY | |
901 | ||
902 | /* | |
903 | * Here we try to restore the original BIOS settings | |
904 | */ | |
905 | ||
906 | static int i8042_suspend(struct device *dev, pm_message_t state, u32 level) | |
907 | { | |
908 | if (level == SUSPEND_DISABLE) { | |
909 | del_timer_sync(&i8042_timer); | |
910 | i8042_controller_reset(); | |
911 | } | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | ||
917 | /* | |
918 | * Here we try to reset everything back to a state in which suspended | |
919 | */ | |
920 | ||
921 | static int i8042_resume(struct device *dev, u32 level) | |
922 | { | |
923 | int i; | |
924 | ||
925 | if (level != RESUME_ENABLE) | |
926 | return 0; | |
927 | ||
2673c836 VP |
928 | if (i8042_ctl_test()) |
929 | return -1; | |
930 | ||
931 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
932 | printk(KERN_ERR "i8042: Can't write CTR\n"); | |
1da177e4 LT |
933 | return -1; |
934 | } | |
935 | ||
936 | if (i8042_mux_present) | |
937 | if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports()) | |
938 | printk(KERN_WARNING "i8042: failed to resume active multiplexor, mouse won't work.\n"); | |
939 | ||
940 | /* | |
941 | * Activate all ports. | |
942 | */ | |
943 | ||
944 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
945 | i8042_activate_port(&i8042_ports[i]); | |
946 | ||
947 | /* | |
948 | * Restart timer (for polling "stuck" data) | |
949 | */ | |
950 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
951 | ||
952 | panic_blink = i8042_panic_blink; | |
953 | ||
954 | return 0; | |
955 | ||
956 | } | |
957 | ||
958 | /* | |
959 | * We need to reset the 8042 back to original mode on system shutdown, | |
960 | * because otherwise BIOSes will be confused. | |
961 | */ | |
962 | ||
963 | static void i8042_shutdown(struct device *dev) | |
964 | { | |
965 | i8042_controller_cleanup(); | |
966 | } | |
967 | ||
968 | static struct device_driver i8042_driver = { | |
969 | .name = "i8042", | |
970 | .bus = &platform_bus_type, | |
971 | .suspend = i8042_suspend, | |
972 | .resume = i8042_resume, | |
973 | .shutdown = i8042_shutdown, | |
974 | }; | |
975 | ||
976 | static void __init i8042_create_kbd_port(void) | |
977 | { | |
978 | struct serio *serio; | |
979 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
980 | ||
981 | serio = kmalloc(sizeof(struct serio), GFP_KERNEL); | |
982 | if (serio) { | |
983 | memset(serio, 0, sizeof(struct serio)); | |
984 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
985 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
986 | serio->open = i8042_open; | |
987 | serio->close = i8042_close; | |
988 | serio->start = i8042_start; | |
989 | serio->stop = i8042_stop; | |
990 | serio->port_data = port; | |
991 | serio->dev.parent = &i8042_platform_device->dev; | |
992 | strlcpy(serio->name, "i8042 Kbd Port", sizeof(serio->name)); | |
993 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); | |
994 | ||
995 | port->serio = serio; | |
996 | i8042_port_register(port); | |
997 | } | |
998 | } | |
999 | ||
1000 | static void __init i8042_create_aux_port(void) | |
1001 | { | |
1002 | struct serio *serio; | |
1003 | struct i8042_port *port = &i8042_ports[I8042_AUX_PORT_NO]; | |
1004 | ||
1005 | serio = kmalloc(sizeof(struct serio), GFP_KERNEL); | |
1006 | if (serio) { | |
1007 | memset(serio, 0, sizeof(struct serio)); | |
1008 | serio->id.type = SERIO_8042; | |
1009 | serio->write = i8042_aux_write; | |
1010 | serio->open = i8042_open; | |
1011 | serio->close = i8042_close; | |
1012 | serio->start = i8042_start; | |
1013 | serio->stop = i8042_stop; | |
1014 | serio->port_data = port; | |
1015 | serio->dev.parent = &i8042_platform_device->dev; | |
1016 | strlcpy(serio->name, "i8042 Aux Port", sizeof(serio->name)); | |
1017 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
1018 | ||
1019 | port->serio = serio; | |
1020 | i8042_port_register(port); | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | static void __init i8042_create_mux_port(int index) | |
1025 | { | |
1026 | struct serio *serio; | |
1027 | struct i8042_port *port = &i8042_ports[I8042_MUX_PORT_NO + index]; | |
1028 | ||
1029 | serio = kmalloc(sizeof(struct serio), GFP_KERNEL); | |
1030 | if (serio) { | |
1031 | memset(serio, 0, sizeof(struct serio)); | |
1032 | serio->id.type = SERIO_8042; | |
1033 | serio->write = i8042_aux_write; | |
1034 | serio->open = i8042_open; | |
1035 | serio->close = i8042_close; | |
1036 | serio->start = i8042_start; | |
1037 | serio->stop = i8042_stop; | |
1038 | serio->port_data = port; | |
1039 | serio->dev.parent = &i8042_platform_device->dev; | |
1040 | snprintf(serio->name, sizeof(serio->name), "i8042 Aux-%d Port", index); | |
1041 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, index + 1); | |
1042 | ||
1043 | *port = i8042_ports[I8042_AUX_PORT_NO]; | |
1044 | port->exists = 0; | |
1045 | snprintf(port->name, sizeof(port->name), "AUX%d", index); | |
1046 | port->mux = index; | |
1047 | port->serio = serio; | |
1048 | i8042_port_register(port); | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | static int __init i8042_init(void) | |
1053 | { | |
1054 | int i; | |
1055 | int err; | |
1056 | ||
1057 | dbg_init(); | |
1058 | ||
1059 | init_timer(&i8042_timer); | |
1060 | i8042_timer.function = i8042_timer_func; | |
1061 | ||
1062 | if (i8042_platform_init()) | |
1063 | return -EBUSY; | |
1064 | ||
1065 | i8042_ports[I8042_AUX_PORT_NO].irq = I8042_AUX_IRQ; | |
1066 | i8042_ports[I8042_KBD_PORT_NO].irq = I8042_KBD_IRQ; | |
1067 | ||
1068 | if (i8042_controller_init()) { | |
1069 | i8042_platform_exit(); | |
1070 | return -ENODEV; | |
1071 | } | |
1072 | ||
1073 | err = driver_register(&i8042_driver); | |
1074 | if (err) { | |
1075 | i8042_platform_exit(); | |
1076 | return err; | |
1077 | } | |
1078 | ||
1079 | i8042_platform_device = platform_device_register_simple("i8042", -1, NULL, 0); | |
1080 | if (IS_ERR(i8042_platform_device)) { | |
1081 | driver_unregister(&i8042_driver); | |
1082 | i8042_platform_exit(); | |
1083 | return PTR_ERR(i8042_platform_device); | |
1084 | } | |
1085 | ||
1086 | if (!i8042_noaux && !i8042_check_aux()) { | |
1087 | if (!i8042_nomux && !i8042_check_mux()) | |
1088 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) | |
1089 | i8042_create_mux_port(i); | |
1090 | else | |
1091 | i8042_create_aux_port(); | |
1092 | } | |
1093 | ||
1094 | i8042_create_kbd_port(); | |
1095 | ||
1096 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static void __exit i8042_exit(void) | |
1102 | { | |
1103 | int i; | |
1104 | ||
1105 | i8042_controller_cleanup(); | |
1106 | ||
1107 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1108 | if (i8042_ports[i].exists) | |
1109 | serio_unregister_port(i8042_ports[i].serio); | |
1110 | ||
1111 | del_timer_sync(&i8042_timer); | |
1112 | ||
1113 | platform_device_unregister(i8042_platform_device); | |
1114 | driver_unregister(&i8042_driver); | |
1115 | ||
1116 | i8042_platform_exit(); | |
1117 | ||
1118 | panic_blink = NULL; | |
1119 | } | |
1120 | ||
1121 | module_init(i8042_init); | |
1122 | module_exit(i8042_exit); |