Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
17f5b569 | 34 | #include <asm/msidef.h> |
b6c02715 | 35 | #include <asm/proto.h> |
46a7fa27 | 36 | #include <asm/iommu.h> |
1d9b16d1 | 37 | #include <asm/gart.h> |
27c2127a | 38 | #include <asm/dma.h> |
403f81d8 JR |
39 | |
40 | #include "amd_iommu_proto.h" | |
41 | #include "amd_iommu_types.h" | |
b6c02715 JR |
42 | |
43 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
44 | ||
815b33fd | 45 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 46 | |
aa3de9c0 OBC |
47 | /* |
48 | * This bitmap is used to advertise the page sizes our hardware support | |
49 | * to the IOMMU core, which will then use this information to split | |
50 | * physically contiguous memory regions it is mapping into page sizes | |
51 | * that we support. | |
52 | * | |
53 | * Traditionally the IOMMU core just handed us the mappings directly, | |
54 | * after making sure the size is an order of a 4KiB page and that the | |
55 | * mapping has natural alignment. | |
56 | * | |
57 | * To retain this behavior, we currently advertise that we support | |
58 | * all page sizes that are an order of 4KiB. | |
59 | * | |
60 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
61 | * we could change this to advertise the real page sizes we support. | |
62 | */ | |
63 | #define AMD_IOMMU_PGSIZES (~0xFFFUL) | |
64 | ||
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
0feae533 JR |
75 | /* |
76 | * Domain for untranslated devices - only allocated | |
77 | * if iommu=pt passed on kernel cmd line. | |
78 | */ | |
79 | static struct protection_domain *pt_domain; | |
80 | ||
26961efe | 81 | static struct iommu_ops amd_iommu_ops; |
26961efe | 82 | |
72e1dcc4 | 83 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 84 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 85 | |
ac1534a5 JR |
86 | static struct dma_map_ops amd_iommu_dma_ops; |
87 | ||
431b2a20 JR |
88 | /* |
89 | * general struct to manage commands send to an IOMMU | |
90 | */ | |
d6449536 | 91 | struct iommu_cmd { |
b6c02715 JR |
92 | u32 data[4]; |
93 | }; | |
94 | ||
04bfdd84 | 95 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 96 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 97 | |
15898bbc JR |
98 | /**************************************************************************** |
99 | * | |
100 | * Helper functions | |
101 | * | |
102 | ****************************************************************************/ | |
103 | ||
f62dda66 | 104 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
105 | { |
106 | struct iommu_dev_data *dev_data; | |
107 | unsigned long flags; | |
108 | ||
109 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
110 | if (!dev_data) | |
111 | return NULL; | |
112 | ||
f62dda66 | 113 | dev_data->devid = devid; |
8fa5f802 JR |
114 | atomic_set(&dev_data->bind, 0); |
115 | ||
116 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
117 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
118 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
119 | ||
120 | return dev_data; | |
121 | } | |
122 | ||
123 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
124 | { | |
125 | unsigned long flags; | |
126 | ||
127 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
128 | list_del(&dev_data->dev_data_list); | |
129 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
130 | ||
131 | kfree(dev_data); | |
132 | } | |
133 | ||
3b03bb74 JR |
134 | static struct iommu_dev_data *search_dev_data(u16 devid) |
135 | { | |
136 | struct iommu_dev_data *dev_data; | |
137 | unsigned long flags; | |
138 | ||
139 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
140 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
141 | if (dev_data->devid == devid) | |
142 | goto out_unlock; | |
143 | } | |
144 | ||
145 | dev_data = NULL; | |
146 | ||
147 | out_unlock: | |
148 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
149 | ||
150 | return dev_data; | |
151 | } | |
152 | ||
153 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
154 | { | |
155 | struct iommu_dev_data *dev_data; | |
156 | ||
157 | dev_data = search_dev_data(devid); | |
158 | ||
159 | if (dev_data == NULL) | |
160 | dev_data = alloc_dev_data(devid); | |
161 | ||
162 | return dev_data; | |
163 | } | |
164 | ||
15898bbc JR |
165 | static inline u16 get_device_id(struct device *dev) |
166 | { | |
167 | struct pci_dev *pdev = to_pci_dev(dev); | |
168 | ||
169 | return calc_devid(pdev->bus->number, pdev->devfn); | |
170 | } | |
171 | ||
657cbb6b JR |
172 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
173 | { | |
174 | return dev->archdata.iommu; | |
175 | } | |
176 | ||
5abcdba4 JR |
177 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
178 | { | |
179 | static const int caps[] = { | |
180 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
181 | PCI_EXT_CAP_ID_PRI, |
182 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
183 | }; |
184 | int i, pos; | |
185 | ||
186 | for (i = 0; i < 3; ++i) { | |
187 | pos = pci_find_ext_capability(pdev, caps[i]); | |
188 | if (pos == 0) | |
189 | return false; | |
190 | } | |
191 | ||
192 | return true; | |
193 | } | |
194 | ||
6a113ddc JR |
195 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
196 | { | |
197 | struct iommu_dev_data *dev_data; | |
198 | ||
199 | dev_data = get_dev_data(&pdev->dev); | |
200 | ||
201 | return dev_data->errata & (1 << erratum) ? true : false; | |
202 | } | |
203 | ||
71c70984 JR |
204 | /* |
205 | * In this function the list of preallocated protection domains is traversed to | |
206 | * find the domain for a specific device | |
207 | */ | |
208 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
209 | { | |
210 | struct dma_ops_domain *entry, *ret = NULL; | |
211 | unsigned long flags; | |
212 | u16 alias = amd_iommu_alias_table[devid]; | |
213 | ||
214 | if (list_empty(&iommu_pd_list)) | |
215 | return NULL; | |
216 | ||
217 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
218 | ||
219 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
220 | if (entry->target_dev == devid || | |
221 | entry->target_dev == alias) { | |
222 | ret = entry; | |
223 | break; | |
224 | } | |
225 | } | |
226 | ||
227 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
228 | ||
229 | return ret; | |
230 | } | |
231 | ||
98fc5a69 JR |
232 | /* |
233 | * This function checks if the driver got a valid device from the caller to | |
234 | * avoid dereferencing invalid pointers. | |
235 | */ | |
236 | static bool check_device(struct device *dev) | |
237 | { | |
238 | u16 devid; | |
239 | ||
240 | if (!dev || !dev->dma_mask) | |
241 | return false; | |
242 | ||
243 | /* No device or no PCI device */ | |
339d3261 | 244 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
245 | return false; |
246 | ||
247 | devid = get_device_id(dev); | |
248 | ||
249 | /* Out of our scope? */ | |
250 | if (devid > amd_iommu_last_bdf) | |
251 | return false; | |
252 | ||
253 | if (amd_iommu_rlookup_table[devid] == NULL) | |
254 | return false; | |
255 | ||
256 | return true; | |
257 | } | |
258 | ||
657cbb6b JR |
259 | static int iommu_init_device(struct device *dev) |
260 | { | |
5abcdba4 | 261 | struct pci_dev *pdev = to_pci_dev(dev); |
657cbb6b | 262 | struct iommu_dev_data *dev_data; |
8fa5f802 | 263 | u16 alias; |
657cbb6b JR |
264 | |
265 | if (dev->archdata.iommu) | |
266 | return 0; | |
267 | ||
3b03bb74 | 268 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
269 | if (!dev_data) |
270 | return -ENOMEM; | |
271 | ||
f62dda66 | 272 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 273 | if (alias != dev_data->devid) { |
71f77580 | 274 | struct iommu_dev_data *alias_data; |
b00d3bcf | 275 | |
71f77580 JR |
276 | alias_data = find_dev_data(alias); |
277 | if (alias_data == NULL) { | |
278 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
279 | dev_name(dev)); | |
2b02b091 JR |
280 | free_dev_data(dev_data); |
281 | return -ENOTSUPP; | |
282 | } | |
71f77580 | 283 | dev_data->alias_data = alias_data; |
26018874 | 284 | } |
657cbb6b | 285 | |
5abcdba4 JR |
286 | if (pci_iommuv2_capable(pdev)) { |
287 | struct amd_iommu *iommu; | |
288 | ||
289 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
290 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
291 | } | |
292 | ||
657cbb6b JR |
293 | dev->archdata.iommu = dev_data; |
294 | ||
657cbb6b JR |
295 | return 0; |
296 | } | |
297 | ||
26018874 JR |
298 | static void iommu_ignore_device(struct device *dev) |
299 | { | |
300 | u16 devid, alias; | |
301 | ||
302 | devid = get_device_id(dev); | |
303 | alias = amd_iommu_alias_table[devid]; | |
304 | ||
305 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
306 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
307 | ||
308 | amd_iommu_rlookup_table[devid] = NULL; | |
309 | amd_iommu_rlookup_table[alias] = NULL; | |
310 | } | |
311 | ||
657cbb6b JR |
312 | static void iommu_uninit_device(struct device *dev) |
313 | { | |
8fa5f802 JR |
314 | /* |
315 | * Nothing to do here - we keep dev_data around for unplugged devices | |
316 | * and reuse it when the device is re-plugged - not doing so would | |
317 | * introduce a ton of races. | |
318 | */ | |
657cbb6b | 319 | } |
b7cc9554 JR |
320 | |
321 | void __init amd_iommu_uninit_devices(void) | |
322 | { | |
8fa5f802 | 323 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
324 | struct pci_dev *pdev = NULL; |
325 | ||
326 | for_each_pci_dev(pdev) { | |
327 | ||
328 | if (!check_device(&pdev->dev)) | |
329 | continue; | |
330 | ||
331 | iommu_uninit_device(&pdev->dev); | |
332 | } | |
8fa5f802 JR |
333 | |
334 | /* Free all of our dev_data structures */ | |
335 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
336 | free_dev_data(dev_data); | |
b7cc9554 JR |
337 | } |
338 | ||
339 | int __init amd_iommu_init_devices(void) | |
340 | { | |
341 | struct pci_dev *pdev = NULL; | |
342 | int ret = 0; | |
343 | ||
344 | for_each_pci_dev(pdev) { | |
345 | ||
346 | if (!check_device(&pdev->dev)) | |
347 | continue; | |
348 | ||
349 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
350 | if (ret == -ENOTSUPP) |
351 | iommu_ignore_device(&pdev->dev); | |
352 | else if (ret) | |
b7cc9554 JR |
353 | goto out_free; |
354 | } | |
355 | ||
356 | return 0; | |
357 | ||
358 | out_free: | |
359 | ||
360 | amd_iommu_uninit_devices(); | |
361 | ||
362 | return ret; | |
363 | } | |
7f26508b JR |
364 | #ifdef CONFIG_AMD_IOMMU_STATS |
365 | ||
366 | /* | |
367 | * Initialization code for statistics collection | |
368 | */ | |
369 | ||
da49f6df | 370 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 371 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 372 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 373 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 374 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 375 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 376 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 377 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 378 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 379 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 380 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 381 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
382 | DECLARE_STATS_COUNTER(complete_ppr); |
383 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
384 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
385 | DECLARE_STATS_COUNTER(pri_requests); | |
386 | ||
7f26508b | 387 | static struct dentry *stats_dir; |
7f26508b JR |
388 | static struct dentry *de_fflush; |
389 | ||
390 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
391 | { | |
392 | if (stats_dir == NULL) | |
393 | return; | |
394 | ||
395 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
396 | &cnt->value); | |
397 | } | |
398 | ||
399 | static void amd_iommu_stats_init(void) | |
400 | { | |
401 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
402 | if (stats_dir == NULL) | |
403 | return; | |
404 | ||
7f26508b | 405 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 406 | &amd_iommu_unmap_flush); |
da49f6df JR |
407 | |
408 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 409 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 410 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 411 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 412 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 413 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 414 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 415 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 416 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 417 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 418 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 419 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
420 | amd_iommu_stats_add(&complete_ppr); |
421 | amd_iommu_stats_add(&invalidate_iotlb); | |
422 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
423 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
424 | } |
425 | ||
426 | #endif | |
427 | ||
a80dc3e0 JR |
428 | /**************************************************************************** |
429 | * | |
430 | * Interrupt handling functions | |
431 | * | |
432 | ****************************************************************************/ | |
433 | ||
e3e59876 JR |
434 | static void dump_dte_entry(u16 devid) |
435 | { | |
436 | int i; | |
437 | ||
ee6c2868 JR |
438 | for (i = 0; i < 4; ++i) |
439 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
440 | amd_iommu_dev_table[devid].data[i]); |
441 | } | |
442 | ||
945b4ac4 JR |
443 | static void dump_command(unsigned long phys_addr) |
444 | { | |
445 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
446 | int i; | |
447 | ||
448 | for (i = 0; i < 4; ++i) | |
449 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
450 | } | |
451 | ||
a345b23b | 452 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 453 | { |
3d06fca8 JR |
454 | int type, devid, domid, flags; |
455 | volatile u32 *event = __evt; | |
456 | int count = 0; | |
457 | u64 address; | |
458 | ||
459 | retry: | |
460 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
461 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
462 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
463 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
464 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
465 | ||
466 | if (type == 0) { | |
467 | /* Did we hit the erratum? */ | |
468 | if (++count == LOOP_TIMEOUT) { | |
469 | pr_err("AMD-Vi: No event written to event log\n"); | |
470 | return; | |
471 | } | |
472 | udelay(1); | |
473 | goto retry; | |
474 | } | |
90008ee4 | 475 | |
4c6f40d4 | 476 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
477 | |
478 | switch (type) { | |
479 | case EVENT_TYPE_ILL_DEV: | |
480 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
481 | "address=0x%016llx flags=0x%04x]\n", | |
482 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
483 | address, flags); | |
e3e59876 | 484 | dump_dte_entry(devid); |
90008ee4 JR |
485 | break; |
486 | case EVENT_TYPE_IO_FAULT: | |
487 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
488 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
489 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
490 | domid, address, flags); | |
491 | break; | |
492 | case EVENT_TYPE_DEV_TAB_ERR: | |
493 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
494 | "address=0x%016llx flags=0x%04x]\n", | |
495 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
496 | address, flags); | |
497 | break; | |
498 | case EVENT_TYPE_PAGE_TAB_ERR: | |
499 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
500 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
501 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
502 | domid, address, flags); | |
503 | break; | |
504 | case EVENT_TYPE_ILL_CMD: | |
505 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 506 | dump_command(address); |
90008ee4 JR |
507 | break; |
508 | case EVENT_TYPE_CMD_HARD_ERR: | |
509 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
510 | "flags=0x%04x]\n", address, flags); | |
511 | break; | |
512 | case EVENT_TYPE_IOTLB_INV_TO: | |
513 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
514 | "address=0x%016llx]\n", | |
515 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
516 | address); | |
517 | break; | |
518 | case EVENT_TYPE_INV_DEV_REQ: | |
519 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
520 | "address=0x%016llx flags=0x%04x]\n", | |
521 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
522 | address, flags); | |
523 | break; | |
524 | default: | |
525 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
526 | } | |
3d06fca8 JR |
527 | |
528 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
529 | } |
530 | ||
531 | static void iommu_poll_events(struct amd_iommu *iommu) | |
532 | { | |
533 | u32 head, tail; | |
534 | unsigned long flags; | |
535 | ||
536 | spin_lock_irqsave(&iommu->lock, flags); | |
537 | ||
538 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
539 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
540 | ||
541 | while (head != tail) { | |
a345b23b | 542 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
543 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
544 | } | |
545 | ||
546 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
547 | ||
548 | spin_unlock_irqrestore(&iommu->lock, flags); | |
549 | } | |
550 | ||
eee53537 | 551 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
552 | { |
553 | struct amd_iommu_fault fault; | |
72e1dcc4 | 554 | |
399be2f5 JR |
555 | INC_STATS_COUNTER(pri_requests); |
556 | ||
72e1dcc4 JR |
557 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
558 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
559 | return; | |
560 | } | |
561 | ||
562 | fault.address = raw[1]; | |
563 | fault.pasid = PPR_PASID(raw[0]); | |
564 | fault.device_id = PPR_DEVID(raw[0]); | |
565 | fault.tag = PPR_TAG(raw[0]); | |
566 | fault.flags = PPR_FLAGS(raw[0]); | |
567 | ||
72e1dcc4 JR |
568 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
569 | } | |
570 | ||
571 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
572 | { | |
573 | unsigned long flags; | |
574 | u32 head, tail; | |
575 | ||
576 | if (iommu->ppr_log == NULL) | |
577 | return; | |
578 | ||
eee53537 JR |
579 | /* enable ppr interrupts again */ |
580 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
581 | ||
72e1dcc4 JR |
582 | spin_lock_irqsave(&iommu->lock, flags); |
583 | ||
584 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
585 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
586 | ||
587 | while (head != tail) { | |
eee53537 JR |
588 | volatile u64 *raw; |
589 | u64 entry[2]; | |
590 | int i; | |
591 | ||
592 | raw = (u64 *)(iommu->ppr_log + head); | |
593 | ||
594 | /* | |
595 | * Hardware bug: Interrupt may arrive before the entry is | |
596 | * written to memory. If this happens we need to wait for the | |
597 | * entry to arrive. | |
598 | */ | |
599 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
600 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
601 | break; | |
602 | udelay(1); | |
603 | } | |
72e1dcc4 | 604 | |
eee53537 JR |
605 | /* Avoid memcpy function-call overhead */ |
606 | entry[0] = raw[0]; | |
607 | entry[1] = raw[1]; | |
72e1dcc4 | 608 | |
eee53537 JR |
609 | /* |
610 | * To detect the hardware bug we need to clear the entry | |
611 | * back to zero. | |
612 | */ | |
613 | raw[0] = raw[1] = 0UL; | |
614 | ||
615 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
616 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
617 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 JR |
618 | |
619 | /* | |
620 | * Release iommu->lock because ppr-handling might need to | |
621 | * re-aquire it | |
622 | */ | |
623 | spin_unlock_irqrestore(&iommu->lock, flags); | |
624 | ||
625 | /* Handle PPR entry */ | |
626 | iommu_handle_ppr_entry(iommu, entry); | |
627 | ||
628 | spin_lock_irqsave(&iommu->lock, flags); | |
629 | ||
630 | /* Refresh ring-buffer information */ | |
631 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
632 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
633 | } | |
634 | ||
72e1dcc4 JR |
635 | spin_unlock_irqrestore(&iommu->lock, flags); |
636 | } | |
637 | ||
72fe00f0 | 638 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 639 | { |
90008ee4 JR |
640 | struct amd_iommu *iommu; |
641 | ||
72e1dcc4 | 642 | for_each_iommu(iommu) { |
90008ee4 | 643 | iommu_poll_events(iommu); |
72e1dcc4 JR |
644 | iommu_poll_ppr_log(iommu); |
645 | } | |
90008ee4 JR |
646 | |
647 | return IRQ_HANDLED; | |
a80dc3e0 JR |
648 | } |
649 | ||
72fe00f0 JR |
650 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
651 | { | |
652 | return IRQ_WAKE_THREAD; | |
653 | } | |
654 | ||
431b2a20 JR |
655 | /**************************************************************************** |
656 | * | |
657 | * IOMMU command queuing functions | |
658 | * | |
659 | ****************************************************************************/ | |
660 | ||
ac0ea6e9 JR |
661 | static int wait_on_sem(volatile u64 *sem) |
662 | { | |
663 | int i = 0; | |
664 | ||
665 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
666 | udelay(1); | |
667 | i += 1; | |
668 | } | |
669 | ||
670 | if (i == LOOP_TIMEOUT) { | |
671 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
672 | return -EIO; | |
673 | } | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
678 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
679 | struct iommu_cmd *cmd, | |
680 | u32 tail) | |
a19ae1ec | 681 | { |
a19ae1ec JR |
682 | u8 *target; |
683 | ||
8a7c5ef3 | 684 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
685 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
686 | ||
687 | /* Copy command to buffer */ | |
688 | memcpy(target, cmd, sizeof(*cmd)); | |
689 | ||
690 | /* Tell the IOMMU about it */ | |
a19ae1ec | 691 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 692 | } |
a19ae1ec | 693 | |
815b33fd | 694 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 695 | { |
815b33fd JR |
696 | WARN_ON(address & 0x7ULL); |
697 | ||
ded46737 | 698 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
699 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
700 | cmd->data[1] = upper_32_bits(__pa(address)); | |
701 | cmd->data[2] = 1; | |
ded46737 JR |
702 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
703 | } | |
704 | ||
94fe79e2 JR |
705 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
706 | { | |
707 | memset(cmd, 0, sizeof(*cmd)); | |
708 | cmd->data[0] = devid; | |
709 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
710 | } | |
711 | ||
11b6402c JR |
712 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
713 | size_t size, u16 domid, int pde) | |
714 | { | |
715 | u64 pages; | |
716 | int s; | |
717 | ||
718 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
719 | s = 0; | |
720 | ||
721 | if (pages > 1) { | |
722 | /* | |
723 | * If we have to flush more than one page, flush all | |
724 | * TLB entries for this domain | |
725 | */ | |
726 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
727 | s = 1; | |
728 | } | |
729 | ||
730 | address &= PAGE_MASK; | |
731 | ||
732 | memset(cmd, 0, sizeof(*cmd)); | |
733 | cmd->data[1] |= domid; | |
734 | cmd->data[2] = lower_32_bits(address); | |
735 | cmd->data[3] = upper_32_bits(address); | |
736 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
737 | if (s) /* size bit - we flush more than one 4kb page */ | |
738 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
739 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
740 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
741 | } | |
742 | ||
cb41ed85 JR |
743 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
744 | u64 address, size_t size) | |
745 | { | |
746 | u64 pages; | |
747 | int s; | |
748 | ||
749 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
750 | s = 0; | |
751 | ||
752 | if (pages > 1) { | |
753 | /* | |
754 | * If we have to flush more than one page, flush all | |
755 | * TLB entries for this domain | |
756 | */ | |
757 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
758 | s = 1; | |
759 | } | |
760 | ||
761 | address &= PAGE_MASK; | |
762 | ||
763 | memset(cmd, 0, sizeof(*cmd)); | |
764 | cmd->data[0] = devid; | |
765 | cmd->data[0] |= (qdep & 0xff) << 24; | |
766 | cmd->data[1] = devid; | |
767 | cmd->data[2] = lower_32_bits(address); | |
768 | cmd->data[3] = upper_32_bits(address); | |
769 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
770 | if (s) | |
771 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
772 | } | |
773 | ||
22e266c7 JR |
774 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
775 | u64 address, bool size) | |
776 | { | |
777 | memset(cmd, 0, sizeof(*cmd)); | |
778 | ||
779 | address &= ~(0xfffULL); | |
780 | ||
781 | cmd->data[0] = pasid & PASID_MASK; | |
782 | cmd->data[1] = domid; | |
783 | cmd->data[2] = lower_32_bits(address); | |
784 | cmd->data[3] = upper_32_bits(address); | |
785 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
786 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
787 | if (size) | |
788 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
789 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
790 | } | |
791 | ||
792 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
793 | int qdep, u64 address, bool size) | |
794 | { | |
795 | memset(cmd, 0, sizeof(*cmd)); | |
796 | ||
797 | address &= ~(0xfffULL); | |
798 | ||
799 | cmd->data[0] = devid; | |
800 | cmd->data[0] |= (pasid & 0xff) << 16; | |
801 | cmd->data[0] |= (qdep & 0xff) << 24; | |
802 | cmd->data[1] = devid; | |
803 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
804 | cmd->data[2] = lower_32_bits(address); | |
805 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
806 | cmd->data[3] = upper_32_bits(address); | |
807 | if (size) | |
808 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
809 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
810 | } | |
811 | ||
c99afa25 JR |
812 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
813 | int status, int tag, bool gn) | |
814 | { | |
815 | memset(cmd, 0, sizeof(*cmd)); | |
816 | ||
817 | cmd->data[0] = devid; | |
818 | if (gn) { | |
819 | cmd->data[1] = pasid & PASID_MASK; | |
820 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
821 | } | |
822 | cmd->data[3] = tag & 0x1ff; | |
823 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
824 | ||
825 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
826 | } | |
827 | ||
58fc7f14 JR |
828 | static void build_inv_all(struct iommu_cmd *cmd) |
829 | { | |
830 | memset(cmd, 0, sizeof(*cmd)); | |
831 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
832 | } |
833 | ||
431b2a20 | 834 | /* |
431b2a20 | 835 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 836 | * hardware about the new command. |
431b2a20 | 837 | */ |
f1ca1512 JR |
838 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
839 | struct iommu_cmd *cmd, | |
840 | bool sync) | |
a19ae1ec | 841 | { |
ac0ea6e9 | 842 | u32 left, tail, head, next_tail; |
a19ae1ec | 843 | unsigned long flags; |
a19ae1ec | 844 | |
549c90dc | 845 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
846 | |
847 | again: | |
a19ae1ec | 848 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 849 | |
ac0ea6e9 JR |
850 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
851 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
852 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
853 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 854 | |
ac0ea6e9 JR |
855 | if (left <= 2) { |
856 | struct iommu_cmd sync_cmd; | |
857 | volatile u64 sem = 0; | |
858 | int ret; | |
8d201968 | 859 | |
ac0ea6e9 JR |
860 | build_completion_wait(&sync_cmd, (u64)&sem); |
861 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 862 | |
ac0ea6e9 JR |
863 | spin_unlock_irqrestore(&iommu->lock, flags); |
864 | ||
865 | if ((ret = wait_on_sem(&sem)) != 0) | |
866 | return ret; | |
867 | ||
868 | goto again; | |
8d201968 JR |
869 | } |
870 | ||
ac0ea6e9 JR |
871 | copy_cmd_to_buffer(iommu, cmd, tail); |
872 | ||
873 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 874 | iommu->need_sync = sync; |
ac0ea6e9 | 875 | |
a19ae1ec | 876 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 877 | |
815b33fd | 878 | return 0; |
8d201968 JR |
879 | } |
880 | ||
f1ca1512 JR |
881 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
882 | { | |
883 | return iommu_queue_command_sync(iommu, cmd, true); | |
884 | } | |
885 | ||
8d201968 JR |
886 | /* |
887 | * This function queues a completion wait command into the command | |
888 | * buffer of an IOMMU | |
889 | */ | |
a19ae1ec | 890 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
891 | { |
892 | struct iommu_cmd cmd; | |
815b33fd | 893 | volatile u64 sem = 0; |
ac0ea6e9 | 894 | int ret; |
8d201968 | 895 | |
09ee17eb | 896 | if (!iommu->need_sync) |
815b33fd | 897 | return 0; |
09ee17eb | 898 | |
815b33fd | 899 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 900 | |
f1ca1512 | 901 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 902 | if (ret) |
815b33fd | 903 | return ret; |
8d201968 | 904 | |
ac0ea6e9 | 905 | return wait_on_sem(&sem); |
8d201968 JR |
906 | } |
907 | ||
d8c13085 | 908 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 909 | { |
d8c13085 | 910 | struct iommu_cmd cmd; |
a19ae1ec | 911 | |
d8c13085 | 912 | build_inv_dte(&cmd, devid); |
7e4f88da | 913 | |
d8c13085 JR |
914 | return iommu_queue_command(iommu, &cmd); |
915 | } | |
09ee17eb | 916 | |
7d0c5cc5 JR |
917 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
918 | { | |
919 | u32 devid; | |
09ee17eb | 920 | |
7d0c5cc5 JR |
921 | for (devid = 0; devid <= 0xffff; ++devid) |
922 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 923 | |
7d0c5cc5 JR |
924 | iommu_completion_wait(iommu); |
925 | } | |
84df8175 | 926 | |
7d0c5cc5 JR |
927 | /* |
928 | * This function uses heavy locking and may disable irqs for some time. But | |
929 | * this is no issue because it is only called during resume. | |
930 | */ | |
931 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
932 | { | |
933 | u32 dom_id; | |
a19ae1ec | 934 | |
7d0c5cc5 JR |
935 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
936 | struct iommu_cmd cmd; | |
937 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
938 | dom_id, 1); | |
939 | iommu_queue_command(iommu, &cmd); | |
940 | } | |
8eed9833 | 941 | |
7d0c5cc5 | 942 | iommu_completion_wait(iommu); |
a19ae1ec JR |
943 | } |
944 | ||
58fc7f14 | 945 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 946 | { |
58fc7f14 | 947 | struct iommu_cmd cmd; |
0518a3a4 | 948 | |
58fc7f14 | 949 | build_inv_all(&cmd); |
0518a3a4 | 950 | |
58fc7f14 JR |
951 | iommu_queue_command(iommu, &cmd); |
952 | iommu_completion_wait(iommu); | |
953 | } | |
954 | ||
7d0c5cc5 JR |
955 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
956 | { | |
58fc7f14 JR |
957 | if (iommu_feature(iommu, FEATURE_IA)) { |
958 | iommu_flush_all(iommu); | |
959 | } else { | |
960 | iommu_flush_dte_all(iommu); | |
961 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
962 | } |
963 | } | |
964 | ||
431b2a20 | 965 | /* |
cb41ed85 | 966 | * Command send function for flushing on-device TLB |
431b2a20 | 967 | */ |
6c542047 JR |
968 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
969 | u64 address, size_t size) | |
3fa43655 JR |
970 | { |
971 | struct amd_iommu *iommu; | |
b00d3bcf | 972 | struct iommu_cmd cmd; |
cb41ed85 | 973 | int qdep; |
3fa43655 | 974 | |
ea61cddb JR |
975 | qdep = dev_data->ats.qdep; |
976 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 977 | |
ea61cddb | 978 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
979 | |
980 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
981 | } |
982 | ||
431b2a20 | 983 | /* |
431b2a20 | 984 | * Command send function for invalidating a device table entry |
431b2a20 | 985 | */ |
6c542047 | 986 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 987 | { |
3fa43655 | 988 | struct amd_iommu *iommu; |
ee2fa743 | 989 | int ret; |
a19ae1ec | 990 | |
6c542047 | 991 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 992 | |
f62dda66 | 993 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
994 | if (ret) |
995 | return ret; | |
996 | ||
ea61cddb | 997 | if (dev_data->ats.enabled) |
6c542047 | 998 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 999 | |
ee2fa743 | 1000 | return ret; |
a19ae1ec JR |
1001 | } |
1002 | ||
431b2a20 JR |
1003 | /* |
1004 | * TLB invalidation function which is called from the mapping functions. | |
1005 | * It invalidates a single PTE if the range to flush is within a single | |
1006 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1007 | */ | |
17b124bf JR |
1008 | static void __domain_flush_pages(struct protection_domain *domain, |
1009 | u64 address, size_t size, int pde) | |
a19ae1ec | 1010 | { |
cb41ed85 | 1011 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1012 | struct iommu_cmd cmd; |
1013 | int ret = 0, i; | |
a19ae1ec | 1014 | |
11b6402c | 1015 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1016 | |
6de8ad9b JR |
1017 | for (i = 0; i < amd_iommus_present; ++i) { |
1018 | if (!domain->dev_iommu[i]) | |
1019 | continue; | |
1020 | ||
1021 | /* | |
1022 | * Devices of this domain are behind this IOMMU | |
1023 | * We need a TLB flush | |
1024 | */ | |
11b6402c | 1025 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1026 | } |
1027 | ||
cb41ed85 | 1028 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1029 | |
ea61cddb | 1030 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1031 | continue; |
1032 | ||
6c542047 | 1033 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1034 | } |
1035 | ||
11b6402c | 1036 | WARN_ON(ret); |
6de8ad9b JR |
1037 | } |
1038 | ||
17b124bf JR |
1039 | static void domain_flush_pages(struct protection_domain *domain, |
1040 | u64 address, size_t size) | |
6de8ad9b | 1041 | { |
17b124bf | 1042 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1043 | } |
b6c02715 | 1044 | |
1c655773 | 1045 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1046 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1047 | { |
17b124bf | 1048 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1049 | } |
1050 | ||
42a49f96 | 1051 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1052 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1053 | { |
17b124bf | 1054 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1055 | } |
1056 | ||
17b124bf | 1057 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1058 | { |
17b124bf | 1059 | int i; |
18811f55 | 1060 | |
17b124bf JR |
1061 | for (i = 0; i < amd_iommus_present; ++i) { |
1062 | if (!domain->dev_iommu[i]) | |
1063 | continue; | |
bfd1be18 | 1064 | |
17b124bf JR |
1065 | /* |
1066 | * Devices of this domain are behind this IOMMU | |
1067 | * We need to wait for completion of all commands. | |
1068 | */ | |
1069 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1070 | } |
e394d72a JR |
1071 | } |
1072 | ||
b00d3bcf | 1073 | |
09b42804 | 1074 | /* |
b00d3bcf | 1075 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1076 | */ |
17b124bf | 1077 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1078 | { |
b00d3bcf | 1079 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1080 | |
b00d3bcf | 1081 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1082 | device_flush_dte(dev_data); |
a345b23b JR |
1083 | } |
1084 | ||
431b2a20 JR |
1085 | /**************************************************************************** |
1086 | * | |
1087 | * The functions below are used the create the page table mappings for | |
1088 | * unity mapped regions. | |
1089 | * | |
1090 | ****************************************************************************/ | |
1091 | ||
308973d3 JR |
1092 | /* |
1093 | * This function is used to add another level to an IO page table. Adding | |
1094 | * another level increases the size of the address space by 9 bits to a size up | |
1095 | * to 64 bits. | |
1096 | */ | |
1097 | static bool increase_address_space(struct protection_domain *domain, | |
1098 | gfp_t gfp) | |
1099 | { | |
1100 | u64 *pte; | |
1101 | ||
1102 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1103 | /* address space already 64 bit large */ | |
1104 | return false; | |
1105 | ||
1106 | pte = (void *)get_zeroed_page(gfp); | |
1107 | if (!pte) | |
1108 | return false; | |
1109 | ||
1110 | *pte = PM_LEVEL_PDE(domain->mode, | |
1111 | virt_to_phys(domain->pt_root)); | |
1112 | domain->pt_root = pte; | |
1113 | domain->mode += 1; | |
1114 | domain->updated = true; | |
1115 | ||
1116 | return true; | |
1117 | } | |
1118 | ||
1119 | static u64 *alloc_pte(struct protection_domain *domain, | |
1120 | unsigned long address, | |
cbb9d729 | 1121 | unsigned long page_size, |
308973d3 JR |
1122 | u64 **pte_page, |
1123 | gfp_t gfp) | |
1124 | { | |
cbb9d729 | 1125 | int level, end_lvl; |
308973d3 | 1126 | u64 *pte, *page; |
cbb9d729 JR |
1127 | |
1128 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1129 | |
1130 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1131 | increase_address_space(domain, gfp); | |
1132 | ||
cbb9d729 JR |
1133 | level = domain->mode - 1; |
1134 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1135 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1136 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1137 | |
1138 | while (level > end_lvl) { | |
1139 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1140 | page = (u64 *)get_zeroed_page(gfp); | |
1141 | if (!page) | |
1142 | return NULL; | |
1143 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1144 | } | |
1145 | ||
cbb9d729 JR |
1146 | /* No level skipping support yet */ |
1147 | if (PM_PTE_LEVEL(*pte) != level) | |
1148 | return NULL; | |
1149 | ||
308973d3 JR |
1150 | level -= 1; |
1151 | ||
1152 | pte = IOMMU_PTE_PAGE(*pte); | |
1153 | ||
1154 | if (pte_page && level == end_lvl) | |
1155 | *pte_page = pte; | |
1156 | ||
1157 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1158 | } | |
1159 | ||
1160 | return pte; | |
1161 | } | |
1162 | ||
1163 | /* | |
1164 | * This function checks if there is a PTE for a given dma address. If | |
1165 | * there is one, it returns the pointer to it. | |
1166 | */ | |
24cd7723 | 1167 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1168 | { |
1169 | int level; | |
1170 | u64 *pte; | |
1171 | ||
24cd7723 JR |
1172 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1173 | return NULL; | |
1174 | ||
1175 | level = domain->mode - 1; | |
1176 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1177 | |
24cd7723 JR |
1178 | while (level > 0) { |
1179 | ||
1180 | /* Not Present */ | |
308973d3 JR |
1181 | if (!IOMMU_PTE_PRESENT(*pte)) |
1182 | return NULL; | |
1183 | ||
24cd7723 JR |
1184 | /* Large PTE */ |
1185 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1186 | unsigned long pte_mask, __pte; | |
1187 | ||
1188 | /* | |
1189 | * If we have a series of large PTEs, make | |
1190 | * sure to return a pointer to the first one. | |
1191 | */ | |
1192 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1193 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1194 | __pte = ((unsigned long)pte) & pte_mask; | |
1195 | ||
1196 | return (u64 *)__pte; | |
1197 | } | |
1198 | ||
1199 | /* No level skipping support yet */ | |
1200 | if (PM_PTE_LEVEL(*pte) != level) | |
1201 | return NULL; | |
1202 | ||
308973d3 JR |
1203 | level -= 1; |
1204 | ||
24cd7723 | 1205 | /* Walk to the next level */ |
308973d3 JR |
1206 | pte = IOMMU_PTE_PAGE(*pte); |
1207 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1208 | } |
1209 | ||
1210 | return pte; | |
1211 | } | |
1212 | ||
431b2a20 JR |
1213 | /* |
1214 | * Generic mapping functions. It maps a physical address into a DMA | |
1215 | * address space. It allocates the page table pages if necessary. | |
1216 | * In the future it can be extended to a generic mapping function | |
1217 | * supporting all features of AMD IOMMU page tables like level skipping | |
1218 | * and full 64 bit address spaces. | |
1219 | */ | |
38e817fe JR |
1220 | static int iommu_map_page(struct protection_domain *dom, |
1221 | unsigned long bus_addr, | |
1222 | unsigned long phys_addr, | |
abdc5eb3 | 1223 | int prot, |
cbb9d729 | 1224 | unsigned long page_size) |
bd0e5211 | 1225 | { |
8bda3092 | 1226 | u64 __pte, *pte; |
cbb9d729 | 1227 | int i, count; |
abdc5eb3 | 1228 | |
bad1cac2 | 1229 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1230 | return -EINVAL; |
1231 | ||
cbb9d729 JR |
1232 | bus_addr = PAGE_ALIGN(bus_addr); |
1233 | phys_addr = PAGE_ALIGN(phys_addr); | |
1234 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1235 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1236 | ||
1237 | for (i = 0; i < count; ++i) | |
1238 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1239 | return -EBUSY; | |
bd0e5211 | 1240 | |
cbb9d729 JR |
1241 | if (page_size > PAGE_SIZE) { |
1242 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1243 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1244 | } else | |
1245 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1246 | |
bd0e5211 JR |
1247 | if (prot & IOMMU_PROT_IR) |
1248 | __pte |= IOMMU_PTE_IR; | |
1249 | if (prot & IOMMU_PROT_IW) | |
1250 | __pte |= IOMMU_PTE_IW; | |
1251 | ||
cbb9d729 JR |
1252 | for (i = 0; i < count; ++i) |
1253 | pte[i] = __pte; | |
bd0e5211 | 1254 | |
04bfdd84 JR |
1255 | update_domain(dom); |
1256 | ||
bd0e5211 JR |
1257 | return 0; |
1258 | } | |
1259 | ||
24cd7723 JR |
1260 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1261 | unsigned long bus_addr, | |
1262 | unsigned long page_size) | |
eb74ff6c | 1263 | { |
24cd7723 JR |
1264 | unsigned long long unmap_size, unmapped; |
1265 | u64 *pte; | |
1266 | ||
1267 | BUG_ON(!is_power_of_2(page_size)); | |
1268 | ||
1269 | unmapped = 0; | |
eb74ff6c | 1270 | |
24cd7723 JR |
1271 | while (unmapped < page_size) { |
1272 | ||
1273 | pte = fetch_pte(dom, bus_addr); | |
1274 | ||
1275 | if (!pte) { | |
1276 | /* | |
1277 | * No PTE for this address | |
1278 | * move forward in 4kb steps | |
1279 | */ | |
1280 | unmap_size = PAGE_SIZE; | |
1281 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1282 | /* 4kb PTE found for this address */ | |
1283 | unmap_size = PAGE_SIZE; | |
1284 | *pte = 0ULL; | |
1285 | } else { | |
1286 | int count, i; | |
1287 | ||
1288 | /* Large PTE found which maps this address */ | |
1289 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1290 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1291 | for (i = 0; i < count; i++) | |
1292 | pte[i] = 0ULL; | |
1293 | } | |
1294 | ||
1295 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1296 | unmapped += unmap_size; | |
1297 | } | |
1298 | ||
1299 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1300 | |
24cd7723 | 1301 | return unmapped; |
eb74ff6c | 1302 | } |
eb74ff6c | 1303 | |
431b2a20 JR |
1304 | /* |
1305 | * This function checks if a specific unity mapping entry is needed for | |
1306 | * this specific IOMMU. | |
1307 | */ | |
bd0e5211 JR |
1308 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1309 | struct unity_map_entry *entry) | |
1310 | { | |
1311 | u16 bdf, i; | |
1312 | ||
1313 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1314 | bdf = amd_iommu_alias_table[i]; | |
1315 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1316 | return 1; | |
1317 | } | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
431b2a20 JR |
1322 | /* |
1323 | * This function actually applies the mapping to the page table of the | |
1324 | * dma_ops domain. | |
1325 | */ | |
bd0e5211 JR |
1326 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1327 | struct unity_map_entry *e) | |
1328 | { | |
1329 | u64 addr; | |
1330 | int ret; | |
1331 | ||
1332 | for (addr = e->address_start; addr < e->address_end; | |
1333 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1334 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1335 | PAGE_SIZE); |
bd0e5211 JR |
1336 | if (ret) |
1337 | return ret; | |
1338 | /* | |
1339 | * if unity mapping is in aperture range mark the page | |
1340 | * as allocated in the aperture | |
1341 | */ | |
1342 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1343 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1344 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1345 | } |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
171e7b37 JR |
1350 | /* |
1351 | * Init the unity mappings for a specific IOMMU in the system | |
1352 | * | |
1353 | * Basically iterates over all unity mapping entries and applies them to | |
1354 | * the default domain DMA of that IOMMU if necessary. | |
1355 | */ | |
1356 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1357 | { | |
1358 | struct unity_map_entry *entry; | |
1359 | int ret; | |
1360 | ||
1361 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1362 | if (!iommu_for_unity_map(iommu, entry)) | |
1363 | continue; | |
1364 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1365 | if (ret) | |
1366 | return ret; | |
1367 | } | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
431b2a20 JR |
1372 | /* |
1373 | * Inits the unity mappings required for a specific device | |
1374 | */ | |
bd0e5211 JR |
1375 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1376 | u16 devid) | |
1377 | { | |
1378 | struct unity_map_entry *e; | |
1379 | int ret; | |
1380 | ||
1381 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1382 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1383 | continue; | |
1384 | ret = dma_ops_unity_map(dma_dom, e); | |
1385 | if (ret) | |
1386 | return ret; | |
1387 | } | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
431b2a20 JR |
1392 | /**************************************************************************** |
1393 | * | |
1394 | * The next functions belong to the address allocator for the dma_ops | |
1395 | * interface functions. They work like the allocators in the other IOMMU | |
1396 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1397 | * the aperture. Maybe it could be enhanced in the future to a more | |
1398 | * efficient allocator. | |
1399 | * | |
1400 | ****************************************************************************/ | |
d3086444 | 1401 | |
431b2a20 | 1402 | /* |
384de729 | 1403 | * The address allocator core functions. |
431b2a20 JR |
1404 | * |
1405 | * called with domain->lock held | |
1406 | */ | |
384de729 | 1407 | |
171e7b37 JR |
1408 | /* |
1409 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1410 | * ranges. | |
1411 | */ | |
1412 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1413 | unsigned long start_page, | |
1414 | unsigned int pages) | |
1415 | { | |
1416 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1417 | ||
1418 | if (start_page + pages > last_page) | |
1419 | pages = last_page - start_page; | |
1420 | ||
1421 | for (i = start_page; i < start_page + pages; ++i) { | |
1422 | int index = i / APERTURE_RANGE_PAGES; | |
1423 | int page = i % APERTURE_RANGE_PAGES; | |
1424 | __set_bit(page, dom->aperture[index]->bitmap); | |
1425 | } | |
1426 | } | |
1427 | ||
9cabe89b JR |
1428 | /* |
1429 | * This function is used to add a new aperture range to an existing | |
1430 | * aperture in case of dma_ops domain allocation or address allocation | |
1431 | * failure. | |
1432 | */ | |
576175c2 | 1433 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1434 | bool populate, gfp_t gfp) |
1435 | { | |
1436 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1437 | struct amd_iommu *iommu; |
17f5b569 | 1438 | unsigned long i, old_size; |
9cabe89b | 1439 | |
f5e9705c JR |
1440 | #ifdef CONFIG_IOMMU_STRESS |
1441 | populate = false; | |
1442 | #endif | |
1443 | ||
9cabe89b JR |
1444 | if (index >= APERTURE_MAX_RANGES) |
1445 | return -ENOMEM; | |
1446 | ||
1447 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1448 | if (!dma_dom->aperture[index]) | |
1449 | return -ENOMEM; | |
1450 | ||
1451 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1452 | if (!dma_dom->aperture[index]->bitmap) | |
1453 | goto out_free; | |
1454 | ||
1455 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1456 | ||
1457 | if (populate) { | |
1458 | unsigned long address = dma_dom->aperture_size; | |
1459 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1460 | u64 *pte, *pte_page; | |
1461 | ||
1462 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1463 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1464 | &pte_page, gfp); |
1465 | if (!pte) | |
1466 | goto out_free; | |
1467 | ||
1468 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1469 | ||
1470 | address += APERTURE_RANGE_SIZE / 64; | |
1471 | } | |
1472 | } | |
1473 | ||
17f5b569 | 1474 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1475 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1476 | ||
17f5b569 JR |
1477 | /* Reserve address range used for MSI messages */ |
1478 | if (old_size < MSI_ADDR_BASE_LO && | |
1479 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1480 | unsigned long spage; | |
1481 | int pages; | |
1482 | ||
1483 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1484 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1485 | ||
1486 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1487 | } | |
1488 | ||
b595076a | 1489 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1490 | for_each_iommu(iommu) { |
1491 | if (iommu->exclusion_start && | |
1492 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1493 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1494 | unsigned long startpage; | |
1495 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1496 | iommu->exclusion_length, | |
1497 | PAGE_SIZE); | |
1498 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1499 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1500 | } | |
00cd122a JR |
1501 | } |
1502 | ||
1503 | /* | |
1504 | * Check for areas already mapped as present in the new aperture | |
1505 | * range and mark those pages as reserved in the allocator. Such | |
1506 | * mappings may already exist as a result of requested unity | |
1507 | * mappings for devices. | |
1508 | */ | |
1509 | for (i = dma_dom->aperture[index]->offset; | |
1510 | i < dma_dom->aperture_size; | |
1511 | i += PAGE_SIZE) { | |
24cd7723 | 1512 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1513 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1514 | continue; | |
1515 | ||
fcd0861d | 1516 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1517 | } |
1518 | ||
04bfdd84 JR |
1519 | update_domain(&dma_dom->domain); |
1520 | ||
9cabe89b JR |
1521 | return 0; |
1522 | ||
1523 | out_free: | |
04bfdd84 JR |
1524 | update_domain(&dma_dom->domain); |
1525 | ||
9cabe89b JR |
1526 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1527 | ||
1528 | kfree(dma_dom->aperture[index]); | |
1529 | dma_dom->aperture[index] = NULL; | |
1530 | ||
1531 | return -ENOMEM; | |
1532 | } | |
1533 | ||
384de729 JR |
1534 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1535 | struct dma_ops_domain *dom, | |
1536 | unsigned int pages, | |
1537 | unsigned long align_mask, | |
1538 | u64 dma_mask, | |
1539 | unsigned long start) | |
1540 | { | |
803b8cb4 | 1541 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1542 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1543 | int i = start >> APERTURE_RANGE_SHIFT; | |
1544 | unsigned long boundary_size; | |
1545 | unsigned long address = -1; | |
1546 | unsigned long limit; | |
1547 | ||
803b8cb4 JR |
1548 | next_bit >>= PAGE_SHIFT; |
1549 | ||
384de729 JR |
1550 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1551 | PAGE_SIZE) >> PAGE_SHIFT; | |
1552 | ||
1553 | for (;i < max_index; ++i) { | |
1554 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1555 | ||
1556 | if (dom->aperture[i]->offset >= dma_mask) | |
1557 | break; | |
1558 | ||
1559 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1560 | dma_mask >> PAGE_SHIFT); | |
1561 | ||
1562 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1563 | limit, next_bit, pages, 0, | |
1564 | boundary_size, align_mask); | |
1565 | if (address != -1) { | |
1566 | address = dom->aperture[i]->offset + | |
1567 | (address << PAGE_SHIFT); | |
803b8cb4 | 1568 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1569 | break; |
1570 | } | |
1571 | ||
1572 | next_bit = 0; | |
1573 | } | |
1574 | ||
1575 | return address; | |
1576 | } | |
1577 | ||
d3086444 JR |
1578 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1579 | struct dma_ops_domain *dom, | |
6d4f343f | 1580 | unsigned int pages, |
832a90c3 JR |
1581 | unsigned long align_mask, |
1582 | u64 dma_mask) | |
d3086444 | 1583 | { |
d3086444 | 1584 | unsigned long address; |
d3086444 | 1585 | |
fe16f088 JR |
1586 | #ifdef CONFIG_IOMMU_STRESS |
1587 | dom->next_address = 0; | |
1588 | dom->need_flush = true; | |
1589 | #endif | |
d3086444 | 1590 | |
384de729 | 1591 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1592 | dma_mask, dom->next_address); |
d3086444 | 1593 | |
1c655773 | 1594 | if (address == -1) { |
803b8cb4 | 1595 | dom->next_address = 0; |
384de729 JR |
1596 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1597 | dma_mask, 0); | |
1c655773 JR |
1598 | dom->need_flush = true; |
1599 | } | |
d3086444 | 1600 | |
384de729 | 1601 | if (unlikely(address == -1)) |
8fd524b3 | 1602 | address = DMA_ERROR_CODE; |
d3086444 JR |
1603 | |
1604 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1605 | ||
1606 | return address; | |
1607 | } | |
1608 | ||
431b2a20 JR |
1609 | /* |
1610 | * The address free function. | |
1611 | * | |
1612 | * called with domain->lock held | |
1613 | */ | |
d3086444 JR |
1614 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1615 | unsigned long address, | |
1616 | unsigned int pages) | |
1617 | { | |
384de729 JR |
1618 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1619 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1620 | |
384de729 JR |
1621 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1622 | ||
47bccd6b JR |
1623 | #ifdef CONFIG_IOMMU_STRESS |
1624 | if (i < 4) | |
1625 | return; | |
1626 | #endif | |
80be308d | 1627 | |
803b8cb4 | 1628 | if (address >= dom->next_address) |
80be308d | 1629 | dom->need_flush = true; |
384de729 JR |
1630 | |
1631 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1632 | |
a66022c4 | 1633 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1634 | |
d3086444 JR |
1635 | } |
1636 | ||
431b2a20 JR |
1637 | /**************************************************************************** |
1638 | * | |
1639 | * The next functions belong to the domain allocation. A domain is | |
1640 | * allocated for every IOMMU as the default domain. If device isolation | |
1641 | * is enabled, every device get its own domain. The most important thing | |
1642 | * about domains is the page table mapping the DMA address space they | |
1643 | * contain. | |
1644 | * | |
1645 | ****************************************************************************/ | |
1646 | ||
aeb26f55 JR |
1647 | /* |
1648 | * This function adds a protection domain to the global protection domain list | |
1649 | */ | |
1650 | static void add_domain_to_list(struct protection_domain *domain) | |
1651 | { | |
1652 | unsigned long flags; | |
1653 | ||
1654 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1655 | list_add(&domain->list, &amd_iommu_pd_list); | |
1656 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1657 | } | |
1658 | ||
1659 | /* | |
1660 | * This function removes a protection domain to the global | |
1661 | * protection domain list | |
1662 | */ | |
1663 | static void del_domain_from_list(struct protection_domain *domain) | |
1664 | { | |
1665 | unsigned long flags; | |
1666 | ||
1667 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1668 | list_del(&domain->list); | |
1669 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1670 | } | |
1671 | ||
ec487d1a JR |
1672 | static u16 domain_id_alloc(void) |
1673 | { | |
1674 | unsigned long flags; | |
1675 | int id; | |
1676 | ||
1677 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1678 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1679 | BUG_ON(id == 0); | |
1680 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1681 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1682 | else | |
1683 | id = 0; | |
1684 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1685 | ||
1686 | return id; | |
1687 | } | |
1688 | ||
a2acfb75 JR |
1689 | static void domain_id_free(int id) |
1690 | { | |
1691 | unsigned long flags; | |
1692 | ||
1693 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1694 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1695 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1696 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1697 | } | |
a2acfb75 | 1698 | |
86db2e5d | 1699 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1700 | { |
1701 | int i, j; | |
1702 | u64 *p1, *p2, *p3; | |
1703 | ||
86db2e5d | 1704 | p1 = domain->pt_root; |
ec487d1a JR |
1705 | |
1706 | if (!p1) | |
1707 | return; | |
1708 | ||
1709 | for (i = 0; i < 512; ++i) { | |
1710 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1711 | continue; | |
1712 | ||
1713 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1714 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1715 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1716 | continue; | |
1717 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1718 | free_page((unsigned long)p3); | |
1719 | } | |
1720 | ||
1721 | free_page((unsigned long)p2); | |
1722 | } | |
1723 | ||
1724 | free_page((unsigned long)p1); | |
86db2e5d JR |
1725 | |
1726 | domain->pt_root = NULL; | |
ec487d1a JR |
1727 | } |
1728 | ||
b16137b1 JR |
1729 | static void free_gcr3_tbl_level1(u64 *tbl) |
1730 | { | |
1731 | u64 *ptr; | |
1732 | int i; | |
1733 | ||
1734 | for (i = 0; i < 512; ++i) { | |
1735 | if (!(tbl[i] & GCR3_VALID)) | |
1736 | continue; | |
1737 | ||
1738 | ptr = __va(tbl[i] & PAGE_MASK); | |
1739 | ||
1740 | free_page((unsigned long)ptr); | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1745 | { | |
1746 | u64 *ptr; | |
1747 | int i; | |
1748 | ||
1749 | for (i = 0; i < 512; ++i) { | |
1750 | if (!(tbl[i] & GCR3_VALID)) | |
1751 | continue; | |
1752 | ||
1753 | ptr = __va(tbl[i] & PAGE_MASK); | |
1754 | ||
1755 | free_gcr3_tbl_level1(ptr); | |
1756 | } | |
1757 | } | |
1758 | ||
52815b75 JR |
1759 | static void free_gcr3_table(struct protection_domain *domain) |
1760 | { | |
b16137b1 JR |
1761 | if (domain->glx == 2) |
1762 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1763 | else if (domain->glx == 1) | |
1764 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1765 | else if (domain->glx != 0) | |
1766 | BUG(); | |
1767 | ||
52815b75 JR |
1768 | free_page((unsigned long)domain->gcr3_tbl); |
1769 | } | |
1770 | ||
431b2a20 JR |
1771 | /* |
1772 | * Free a domain, only used if something went wrong in the | |
1773 | * allocation path and we need to free an already allocated page table | |
1774 | */ | |
ec487d1a JR |
1775 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1776 | { | |
384de729 JR |
1777 | int i; |
1778 | ||
ec487d1a JR |
1779 | if (!dom) |
1780 | return; | |
1781 | ||
aeb26f55 JR |
1782 | del_domain_from_list(&dom->domain); |
1783 | ||
86db2e5d | 1784 | free_pagetable(&dom->domain); |
ec487d1a | 1785 | |
384de729 JR |
1786 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1787 | if (!dom->aperture[i]) | |
1788 | continue; | |
1789 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1790 | kfree(dom->aperture[i]); | |
1791 | } | |
ec487d1a JR |
1792 | |
1793 | kfree(dom); | |
1794 | } | |
1795 | ||
431b2a20 JR |
1796 | /* |
1797 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1798 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1799 | * structures required for the dma_ops interface |
1800 | */ | |
87a64d52 | 1801 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1802 | { |
1803 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1804 | |
1805 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1806 | if (!dma_dom) | |
1807 | return NULL; | |
1808 | ||
1809 | spin_lock_init(&dma_dom->domain.lock); | |
1810 | ||
1811 | dma_dom->domain.id = domain_id_alloc(); | |
1812 | if (dma_dom->domain.id == 0) | |
1813 | goto free_dma_dom; | |
7c392cbe | 1814 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1815 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1816 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1817 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1818 | dma_dom->domain.priv = dma_dom; |
1819 | if (!dma_dom->domain.pt_root) | |
1820 | goto free_dma_dom; | |
ec487d1a | 1821 | |
1c655773 | 1822 | dma_dom->need_flush = false; |
bd60b735 | 1823 | dma_dom->target_dev = 0xffff; |
1c655773 | 1824 | |
aeb26f55 JR |
1825 | add_domain_to_list(&dma_dom->domain); |
1826 | ||
576175c2 | 1827 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1828 | goto free_dma_dom; |
ec487d1a | 1829 | |
431b2a20 | 1830 | /* |
ec487d1a JR |
1831 | * mark the first page as allocated so we never return 0 as |
1832 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1833 | */ |
384de729 | 1834 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1835 | dma_dom->next_address = 0; |
ec487d1a | 1836 | |
ec487d1a JR |
1837 | |
1838 | return dma_dom; | |
1839 | ||
1840 | free_dma_dom: | |
1841 | dma_ops_domain_free(dma_dom); | |
1842 | ||
1843 | return NULL; | |
1844 | } | |
1845 | ||
5b28df6f JR |
1846 | /* |
1847 | * little helper function to check whether a given protection domain is a | |
1848 | * dma_ops domain | |
1849 | */ | |
1850 | static bool dma_ops_domain(struct protection_domain *domain) | |
1851 | { | |
1852 | return domain->flags & PD_DMA_OPS_MASK; | |
1853 | } | |
1854 | ||
fd7b5535 | 1855 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1856 | { |
132bd68f | 1857 | u64 pte_root = 0; |
ee6c2868 | 1858 | u64 flags = 0; |
863c74eb | 1859 | |
132bd68f JR |
1860 | if (domain->mode != PAGE_MODE_NONE) |
1861 | pte_root = virt_to_phys(domain->pt_root); | |
1862 | ||
38ddf41b JR |
1863 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1864 | << DEV_ENTRY_MODE_SHIFT; | |
1865 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1866 | |
ee6c2868 JR |
1867 | flags = amd_iommu_dev_table[devid].data[1]; |
1868 | ||
fd7b5535 JR |
1869 | if (ats) |
1870 | flags |= DTE_FLAG_IOTLB; | |
1871 | ||
52815b75 JR |
1872 | if (domain->flags & PD_IOMMUV2_MASK) { |
1873 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1874 | u64 glx = domain->glx; | |
1875 | u64 tmp; | |
1876 | ||
1877 | pte_root |= DTE_FLAG_GV; | |
1878 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1879 | ||
1880 | /* First mask out possible old values for GCR3 table */ | |
1881 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1882 | flags &= ~tmp; | |
1883 | ||
1884 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1885 | flags &= ~tmp; | |
1886 | ||
1887 | /* Encode GCR3 table into DTE */ | |
1888 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1889 | pte_root |= tmp; | |
1890 | ||
1891 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1892 | flags |= tmp; | |
1893 | ||
1894 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1895 | flags |= tmp; | |
1896 | } | |
1897 | ||
ee6c2868 JR |
1898 | flags &= ~(0xffffUL); |
1899 | flags |= domain->id; | |
1900 | ||
1901 | amd_iommu_dev_table[devid].data[1] = flags; | |
1902 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1903 | } |
1904 | ||
1905 | static void clear_dte_entry(u16 devid) | |
1906 | { | |
15898bbc JR |
1907 | /* remove entry from the device table seen by the hardware */ |
1908 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1909 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1910 | |
1911 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1912 | } |
1913 | ||
ec9e79ef JR |
1914 | static void do_attach(struct iommu_dev_data *dev_data, |
1915 | struct protection_domain *domain) | |
7f760ddd | 1916 | { |
7f760ddd | 1917 | struct amd_iommu *iommu; |
ec9e79ef | 1918 | bool ats; |
fd7b5535 | 1919 | |
ec9e79ef JR |
1920 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1921 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1922 | |
1923 | /* Update data structures */ | |
1924 | dev_data->domain = domain; | |
1925 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1926 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1927 | |
1928 | /* Do reference counting */ | |
1929 | domain->dev_iommu[iommu->index] += 1; | |
1930 | domain->dev_cnt += 1; | |
1931 | ||
1932 | /* Flush the DTE entry */ | |
6c542047 | 1933 | device_flush_dte(dev_data); |
7f760ddd JR |
1934 | } |
1935 | ||
ec9e79ef | 1936 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1937 | { |
7f760ddd | 1938 | struct amd_iommu *iommu; |
7f760ddd | 1939 | |
ec9e79ef | 1940 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1941 | |
1942 | /* decrease reference counters */ | |
7f760ddd JR |
1943 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1944 | dev_data->domain->dev_cnt -= 1; | |
1945 | ||
1946 | /* Update data structures */ | |
1947 | dev_data->domain = NULL; | |
1948 | list_del(&dev_data->list); | |
f62dda66 | 1949 | clear_dte_entry(dev_data->devid); |
15898bbc | 1950 | |
7f760ddd | 1951 | /* Flush the DTE entry */ |
6c542047 | 1952 | device_flush_dte(dev_data); |
2b681faf JR |
1953 | } |
1954 | ||
1955 | /* | |
1956 | * If a device is not yet associated with a domain, this function does | |
1957 | * assigns it visible for the hardware | |
1958 | */ | |
ec9e79ef | 1959 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1960 | struct protection_domain *domain) |
2b681faf | 1961 | { |
84fe6c19 | 1962 | int ret; |
657cbb6b | 1963 | |
2b681faf JR |
1964 | /* lock domain */ |
1965 | spin_lock(&domain->lock); | |
1966 | ||
71f77580 JR |
1967 | if (dev_data->alias_data != NULL) { |
1968 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1969 | |
2b02b091 JR |
1970 | /* Some sanity checks */ |
1971 | ret = -EBUSY; | |
1972 | if (alias_data->domain != NULL && | |
1973 | alias_data->domain != domain) | |
1974 | goto out_unlock; | |
eba6ac60 | 1975 | |
2b02b091 JR |
1976 | if (dev_data->domain != NULL && |
1977 | dev_data->domain != domain) | |
1978 | goto out_unlock; | |
15898bbc | 1979 | |
2b02b091 | 1980 | /* Do real assignment */ |
7f760ddd | 1981 | if (alias_data->domain == NULL) |
ec9e79ef | 1982 | do_attach(alias_data, domain); |
24100055 JR |
1983 | |
1984 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1985 | } |
15898bbc | 1986 | |
7f760ddd | 1987 | if (dev_data->domain == NULL) |
ec9e79ef | 1988 | do_attach(dev_data, domain); |
eba6ac60 | 1989 | |
24100055 JR |
1990 | atomic_inc(&dev_data->bind); |
1991 | ||
84fe6c19 JL |
1992 | ret = 0; |
1993 | ||
1994 | out_unlock: | |
1995 | ||
eba6ac60 JR |
1996 | /* ready */ |
1997 | spin_unlock(&domain->lock); | |
15898bbc | 1998 | |
84fe6c19 | 1999 | return ret; |
0feae533 | 2000 | } |
b20ac0d4 | 2001 | |
52815b75 JR |
2002 | |
2003 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2004 | { | |
2005 | pci_disable_ats(pdev); | |
2006 | pci_disable_pri(pdev); | |
2007 | pci_disable_pasid(pdev); | |
2008 | } | |
2009 | ||
6a113ddc JR |
2010 | /* FIXME: Change generic reset-function to do the same */ |
2011 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2012 | { | |
2013 | u16 control; | |
2014 | int pos; | |
2015 | ||
46277b75 | 2016 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2017 | if (!pos) |
2018 | return -EINVAL; | |
2019 | ||
46277b75 JR |
2020 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2021 | control |= PCI_PRI_CTRL_RESET; | |
2022 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2023 | |
2024 | return 0; | |
2025 | } | |
2026 | ||
52815b75 JR |
2027 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2028 | { | |
6a113ddc JR |
2029 | bool reset_enable; |
2030 | int reqs, ret; | |
2031 | ||
2032 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2033 | reqs = 32; | |
2034 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2035 | reqs = 1; | |
2036 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2037 | |
2038 | /* Only allow access to user-accessible pages */ | |
2039 | ret = pci_enable_pasid(pdev, 0); | |
2040 | if (ret) | |
2041 | goto out_err; | |
2042 | ||
2043 | /* First reset the PRI state of the device */ | |
2044 | ret = pci_reset_pri(pdev); | |
2045 | if (ret) | |
2046 | goto out_err; | |
2047 | ||
6a113ddc JR |
2048 | /* Enable PRI */ |
2049 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2050 | if (ret) |
2051 | goto out_err; | |
2052 | ||
6a113ddc JR |
2053 | if (reset_enable) { |
2054 | ret = pri_reset_while_enabled(pdev); | |
2055 | if (ret) | |
2056 | goto out_err; | |
2057 | } | |
2058 | ||
52815b75 JR |
2059 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2060 | if (ret) | |
2061 | goto out_err; | |
2062 | ||
2063 | return 0; | |
2064 | ||
2065 | out_err: | |
2066 | pci_disable_pri(pdev); | |
2067 | pci_disable_pasid(pdev); | |
2068 | ||
2069 | return ret; | |
2070 | } | |
2071 | ||
c99afa25 | 2072 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2073 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2074 | |
98f1ad25 | 2075 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2076 | { |
a3b93121 | 2077 | u16 status; |
c99afa25 JR |
2078 | int pos; |
2079 | ||
46277b75 | 2080 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2081 | if (!pos) |
2082 | return false; | |
2083 | ||
a3b93121 | 2084 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2085 | |
a3b93121 | 2086 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2087 | } |
2088 | ||
407d733e JR |
2089 | /* |
2090 | * If a device is not yet associated with a domain, this function does | |
2091 | * assigns it visible for the hardware | |
2092 | */ | |
15898bbc JR |
2093 | static int attach_device(struct device *dev, |
2094 | struct protection_domain *domain) | |
0feae533 | 2095 | { |
fd7b5535 | 2096 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2097 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2098 | unsigned long flags; |
15898bbc | 2099 | int ret; |
eba6ac60 | 2100 | |
ea61cddb JR |
2101 | dev_data = get_dev_data(dev); |
2102 | ||
52815b75 JR |
2103 | if (domain->flags & PD_IOMMUV2_MASK) { |
2104 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2105 | return -EINVAL; | |
2106 | ||
2107 | if (pdev_iommuv2_enable(pdev) != 0) | |
2108 | return -EINVAL; | |
2109 | ||
2110 | dev_data->ats.enabled = true; | |
2111 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2112 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2113 | } else if (amd_iommu_iotlb_sup && |
2114 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2115 | dev_data->ats.enabled = true; |
2116 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2117 | } | |
fd7b5535 | 2118 | |
eba6ac60 | 2119 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2120 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2121 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2122 | ||
0feae533 JR |
2123 | /* |
2124 | * We might boot into a crash-kernel here. The crashed kernel | |
2125 | * left the caches in the IOMMU dirty. So we have to flush | |
2126 | * here to evict all dirty stuff. | |
2127 | */ | |
17b124bf | 2128 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2129 | |
2130 | return ret; | |
b20ac0d4 JR |
2131 | } |
2132 | ||
355bf553 JR |
2133 | /* |
2134 | * Removes a device from a protection domain (unlocked) | |
2135 | */ | |
ec9e79ef | 2136 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2137 | { |
2ca76279 | 2138 | struct protection_domain *domain; |
7c392cbe | 2139 | unsigned long flags; |
c4596114 | 2140 | |
7f760ddd | 2141 | BUG_ON(!dev_data->domain); |
355bf553 | 2142 | |
2ca76279 JR |
2143 | domain = dev_data->domain; |
2144 | ||
2145 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2146 | |
71f77580 JR |
2147 | if (dev_data->alias_data != NULL) { |
2148 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2149 | ||
7f760ddd | 2150 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2151 | do_detach(alias_data); |
24100055 JR |
2152 | } |
2153 | ||
7f760ddd | 2154 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2155 | do_detach(dev_data); |
7f760ddd | 2156 | |
2ca76279 | 2157 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2158 | |
2159 | /* | |
2160 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2161 | * passthrough domain if it is detached from any other domain. |
2162 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2163 | */ |
5abcdba4 | 2164 | if (dev_data->passthrough && |
d3ad9373 | 2165 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2166 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2167 | } |
2168 | ||
2169 | /* | |
2170 | * Removes a device from a protection domain (with devtable_lock held) | |
2171 | */ | |
15898bbc | 2172 | static void detach_device(struct device *dev) |
355bf553 | 2173 | { |
52815b75 | 2174 | struct protection_domain *domain; |
ea61cddb | 2175 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2176 | unsigned long flags; |
2177 | ||
ec9e79ef | 2178 | dev_data = get_dev_data(dev); |
52815b75 | 2179 | domain = dev_data->domain; |
ec9e79ef | 2180 | |
355bf553 JR |
2181 | /* lock device table */ |
2182 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2183 | __detach_device(dev_data); |
355bf553 | 2184 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2185 | |
52815b75 JR |
2186 | if (domain->flags & PD_IOMMUV2_MASK) |
2187 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2188 | else if (dev_data->ats.enabled) | |
ea61cddb | 2189 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2190 | |
2191 | dev_data->ats.enabled = false; | |
355bf553 | 2192 | } |
e275a2a0 | 2193 | |
15898bbc JR |
2194 | /* |
2195 | * Find out the protection domain structure for a given PCI device. This | |
2196 | * will give us the pointer to the page table root for example. | |
2197 | */ | |
2198 | static struct protection_domain *domain_for_device(struct device *dev) | |
2199 | { | |
71f77580 | 2200 | struct iommu_dev_data *dev_data; |
2b02b091 | 2201 | struct protection_domain *dom = NULL; |
15898bbc | 2202 | unsigned long flags; |
15898bbc | 2203 | |
657cbb6b | 2204 | dev_data = get_dev_data(dev); |
15898bbc | 2205 | |
2b02b091 JR |
2206 | if (dev_data->domain) |
2207 | return dev_data->domain; | |
15898bbc | 2208 | |
71f77580 JR |
2209 | if (dev_data->alias_data != NULL) { |
2210 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2211 | |
2212 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2213 | if (alias_data->domain != NULL) { | |
2214 | __attach_device(dev_data, alias_data->domain); | |
2215 | dom = alias_data->domain; | |
2216 | } | |
2217 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2218 | } | |
15898bbc JR |
2219 | |
2220 | return dom; | |
2221 | } | |
2222 | ||
e275a2a0 JR |
2223 | static int device_change_notifier(struct notifier_block *nb, |
2224 | unsigned long action, void *data) | |
2225 | { | |
e275a2a0 | 2226 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2227 | struct protection_domain *domain; |
2228 | struct iommu_dev_data *dev_data; | |
2229 | struct device *dev = data; | |
e275a2a0 | 2230 | struct amd_iommu *iommu; |
1ac4cbbc | 2231 | unsigned long flags; |
5abcdba4 | 2232 | u16 devid; |
e275a2a0 | 2233 | |
98fc5a69 JR |
2234 | if (!check_device(dev)) |
2235 | return 0; | |
e275a2a0 | 2236 | |
5abcdba4 JR |
2237 | devid = get_device_id(dev); |
2238 | iommu = amd_iommu_rlookup_table[devid]; | |
2239 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2240 | |
2241 | switch (action) { | |
c1eee67b | 2242 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2243 | |
2244 | domain = domain_for_device(dev); | |
2245 | ||
e275a2a0 JR |
2246 | if (!domain) |
2247 | goto out; | |
5abcdba4 | 2248 | if (dev_data->passthrough) |
a1ca331c | 2249 | break; |
15898bbc | 2250 | detach_device(dev); |
1ac4cbbc JR |
2251 | break; |
2252 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2253 | |
2254 | iommu_init_device(dev); | |
2255 | ||
2256 | domain = domain_for_device(dev); | |
2257 | ||
1ac4cbbc JR |
2258 | /* allocate a protection domain if a device is added */ |
2259 | dma_domain = find_protection_domain(devid); | |
2260 | if (dma_domain) | |
2261 | goto out; | |
87a64d52 | 2262 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
2263 | if (!dma_domain) |
2264 | goto out; | |
2265 | dma_domain->target_dev = devid; | |
2266 | ||
2267 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2268 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2269 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2270 | ||
ac1534a5 JR |
2271 | dev_data = get_dev_data(dev); |
2272 | ||
2273 | if (!dev_data->passthrough) | |
2274 | dev->archdata.dma_ops = &amd_iommu_dma_ops; | |
2275 | else | |
2276 | dev->archdata.dma_ops = &nommu_dma_ops; | |
2277 | ||
e275a2a0 | 2278 | break; |
657cbb6b JR |
2279 | case BUS_NOTIFY_DEL_DEVICE: |
2280 | ||
2281 | iommu_uninit_device(dev); | |
2282 | ||
e275a2a0 JR |
2283 | default: |
2284 | goto out; | |
2285 | } | |
2286 | ||
e275a2a0 JR |
2287 | iommu_completion_wait(iommu); |
2288 | ||
2289 | out: | |
2290 | return 0; | |
2291 | } | |
2292 | ||
b25ae679 | 2293 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2294 | .notifier_call = device_change_notifier, |
2295 | }; | |
355bf553 | 2296 | |
8638c491 JR |
2297 | void amd_iommu_init_notifier(void) |
2298 | { | |
2299 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2300 | } | |
2301 | ||
431b2a20 JR |
2302 | /***************************************************************************** |
2303 | * | |
2304 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2305 | * | |
2306 | *****************************************************************************/ | |
2307 | ||
2308 | /* | |
2309 | * In the dma_ops path we only have the struct device. This function | |
2310 | * finds the corresponding IOMMU, the protection domain and the | |
2311 | * requestor id for a given device. | |
2312 | * If the device is not yet associated with a domain this is also done | |
2313 | * in this function. | |
2314 | */ | |
94f6d190 | 2315 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2316 | { |
94f6d190 | 2317 | struct protection_domain *domain; |
b20ac0d4 | 2318 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2319 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2320 | |
f99c0f1c | 2321 | if (!check_device(dev)) |
94f6d190 | 2322 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2323 | |
94f6d190 JR |
2324 | domain = domain_for_device(dev); |
2325 | if (domain != NULL && !dma_ops_domain(domain)) | |
2326 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2327 | |
94f6d190 JR |
2328 | if (domain != NULL) |
2329 | return domain; | |
b20ac0d4 | 2330 | |
15898bbc | 2331 | /* Device not bount yet - bind it */ |
94f6d190 | 2332 | dma_dom = find_protection_domain(devid); |
15898bbc | 2333 | if (!dma_dom) |
94f6d190 JR |
2334 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2335 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2336 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2337 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2338 | |
94f6d190 | 2339 | return &dma_dom->domain; |
b20ac0d4 JR |
2340 | } |
2341 | ||
04bfdd84 JR |
2342 | static void update_device_table(struct protection_domain *domain) |
2343 | { | |
492667da | 2344 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2345 | |
ea61cddb JR |
2346 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2347 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2348 | } |
2349 | ||
2350 | static void update_domain(struct protection_domain *domain) | |
2351 | { | |
2352 | if (!domain->updated) | |
2353 | return; | |
2354 | ||
2355 | update_device_table(domain); | |
17b124bf JR |
2356 | |
2357 | domain_flush_devices(domain); | |
2358 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2359 | |
2360 | domain->updated = false; | |
2361 | } | |
2362 | ||
8bda3092 JR |
2363 | /* |
2364 | * This function fetches the PTE for a given address in the aperture | |
2365 | */ | |
2366 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2367 | unsigned long address) | |
2368 | { | |
384de729 | 2369 | struct aperture_range *aperture; |
8bda3092 JR |
2370 | u64 *pte, *pte_page; |
2371 | ||
384de729 JR |
2372 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2373 | if (!aperture) | |
2374 | return NULL; | |
2375 | ||
2376 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2377 | if (!pte) { |
cbb9d729 | 2378 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2379 | GFP_ATOMIC); |
384de729 JR |
2380 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2381 | } else | |
8c8c143c | 2382 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2383 | |
04bfdd84 | 2384 | update_domain(&dom->domain); |
8bda3092 JR |
2385 | |
2386 | return pte; | |
2387 | } | |
2388 | ||
431b2a20 JR |
2389 | /* |
2390 | * This is the generic map function. It maps one 4kb page at paddr to | |
2391 | * the given address in the DMA address space for the domain. | |
2392 | */ | |
680525e0 | 2393 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2394 | unsigned long address, |
2395 | phys_addr_t paddr, | |
2396 | int direction) | |
2397 | { | |
2398 | u64 *pte, __pte; | |
2399 | ||
2400 | WARN_ON(address > dom->aperture_size); | |
2401 | ||
2402 | paddr &= PAGE_MASK; | |
2403 | ||
8bda3092 | 2404 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2405 | if (!pte) |
8fd524b3 | 2406 | return DMA_ERROR_CODE; |
cb76c322 JR |
2407 | |
2408 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2409 | ||
2410 | if (direction == DMA_TO_DEVICE) | |
2411 | __pte |= IOMMU_PTE_IR; | |
2412 | else if (direction == DMA_FROM_DEVICE) | |
2413 | __pte |= IOMMU_PTE_IW; | |
2414 | else if (direction == DMA_BIDIRECTIONAL) | |
2415 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2416 | ||
2417 | WARN_ON(*pte); | |
2418 | ||
2419 | *pte = __pte; | |
2420 | ||
2421 | return (dma_addr_t)address; | |
2422 | } | |
2423 | ||
431b2a20 JR |
2424 | /* |
2425 | * The generic unmapping function for on page in the DMA address space. | |
2426 | */ | |
680525e0 | 2427 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2428 | unsigned long address) |
2429 | { | |
384de729 | 2430 | struct aperture_range *aperture; |
cb76c322 JR |
2431 | u64 *pte; |
2432 | ||
2433 | if (address >= dom->aperture_size) | |
2434 | return; | |
2435 | ||
384de729 JR |
2436 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2437 | if (!aperture) | |
2438 | return; | |
2439 | ||
2440 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2441 | if (!pte) | |
2442 | return; | |
cb76c322 | 2443 | |
8c8c143c | 2444 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2445 | |
2446 | WARN_ON(!*pte); | |
2447 | ||
2448 | *pte = 0ULL; | |
2449 | } | |
2450 | ||
431b2a20 JR |
2451 | /* |
2452 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2453 | * contiguous memory region into DMA address space. It is used by all |
2454 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2455 | * Must be called with the domain lock held. |
2456 | */ | |
cb76c322 | 2457 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2458 | struct dma_ops_domain *dma_dom, |
2459 | phys_addr_t paddr, | |
2460 | size_t size, | |
6d4f343f | 2461 | int dir, |
832a90c3 JR |
2462 | bool align, |
2463 | u64 dma_mask) | |
cb76c322 JR |
2464 | { |
2465 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2466 | dma_addr_t address, start, ret; |
cb76c322 | 2467 | unsigned int pages; |
6d4f343f | 2468 | unsigned long align_mask = 0; |
cb76c322 JR |
2469 | int i; |
2470 | ||
e3c449f5 | 2471 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2472 | paddr &= PAGE_MASK; |
2473 | ||
8ecaf8f1 JR |
2474 | INC_STATS_COUNTER(total_map_requests); |
2475 | ||
c1858976 JR |
2476 | if (pages > 1) |
2477 | INC_STATS_COUNTER(cross_page); | |
2478 | ||
6d4f343f JR |
2479 | if (align) |
2480 | align_mask = (1UL << get_order(size)) - 1; | |
2481 | ||
11b83888 | 2482 | retry: |
832a90c3 JR |
2483 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2484 | dma_mask); | |
8fd524b3 | 2485 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2486 | /* |
2487 | * setting next_address here will let the address | |
2488 | * allocator only scan the new allocated range in the | |
2489 | * first run. This is a small optimization. | |
2490 | */ | |
2491 | dma_dom->next_address = dma_dom->aperture_size; | |
2492 | ||
576175c2 | 2493 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2494 | goto out; |
2495 | ||
2496 | /* | |
af901ca1 | 2497 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2498 | * allocation again |
2499 | */ | |
2500 | goto retry; | |
2501 | } | |
cb76c322 JR |
2502 | |
2503 | start = address; | |
2504 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2505 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2506 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2507 | goto out_unmap; |
2508 | ||
cb76c322 JR |
2509 | paddr += PAGE_SIZE; |
2510 | start += PAGE_SIZE; | |
2511 | } | |
2512 | address += offset; | |
2513 | ||
5774f7c5 JR |
2514 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2515 | ||
afa9fdc2 | 2516 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2517 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2518 | dma_dom->need_flush = false; |
318afd41 | 2519 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2520 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2521 | |
cb76c322 JR |
2522 | out: |
2523 | return address; | |
53812c11 JR |
2524 | |
2525 | out_unmap: | |
2526 | ||
2527 | for (--i; i >= 0; --i) { | |
2528 | start -= PAGE_SIZE; | |
680525e0 | 2529 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2530 | } |
2531 | ||
2532 | dma_ops_free_addresses(dma_dom, address, pages); | |
2533 | ||
8fd524b3 | 2534 | return DMA_ERROR_CODE; |
cb76c322 JR |
2535 | } |
2536 | ||
431b2a20 JR |
2537 | /* |
2538 | * Does the reverse of the __map_single function. Must be called with | |
2539 | * the domain lock held too | |
2540 | */ | |
cd8c82e8 | 2541 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2542 | dma_addr_t dma_addr, |
2543 | size_t size, | |
2544 | int dir) | |
2545 | { | |
04e0463e | 2546 | dma_addr_t flush_addr; |
cb76c322 JR |
2547 | dma_addr_t i, start; |
2548 | unsigned int pages; | |
2549 | ||
8fd524b3 | 2550 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2551 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2552 | return; |
2553 | ||
04e0463e | 2554 | flush_addr = dma_addr; |
e3c449f5 | 2555 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2556 | dma_addr &= PAGE_MASK; |
2557 | start = dma_addr; | |
2558 | ||
2559 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2560 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2561 | start += PAGE_SIZE; |
2562 | } | |
2563 | ||
5774f7c5 JR |
2564 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2565 | ||
cb76c322 | 2566 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2567 | |
80be308d | 2568 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2569 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2570 | dma_dom->need_flush = false; |
2571 | } | |
cb76c322 JR |
2572 | } |
2573 | ||
431b2a20 JR |
2574 | /* |
2575 | * The exported map_single function for dma_ops. | |
2576 | */ | |
51491367 FT |
2577 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2578 | unsigned long offset, size_t size, | |
2579 | enum dma_data_direction dir, | |
2580 | struct dma_attrs *attrs) | |
4da70b9e JR |
2581 | { |
2582 | unsigned long flags; | |
4da70b9e | 2583 | struct protection_domain *domain; |
4da70b9e | 2584 | dma_addr_t addr; |
832a90c3 | 2585 | u64 dma_mask; |
51491367 | 2586 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2587 | |
0f2a86f2 JR |
2588 | INC_STATS_COUNTER(cnt_map_single); |
2589 | ||
94f6d190 JR |
2590 | domain = get_domain(dev); |
2591 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2592 | return (dma_addr_t)paddr; |
94f6d190 JR |
2593 | else if (IS_ERR(domain)) |
2594 | return DMA_ERROR_CODE; | |
4da70b9e | 2595 | |
f99c0f1c JR |
2596 | dma_mask = *dev->dma_mask; |
2597 | ||
4da70b9e | 2598 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2599 | |
cd8c82e8 | 2600 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2601 | dma_mask); |
8fd524b3 | 2602 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2603 | goto out; |
2604 | ||
17b124bf | 2605 | domain_flush_complete(domain); |
4da70b9e JR |
2606 | |
2607 | out: | |
2608 | spin_unlock_irqrestore(&domain->lock, flags); | |
2609 | ||
2610 | return addr; | |
2611 | } | |
2612 | ||
431b2a20 JR |
2613 | /* |
2614 | * The exported unmap_single function for dma_ops. | |
2615 | */ | |
51491367 FT |
2616 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2617 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2618 | { |
2619 | unsigned long flags; | |
4da70b9e | 2620 | struct protection_domain *domain; |
4da70b9e | 2621 | |
146a6917 JR |
2622 | INC_STATS_COUNTER(cnt_unmap_single); |
2623 | ||
94f6d190 JR |
2624 | domain = get_domain(dev); |
2625 | if (IS_ERR(domain)) | |
5b28df6f JR |
2626 | return; |
2627 | ||
4da70b9e JR |
2628 | spin_lock_irqsave(&domain->lock, flags); |
2629 | ||
cd8c82e8 | 2630 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2631 | |
17b124bf | 2632 | domain_flush_complete(domain); |
4da70b9e JR |
2633 | |
2634 | spin_unlock_irqrestore(&domain->lock, flags); | |
2635 | } | |
2636 | ||
431b2a20 JR |
2637 | /* |
2638 | * This is a special map_sg function which is used if we should map a | |
2639 | * device which is not handled by an AMD IOMMU in the system. | |
2640 | */ | |
65b050ad JR |
2641 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2642 | int nelems, int dir) | |
2643 | { | |
2644 | struct scatterlist *s; | |
2645 | int i; | |
2646 | ||
2647 | for_each_sg(sglist, s, nelems, i) { | |
2648 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2649 | s->dma_length = s->length; | |
2650 | } | |
2651 | ||
2652 | return nelems; | |
2653 | } | |
2654 | ||
431b2a20 JR |
2655 | /* |
2656 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2657 | * lists). | |
2658 | */ | |
65b050ad | 2659 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2660 | int nelems, enum dma_data_direction dir, |
2661 | struct dma_attrs *attrs) | |
65b050ad JR |
2662 | { |
2663 | unsigned long flags; | |
65b050ad | 2664 | struct protection_domain *domain; |
65b050ad JR |
2665 | int i; |
2666 | struct scatterlist *s; | |
2667 | phys_addr_t paddr; | |
2668 | int mapped_elems = 0; | |
832a90c3 | 2669 | u64 dma_mask; |
65b050ad | 2670 | |
d03f067a JR |
2671 | INC_STATS_COUNTER(cnt_map_sg); |
2672 | ||
94f6d190 JR |
2673 | domain = get_domain(dev); |
2674 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2675 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2676 | else if (IS_ERR(domain)) |
2677 | return 0; | |
dbcc112e | 2678 | |
832a90c3 | 2679 | dma_mask = *dev->dma_mask; |
65b050ad | 2680 | |
65b050ad JR |
2681 | spin_lock_irqsave(&domain->lock, flags); |
2682 | ||
2683 | for_each_sg(sglist, s, nelems, i) { | |
2684 | paddr = sg_phys(s); | |
2685 | ||
cd8c82e8 | 2686 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2687 | paddr, s->length, dir, false, |
2688 | dma_mask); | |
65b050ad JR |
2689 | |
2690 | if (s->dma_address) { | |
2691 | s->dma_length = s->length; | |
2692 | mapped_elems++; | |
2693 | } else | |
2694 | goto unmap; | |
65b050ad JR |
2695 | } |
2696 | ||
17b124bf | 2697 | domain_flush_complete(domain); |
65b050ad JR |
2698 | |
2699 | out: | |
2700 | spin_unlock_irqrestore(&domain->lock, flags); | |
2701 | ||
2702 | return mapped_elems; | |
2703 | unmap: | |
2704 | for_each_sg(sglist, s, mapped_elems, i) { | |
2705 | if (s->dma_address) | |
cd8c82e8 | 2706 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2707 | s->dma_length, dir); |
2708 | s->dma_address = s->dma_length = 0; | |
2709 | } | |
2710 | ||
2711 | mapped_elems = 0; | |
2712 | ||
2713 | goto out; | |
2714 | } | |
2715 | ||
431b2a20 JR |
2716 | /* |
2717 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2718 | * lists). | |
2719 | */ | |
65b050ad | 2720 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2721 | int nelems, enum dma_data_direction dir, |
2722 | struct dma_attrs *attrs) | |
65b050ad JR |
2723 | { |
2724 | unsigned long flags; | |
65b050ad JR |
2725 | struct protection_domain *domain; |
2726 | struct scatterlist *s; | |
65b050ad JR |
2727 | int i; |
2728 | ||
55877a6b JR |
2729 | INC_STATS_COUNTER(cnt_unmap_sg); |
2730 | ||
94f6d190 JR |
2731 | domain = get_domain(dev); |
2732 | if (IS_ERR(domain)) | |
5b28df6f JR |
2733 | return; |
2734 | ||
65b050ad JR |
2735 | spin_lock_irqsave(&domain->lock, flags); |
2736 | ||
2737 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2738 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2739 | s->dma_length, dir); |
65b050ad JR |
2740 | s->dma_address = s->dma_length = 0; |
2741 | } | |
2742 | ||
17b124bf | 2743 | domain_flush_complete(domain); |
65b050ad JR |
2744 | |
2745 | spin_unlock_irqrestore(&domain->lock, flags); | |
2746 | } | |
2747 | ||
431b2a20 JR |
2748 | /* |
2749 | * The exported alloc_coherent function for dma_ops. | |
2750 | */ | |
5d8b53cf | 2751 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2752 | dma_addr_t *dma_addr, gfp_t flag, |
2753 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2754 | { |
2755 | unsigned long flags; | |
2756 | void *virt_addr; | |
5d8b53cf | 2757 | struct protection_domain *domain; |
5d8b53cf | 2758 | phys_addr_t paddr; |
832a90c3 | 2759 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2760 | |
c8f0fb36 JR |
2761 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2762 | ||
94f6d190 JR |
2763 | domain = get_domain(dev); |
2764 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2765 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2766 | *dma_addr = __pa(virt_addr); | |
2767 | return virt_addr; | |
94f6d190 JR |
2768 | } else if (IS_ERR(domain)) |
2769 | return NULL; | |
5d8b53cf | 2770 | |
f99c0f1c JR |
2771 | dma_mask = dev->coherent_dma_mask; |
2772 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2773 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2774 | |
2775 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2776 | if (!virt_addr) | |
b25ae679 | 2777 | return NULL; |
5d8b53cf | 2778 | |
5d8b53cf JR |
2779 | paddr = virt_to_phys(virt_addr); |
2780 | ||
832a90c3 JR |
2781 | if (!dma_mask) |
2782 | dma_mask = *dev->dma_mask; | |
2783 | ||
5d8b53cf JR |
2784 | spin_lock_irqsave(&domain->lock, flags); |
2785 | ||
cd8c82e8 | 2786 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2787 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2788 | |
8fd524b3 | 2789 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2790 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2791 | goto out_free; |
367d04c4 | 2792 | } |
5d8b53cf | 2793 | |
17b124bf | 2794 | domain_flush_complete(domain); |
5d8b53cf | 2795 | |
5d8b53cf JR |
2796 | spin_unlock_irqrestore(&domain->lock, flags); |
2797 | ||
2798 | return virt_addr; | |
5b28df6f JR |
2799 | |
2800 | out_free: | |
2801 | ||
2802 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2803 | ||
2804 | return NULL; | |
5d8b53cf JR |
2805 | } |
2806 | ||
431b2a20 JR |
2807 | /* |
2808 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2809 | */ |
5d8b53cf | 2810 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2811 | void *virt_addr, dma_addr_t dma_addr, |
2812 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2813 | { |
2814 | unsigned long flags; | |
5d8b53cf | 2815 | struct protection_domain *domain; |
5d8b53cf | 2816 | |
5d31ee7e JR |
2817 | INC_STATS_COUNTER(cnt_free_coherent); |
2818 | ||
94f6d190 JR |
2819 | domain = get_domain(dev); |
2820 | if (IS_ERR(domain)) | |
5b28df6f JR |
2821 | goto free_mem; |
2822 | ||
5d8b53cf JR |
2823 | spin_lock_irqsave(&domain->lock, flags); |
2824 | ||
cd8c82e8 | 2825 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2826 | |
17b124bf | 2827 | domain_flush_complete(domain); |
5d8b53cf JR |
2828 | |
2829 | spin_unlock_irqrestore(&domain->lock, flags); | |
2830 | ||
2831 | free_mem: | |
2832 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2833 | } | |
2834 | ||
b39ba6ad JR |
2835 | /* |
2836 | * This function is called by the DMA layer to find out if we can handle a | |
2837 | * particular device. It is part of the dma_ops. | |
2838 | */ | |
2839 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2840 | { | |
420aef8a | 2841 | return check_device(dev); |
b39ba6ad JR |
2842 | } |
2843 | ||
c432f3df | 2844 | /* |
431b2a20 JR |
2845 | * The function for pre-allocating protection domains. |
2846 | * | |
c432f3df JR |
2847 | * If the driver core informs the DMA layer if a driver grabs a device |
2848 | * we don't need to preallocate the protection domains anymore. | |
2849 | * For now we have to. | |
2850 | */ | |
943bc7e1 | 2851 | static void __init prealloc_protection_domains(void) |
c432f3df | 2852 | { |
5abcdba4 | 2853 | struct iommu_dev_data *dev_data; |
c432f3df | 2854 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 2855 | struct pci_dev *dev = NULL; |
98fc5a69 | 2856 | u16 devid; |
c432f3df | 2857 | |
d18c69d3 | 2858 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2859 | |
2860 | /* Do we handle this device? */ | |
2861 | if (!check_device(&dev->dev)) | |
c432f3df | 2862 | continue; |
98fc5a69 | 2863 | |
5abcdba4 JR |
2864 | dev_data = get_dev_data(&dev->dev); |
2865 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
2866 | /* Make sure passthrough domain is allocated */ | |
2867 | alloc_passthrough_domain(); | |
2868 | dev_data->passthrough = true; | |
2869 | attach_device(&dev->dev, pt_domain); | |
2870 | pr_info("AMD-Vi: Using passthough domain for device %s\n", | |
2871 | dev_name(&dev->dev)); | |
2872 | } | |
2873 | ||
98fc5a69 | 2874 | /* Is there already any domain for it? */ |
15898bbc | 2875 | if (domain_for_device(&dev->dev)) |
c432f3df | 2876 | continue; |
98fc5a69 JR |
2877 | |
2878 | devid = get_device_id(&dev->dev); | |
2879 | ||
87a64d52 | 2880 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2881 | if (!dma_dom) |
2882 | continue; | |
2883 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2884 | dma_dom->target_dev = devid; |
2885 | ||
15898bbc | 2886 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2887 | |
bd60b735 | 2888 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2889 | } |
2890 | } | |
2891 | ||
160c1d8e | 2892 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
2893 | .alloc = alloc_coherent, |
2894 | .free = free_coherent, | |
51491367 FT |
2895 | .map_page = map_page, |
2896 | .unmap_page = unmap_page, | |
6631ee9d JR |
2897 | .map_sg = map_sg, |
2898 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2899 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2900 | }; |
2901 | ||
27c2127a JR |
2902 | static unsigned device_dma_ops_init(void) |
2903 | { | |
5abcdba4 | 2904 | struct iommu_dev_data *dev_data; |
27c2127a JR |
2905 | struct pci_dev *pdev = NULL; |
2906 | unsigned unhandled = 0; | |
2907 | ||
2908 | for_each_pci_dev(pdev) { | |
2909 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
2910 | |
2911 | iommu_ignore_device(&pdev->dev); | |
2912 | ||
27c2127a JR |
2913 | unhandled += 1; |
2914 | continue; | |
2915 | } | |
2916 | ||
5abcdba4 JR |
2917 | dev_data = get_dev_data(&pdev->dev); |
2918 | ||
2919 | if (!dev_data->passthrough) | |
2920 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2921 | else | |
2922 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
2923 | } |
2924 | ||
2925 | return unhandled; | |
2926 | } | |
2927 | ||
431b2a20 JR |
2928 | /* |
2929 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2930 | */ | |
f5325094 JR |
2931 | |
2932 | void __init amd_iommu_init_api(void) | |
2933 | { | |
2cc21c42 | 2934 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2935 | } |
2936 | ||
6631ee9d JR |
2937 | int __init amd_iommu_init_dma_ops(void) |
2938 | { | |
2939 | struct amd_iommu *iommu; | |
27c2127a | 2940 | int ret, unhandled; |
6631ee9d | 2941 | |
431b2a20 JR |
2942 | /* |
2943 | * first allocate a default protection domain for every IOMMU we | |
2944 | * found in the system. Devices not assigned to any other | |
2945 | * protection domain will be assigned to the default one. | |
2946 | */ | |
3bd22172 | 2947 | for_each_iommu(iommu) { |
87a64d52 | 2948 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2949 | if (iommu->default_dom == NULL) |
2950 | return -ENOMEM; | |
e2dc14a2 | 2951 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2952 | ret = iommu_init_unity_mappings(iommu); |
2953 | if (ret) | |
2954 | goto free_domains; | |
2955 | } | |
2956 | ||
431b2a20 | 2957 | /* |
8793abeb | 2958 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2959 | */ |
8793abeb | 2960 | prealloc_protection_domains(); |
6631ee9d JR |
2961 | |
2962 | iommu_detected = 1; | |
75f1cdf1 | 2963 | swiotlb = 0; |
6631ee9d | 2964 | |
431b2a20 | 2965 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2966 | unhandled = device_dma_ops_init(); |
2967 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2968 | /* There are unhandled devices - initialize swiotlb for them */ | |
2969 | swiotlb = 1; | |
2970 | } | |
6631ee9d | 2971 | |
7f26508b JR |
2972 | amd_iommu_stats_init(); |
2973 | ||
6631ee9d JR |
2974 | return 0; |
2975 | ||
2976 | free_domains: | |
2977 | ||
3bd22172 | 2978 | for_each_iommu(iommu) { |
6631ee9d JR |
2979 | if (iommu->default_dom) |
2980 | dma_ops_domain_free(iommu->default_dom); | |
2981 | } | |
2982 | ||
2983 | return ret; | |
2984 | } | |
6d98cd80 JR |
2985 | |
2986 | /***************************************************************************** | |
2987 | * | |
2988 | * The following functions belong to the exported interface of AMD IOMMU | |
2989 | * | |
2990 | * This interface allows access to lower level functions of the IOMMU | |
2991 | * like protection domain handling and assignement of devices to domains | |
2992 | * which is not possible with the dma_ops interface. | |
2993 | * | |
2994 | *****************************************************************************/ | |
2995 | ||
6d98cd80 JR |
2996 | static void cleanup_domain(struct protection_domain *domain) |
2997 | { | |
492667da | 2998 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2999 | unsigned long flags; |
6d98cd80 JR |
3000 | |
3001 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3002 | ||
492667da | 3003 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 3004 | __detach_device(dev_data); |
492667da JR |
3005 | atomic_set(&dev_data->bind, 0); |
3006 | } | |
6d98cd80 JR |
3007 | |
3008 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3009 | } | |
3010 | ||
2650815f JR |
3011 | static void protection_domain_free(struct protection_domain *domain) |
3012 | { | |
3013 | if (!domain) | |
3014 | return; | |
3015 | ||
aeb26f55 JR |
3016 | del_domain_from_list(domain); |
3017 | ||
2650815f JR |
3018 | if (domain->id) |
3019 | domain_id_free(domain->id); | |
3020 | ||
3021 | kfree(domain); | |
3022 | } | |
3023 | ||
3024 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3025 | { |
3026 | struct protection_domain *domain; | |
3027 | ||
3028 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3029 | if (!domain) | |
2650815f | 3030 | return NULL; |
c156e347 JR |
3031 | |
3032 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3033 | mutex_init(&domain->api_lock); |
c156e347 JR |
3034 | domain->id = domain_id_alloc(); |
3035 | if (!domain->id) | |
2650815f | 3036 | goto out_err; |
7c392cbe | 3037 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3038 | |
aeb26f55 JR |
3039 | add_domain_to_list(domain); |
3040 | ||
2650815f JR |
3041 | return domain; |
3042 | ||
3043 | out_err: | |
3044 | kfree(domain); | |
3045 | ||
3046 | return NULL; | |
3047 | } | |
3048 | ||
5abcdba4 JR |
3049 | static int __init alloc_passthrough_domain(void) |
3050 | { | |
3051 | if (pt_domain != NULL) | |
3052 | return 0; | |
3053 | ||
3054 | /* allocate passthrough domain */ | |
3055 | pt_domain = protection_domain_alloc(); | |
3056 | if (!pt_domain) | |
3057 | return -ENOMEM; | |
3058 | ||
3059 | pt_domain->mode = PAGE_MODE_NONE; | |
3060 | ||
3061 | return 0; | |
3062 | } | |
2650815f JR |
3063 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3064 | { | |
3065 | struct protection_domain *domain; | |
3066 | ||
3067 | domain = protection_domain_alloc(); | |
3068 | if (!domain) | |
c156e347 | 3069 | goto out_free; |
2650815f JR |
3070 | |
3071 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3072 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3073 | if (!domain->pt_root) | |
3074 | goto out_free; | |
3075 | ||
f3572db8 JR |
3076 | domain->iommu_domain = dom; |
3077 | ||
c156e347 JR |
3078 | dom->priv = domain; |
3079 | ||
3080 | return 0; | |
3081 | ||
3082 | out_free: | |
2650815f | 3083 | protection_domain_free(domain); |
c156e347 JR |
3084 | |
3085 | return -ENOMEM; | |
3086 | } | |
3087 | ||
98383fc3 JR |
3088 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3089 | { | |
3090 | struct protection_domain *domain = dom->priv; | |
3091 | ||
3092 | if (!domain) | |
3093 | return; | |
3094 | ||
3095 | if (domain->dev_cnt > 0) | |
3096 | cleanup_domain(domain); | |
3097 | ||
3098 | BUG_ON(domain->dev_cnt != 0); | |
3099 | ||
132bd68f JR |
3100 | if (domain->mode != PAGE_MODE_NONE) |
3101 | free_pagetable(domain); | |
98383fc3 | 3102 | |
52815b75 JR |
3103 | if (domain->flags & PD_IOMMUV2_MASK) |
3104 | free_gcr3_table(domain); | |
3105 | ||
8b408fe4 | 3106 | protection_domain_free(domain); |
98383fc3 JR |
3107 | |
3108 | dom->priv = NULL; | |
3109 | } | |
3110 | ||
684f2888 JR |
3111 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3112 | struct device *dev) | |
3113 | { | |
657cbb6b | 3114 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3115 | struct amd_iommu *iommu; |
684f2888 JR |
3116 | u16 devid; |
3117 | ||
98fc5a69 | 3118 | if (!check_device(dev)) |
684f2888 JR |
3119 | return; |
3120 | ||
98fc5a69 | 3121 | devid = get_device_id(dev); |
684f2888 | 3122 | |
657cbb6b | 3123 | if (dev_data->domain != NULL) |
15898bbc | 3124 | detach_device(dev); |
684f2888 JR |
3125 | |
3126 | iommu = amd_iommu_rlookup_table[devid]; | |
3127 | if (!iommu) | |
3128 | return; | |
3129 | ||
684f2888 JR |
3130 | iommu_completion_wait(iommu); |
3131 | } | |
3132 | ||
01106066 JR |
3133 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3134 | struct device *dev) | |
3135 | { | |
3136 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3137 | struct iommu_dev_data *dev_data; |
01106066 | 3138 | struct amd_iommu *iommu; |
15898bbc | 3139 | int ret; |
01106066 | 3140 | |
98fc5a69 | 3141 | if (!check_device(dev)) |
01106066 JR |
3142 | return -EINVAL; |
3143 | ||
657cbb6b JR |
3144 | dev_data = dev->archdata.iommu; |
3145 | ||
f62dda66 | 3146 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3147 | if (!iommu) |
3148 | return -EINVAL; | |
3149 | ||
657cbb6b | 3150 | if (dev_data->domain) |
15898bbc | 3151 | detach_device(dev); |
01106066 | 3152 | |
15898bbc | 3153 | ret = attach_device(dev, domain); |
01106066 JR |
3154 | |
3155 | iommu_completion_wait(iommu); | |
3156 | ||
15898bbc | 3157 | return ret; |
01106066 JR |
3158 | } |
3159 | ||
468e2366 | 3160 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3161 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3162 | { |
3163 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3164 | int prot = 0; |
3165 | int ret; | |
3166 | ||
132bd68f JR |
3167 | if (domain->mode == PAGE_MODE_NONE) |
3168 | return -EINVAL; | |
3169 | ||
c6229ca6 JR |
3170 | if (iommu_prot & IOMMU_READ) |
3171 | prot |= IOMMU_PROT_IR; | |
3172 | if (iommu_prot & IOMMU_WRITE) | |
3173 | prot |= IOMMU_PROT_IW; | |
3174 | ||
5d214fe6 | 3175 | mutex_lock(&domain->api_lock); |
795e74f7 | 3176 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3177 | mutex_unlock(&domain->api_lock); |
3178 | ||
795e74f7 | 3179 | return ret; |
c6229ca6 JR |
3180 | } |
3181 | ||
5009065d OBC |
3182 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3183 | size_t page_size) | |
eb74ff6c | 3184 | { |
eb74ff6c | 3185 | struct protection_domain *domain = dom->priv; |
5009065d | 3186 | size_t unmap_size; |
eb74ff6c | 3187 | |
132bd68f JR |
3188 | if (domain->mode == PAGE_MODE_NONE) |
3189 | return -EINVAL; | |
3190 | ||
5d214fe6 | 3191 | mutex_lock(&domain->api_lock); |
468e2366 | 3192 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3193 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3194 | |
17b124bf | 3195 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3196 | |
5009065d | 3197 | return unmap_size; |
eb74ff6c JR |
3198 | } |
3199 | ||
645c4c8d JR |
3200 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
3201 | unsigned long iova) | |
3202 | { | |
3203 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3204 | unsigned long offset_mask; |
645c4c8d | 3205 | phys_addr_t paddr; |
f03152bb | 3206 | u64 *pte, __pte; |
645c4c8d | 3207 | |
132bd68f JR |
3208 | if (domain->mode == PAGE_MODE_NONE) |
3209 | return iova; | |
3210 | ||
24cd7723 | 3211 | pte = fetch_pte(domain, iova); |
645c4c8d | 3212 | |
a6d41a40 | 3213 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3214 | return 0; |
3215 | ||
f03152bb JR |
3216 | if (PM_PTE_LEVEL(*pte) == 0) |
3217 | offset_mask = PAGE_SIZE - 1; | |
3218 | else | |
3219 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3220 | ||
3221 | __pte = *pte & PM_ADDR_MASK; | |
3222 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3223 | |
3224 | return paddr; | |
3225 | } | |
3226 | ||
dbb9fd86 SY |
3227 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3228 | unsigned long cap) | |
3229 | { | |
80a506b8 JR |
3230 | switch (cap) { |
3231 | case IOMMU_CAP_CACHE_COHERENCY: | |
3232 | return 1; | |
3233 | } | |
3234 | ||
dbb9fd86 SY |
3235 | return 0; |
3236 | } | |
3237 | ||
8fbdce65 AW |
3238 | static int amd_iommu_device_group(struct device *dev, unsigned int *groupid) |
3239 | { | |
3240 | struct iommu_dev_data *dev_data = dev->archdata.iommu; | |
bcb71abe AW |
3241 | struct pci_dev *pdev = to_pci_dev(dev); |
3242 | u16 devid; | |
8fbdce65 AW |
3243 | |
3244 | if (!dev_data) | |
3245 | return -ENODEV; | |
3246 | ||
bcb71abe AW |
3247 | if (pdev->is_virtfn || !iommu_group_mf) |
3248 | devid = dev_data->devid; | |
3249 | else | |
3250 | devid = calc_devid(pdev->bus->number, | |
3251 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); | |
3252 | ||
3253 | *groupid = amd_iommu_alias_table[devid]; | |
8fbdce65 AW |
3254 | |
3255 | return 0; | |
3256 | } | |
3257 | ||
26961efe JR |
3258 | static struct iommu_ops amd_iommu_ops = { |
3259 | .domain_init = amd_iommu_domain_init, | |
3260 | .domain_destroy = amd_iommu_domain_destroy, | |
3261 | .attach_dev = amd_iommu_attach_device, | |
3262 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3263 | .map = amd_iommu_map, |
3264 | .unmap = amd_iommu_unmap, | |
26961efe | 3265 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3266 | .domain_has_cap = amd_iommu_domain_has_cap, |
8fbdce65 | 3267 | .device_group = amd_iommu_device_group, |
aa3de9c0 | 3268 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3269 | }; |
3270 | ||
0feae533 JR |
3271 | /***************************************************************************** |
3272 | * | |
3273 | * The next functions do a basic initialization of IOMMU for pass through | |
3274 | * mode | |
3275 | * | |
3276 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3277 | * DMA-API translation. | |
3278 | * | |
3279 | *****************************************************************************/ | |
3280 | ||
3281 | int __init amd_iommu_init_passthrough(void) | |
3282 | { | |
5abcdba4 | 3283 | struct iommu_dev_data *dev_data; |
0feae533 | 3284 | struct pci_dev *dev = NULL; |
5abcdba4 | 3285 | struct amd_iommu *iommu; |
15898bbc | 3286 | u16 devid; |
5abcdba4 | 3287 | int ret; |
0feae533 | 3288 | |
5abcdba4 JR |
3289 | ret = alloc_passthrough_domain(); |
3290 | if (ret) | |
3291 | return ret; | |
0feae533 | 3292 | |
6c54aabd | 3293 | for_each_pci_dev(dev) { |
98fc5a69 | 3294 | if (!check_device(&dev->dev)) |
0feae533 JR |
3295 | continue; |
3296 | ||
5abcdba4 JR |
3297 | dev_data = get_dev_data(&dev->dev); |
3298 | dev_data->passthrough = true; | |
3299 | ||
98fc5a69 JR |
3300 | devid = get_device_id(&dev->dev); |
3301 | ||
15898bbc | 3302 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3303 | if (!iommu) |
3304 | continue; | |
3305 | ||
15898bbc | 3306 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3307 | } |
3308 | ||
2655d7a2 JR |
3309 | amd_iommu_stats_init(); |
3310 | ||
0feae533 JR |
3311 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3312 | ||
3313 | return 0; | |
3314 | } | |
72e1dcc4 JR |
3315 | |
3316 | /* IOMMUv2 specific functions */ | |
3317 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3318 | { | |
3319 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3320 | } | |
3321 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3322 | ||
3323 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3324 | { | |
3325 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3326 | } | |
3327 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3328 | |
3329 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3330 | { | |
3331 | struct protection_domain *domain = dom->priv; | |
3332 | unsigned long flags; | |
3333 | ||
3334 | spin_lock_irqsave(&domain->lock, flags); | |
3335 | ||
3336 | /* Update data structure */ | |
3337 | domain->mode = PAGE_MODE_NONE; | |
3338 | domain->updated = true; | |
3339 | ||
3340 | /* Make changes visible to IOMMUs */ | |
3341 | update_domain(domain); | |
3342 | ||
3343 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3344 | free_pagetable(domain); | |
3345 | ||
3346 | spin_unlock_irqrestore(&domain->lock, flags); | |
3347 | } | |
3348 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3349 | |
3350 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3351 | { | |
3352 | struct protection_domain *domain = dom->priv; | |
3353 | unsigned long flags; | |
3354 | int levels, ret; | |
3355 | ||
3356 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3357 | return -EINVAL; | |
3358 | ||
3359 | /* Number of GCR3 table levels required */ | |
3360 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3361 | levels += 1; | |
3362 | ||
3363 | if (levels > amd_iommu_max_glx_val) | |
3364 | return -EINVAL; | |
3365 | ||
3366 | spin_lock_irqsave(&domain->lock, flags); | |
3367 | ||
3368 | /* | |
3369 | * Save us all sanity checks whether devices already in the | |
3370 | * domain support IOMMUv2. Just force that the domain has no | |
3371 | * devices attached when it is switched into IOMMUv2 mode. | |
3372 | */ | |
3373 | ret = -EBUSY; | |
3374 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3375 | goto out; | |
3376 | ||
3377 | ret = -ENOMEM; | |
3378 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3379 | if (domain->gcr3_tbl == NULL) | |
3380 | goto out; | |
3381 | ||
3382 | domain->glx = levels; | |
3383 | domain->flags |= PD_IOMMUV2_MASK; | |
3384 | domain->updated = true; | |
3385 | ||
3386 | update_domain(domain); | |
3387 | ||
3388 | ret = 0; | |
3389 | ||
3390 | out: | |
3391 | spin_unlock_irqrestore(&domain->lock, flags); | |
3392 | ||
3393 | return ret; | |
3394 | } | |
3395 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3396 | |
3397 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3398 | u64 address, bool size) | |
3399 | { | |
3400 | struct iommu_dev_data *dev_data; | |
3401 | struct iommu_cmd cmd; | |
3402 | int i, ret; | |
3403 | ||
3404 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3405 | return -EINVAL; | |
3406 | ||
3407 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3408 | ||
3409 | /* | |
3410 | * IOMMU TLB needs to be flushed before Device TLB to | |
3411 | * prevent device TLB refill from IOMMU TLB | |
3412 | */ | |
3413 | for (i = 0; i < amd_iommus_present; ++i) { | |
3414 | if (domain->dev_iommu[i] == 0) | |
3415 | continue; | |
3416 | ||
3417 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3418 | if (ret != 0) | |
3419 | goto out; | |
3420 | } | |
3421 | ||
3422 | /* Wait until IOMMU TLB flushes are complete */ | |
3423 | domain_flush_complete(domain); | |
3424 | ||
3425 | /* Now flush device TLBs */ | |
3426 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3427 | struct amd_iommu *iommu; | |
3428 | int qdep; | |
3429 | ||
3430 | BUG_ON(!dev_data->ats.enabled); | |
3431 | ||
3432 | qdep = dev_data->ats.qdep; | |
3433 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3434 | ||
3435 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3436 | qdep, address, size); | |
3437 | ||
3438 | ret = iommu_queue_command(iommu, &cmd); | |
3439 | if (ret != 0) | |
3440 | goto out; | |
3441 | } | |
3442 | ||
3443 | /* Wait until all device TLBs are flushed */ | |
3444 | domain_flush_complete(domain); | |
3445 | ||
3446 | ret = 0; | |
3447 | ||
3448 | out: | |
3449 | ||
3450 | return ret; | |
3451 | } | |
3452 | ||
3453 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3454 | u64 address) | |
3455 | { | |
399be2f5 JR |
3456 | INC_STATS_COUNTER(invalidate_iotlb); |
3457 | ||
22e266c7 JR |
3458 | return __flush_pasid(domain, pasid, address, false); |
3459 | } | |
3460 | ||
3461 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3462 | u64 address) | |
3463 | { | |
3464 | struct protection_domain *domain = dom->priv; | |
3465 | unsigned long flags; | |
3466 | int ret; | |
3467 | ||
3468 | spin_lock_irqsave(&domain->lock, flags); | |
3469 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3470 | spin_unlock_irqrestore(&domain->lock, flags); | |
3471 | ||
3472 | return ret; | |
3473 | } | |
3474 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3475 | ||
3476 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3477 | { | |
399be2f5 JR |
3478 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3479 | ||
22e266c7 JR |
3480 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3481 | true); | |
3482 | } | |
3483 | ||
3484 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3485 | { | |
3486 | struct protection_domain *domain = dom->priv; | |
3487 | unsigned long flags; | |
3488 | int ret; | |
3489 | ||
3490 | spin_lock_irqsave(&domain->lock, flags); | |
3491 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3492 | spin_unlock_irqrestore(&domain->lock, flags); | |
3493 | ||
3494 | return ret; | |
3495 | } | |
3496 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3497 | ||
b16137b1 JR |
3498 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3499 | { | |
3500 | int index; | |
3501 | u64 *pte; | |
3502 | ||
3503 | while (true) { | |
3504 | ||
3505 | index = (pasid >> (9 * level)) & 0x1ff; | |
3506 | pte = &root[index]; | |
3507 | ||
3508 | if (level == 0) | |
3509 | break; | |
3510 | ||
3511 | if (!(*pte & GCR3_VALID)) { | |
3512 | if (!alloc) | |
3513 | return NULL; | |
3514 | ||
3515 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3516 | if (root == NULL) | |
3517 | return NULL; | |
3518 | ||
3519 | *pte = __pa(root) | GCR3_VALID; | |
3520 | } | |
3521 | ||
3522 | root = __va(*pte & PAGE_MASK); | |
3523 | ||
3524 | level -= 1; | |
3525 | } | |
3526 | ||
3527 | return pte; | |
3528 | } | |
3529 | ||
3530 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3531 | unsigned long cr3) | |
3532 | { | |
3533 | u64 *pte; | |
3534 | ||
3535 | if (domain->mode != PAGE_MODE_NONE) | |
3536 | return -EINVAL; | |
3537 | ||
3538 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3539 | if (pte == NULL) | |
3540 | return -ENOMEM; | |
3541 | ||
3542 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3543 | ||
3544 | return __amd_iommu_flush_tlb(domain, pasid); | |
3545 | } | |
3546 | ||
3547 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3548 | { | |
3549 | u64 *pte; | |
3550 | ||
3551 | if (domain->mode != PAGE_MODE_NONE) | |
3552 | return -EINVAL; | |
3553 | ||
3554 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3555 | if (pte == NULL) | |
3556 | return 0; | |
3557 | ||
3558 | *pte = 0; | |
3559 | ||
3560 | return __amd_iommu_flush_tlb(domain, pasid); | |
3561 | } | |
3562 | ||
3563 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3564 | unsigned long cr3) | |
3565 | { | |
3566 | struct protection_domain *domain = dom->priv; | |
3567 | unsigned long flags; | |
3568 | int ret; | |
3569 | ||
3570 | spin_lock_irqsave(&domain->lock, flags); | |
3571 | ret = __set_gcr3(domain, pasid, cr3); | |
3572 | spin_unlock_irqrestore(&domain->lock, flags); | |
3573 | ||
3574 | return ret; | |
3575 | } | |
3576 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3577 | ||
3578 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3579 | { | |
3580 | struct protection_domain *domain = dom->priv; | |
3581 | unsigned long flags; | |
3582 | int ret; | |
3583 | ||
3584 | spin_lock_irqsave(&domain->lock, flags); | |
3585 | ret = __clear_gcr3(domain, pasid); | |
3586 | spin_unlock_irqrestore(&domain->lock, flags); | |
3587 | ||
3588 | return ret; | |
3589 | } | |
3590 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3591 | |
3592 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3593 | int status, int tag) | |
3594 | { | |
3595 | struct iommu_dev_data *dev_data; | |
3596 | struct amd_iommu *iommu; | |
3597 | struct iommu_cmd cmd; | |
3598 | ||
399be2f5 JR |
3599 | INC_STATS_COUNTER(complete_ppr); |
3600 | ||
c99afa25 JR |
3601 | dev_data = get_dev_data(&pdev->dev); |
3602 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3603 | ||
3604 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3605 | tag, dev_data->pri_tlp); | |
3606 | ||
3607 | return iommu_queue_command(iommu, &cmd); | |
3608 | } | |
3609 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3610 | |
3611 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3612 | { | |
3613 | struct protection_domain *domain; | |
3614 | ||
3615 | domain = get_domain(&pdev->dev); | |
3616 | if (IS_ERR(domain)) | |
3617 | return NULL; | |
3618 | ||
3619 | /* Only return IOMMUv2 domains */ | |
3620 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3621 | return NULL; | |
3622 | ||
3623 | return domain->iommu_domain; | |
3624 | } | |
3625 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3626 | |
3627 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3628 | { | |
3629 | struct iommu_dev_data *dev_data; | |
3630 | ||
3631 | if (!amd_iommu_v2_supported()) | |
3632 | return; | |
3633 | ||
3634 | dev_data = get_dev_data(&pdev->dev); | |
3635 | dev_data->errata |= (1 << erratum); | |
3636 | } | |
3637 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3638 | |
3639 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3640 | struct amd_iommu_device_info *info) | |
3641 | { | |
3642 | int max_pasids; | |
3643 | int pos; | |
3644 | ||
3645 | if (pdev == NULL || info == NULL) | |
3646 | return -EINVAL; | |
3647 | ||
3648 | if (!amd_iommu_v2_supported()) | |
3649 | return -EINVAL; | |
3650 | ||
3651 | memset(info, 0, sizeof(*info)); | |
3652 | ||
3653 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3654 | if (pos) | |
3655 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3656 | ||
3657 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3658 | if (pos) | |
3659 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3660 | ||
3661 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3662 | if (pos) { | |
3663 | int features; | |
3664 | ||
3665 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3666 | max_pasids = min(max_pasids, (1 << 20)); | |
3667 | ||
3668 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3669 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3670 | ||
3671 | features = pci_pasid_features(pdev); | |
3672 | if (features & PCI_PASID_CAP_EXEC) | |
3673 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3674 | if (features & PCI_PASID_CAP_PRIV) | |
3675 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3676 | } | |
3677 | ||
3678 | return 0; | |
3679 | } | |
3680 | EXPORT_SYMBOL(amd_iommu_device_info); |