Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
36 | #include <asm/irq_remapping.h> | |
37 | #include <asm/io_apic.h> | |
38 | #include <asm/apic.h> | |
39 | #include <asm/hw_irq.h> | |
17f5b569 | 40 | #include <asm/msidef.h> |
b6c02715 | 41 | #include <asm/proto.h> |
46a7fa27 | 42 | #include <asm/iommu.h> |
1d9b16d1 | 43 | #include <asm/gart.h> |
27c2127a | 44 | #include <asm/dma.h> |
403f81d8 JR |
45 | |
46 | #include "amd_iommu_proto.h" | |
47 | #include "amd_iommu_types.h" | |
6b474b82 | 48 | #include "irq_remapping.h" |
b6c02715 JR |
49 | |
50 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
51 | ||
815b33fd | 52 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 53 | |
aa3de9c0 OBC |
54 | /* |
55 | * This bitmap is used to advertise the page sizes our hardware support | |
56 | * to the IOMMU core, which will then use this information to split | |
57 | * physically contiguous memory regions it is mapping into page sizes | |
58 | * that we support. | |
59 | * | |
60 | * Traditionally the IOMMU core just handed us the mappings directly, | |
61 | * after making sure the size is an order of a 4KiB page and that the | |
62 | * mapping has natural alignment. | |
63 | * | |
64 | * To retain this behavior, we currently advertise that we support | |
65 | * all page sizes that are an order of 4KiB. | |
66 | * | |
67 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
68 | * we could change this to advertise the real page sizes we support. | |
69 | */ | |
70 | #define AMD_IOMMU_PGSIZES (~0xFFFUL) | |
71 | ||
b6c02715 JR |
72 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
73 | ||
bd60b735 JR |
74 | /* A list of preallocated protection domains */ |
75 | static LIST_HEAD(iommu_pd_list); | |
76 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
77 | ||
8fa5f802 JR |
78 | /* List of all available dev_data structures */ |
79 | static LIST_HEAD(dev_data_list); | |
80 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
81 | ||
6efed63b JR |
82 | LIST_HEAD(ioapic_map); |
83 | LIST_HEAD(hpet_map); | |
84 | ||
0feae533 JR |
85 | /* |
86 | * Domain for untranslated devices - only allocated | |
87 | * if iommu=pt passed on kernel cmd line. | |
88 | */ | |
89 | static struct protection_domain *pt_domain; | |
90 | ||
26961efe | 91 | static struct iommu_ops amd_iommu_ops; |
26961efe | 92 | |
72e1dcc4 | 93 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 94 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 95 | |
ac1534a5 JR |
96 | static struct dma_map_ops amd_iommu_dma_ops; |
97 | ||
431b2a20 JR |
98 | /* |
99 | * general struct to manage commands send to an IOMMU | |
100 | */ | |
d6449536 | 101 | struct iommu_cmd { |
b6c02715 JR |
102 | u32 data[4]; |
103 | }; | |
104 | ||
05152a04 JR |
105 | struct kmem_cache *amd_iommu_irq_cache; |
106 | ||
04bfdd84 | 107 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 108 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 109 | |
15898bbc JR |
110 | /**************************************************************************** |
111 | * | |
112 | * Helper functions | |
113 | * | |
114 | ****************************************************************************/ | |
115 | ||
f62dda66 | 116 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
117 | { |
118 | struct iommu_dev_data *dev_data; | |
119 | unsigned long flags; | |
120 | ||
121 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
122 | if (!dev_data) | |
123 | return NULL; | |
124 | ||
f62dda66 | 125 | dev_data->devid = devid; |
8fa5f802 JR |
126 | atomic_set(&dev_data->bind, 0); |
127 | ||
128 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
129 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
130 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
131 | ||
132 | return dev_data; | |
133 | } | |
134 | ||
135 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
136 | { | |
137 | unsigned long flags; | |
138 | ||
139 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
140 | list_del(&dev_data->dev_data_list); | |
141 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
142 | ||
143 | kfree(dev_data); | |
144 | } | |
145 | ||
3b03bb74 JR |
146 | static struct iommu_dev_data *search_dev_data(u16 devid) |
147 | { | |
148 | struct iommu_dev_data *dev_data; | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
152 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
153 | if (dev_data->devid == devid) | |
154 | goto out_unlock; | |
155 | } | |
156 | ||
157 | dev_data = NULL; | |
158 | ||
159 | out_unlock: | |
160 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
161 | ||
162 | return dev_data; | |
163 | } | |
164 | ||
165 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
166 | { | |
167 | struct iommu_dev_data *dev_data; | |
168 | ||
169 | dev_data = search_dev_data(devid); | |
170 | ||
171 | if (dev_data == NULL) | |
172 | dev_data = alloc_dev_data(devid); | |
173 | ||
174 | return dev_data; | |
175 | } | |
176 | ||
15898bbc JR |
177 | static inline u16 get_device_id(struct device *dev) |
178 | { | |
179 | struct pci_dev *pdev = to_pci_dev(dev); | |
180 | ||
181 | return calc_devid(pdev->bus->number, pdev->devfn); | |
182 | } | |
183 | ||
657cbb6b JR |
184 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
185 | { | |
186 | return dev->archdata.iommu; | |
187 | } | |
188 | ||
5abcdba4 JR |
189 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
190 | { | |
191 | static const int caps[] = { | |
192 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
193 | PCI_EXT_CAP_ID_PRI, |
194 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
195 | }; |
196 | int i, pos; | |
197 | ||
198 | for (i = 0; i < 3; ++i) { | |
199 | pos = pci_find_ext_capability(pdev, caps[i]); | |
200 | if (pos == 0) | |
201 | return false; | |
202 | } | |
203 | ||
204 | return true; | |
205 | } | |
206 | ||
6a113ddc JR |
207 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
208 | { | |
209 | struct iommu_dev_data *dev_data; | |
210 | ||
211 | dev_data = get_dev_data(&pdev->dev); | |
212 | ||
213 | return dev_data->errata & (1 << erratum) ? true : false; | |
214 | } | |
215 | ||
71c70984 JR |
216 | /* |
217 | * In this function the list of preallocated protection domains is traversed to | |
218 | * find the domain for a specific device | |
219 | */ | |
220 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
221 | { | |
222 | struct dma_ops_domain *entry, *ret = NULL; | |
223 | unsigned long flags; | |
224 | u16 alias = amd_iommu_alias_table[devid]; | |
225 | ||
226 | if (list_empty(&iommu_pd_list)) | |
227 | return NULL; | |
228 | ||
229 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
230 | ||
231 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
232 | if (entry->target_dev == devid || | |
233 | entry->target_dev == alias) { | |
234 | ret = entry; | |
235 | break; | |
236 | } | |
237 | } | |
238 | ||
239 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
240 | ||
241 | return ret; | |
242 | } | |
243 | ||
98fc5a69 JR |
244 | /* |
245 | * This function checks if the driver got a valid device from the caller to | |
246 | * avoid dereferencing invalid pointers. | |
247 | */ | |
248 | static bool check_device(struct device *dev) | |
249 | { | |
250 | u16 devid; | |
251 | ||
252 | if (!dev || !dev->dma_mask) | |
253 | return false; | |
254 | ||
255 | /* No device or no PCI device */ | |
339d3261 | 256 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
257 | return false; |
258 | ||
259 | devid = get_device_id(dev); | |
260 | ||
261 | /* Out of our scope? */ | |
262 | if (devid > amd_iommu_last_bdf) | |
263 | return false; | |
264 | ||
265 | if (amd_iommu_rlookup_table[devid] == NULL) | |
266 | return false; | |
267 | ||
268 | return true; | |
269 | } | |
270 | ||
664b6003 AW |
271 | static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) |
272 | { | |
273 | pci_dev_put(*from); | |
274 | *from = to; | |
275 | } | |
276 | ||
2bff6a50 AW |
277 | static struct pci_bus *find_hosted_bus(struct pci_bus *bus) |
278 | { | |
279 | while (!bus->self) { | |
280 | if (!pci_is_root_bus(bus)) | |
281 | bus = bus->parent; | |
282 | else | |
283 | return ERR_PTR(-ENODEV); | |
284 | } | |
285 | ||
286 | return bus; | |
287 | } | |
288 | ||
664b6003 AW |
289 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) |
290 | ||
2851db21 | 291 | static struct pci_dev *get_isolation_root(struct pci_dev *pdev) |
657cbb6b | 292 | { |
2851db21 | 293 | struct pci_dev *dma_pdev = pdev; |
9dcd6130 | 294 | |
31fe9435 | 295 | /* Account for quirked devices */ |
664b6003 AW |
296 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
297 | ||
31fe9435 AW |
298 | /* |
299 | * If it's a multifunction device that does not support our | |
300 | * required ACS flags, add to the same group as function 0. | |
301 | */ | |
664b6003 AW |
302 | if (dma_pdev->multifunction && |
303 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) | |
304 | swap_pci_ref(&dma_pdev, | |
305 | pci_get_slot(dma_pdev->bus, | |
306 | PCI_DEVFN(PCI_SLOT(dma_pdev->devfn), | |
307 | 0))); | |
308 | ||
31fe9435 AW |
309 | /* |
310 | * Devices on the root bus go through the iommu. If that's not us, | |
311 | * find the next upstream device and test ACS up to the root bus. | |
312 | * Finding the next device may require skipping virtual buses. | |
313 | */ | |
664b6003 | 314 | while (!pci_is_root_bus(dma_pdev->bus)) { |
2bff6a50 AW |
315 | struct pci_bus *bus = find_hosted_bus(dma_pdev->bus); |
316 | if (IS_ERR(bus)) | |
317 | break; | |
31fe9435 AW |
318 | |
319 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) | |
664b6003 AW |
320 | break; |
321 | ||
31fe9435 | 322 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
664b6003 AW |
323 | } |
324 | ||
2851db21 AW |
325 | return dma_pdev; |
326 | } | |
327 | ||
328 | static int init_iommu_group(struct device *dev) | |
329 | { | |
330 | struct iommu_dev_data *dev_data; | |
331 | struct iommu_group *group; | |
332 | struct pci_dev *dma_pdev = NULL; | |
333 | int ret; | |
334 | ||
335 | group = iommu_group_get(dev); | |
336 | if (group) { | |
337 | iommu_group_put(group); | |
338 | return 0; | |
339 | } | |
340 | ||
341 | dev_data = find_dev_data(get_device_id(dev)); | |
342 | if (!dev_data) | |
343 | return -ENOMEM; | |
344 | ||
345 | if (dev_data->alias_data) { | |
346 | u16 alias; | |
347 | ||
348 | alias = amd_iommu_alias_table[dev_data->devid]; | |
349 | dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); | |
350 | } | |
351 | ||
352 | if (!dma_pdev) | |
353 | dma_pdev = pci_dev_get(to_pci_dev(dev)); | |
354 | ||
355 | dma_pdev = get_isolation_root(dma_pdev); | |
9dcd6130 AW |
356 | group = iommu_group_get(&dma_pdev->dev); |
357 | pci_dev_put(dma_pdev); | |
358 | if (!group) { | |
359 | group = iommu_group_alloc(); | |
360 | if (IS_ERR(group)) | |
361 | return PTR_ERR(group); | |
26018874 | 362 | } |
657cbb6b | 363 | |
9dcd6130 AW |
364 | ret = iommu_group_add_device(group, dev); |
365 | ||
366 | iommu_group_put(group); | |
367 | ||
eb9c9527 AW |
368 | return ret; |
369 | } | |
370 | ||
371 | static int iommu_init_device(struct device *dev) | |
372 | { | |
373 | struct pci_dev *pdev = to_pci_dev(dev); | |
374 | struct iommu_dev_data *dev_data; | |
375 | u16 alias; | |
376 | int ret; | |
377 | ||
378 | if (dev->archdata.iommu) | |
379 | return 0; | |
380 | ||
381 | dev_data = find_dev_data(get_device_id(dev)); | |
382 | if (!dev_data) | |
383 | return -ENOMEM; | |
384 | ||
385 | alias = amd_iommu_alias_table[dev_data->devid]; | |
386 | if (alias != dev_data->devid) { | |
387 | struct iommu_dev_data *alias_data; | |
388 | ||
389 | alias_data = find_dev_data(alias); | |
390 | if (alias_data == NULL) { | |
391 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
392 | dev_name(dev)); | |
393 | free_dev_data(dev_data); | |
394 | return -ENOTSUPP; | |
395 | } | |
396 | dev_data->alias_data = alias_data; | |
397 | } | |
398 | ||
399 | ret = init_iommu_group(dev); | |
9dcd6130 AW |
400 | if (ret) |
401 | return ret; | |
402 | ||
5abcdba4 JR |
403 | if (pci_iommuv2_capable(pdev)) { |
404 | struct amd_iommu *iommu; | |
405 | ||
406 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
407 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
408 | } | |
409 | ||
657cbb6b JR |
410 | dev->archdata.iommu = dev_data; |
411 | ||
657cbb6b JR |
412 | return 0; |
413 | } | |
414 | ||
26018874 JR |
415 | static void iommu_ignore_device(struct device *dev) |
416 | { | |
417 | u16 devid, alias; | |
418 | ||
419 | devid = get_device_id(dev); | |
420 | alias = amd_iommu_alias_table[devid]; | |
421 | ||
422 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
423 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
424 | ||
425 | amd_iommu_rlookup_table[devid] = NULL; | |
426 | amd_iommu_rlookup_table[alias] = NULL; | |
427 | } | |
428 | ||
657cbb6b JR |
429 | static void iommu_uninit_device(struct device *dev) |
430 | { | |
9dcd6130 AW |
431 | iommu_group_remove_device(dev); |
432 | ||
8fa5f802 JR |
433 | /* |
434 | * Nothing to do here - we keep dev_data around for unplugged devices | |
435 | * and reuse it when the device is re-plugged - not doing so would | |
436 | * introduce a ton of races. | |
437 | */ | |
657cbb6b | 438 | } |
b7cc9554 JR |
439 | |
440 | void __init amd_iommu_uninit_devices(void) | |
441 | { | |
8fa5f802 | 442 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
443 | struct pci_dev *pdev = NULL; |
444 | ||
445 | for_each_pci_dev(pdev) { | |
446 | ||
447 | if (!check_device(&pdev->dev)) | |
448 | continue; | |
449 | ||
450 | iommu_uninit_device(&pdev->dev); | |
451 | } | |
8fa5f802 JR |
452 | |
453 | /* Free all of our dev_data structures */ | |
454 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
455 | free_dev_data(dev_data); | |
b7cc9554 JR |
456 | } |
457 | ||
458 | int __init amd_iommu_init_devices(void) | |
459 | { | |
460 | struct pci_dev *pdev = NULL; | |
461 | int ret = 0; | |
462 | ||
463 | for_each_pci_dev(pdev) { | |
464 | ||
465 | if (!check_device(&pdev->dev)) | |
466 | continue; | |
467 | ||
468 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
469 | if (ret == -ENOTSUPP) |
470 | iommu_ignore_device(&pdev->dev); | |
471 | else if (ret) | |
b7cc9554 JR |
472 | goto out_free; |
473 | } | |
474 | ||
475 | return 0; | |
476 | ||
477 | out_free: | |
478 | ||
479 | amd_iommu_uninit_devices(); | |
480 | ||
481 | return ret; | |
482 | } | |
7f26508b JR |
483 | #ifdef CONFIG_AMD_IOMMU_STATS |
484 | ||
485 | /* | |
486 | * Initialization code for statistics collection | |
487 | */ | |
488 | ||
da49f6df | 489 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 490 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 491 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 492 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 493 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 494 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 495 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 496 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 497 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 498 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 499 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 500 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
501 | DECLARE_STATS_COUNTER(complete_ppr); |
502 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
503 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
504 | DECLARE_STATS_COUNTER(pri_requests); | |
505 | ||
7f26508b | 506 | static struct dentry *stats_dir; |
7f26508b JR |
507 | static struct dentry *de_fflush; |
508 | ||
509 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
510 | { | |
511 | if (stats_dir == NULL) | |
512 | return; | |
513 | ||
514 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
515 | &cnt->value); | |
516 | } | |
517 | ||
518 | static void amd_iommu_stats_init(void) | |
519 | { | |
520 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
521 | if (stats_dir == NULL) | |
522 | return; | |
523 | ||
7f26508b | 524 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 525 | &amd_iommu_unmap_flush); |
da49f6df JR |
526 | |
527 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 528 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 529 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 530 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 531 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 532 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 533 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 534 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 535 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 536 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 537 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 538 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
539 | amd_iommu_stats_add(&complete_ppr); |
540 | amd_iommu_stats_add(&invalidate_iotlb); | |
541 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
542 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
543 | } |
544 | ||
545 | #endif | |
546 | ||
a80dc3e0 JR |
547 | /**************************************************************************** |
548 | * | |
549 | * Interrupt handling functions | |
550 | * | |
551 | ****************************************************************************/ | |
552 | ||
e3e59876 JR |
553 | static void dump_dte_entry(u16 devid) |
554 | { | |
555 | int i; | |
556 | ||
ee6c2868 JR |
557 | for (i = 0; i < 4; ++i) |
558 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
559 | amd_iommu_dev_table[devid].data[i]); |
560 | } | |
561 | ||
945b4ac4 JR |
562 | static void dump_command(unsigned long phys_addr) |
563 | { | |
564 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
565 | int i; | |
566 | ||
567 | for (i = 0; i < 4; ++i) | |
568 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
569 | } | |
570 | ||
a345b23b | 571 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 572 | { |
3d06fca8 JR |
573 | int type, devid, domid, flags; |
574 | volatile u32 *event = __evt; | |
575 | int count = 0; | |
576 | u64 address; | |
577 | ||
578 | retry: | |
579 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
580 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
581 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
582 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
583 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
584 | ||
585 | if (type == 0) { | |
586 | /* Did we hit the erratum? */ | |
587 | if (++count == LOOP_TIMEOUT) { | |
588 | pr_err("AMD-Vi: No event written to event log\n"); | |
589 | return; | |
590 | } | |
591 | udelay(1); | |
592 | goto retry; | |
593 | } | |
90008ee4 | 594 | |
4c6f40d4 | 595 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
596 | |
597 | switch (type) { | |
598 | case EVENT_TYPE_ILL_DEV: | |
599 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
600 | "address=0x%016llx flags=0x%04x]\n", | |
601 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
602 | address, flags); | |
e3e59876 | 603 | dump_dte_entry(devid); |
90008ee4 JR |
604 | break; |
605 | case EVENT_TYPE_IO_FAULT: | |
606 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
607 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
608 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
609 | domid, address, flags); | |
610 | break; | |
611 | case EVENT_TYPE_DEV_TAB_ERR: | |
612 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
613 | "address=0x%016llx flags=0x%04x]\n", | |
614 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
615 | address, flags); | |
616 | break; | |
617 | case EVENT_TYPE_PAGE_TAB_ERR: | |
618 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
619 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
620 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
621 | domid, address, flags); | |
622 | break; | |
623 | case EVENT_TYPE_ILL_CMD: | |
624 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 625 | dump_command(address); |
90008ee4 JR |
626 | break; |
627 | case EVENT_TYPE_CMD_HARD_ERR: | |
628 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
629 | "flags=0x%04x]\n", address, flags); | |
630 | break; | |
631 | case EVENT_TYPE_IOTLB_INV_TO: | |
632 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
633 | "address=0x%016llx]\n", | |
634 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
635 | address); | |
636 | break; | |
637 | case EVENT_TYPE_INV_DEV_REQ: | |
638 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
639 | "address=0x%016llx flags=0x%04x]\n", | |
640 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
641 | address, flags); | |
642 | break; | |
643 | default: | |
644 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
645 | } | |
3d06fca8 JR |
646 | |
647 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
648 | } |
649 | ||
650 | static void iommu_poll_events(struct amd_iommu *iommu) | |
651 | { | |
652 | u32 head, tail; | |
653 | unsigned long flags; | |
654 | ||
655 | spin_lock_irqsave(&iommu->lock, flags); | |
656 | ||
657 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
658 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
659 | ||
660 | while (head != tail) { | |
a345b23b | 661 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
662 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
663 | } | |
664 | ||
665 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
666 | ||
667 | spin_unlock_irqrestore(&iommu->lock, flags); | |
668 | } | |
669 | ||
eee53537 | 670 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
671 | { |
672 | struct amd_iommu_fault fault; | |
72e1dcc4 | 673 | |
399be2f5 JR |
674 | INC_STATS_COUNTER(pri_requests); |
675 | ||
72e1dcc4 JR |
676 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
677 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
678 | return; | |
679 | } | |
680 | ||
681 | fault.address = raw[1]; | |
682 | fault.pasid = PPR_PASID(raw[0]); | |
683 | fault.device_id = PPR_DEVID(raw[0]); | |
684 | fault.tag = PPR_TAG(raw[0]); | |
685 | fault.flags = PPR_FLAGS(raw[0]); | |
686 | ||
72e1dcc4 JR |
687 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
688 | } | |
689 | ||
690 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
691 | { | |
692 | unsigned long flags; | |
693 | u32 head, tail; | |
694 | ||
695 | if (iommu->ppr_log == NULL) | |
696 | return; | |
697 | ||
eee53537 JR |
698 | /* enable ppr interrupts again */ |
699 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
700 | ||
72e1dcc4 JR |
701 | spin_lock_irqsave(&iommu->lock, flags); |
702 | ||
703 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
704 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
705 | ||
706 | while (head != tail) { | |
eee53537 JR |
707 | volatile u64 *raw; |
708 | u64 entry[2]; | |
709 | int i; | |
710 | ||
711 | raw = (u64 *)(iommu->ppr_log + head); | |
712 | ||
713 | /* | |
714 | * Hardware bug: Interrupt may arrive before the entry is | |
715 | * written to memory. If this happens we need to wait for the | |
716 | * entry to arrive. | |
717 | */ | |
718 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
719 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
720 | break; | |
721 | udelay(1); | |
722 | } | |
72e1dcc4 | 723 | |
eee53537 JR |
724 | /* Avoid memcpy function-call overhead */ |
725 | entry[0] = raw[0]; | |
726 | entry[1] = raw[1]; | |
72e1dcc4 | 727 | |
eee53537 JR |
728 | /* |
729 | * To detect the hardware bug we need to clear the entry | |
730 | * back to zero. | |
731 | */ | |
732 | raw[0] = raw[1] = 0UL; | |
733 | ||
734 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
735 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
736 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 JR |
737 | |
738 | /* | |
739 | * Release iommu->lock because ppr-handling might need to | |
df805abb | 740 | * re-acquire it |
eee53537 JR |
741 | */ |
742 | spin_unlock_irqrestore(&iommu->lock, flags); | |
743 | ||
744 | /* Handle PPR entry */ | |
745 | iommu_handle_ppr_entry(iommu, entry); | |
746 | ||
747 | spin_lock_irqsave(&iommu->lock, flags); | |
748 | ||
749 | /* Refresh ring-buffer information */ | |
750 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
751 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
752 | } | |
753 | ||
72e1dcc4 JR |
754 | spin_unlock_irqrestore(&iommu->lock, flags); |
755 | } | |
756 | ||
72fe00f0 | 757 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 758 | { |
90008ee4 JR |
759 | struct amd_iommu *iommu; |
760 | ||
72e1dcc4 | 761 | for_each_iommu(iommu) { |
90008ee4 | 762 | iommu_poll_events(iommu); |
72e1dcc4 JR |
763 | iommu_poll_ppr_log(iommu); |
764 | } | |
90008ee4 JR |
765 | |
766 | return IRQ_HANDLED; | |
a80dc3e0 JR |
767 | } |
768 | ||
72fe00f0 JR |
769 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
770 | { | |
771 | return IRQ_WAKE_THREAD; | |
772 | } | |
773 | ||
431b2a20 JR |
774 | /**************************************************************************** |
775 | * | |
776 | * IOMMU command queuing functions | |
777 | * | |
778 | ****************************************************************************/ | |
779 | ||
ac0ea6e9 JR |
780 | static int wait_on_sem(volatile u64 *sem) |
781 | { | |
782 | int i = 0; | |
783 | ||
784 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
785 | udelay(1); | |
786 | i += 1; | |
787 | } | |
788 | ||
789 | if (i == LOOP_TIMEOUT) { | |
790 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
791 | return -EIO; | |
792 | } | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
797 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
798 | struct iommu_cmd *cmd, | |
799 | u32 tail) | |
a19ae1ec | 800 | { |
a19ae1ec JR |
801 | u8 *target; |
802 | ||
8a7c5ef3 | 803 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
804 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
805 | ||
806 | /* Copy command to buffer */ | |
807 | memcpy(target, cmd, sizeof(*cmd)); | |
808 | ||
809 | /* Tell the IOMMU about it */ | |
a19ae1ec | 810 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 811 | } |
a19ae1ec | 812 | |
815b33fd | 813 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 814 | { |
815b33fd JR |
815 | WARN_ON(address & 0x7ULL); |
816 | ||
ded46737 | 817 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
818 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
819 | cmd->data[1] = upper_32_bits(__pa(address)); | |
820 | cmd->data[2] = 1; | |
ded46737 JR |
821 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
822 | } | |
823 | ||
94fe79e2 JR |
824 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
825 | { | |
826 | memset(cmd, 0, sizeof(*cmd)); | |
827 | cmd->data[0] = devid; | |
828 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
829 | } | |
830 | ||
11b6402c JR |
831 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
832 | size_t size, u16 domid, int pde) | |
833 | { | |
834 | u64 pages; | |
835 | int s; | |
836 | ||
837 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
838 | s = 0; | |
839 | ||
840 | if (pages > 1) { | |
841 | /* | |
842 | * If we have to flush more than one page, flush all | |
843 | * TLB entries for this domain | |
844 | */ | |
845 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
846 | s = 1; | |
847 | } | |
848 | ||
849 | address &= PAGE_MASK; | |
850 | ||
851 | memset(cmd, 0, sizeof(*cmd)); | |
852 | cmd->data[1] |= domid; | |
853 | cmd->data[2] = lower_32_bits(address); | |
854 | cmd->data[3] = upper_32_bits(address); | |
855 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
856 | if (s) /* size bit - we flush more than one 4kb page */ | |
857 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 858 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
859 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
860 | } | |
861 | ||
cb41ed85 JR |
862 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
863 | u64 address, size_t size) | |
864 | { | |
865 | u64 pages; | |
866 | int s; | |
867 | ||
868 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
869 | s = 0; | |
870 | ||
871 | if (pages > 1) { | |
872 | /* | |
873 | * If we have to flush more than one page, flush all | |
874 | * TLB entries for this domain | |
875 | */ | |
876 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
877 | s = 1; | |
878 | } | |
879 | ||
880 | address &= PAGE_MASK; | |
881 | ||
882 | memset(cmd, 0, sizeof(*cmd)); | |
883 | cmd->data[0] = devid; | |
884 | cmd->data[0] |= (qdep & 0xff) << 24; | |
885 | cmd->data[1] = devid; | |
886 | cmd->data[2] = lower_32_bits(address); | |
887 | cmd->data[3] = upper_32_bits(address); | |
888 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
889 | if (s) | |
890 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
891 | } | |
892 | ||
22e266c7 JR |
893 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
894 | u64 address, bool size) | |
895 | { | |
896 | memset(cmd, 0, sizeof(*cmd)); | |
897 | ||
898 | address &= ~(0xfffULL); | |
899 | ||
900 | cmd->data[0] = pasid & PASID_MASK; | |
901 | cmd->data[1] = domid; | |
902 | cmd->data[2] = lower_32_bits(address); | |
903 | cmd->data[3] = upper_32_bits(address); | |
904 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
905 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
906 | if (size) | |
907 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
908 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
909 | } | |
910 | ||
911 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
912 | int qdep, u64 address, bool size) | |
913 | { | |
914 | memset(cmd, 0, sizeof(*cmd)); | |
915 | ||
916 | address &= ~(0xfffULL); | |
917 | ||
918 | cmd->data[0] = devid; | |
919 | cmd->data[0] |= (pasid & 0xff) << 16; | |
920 | cmd->data[0] |= (qdep & 0xff) << 24; | |
921 | cmd->data[1] = devid; | |
922 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
923 | cmd->data[2] = lower_32_bits(address); | |
924 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
925 | cmd->data[3] = upper_32_bits(address); | |
926 | if (size) | |
927 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
928 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
929 | } | |
930 | ||
c99afa25 JR |
931 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
932 | int status, int tag, bool gn) | |
933 | { | |
934 | memset(cmd, 0, sizeof(*cmd)); | |
935 | ||
936 | cmd->data[0] = devid; | |
937 | if (gn) { | |
938 | cmd->data[1] = pasid & PASID_MASK; | |
939 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
940 | } | |
941 | cmd->data[3] = tag & 0x1ff; | |
942 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
943 | ||
944 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
945 | } | |
946 | ||
58fc7f14 JR |
947 | static void build_inv_all(struct iommu_cmd *cmd) |
948 | { | |
949 | memset(cmd, 0, sizeof(*cmd)); | |
950 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
951 | } |
952 | ||
7ef2798d JR |
953 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
954 | { | |
955 | memset(cmd, 0, sizeof(*cmd)); | |
956 | cmd->data[0] = devid; | |
957 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
958 | } | |
959 | ||
431b2a20 | 960 | /* |
431b2a20 | 961 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 962 | * hardware about the new command. |
431b2a20 | 963 | */ |
f1ca1512 JR |
964 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
965 | struct iommu_cmd *cmd, | |
966 | bool sync) | |
a19ae1ec | 967 | { |
ac0ea6e9 | 968 | u32 left, tail, head, next_tail; |
a19ae1ec | 969 | unsigned long flags; |
a19ae1ec | 970 | |
549c90dc | 971 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
972 | |
973 | again: | |
a19ae1ec | 974 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 975 | |
ac0ea6e9 JR |
976 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
977 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
978 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
979 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 980 | |
ac0ea6e9 JR |
981 | if (left <= 2) { |
982 | struct iommu_cmd sync_cmd; | |
983 | volatile u64 sem = 0; | |
984 | int ret; | |
8d201968 | 985 | |
ac0ea6e9 JR |
986 | build_completion_wait(&sync_cmd, (u64)&sem); |
987 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 988 | |
ac0ea6e9 JR |
989 | spin_unlock_irqrestore(&iommu->lock, flags); |
990 | ||
991 | if ((ret = wait_on_sem(&sem)) != 0) | |
992 | return ret; | |
993 | ||
994 | goto again; | |
8d201968 JR |
995 | } |
996 | ||
ac0ea6e9 JR |
997 | copy_cmd_to_buffer(iommu, cmd, tail); |
998 | ||
999 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1000 | iommu->need_sync = sync; |
ac0ea6e9 | 1001 | |
a19ae1ec | 1002 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1003 | |
815b33fd | 1004 | return 0; |
8d201968 JR |
1005 | } |
1006 | ||
f1ca1512 JR |
1007 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1008 | { | |
1009 | return iommu_queue_command_sync(iommu, cmd, true); | |
1010 | } | |
1011 | ||
8d201968 JR |
1012 | /* |
1013 | * This function queues a completion wait command into the command | |
1014 | * buffer of an IOMMU | |
1015 | */ | |
a19ae1ec | 1016 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1017 | { |
1018 | struct iommu_cmd cmd; | |
815b33fd | 1019 | volatile u64 sem = 0; |
ac0ea6e9 | 1020 | int ret; |
8d201968 | 1021 | |
09ee17eb | 1022 | if (!iommu->need_sync) |
815b33fd | 1023 | return 0; |
09ee17eb | 1024 | |
815b33fd | 1025 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1026 | |
f1ca1512 | 1027 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1028 | if (ret) |
815b33fd | 1029 | return ret; |
8d201968 | 1030 | |
ac0ea6e9 | 1031 | return wait_on_sem(&sem); |
8d201968 JR |
1032 | } |
1033 | ||
d8c13085 | 1034 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1035 | { |
d8c13085 | 1036 | struct iommu_cmd cmd; |
a19ae1ec | 1037 | |
d8c13085 | 1038 | build_inv_dte(&cmd, devid); |
7e4f88da | 1039 | |
d8c13085 JR |
1040 | return iommu_queue_command(iommu, &cmd); |
1041 | } | |
09ee17eb | 1042 | |
7d0c5cc5 JR |
1043 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1044 | { | |
1045 | u32 devid; | |
09ee17eb | 1046 | |
7d0c5cc5 JR |
1047 | for (devid = 0; devid <= 0xffff; ++devid) |
1048 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1049 | |
7d0c5cc5 JR |
1050 | iommu_completion_wait(iommu); |
1051 | } | |
84df8175 | 1052 | |
7d0c5cc5 JR |
1053 | /* |
1054 | * This function uses heavy locking and may disable irqs for some time. But | |
1055 | * this is no issue because it is only called during resume. | |
1056 | */ | |
1057 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1058 | { | |
1059 | u32 dom_id; | |
a19ae1ec | 1060 | |
7d0c5cc5 JR |
1061 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1062 | struct iommu_cmd cmd; | |
1063 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1064 | dom_id, 1); | |
1065 | iommu_queue_command(iommu, &cmd); | |
1066 | } | |
8eed9833 | 1067 | |
7d0c5cc5 | 1068 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1069 | } |
1070 | ||
58fc7f14 | 1071 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1072 | { |
58fc7f14 | 1073 | struct iommu_cmd cmd; |
0518a3a4 | 1074 | |
58fc7f14 | 1075 | build_inv_all(&cmd); |
0518a3a4 | 1076 | |
58fc7f14 JR |
1077 | iommu_queue_command(iommu, &cmd); |
1078 | iommu_completion_wait(iommu); | |
1079 | } | |
1080 | ||
7ef2798d JR |
1081 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1082 | { | |
1083 | struct iommu_cmd cmd; | |
1084 | ||
1085 | build_inv_irt(&cmd, devid); | |
1086 | ||
1087 | iommu_queue_command(iommu, &cmd); | |
1088 | } | |
1089 | ||
1090 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1091 | { | |
1092 | u32 devid; | |
1093 | ||
1094 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1095 | iommu_flush_irt(iommu, devid); | |
1096 | ||
1097 | iommu_completion_wait(iommu); | |
1098 | } | |
1099 | ||
7d0c5cc5 JR |
1100 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1101 | { | |
58fc7f14 JR |
1102 | if (iommu_feature(iommu, FEATURE_IA)) { |
1103 | iommu_flush_all(iommu); | |
1104 | } else { | |
1105 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1106 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1107 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1108 | } |
1109 | } | |
1110 | ||
431b2a20 | 1111 | /* |
cb41ed85 | 1112 | * Command send function for flushing on-device TLB |
431b2a20 | 1113 | */ |
6c542047 JR |
1114 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1115 | u64 address, size_t size) | |
3fa43655 JR |
1116 | { |
1117 | struct amd_iommu *iommu; | |
b00d3bcf | 1118 | struct iommu_cmd cmd; |
cb41ed85 | 1119 | int qdep; |
3fa43655 | 1120 | |
ea61cddb JR |
1121 | qdep = dev_data->ats.qdep; |
1122 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1123 | |
ea61cddb | 1124 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1125 | |
1126 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1127 | } |
1128 | ||
431b2a20 | 1129 | /* |
431b2a20 | 1130 | * Command send function for invalidating a device table entry |
431b2a20 | 1131 | */ |
6c542047 | 1132 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1133 | { |
3fa43655 | 1134 | struct amd_iommu *iommu; |
ee2fa743 | 1135 | int ret; |
a19ae1ec | 1136 | |
6c542047 | 1137 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1138 | |
f62dda66 | 1139 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1140 | if (ret) |
1141 | return ret; | |
1142 | ||
ea61cddb | 1143 | if (dev_data->ats.enabled) |
6c542047 | 1144 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1145 | |
ee2fa743 | 1146 | return ret; |
a19ae1ec JR |
1147 | } |
1148 | ||
431b2a20 JR |
1149 | /* |
1150 | * TLB invalidation function which is called from the mapping functions. | |
1151 | * It invalidates a single PTE if the range to flush is within a single | |
1152 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1153 | */ | |
17b124bf JR |
1154 | static void __domain_flush_pages(struct protection_domain *domain, |
1155 | u64 address, size_t size, int pde) | |
a19ae1ec | 1156 | { |
cb41ed85 | 1157 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1158 | struct iommu_cmd cmd; |
1159 | int ret = 0, i; | |
a19ae1ec | 1160 | |
11b6402c | 1161 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1162 | |
6de8ad9b JR |
1163 | for (i = 0; i < amd_iommus_present; ++i) { |
1164 | if (!domain->dev_iommu[i]) | |
1165 | continue; | |
1166 | ||
1167 | /* | |
1168 | * Devices of this domain are behind this IOMMU | |
1169 | * We need a TLB flush | |
1170 | */ | |
11b6402c | 1171 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1172 | } |
1173 | ||
cb41ed85 | 1174 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1175 | |
ea61cddb | 1176 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1177 | continue; |
1178 | ||
6c542047 | 1179 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1180 | } |
1181 | ||
11b6402c | 1182 | WARN_ON(ret); |
6de8ad9b JR |
1183 | } |
1184 | ||
17b124bf JR |
1185 | static void domain_flush_pages(struct protection_domain *domain, |
1186 | u64 address, size_t size) | |
6de8ad9b | 1187 | { |
17b124bf | 1188 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1189 | } |
b6c02715 | 1190 | |
1c655773 | 1191 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1192 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1193 | { |
17b124bf | 1194 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1195 | } |
1196 | ||
42a49f96 | 1197 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1198 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1199 | { |
17b124bf | 1200 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1201 | } |
1202 | ||
17b124bf | 1203 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1204 | { |
17b124bf | 1205 | int i; |
18811f55 | 1206 | |
17b124bf JR |
1207 | for (i = 0; i < amd_iommus_present; ++i) { |
1208 | if (!domain->dev_iommu[i]) | |
1209 | continue; | |
bfd1be18 | 1210 | |
17b124bf JR |
1211 | /* |
1212 | * Devices of this domain are behind this IOMMU | |
1213 | * We need to wait for completion of all commands. | |
1214 | */ | |
1215 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1216 | } |
e394d72a JR |
1217 | } |
1218 | ||
b00d3bcf | 1219 | |
09b42804 | 1220 | /* |
b00d3bcf | 1221 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1222 | */ |
17b124bf | 1223 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1224 | { |
b00d3bcf | 1225 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1226 | |
b00d3bcf | 1227 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1228 | device_flush_dte(dev_data); |
a345b23b JR |
1229 | } |
1230 | ||
431b2a20 JR |
1231 | /**************************************************************************** |
1232 | * | |
1233 | * The functions below are used the create the page table mappings for | |
1234 | * unity mapped regions. | |
1235 | * | |
1236 | ****************************************************************************/ | |
1237 | ||
308973d3 JR |
1238 | /* |
1239 | * This function is used to add another level to an IO page table. Adding | |
1240 | * another level increases the size of the address space by 9 bits to a size up | |
1241 | * to 64 bits. | |
1242 | */ | |
1243 | static bool increase_address_space(struct protection_domain *domain, | |
1244 | gfp_t gfp) | |
1245 | { | |
1246 | u64 *pte; | |
1247 | ||
1248 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1249 | /* address space already 64 bit large */ | |
1250 | return false; | |
1251 | ||
1252 | pte = (void *)get_zeroed_page(gfp); | |
1253 | if (!pte) | |
1254 | return false; | |
1255 | ||
1256 | *pte = PM_LEVEL_PDE(domain->mode, | |
1257 | virt_to_phys(domain->pt_root)); | |
1258 | domain->pt_root = pte; | |
1259 | domain->mode += 1; | |
1260 | domain->updated = true; | |
1261 | ||
1262 | return true; | |
1263 | } | |
1264 | ||
1265 | static u64 *alloc_pte(struct protection_domain *domain, | |
1266 | unsigned long address, | |
cbb9d729 | 1267 | unsigned long page_size, |
308973d3 JR |
1268 | u64 **pte_page, |
1269 | gfp_t gfp) | |
1270 | { | |
cbb9d729 | 1271 | int level, end_lvl; |
308973d3 | 1272 | u64 *pte, *page; |
cbb9d729 JR |
1273 | |
1274 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1275 | |
1276 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1277 | increase_address_space(domain, gfp); | |
1278 | ||
cbb9d729 JR |
1279 | level = domain->mode - 1; |
1280 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1281 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1282 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1283 | |
1284 | while (level > end_lvl) { | |
1285 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1286 | page = (u64 *)get_zeroed_page(gfp); | |
1287 | if (!page) | |
1288 | return NULL; | |
1289 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1290 | } | |
1291 | ||
cbb9d729 JR |
1292 | /* No level skipping support yet */ |
1293 | if (PM_PTE_LEVEL(*pte) != level) | |
1294 | return NULL; | |
1295 | ||
308973d3 JR |
1296 | level -= 1; |
1297 | ||
1298 | pte = IOMMU_PTE_PAGE(*pte); | |
1299 | ||
1300 | if (pte_page && level == end_lvl) | |
1301 | *pte_page = pte; | |
1302 | ||
1303 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1304 | } | |
1305 | ||
1306 | return pte; | |
1307 | } | |
1308 | ||
1309 | /* | |
1310 | * This function checks if there is a PTE for a given dma address. If | |
1311 | * there is one, it returns the pointer to it. | |
1312 | */ | |
24cd7723 | 1313 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1314 | { |
1315 | int level; | |
1316 | u64 *pte; | |
1317 | ||
24cd7723 JR |
1318 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1319 | return NULL; | |
1320 | ||
1321 | level = domain->mode - 1; | |
1322 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1323 | |
24cd7723 JR |
1324 | while (level > 0) { |
1325 | ||
1326 | /* Not Present */ | |
308973d3 JR |
1327 | if (!IOMMU_PTE_PRESENT(*pte)) |
1328 | return NULL; | |
1329 | ||
24cd7723 JR |
1330 | /* Large PTE */ |
1331 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1332 | unsigned long pte_mask, __pte; | |
1333 | ||
1334 | /* | |
1335 | * If we have a series of large PTEs, make | |
1336 | * sure to return a pointer to the first one. | |
1337 | */ | |
1338 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1339 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1340 | __pte = ((unsigned long)pte) & pte_mask; | |
1341 | ||
1342 | return (u64 *)__pte; | |
1343 | } | |
1344 | ||
1345 | /* No level skipping support yet */ | |
1346 | if (PM_PTE_LEVEL(*pte) != level) | |
1347 | return NULL; | |
1348 | ||
308973d3 JR |
1349 | level -= 1; |
1350 | ||
24cd7723 | 1351 | /* Walk to the next level */ |
308973d3 JR |
1352 | pte = IOMMU_PTE_PAGE(*pte); |
1353 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1354 | } |
1355 | ||
1356 | return pte; | |
1357 | } | |
1358 | ||
431b2a20 JR |
1359 | /* |
1360 | * Generic mapping functions. It maps a physical address into a DMA | |
1361 | * address space. It allocates the page table pages if necessary. | |
1362 | * In the future it can be extended to a generic mapping function | |
1363 | * supporting all features of AMD IOMMU page tables like level skipping | |
1364 | * and full 64 bit address spaces. | |
1365 | */ | |
38e817fe JR |
1366 | static int iommu_map_page(struct protection_domain *dom, |
1367 | unsigned long bus_addr, | |
1368 | unsigned long phys_addr, | |
abdc5eb3 | 1369 | int prot, |
cbb9d729 | 1370 | unsigned long page_size) |
bd0e5211 | 1371 | { |
8bda3092 | 1372 | u64 __pte, *pte; |
cbb9d729 | 1373 | int i, count; |
abdc5eb3 | 1374 | |
bad1cac2 | 1375 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1376 | return -EINVAL; |
1377 | ||
cbb9d729 JR |
1378 | bus_addr = PAGE_ALIGN(bus_addr); |
1379 | phys_addr = PAGE_ALIGN(phys_addr); | |
1380 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1381 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1382 | ||
1383 | for (i = 0; i < count; ++i) | |
1384 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1385 | return -EBUSY; | |
bd0e5211 | 1386 | |
cbb9d729 JR |
1387 | if (page_size > PAGE_SIZE) { |
1388 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1389 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1390 | } else | |
1391 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1392 | |
bd0e5211 JR |
1393 | if (prot & IOMMU_PROT_IR) |
1394 | __pte |= IOMMU_PTE_IR; | |
1395 | if (prot & IOMMU_PROT_IW) | |
1396 | __pte |= IOMMU_PTE_IW; | |
1397 | ||
cbb9d729 JR |
1398 | for (i = 0; i < count; ++i) |
1399 | pte[i] = __pte; | |
bd0e5211 | 1400 | |
04bfdd84 JR |
1401 | update_domain(dom); |
1402 | ||
bd0e5211 JR |
1403 | return 0; |
1404 | } | |
1405 | ||
24cd7723 JR |
1406 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1407 | unsigned long bus_addr, | |
1408 | unsigned long page_size) | |
eb74ff6c | 1409 | { |
24cd7723 JR |
1410 | unsigned long long unmap_size, unmapped; |
1411 | u64 *pte; | |
1412 | ||
1413 | BUG_ON(!is_power_of_2(page_size)); | |
1414 | ||
1415 | unmapped = 0; | |
eb74ff6c | 1416 | |
24cd7723 JR |
1417 | while (unmapped < page_size) { |
1418 | ||
1419 | pte = fetch_pte(dom, bus_addr); | |
1420 | ||
1421 | if (!pte) { | |
1422 | /* | |
1423 | * No PTE for this address | |
1424 | * move forward in 4kb steps | |
1425 | */ | |
1426 | unmap_size = PAGE_SIZE; | |
1427 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1428 | /* 4kb PTE found for this address */ | |
1429 | unmap_size = PAGE_SIZE; | |
1430 | *pte = 0ULL; | |
1431 | } else { | |
1432 | int count, i; | |
1433 | ||
1434 | /* Large PTE found which maps this address */ | |
1435 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1436 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1437 | for (i = 0; i < count; i++) | |
1438 | pte[i] = 0ULL; | |
1439 | } | |
1440 | ||
1441 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1442 | unmapped += unmap_size; | |
1443 | } | |
1444 | ||
1445 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1446 | |
24cd7723 | 1447 | return unmapped; |
eb74ff6c | 1448 | } |
eb74ff6c | 1449 | |
431b2a20 JR |
1450 | /* |
1451 | * This function checks if a specific unity mapping entry is needed for | |
1452 | * this specific IOMMU. | |
1453 | */ | |
bd0e5211 JR |
1454 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1455 | struct unity_map_entry *entry) | |
1456 | { | |
1457 | u16 bdf, i; | |
1458 | ||
1459 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1460 | bdf = amd_iommu_alias_table[i]; | |
1461 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1462 | return 1; | |
1463 | } | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
431b2a20 JR |
1468 | /* |
1469 | * This function actually applies the mapping to the page table of the | |
1470 | * dma_ops domain. | |
1471 | */ | |
bd0e5211 JR |
1472 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1473 | struct unity_map_entry *e) | |
1474 | { | |
1475 | u64 addr; | |
1476 | int ret; | |
1477 | ||
1478 | for (addr = e->address_start; addr < e->address_end; | |
1479 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1480 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1481 | PAGE_SIZE); |
bd0e5211 JR |
1482 | if (ret) |
1483 | return ret; | |
1484 | /* | |
1485 | * if unity mapping is in aperture range mark the page | |
1486 | * as allocated in the aperture | |
1487 | */ | |
1488 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1489 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1490 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1491 | } |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
171e7b37 JR |
1496 | /* |
1497 | * Init the unity mappings for a specific IOMMU in the system | |
1498 | * | |
1499 | * Basically iterates over all unity mapping entries and applies them to | |
1500 | * the default domain DMA of that IOMMU if necessary. | |
1501 | */ | |
1502 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1503 | { | |
1504 | struct unity_map_entry *entry; | |
1505 | int ret; | |
1506 | ||
1507 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1508 | if (!iommu_for_unity_map(iommu, entry)) | |
1509 | continue; | |
1510 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1511 | if (ret) | |
1512 | return ret; | |
1513 | } | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
431b2a20 JR |
1518 | /* |
1519 | * Inits the unity mappings required for a specific device | |
1520 | */ | |
bd0e5211 JR |
1521 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1522 | u16 devid) | |
1523 | { | |
1524 | struct unity_map_entry *e; | |
1525 | int ret; | |
1526 | ||
1527 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1528 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1529 | continue; | |
1530 | ret = dma_ops_unity_map(dma_dom, e); | |
1531 | if (ret) | |
1532 | return ret; | |
1533 | } | |
1534 | ||
1535 | return 0; | |
1536 | } | |
1537 | ||
431b2a20 JR |
1538 | /**************************************************************************** |
1539 | * | |
1540 | * The next functions belong to the address allocator for the dma_ops | |
1541 | * interface functions. They work like the allocators in the other IOMMU | |
1542 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1543 | * the aperture. Maybe it could be enhanced in the future to a more | |
1544 | * efficient allocator. | |
1545 | * | |
1546 | ****************************************************************************/ | |
d3086444 | 1547 | |
431b2a20 | 1548 | /* |
384de729 | 1549 | * The address allocator core functions. |
431b2a20 JR |
1550 | * |
1551 | * called with domain->lock held | |
1552 | */ | |
384de729 | 1553 | |
171e7b37 JR |
1554 | /* |
1555 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1556 | * ranges. | |
1557 | */ | |
1558 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1559 | unsigned long start_page, | |
1560 | unsigned int pages) | |
1561 | { | |
1562 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1563 | ||
1564 | if (start_page + pages > last_page) | |
1565 | pages = last_page - start_page; | |
1566 | ||
1567 | for (i = start_page; i < start_page + pages; ++i) { | |
1568 | int index = i / APERTURE_RANGE_PAGES; | |
1569 | int page = i % APERTURE_RANGE_PAGES; | |
1570 | __set_bit(page, dom->aperture[index]->bitmap); | |
1571 | } | |
1572 | } | |
1573 | ||
9cabe89b JR |
1574 | /* |
1575 | * This function is used to add a new aperture range to an existing | |
1576 | * aperture in case of dma_ops domain allocation or address allocation | |
1577 | * failure. | |
1578 | */ | |
576175c2 | 1579 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1580 | bool populate, gfp_t gfp) |
1581 | { | |
1582 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1583 | struct amd_iommu *iommu; |
17f5b569 | 1584 | unsigned long i, old_size; |
9cabe89b | 1585 | |
f5e9705c JR |
1586 | #ifdef CONFIG_IOMMU_STRESS |
1587 | populate = false; | |
1588 | #endif | |
1589 | ||
9cabe89b JR |
1590 | if (index >= APERTURE_MAX_RANGES) |
1591 | return -ENOMEM; | |
1592 | ||
1593 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1594 | if (!dma_dom->aperture[index]) | |
1595 | return -ENOMEM; | |
1596 | ||
1597 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1598 | if (!dma_dom->aperture[index]->bitmap) | |
1599 | goto out_free; | |
1600 | ||
1601 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1602 | ||
1603 | if (populate) { | |
1604 | unsigned long address = dma_dom->aperture_size; | |
1605 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1606 | u64 *pte, *pte_page; | |
1607 | ||
1608 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1609 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1610 | &pte_page, gfp); |
1611 | if (!pte) | |
1612 | goto out_free; | |
1613 | ||
1614 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1615 | ||
1616 | address += APERTURE_RANGE_SIZE / 64; | |
1617 | } | |
1618 | } | |
1619 | ||
17f5b569 | 1620 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1621 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1622 | ||
17f5b569 JR |
1623 | /* Reserve address range used for MSI messages */ |
1624 | if (old_size < MSI_ADDR_BASE_LO && | |
1625 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1626 | unsigned long spage; | |
1627 | int pages; | |
1628 | ||
1629 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1630 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1631 | ||
1632 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1633 | } | |
1634 | ||
b595076a | 1635 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1636 | for_each_iommu(iommu) { |
1637 | if (iommu->exclusion_start && | |
1638 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1639 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1640 | unsigned long startpage; | |
1641 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1642 | iommu->exclusion_length, | |
1643 | PAGE_SIZE); | |
1644 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1645 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1646 | } | |
00cd122a JR |
1647 | } |
1648 | ||
1649 | /* | |
1650 | * Check for areas already mapped as present in the new aperture | |
1651 | * range and mark those pages as reserved in the allocator. Such | |
1652 | * mappings may already exist as a result of requested unity | |
1653 | * mappings for devices. | |
1654 | */ | |
1655 | for (i = dma_dom->aperture[index]->offset; | |
1656 | i < dma_dom->aperture_size; | |
1657 | i += PAGE_SIZE) { | |
24cd7723 | 1658 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1659 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1660 | continue; | |
1661 | ||
fcd0861d | 1662 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1663 | } |
1664 | ||
04bfdd84 JR |
1665 | update_domain(&dma_dom->domain); |
1666 | ||
9cabe89b JR |
1667 | return 0; |
1668 | ||
1669 | out_free: | |
04bfdd84 JR |
1670 | update_domain(&dma_dom->domain); |
1671 | ||
9cabe89b JR |
1672 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1673 | ||
1674 | kfree(dma_dom->aperture[index]); | |
1675 | dma_dom->aperture[index] = NULL; | |
1676 | ||
1677 | return -ENOMEM; | |
1678 | } | |
1679 | ||
384de729 JR |
1680 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1681 | struct dma_ops_domain *dom, | |
1682 | unsigned int pages, | |
1683 | unsigned long align_mask, | |
1684 | u64 dma_mask, | |
1685 | unsigned long start) | |
1686 | { | |
803b8cb4 | 1687 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1688 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1689 | int i = start >> APERTURE_RANGE_SHIFT; | |
1690 | unsigned long boundary_size; | |
1691 | unsigned long address = -1; | |
1692 | unsigned long limit; | |
1693 | ||
803b8cb4 JR |
1694 | next_bit >>= PAGE_SHIFT; |
1695 | ||
384de729 JR |
1696 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1697 | PAGE_SIZE) >> PAGE_SHIFT; | |
1698 | ||
1699 | for (;i < max_index; ++i) { | |
1700 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1701 | ||
1702 | if (dom->aperture[i]->offset >= dma_mask) | |
1703 | break; | |
1704 | ||
1705 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1706 | dma_mask >> PAGE_SHIFT); | |
1707 | ||
1708 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1709 | limit, next_bit, pages, 0, | |
1710 | boundary_size, align_mask); | |
1711 | if (address != -1) { | |
1712 | address = dom->aperture[i]->offset + | |
1713 | (address << PAGE_SHIFT); | |
803b8cb4 | 1714 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1715 | break; |
1716 | } | |
1717 | ||
1718 | next_bit = 0; | |
1719 | } | |
1720 | ||
1721 | return address; | |
1722 | } | |
1723 | ||
d3086444 JR |
1724 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1725 | struct dma_ops_domain *dom, | |
6d4f343f | 1726 | unsigned int pages, |
832a90c3 JR |
1727 | unsigned long align_mask, |
1728 | u64 dma_mask) | |
d3086444 | 1729 | { |
d3086444 | 1730 | unsigned long address; |
d3086444 | 1731 | |
fe16f088 JR |
1732 | #ifdef CONFIG_IOMMU_STRESS |
1733 | dom->next_address = 0; | |
1734 | dom->need_flush = true; | |
1735 | #endif | |
d3086444 | 1736 | |
384de729 | 1737 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1738 | dma_mask, dom->next_address); |
d3086444 | 1739 | |
1c655773 | 1740 | if (address == -1) { |
803b8cb4 | 1741 | dom->next_address = 0; |
384de729 JR |
1742 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1743 | dma_mask, 0); | |
1c655773 JR |
1744 | dom->need_flush = true; |
1745 | } | |
d3086444 | 1746 | |
384de729 | 1747 | if (unlikely(address == -1)) |
8fd524b3 | 1748 | address = DMA_ERROR_CODE; |
d3086444 JR |
1749 | |
1750 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1751 | ||
1752 | return address; | |
1753 | } | |
1754 | ||
431b2a20 JR |
1755 | /* |
1756 | * The address free function. | |
1757 | * | |
1758 | * called with domain->lock held | |
1759 | */ | |
d3086444 JR |
1760 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1761 | unsigned long address, | |
1762 | unsigned int pages) | |
1763 | { | |
384de729 JR |
1764 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1765 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1766 | |
384de729 JR |
1767 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1768 | ||
47bccd6b JR |
1769 | #ifdef CONFIG_IOMMU_STRESS |
1770 | if (i < 4) | |
1771 | return; | |
1772 | #endif | |
80be308d | 1773 | |
803b8cb4 | 1774 | if (address >= dom->next_address) |
80be308d | 1775 | dom->need_flush = true; |
384de729 JR |
1776 | |
1777 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1778 | |
a66022c4 | 1779 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1780 | |
d3086444 JR |
1781 | } |
1782 | ||
431b2a20 JR |
1783 | /**************************************************************************** |
1784 | * | |
1785 | * The next functions belong to the domain allocation. A domain is | |
1786 | * allocated for every IOMMU as the default domain. If device isolation | |
1787 | * is enabled, every device get its own domain. The most important thing | |
1788 | * about domains is the page table mapping the DMA address space they | |
1789 | * contain. | |
1790 | * | |
1791 | ****************************************************************************/ | |
1792 | ||
aeb26f55 JR |
1793 | /* |
1794 | * This function adds a protection domain to the global protection domain list | |
1795 | */ | |
1796 | static void add_domain_to_list(struct protection_domain *domain) | |
1797 | { | |
1798 | unsigned long flags; | |
1799 | ||
1800 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1801 | list_add(&domain->list, &amd_iommu_pd_list); | |
1802 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1803 | } | |
1804 | ||
1805 | /* | |
1806 | * This function removes a protection domain to the global | |
1807 | * protection domain list | |
1808 | */ | |
1809 | static void del_domain_from_list(struct protection_domain *domain) | |
1810 | { | |
1811 | unsigned long flags; | |
1812 | ||
1813 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1814 | list_del(&domain->list); | |
1815 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1816 | } | |
1817 | ||
ec487d1a JR |
1818 | static u16 domain_id_alloc(void) |
1819 | { | |
1820 | unsigned long flags; | |
1821 | int id; | |
1822 | ||
1823 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1824 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1825 | BUG_ON(id == 0); | |
1826 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1827 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1828 | else | |
1829 | id = 0; | |
1830 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1831 | ||
1832 | return id; | |
1833 | } | |
1834 | ||
a2acfb75 JR |
1835 | static void domain_id_free(int id) |
1836 | { | |
1837 | unsigned long flags; | |
1838 | ||
1839 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1840 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1841 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1842 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1843 | } | |
a2acfb75 | 1844 | |
86db2e5d | 1845 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1846 | { |
1847 | int i, j; | |
1848 | u64 *p1, *p2, *p3; | |
1849 | ||
86db2e5d | 1850 | p1 = domain->pt_root; |
ec487d1a JR |
1851 | |
1852 | if (!p1) | |
1853 | return; | |
1854 | ||
1855 | for (i = 0; i < 512; ++i) { | |
1856 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1857 | continue; | |
1858 | ||
1859 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1860 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1861 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1862 | continue; | |
1863 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1864 | free_page((unsigned long)p3); | |
1865 | } | |
1866 | ||
1867 | free_page((unsigned long)p2); | |
1868 | } | |
1869 | ||
1870 | free_page((unsigned long)p1); | |
86db2e5d JR |
1871 | |
1872 | domain->pt_root = NULL; | |
ec487d1a JR |
1873 | } |
1874 | ||
b16137b1 JR |
1875 | static void free_gcr3_tbl_level1(u64 *tbl) |
1876 | { | |
1877 | u64 *ptr; | |
1878 | int i; | |
1879 | ||
1880 | for (i = 0; i < 512; ++i) { | |
1881 | if (!(tbl[i] & GCR3_VALID)) | |
1882 | continue; | |
1883 | ||
1884 | ptr = __va(tbl[i] & PAGE_MASK); | |
1885 | ||
1886 | free_page((unsigned long)ptr); | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1891 | { | |
1892 | u64 *ptr; | |
1893 | int i; | |
1894 | ||
1895 | for (i = 0; i < 512; ++i) { | |
1896 | if (!(tbl[i] & GCR3_VALID)) | |
1897 | continue; | |
1898 | ||
1899 | ptr = __va(tbl[i] & PAGE_MASK); | |
1900 | ||
1901 | free_gcr3_tbl_level1(ptr); | |
1902 | } | |
1903 | } | |
1904 | ||
52815b75 JR |
1905 | static void free_gcr3_table(struct protection_domain *domain) |
1906 | { | |
b16137b1 JR |
1907 | if (domain->glx == 2) |
1908 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1909 | else if (domain->glx == 1) | |
1910 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1911 | else if (domain->glx != 0) | |
1912 | BUG(); | |
1913 | ||
52815b75 JR |
1914 | free_page((unsigned long)domain->gcr3_tbl); |
1915 | } | |
1916 | ||
431b2a20 JR |
1917 | /* |
1918 | * Free a domain, only used if something went wrong in the | |
1919 | * allocation path and we need to free an already allocated page table | |
1920 | */ | |
ec487d1a JR |
1921 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1922 | { | |
384de729 JR |
1923 | int i; |
1924 | ||
ec487d1a JR |
1925 | if (!dom) |
1926 | return; | |
1927 | ||
aeb26f55 JR |
1928 | del_domain_from_list(&dom->domain); |
1929 | ||
86db2e5d | 1930 | free_pagetable(&dom->domain); |
ec487d1a | 1931 | |
384de729 JR |
1932 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1933 | if (!dom->aperture[i]) | |
1934 | continue; | |
1935 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1936 | kfree(dom->aperture[i]); | |
1937 | } | |
ec487d1a JR |
1938 | |
1939 | kfree(dom); | |
1940 | } | |
1941 | ||
431b2a20 JR |
1942 | /* |
1943 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1944 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1945 | * structures required for the dma_ops interface |
1946 | */ | |
87a64d52 | 1947 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1948 | { |
1949 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1950 | |
1951 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1952 | if (!dma_dom) | |
1953 | return NULL; | |
1954 | ||
1955 | spin_lock_init(&dma_dom->domain.lock); | |
1956 | ||
1957 | dma_dom->domain.id = domain_id_alloc(); | |
1958 | if (dma_dom->domain.id == 0) | |
1959 | goto free_dma_dom; | |
7c392cbe | 1960 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1961 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1962 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1963 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1964 | dma_dom->domain.priv = dma_dom; |
1965 | if (!dma_dom->domain.pt_root) | |
1966 | goto free_dma_dom; | |
ec487d1a | 1967 | |
1c655773 | 1968 | dma_dom->need_flush = false; |
bd60b735 | 1969 | dma_dom->target_dev = 0xffff; |
1c655773 | 1970 | |
aeb26f55 JR |
1971 | add_domain_to_list(&dma_dom->domain); |
1972 | ||
576175c2 | 1973 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1974 | goto free_dma_dom; |
ec487d1a | 1975 | |
431b2a20 | 1976 | /* |
ec487d1a JR |
1977 | * mark the first page as allocated so we never return 0 as |
1978 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1979 | */ |
384de729 | 1980 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1981 | dma_dom->next_address = 0; |
ec487d1a | 1982 | |
ec487d1a JR |
1983 | |
1984 | return dma_dom; | |
1985 | ||
1986 | free_dma_dom: | |
1987 | dma_ops_domain_free(dma_dom); | |
1988 | ||
1989 | return NULL; | |
1990 | } | |
1991 | ||
5b28df6f JR |
1992 | /* |
1993 | * little helper function to check whether a given protection domain is a | |
1994 | * dma_ops domain | |
1995 | */ | |
1996 | static bool dma_ops_domain(struct protection_domain *domain) | |
1997 | { | |
1998 | return domain->flags & PD_DMA_OPS_MASK; | |
1999 | } | |
2000 | ||
fd7b5535 | 2001 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2002 | { |
132bd68f | 2003 | u64 pte_root = 0; |
ee6c2868 | 2004 | u64 flags = 0; |
863c74eb | 2005 | |
132bd68f JR |
2006 | if (domain->mode != PAGE_MODE_NONE) |
2007 | pte_root = virt_to_phys(domain->pt_root); | |
2008 | ||
38ddf41b JR |
2009 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2010 | << DEV_ENTRY_MODE_SHIFT; | |
2011 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2012 | |
ee6c2868 JR |
2013 | flags = amd_iommu_dev_table[devid].data[1]; |
2014 | ||
fd7b5535 JR |
2015 | if (ats) |
2016 | flags |= DTE_FLAG_IOTLB; | |
2017 | ||
52815b75 JR |
2018 | if (domain->flags & PD_IOMMUV2_MASK) { |
2019 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2020 | u64 glx = domain->glx; | |
2021 | u64 tmp; | |
2022 | ||
2023 | pte_root |= DTE_FLAG_GV; | |
2024 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2025 | ||
2026 | /* First mask out possible old values for GCR3 table */ | |
2027 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2028 | flags &= ~tmp; | |
2029 | ||
2030 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2031 | flags &= ~tmp; | |
2032 | ||
2033 | /* Encode GCR3 table into DTE */ | |
2034 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2035 | pte_root |= tmp; | |
2036 | ||
2037 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2038 | flags |= tmp; | |
2039 | ||
2040 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2041 | flags |= tmp; | |
2042 | } | |
2043 | ||
ee6c2868 JR |
2044 | flags &= ~(0xffffUL); |
2045 | flags |= domain->id; | |
2046 | ||
2047 | amd_iommu_dev_table[devid].data[1] = flags; | |
2048 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2049 | } |
2050 | ||
2051 | static void clear_dte_entry(u16 devid) | |
2052 | { | |
15898bbc JR |
2053 | /* remove entry from the device table seen by the hardware */ |
2054 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2055 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2056 | |
2057 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2058 | } |
2059 | ||
ec9e79ef JR |
2060 | static void do_attach(struct iommu_dev_data *dev_data, |
2061 | struct protection_domain *domain) | |
7f760ddd | 2062 | { |
7f760ddd | 2063 | struct amd_iommu *iommu; |
ec9e79ef | 2064 | bool ats; |
fd7b5535 | 2065 | |
ec9e79ef JR |
2066 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2067 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2068 | |
2069 | /* Update data structures */ | |
2070 | dev_data->domain = domain; | |
2071 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2072 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2073 | |
2074 | /* Do reference counting */ | |
2075 | domain->dev_iommu[iommu->index] += 1; | |
2076 | domain->dev_cnt += 1; | |
2077 | ||
2078 | /* Flush the DTE entry */ | |
6c542047 | 2079 | device_flush_dte(dev_data); |
7f760ddd JR |
2080 | } |
2081 | ||
ec9e79ef | 2082 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2083 | { |
7f760ddd | 2084 | struct amd_iommu *iommu; |
7f760ddd | 2085 | |
ec9e79ef | 2086 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2087 | |
2088 | /* decrease reference counters */ | |
7f760ddd JR |
2089 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2090 | dev_data->domain->dev_cnt -= 1; | |
2091 | ||
2092 | /* Update data structures */ | |
2093 | dev_data->domain = NULL; | |
2094 | list_del(&dev_data->list); | |
f62dda66 | 2095 | clear_dte_entry(dev_data->devid); |
15898bbc | 2096 | |
7f760ddd | 2097 | /* Flush the DTE entry */ |
6c542047 | 2098 | device_flush_dte(dev_data); |
2b681faf JR |
2099 | } |
2100 | ||
2101 | /* | |
2102 | * If a device is not yet associated with a domain, this function does | |
2103 | * assigns it visible for the hardware | |
2104 | */ | |
ec9e79ef | 2105 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2106 | struct protection_domain *domain) |
2b681faf | 2107 | { |
84fe6c19 | 2108 | int ret; |
657cbb6b | 2109 | |
2b681faf JR |
2110 | /* lock domain */ |
2111 | spin_lock(&domain->lock); | |
2112 | ||
71f77580 JR |
2113 | if (dev_data->alias_data != NULL) { |
2114 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 2115 | |
2b02b091 JR |
2116 | /* Some sanity checks */ |
2117 | ret = -EBUSY; | |
2118 | if (alias_data->domain != NULL && | |
2119 | alias_data->domain != domain) | |
2120 | goto out_unlock; | |
eba6ac60 | 2121 | |
2b02b091 JR |
2122 | if (dev_data->domain != NULL && |
2123 | dev_data->domain != domain) | |
2124 | goto out_unlock; | |
15898bbc | 2125 | |
2b02b091 | 2126 | /* Do real assignment */ |
7f760ddd | 2127 | if (alias_data->domain == NULL) |
ec9e79ef | 2128 | do_attach(alias_data, domain); |
24100055 JR |
2129 | |
2130 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2131 | } |
15898bbc | 2132 | |
7f760ddd | 2133 | if (dev_data->domain == NULL) |
ec9e79ef | 2134 | do_attach(dev_data, domain); |
eba6ac60 | 2135 | |
24100055 JR |
2136 | atomic_inc(&dev_data->bind); |
2137 | ||
84fe6c19 JL |
2138 | ret = 0; |
2139 | ||
2140 | out_unlock: | |
2141 | ||
eba6ac60 JR |
2142 | /* ready */ |
2143 | spin_unlock(&domain->lock); | |
15898bbc | 2144 | |
84fe6c19 | 2145 | return ret; |
0feae533 | 2146 | } |
b20ac0d4 | 2147 | |
52815b75 JR |
2148 | |
2149 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2150 | { | |
2151 | pci_disable_ats(pdev); | |
2152 | pci_disable_pri(pdev); | |
2153 | pci_disable_pasid(pdev); | |
2154 | } | |
2155 | ||
6a113ddc JR |
2156 | /* FIXME: Change generic reset-function to do the same */ |
2157 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2158 | { | |
2159 | u16 control; | |
2160 | int pos; | |
2161 | ||
46277b75 | 2162 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2163 | if (!pos) |
2164 | return -EINVAL; | |
2165 | ||
46277b75 JR |
2166 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2167 | control |= PCI_PRI_CTRL_RESET; | |
2168 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2169 | |
2170 | return 0; | |
2171 | } | |
2172 | ||
52815b75 JR |
2173 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2174 | { | |
6a113ddc JR |
2175 | bool reset_enable; |
2176 | int reqs, ret; | |
2177 | ||
2178 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2179 | reqs = 32; | |
2180 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2181 | reqs = 1; | |
2182 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2183 | |
2184 | /* Only allow access to user-accessible pages */ | |
2185 | ret = pci_enable_pasid(pdev, 0); | |
2186 | if (ret) | |
2187 | goto out_err; | |
2188 | ||
2189 | /* First reset the PRI state of the device */ | |
2190 | ret = pci_reset_pri(pdev); | |
2191 | if (ret) | |
2192 | goto out_err; | |
2193 | ||
6a113ddc JR |
2194 | /* Enable PRI */ |
2195 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2196 | if (ret) |
2197 | goto out_err; | |
2198 | ||
6a113ddc JR |
2199 | if (reset_enable) { |
2200 | ret = pri_reset_while_enabled(pdev); | |
2201 | if (ret) | |
2202 | goto out_err; | |
2203 | } | |
2204 | ||
52815b75 JR |
2205 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2206 | if (ret) | |
2207 | goto out_err; | |
2208 | ||
2209 | return 0; | |
2210 | ||
2211 | out_err: | |
2212 | pci_disable_pri(pdev); | |
2213 | pci_disable_pasid(pdev); | |
2214 | ||
2215 | return ret; | |
2216 | } | |
2217 | ||
c99afa25 | 2218 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2219 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2220 | |
98f1ad25 | 2221 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2222 | { |
a3b93121 | 2223 | u16 status; |
c99afa25 JR |
2224 | int pos; |
2225 | ||
46277b75 | 2226 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2227 | if (!pos) |
2228 | return false; | |
2229 | ||
a3b93121 | 2230 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2231 | |
a3b93121 | 2232 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2233 | } |
2234 | ||
407d733e | 2235 | /* |
df805abb | 2236 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2237 | * assigns it visible for the hardware |
2238 | */ | |
15898bbc JR |
2239 | static int attach_device(struct device *dev, |
2240 | struct protection_domain *domain) | |
0feae533 | 2241 | { |
fd7b5535 | 2242 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2243 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2244 | unsigned long flags; |
15898bbc | 2245 | int ret; |
eba6ac60 | 2246 | |
ea61cddb JR |
2247 | dev_data = get_dev_data(dev); |
2248 | ||
52815b75 JR |
2249 | if (domain->flags & PD_IOMMUV2_MASK) { |
2250 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2251 | return -EINVAL; | |
2252 | ||
2253 | if (pdev_iommuv2_enable(pdev) != 0) | |
2254 | return -EINVAL; | |
2255 | ||
2256 | dev_data->ats.enabled = true; | |
2257 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2258 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2259 | } else if (amd_iommu_iotlb_sup && |
2260 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2261 | dev_data->ats.enabled = true; |
2262 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2263 | } | |
fd7b5535 | 2264 | |
eba6ac60 | 2265 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2266 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2267 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2268 | ||
0feae533 JR |
2269 | /* |
2270 | * We might boot into a crash-kernel here. The crashed kernel | |
2271 | * left the caches in the IOMMU dirty. So we have to flush | |
2272 | * here to evict all dirty stuff. | |
2273 | */ | |
17b124bf | 2274 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2275 | |
2276 | return ret; | |
b20ac0d4 JR |
2277 | } |
2278 | ||
355bf553 JR |
2279 | /* |
2280 | * Removes a device from a protection domain (unlocked) | |
2281 | */ | |
ec9e79ef | 2282 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2283 | { |
2ca76279 | 2284 | struct protection_domain *domain; |
7c392cbe | 2285 | unsigned long flags; |
c4596114 | 2286 | |
7f760ddd | 2287 | BUG_ON(!dev_data->domain); |
355bf553 | 2288 | |
2ca76279 JR |
2289 | domain = dev_data->domain; |
2290 | ||
2291 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2292 | |
71f77580 JR |
2293 | if (dev_data->alias_data != NULL) { |
2294 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2295 | ||
7f760ddd | 2296 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2297 | do_detach(alias_data); |
24100055 JR |
2298 | } |
2299 | ||
7f760ddd | 2300 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2301 | do_detach(dev_data); |
7f760ddd | 2302 | |
2ca76279 | 2303 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2304 | |
2305 | /* | |
2306 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2307 | * passthrough domain if it is detached from any other domain. |
2308 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2309 | */ |
5abcdba4 | 2310 | if (dev_data->passthrough && |
d3ad9373 | 2311 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2312 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2313 | } |
2314 | ||
2315 | /* | |
2316 | * Removes a device from a protection domain (with devtable_lock held) | |
2317 | */ | |
15898bbc | 2318 | static void detach_device(struct device *dev) |
355bf553 | 2319 | { |
52815b75 | 2320 | struct protection_domain *domain; |
ea61cddb | 2321 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2322 | unsigned long flags; |
2323 | ||
ec9e79ef | 2324 | dev_data = get_dev_data(dev); |
52815b75 | 2325 | domain = dev_data->domain; |
ec9e79ef | 2326 | |
355bf553 JR |
2327 | /* lock device table */ |
2328 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2329 | __detach_device(dev_data); |
355bf553 | 2330 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2331 | |
52815b75 JR |
2332 | if (domain->flags & PD_IOMMUV2_MASK) |
2333 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2334 | else if (dev_data->ats.enabled) | |
ea61cddb | 2335 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2336 | |
2337 | dev_data->ats.enabled = false; | |
355bf553 | 2338 | } |
e275a2a0 | 2339 | |
15898bbc JR |
2340 | /* |
2341 | * Find out the protection domain structure for a given PCI device. This | |
2342 | * will give us the pointer to the page table root for example. | |
2343 | */ | |
2344 | static struct protection_domain *domain_for_device(struct device *dev) | |
2345 | { | |
71f77580 | 2346 | struct iommu_dev_data *dev_data; |
2b02b091 | 2347 | struct protection_domain *dom = NULL; |
15898bbc | 2348 | unsigned long flags; |
15898bbc | 2349 | |
657cbb6b | 2350 | dev_data = get_dev_data(dev); |
15898bbc | 2351 | |
2b02b091 JR |
2352 | if (dev_data->domain) |
2353 | return dev_data->domain; | |
15898bbc | 2354 | |
71f77580 JR |
2355 | if (dev_data->alias_data != NULL) { |
2356 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2357 | |
2358 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2359 | if (alias_data->domain != NULL) { | |
2360 | __attach_device(dev_data, alias_data->domain); | |
2361 | dom = alias_data->domain; | |
2362 | } | |
2363 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2364 | } | |
15898bbc JR |
2365 | |
2366 | return dom; | |
2367 | } | |
2368 | ||
e275a2a0 JR |
2369 | static int device_change_notifier(struct notifier_block *nb, |
2370 | unsigned long action, void *data) | |
2371 | { | |
e275a2a0 | 2372 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2373 | struct protection_domain *domain; |
2374 | struct iommu_dev_data *dev_data; | |
2375 | struct device *dev = data; | |
e275a2a0 | 2376 | struct amd_iommu *iommu; |
1ac4cbbc | 2377 | unsigned long flags; |
5abcdba4 | 2378 | u16 devid; |
e275a2a0 | 2379 | |
98fc5a69 JR |
2380 | if (!check_device(dev)) |
2381 | return 0; | |
e275a2a0 | 2382 | |
5abcdba4 JR |
2383 | devid = get_device_id(dev); |
2384 | iommu = amd_iommu_rlookup_table[devid]; | |
2385 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2386 | |
2387 | switch (action) { | |
c1eee67b | 2388 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2389 | |
2390 | domain = domain_for_device(dev); | |
2391 | ||
e275a2a0 JR |
2392 | if (!domain) |
2393 | goto out; | |
5abcdba4 | 2394 | if (dev_data->passthrough) |
a1ca331c | 2395 | break; |
15898bbc | 2396 | detach_device(dev); |
1ac4cbbc JR |
2397 | break; |
2398 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2399 | |
2400 | iommu_init_device(dev); | |
2401 | ||
2c9195e9 JR |
2402 | /* |
2403 | * dev_data is still NULL and | |
2404 | * got initialized in iommu_init_device | |
2405 | */ | |
2406 | dev_data = get_dev_data(dev); | |
2407 | ||
2408 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2409 | dev_data->passthrough = true; | |
2410 | attach_device(dev, pt_domain); | |
2411 | break; | |
2412 | } | |
2413 | ||
657cbb6b JR |
2414 | domain = domain_for_device(dev); |
2415 | ||
1ac4cbbc JR |
2416 | /* allocate a protection domain if a device is added */ |
2417 | dma_domain = find_protection_domain(devid); | |
2418 | if (dma_domain) | |
2419 | goto out; | |
87a64d52 | 2420 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
2421 | if (!dma_domain) |
2422 | goto out; | |
2423 | dma_domain->target_dev = devid; | |
2424 | ||
2425 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2426 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2427 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2428 | ||
ac1534a5 JR |
2429 | dev_data = get_dev_data(dev); |
2430 | ||
2c9195e9 | 2431 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2432 | |
e275a2a0 | 2433 | break; |
657cbb6b JR |
2434 | case BUS_NOTIFY_DEL_DEVICE: |
2435 | ||
2436 | iommu_uninit_device(dev); | |
2437 | ||
e275a2a0 JR |
2438 | default: |
2439 | goto out; | |
2440 | } | |
2441 | ||
e275a2a0 JR |
2442 | iommu_completion_wait(iommu); |
2443 | ||
2444 | out: | |
2445 | return 0; | |
2446 | } | |
2447 | ||
b25ae679 | 2448 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2449 | .notifier_call = device_change_notifier, |
2450 | }; | |
355bf553 | 2451 | |
8638c491 JR |
2452 | void amd_iommu_init_notifier(void) |
2453 | { | |
2454 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2455 | } | |
2456 | ||
431b2a20 JR |
2457 | /***************************************************************************** |
2458 | * | |
2459 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2460 | * | |
2461 | *****************************************************************************/ | |
2462 | ||
2463 | /* | |
2464 | * In the dma_ops path we only have the struct device. This function | |
2465 | * finds the corresponding IOMMU, the protection domain and the | |
2466 | * requestor id for a given device. | |
2467 | * If the device is not yet associated with a domain this is also done | |
2468 | * in this function. | |
2469 | */ | |
94f6d190 | 2470 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2471 | { |
94f6d190 | 2472 | struct protection_domain *domain; |
b20ac0d4 | 2473 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2474 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2475 | |
f99c0f1c | 2476 | if (!check_device(dev)) |
94f6d190 | 2477 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2478 | |
94f6d190 JR |
2479 | domain = domain_for_device(dev); |
2480 | if (domain != NULL && !dma_ops_domain(domain)) | |
2481 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2482 | |
94f6d190 JR |
2483 | if (domain != NULL) |
2484 | return domain; | |
b20ac0d4 | 2485 | |
df805abb | 2486 | /* Device not bound yet - bind it */ |
94f6d190 | 2487 | dma_dom = find_protection_domain(devid); |
15898bbc | 2488 | if (!dma_dom) |
94f6d190 JR |
2489 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2490 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2491 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2492 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2493 | |
94f6d190 | 2494 | return &dma_dom->domain; |
b20ac0d4 JR |
2495 | } |
2496 | ||
04bfdd84 JR |
2497 | static void update_device_table(struct protection_domain *domain) |
2498 | { | |
492667da | 2499 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2500 | |
ea61cddb JR |
2501 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2502 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2503 | } |
2504 | ||
2505 | static void update_domain(struct protection_domain *domain) | |
2506 | { | |
2507 | if (!domain->updated) | |
2508 | return; | |
2509 | ||
2510 | update_device_table(domain); | |
17b124bf JR |
2511 | |
2512 | domain_flush_devices(domain); | |
2513 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2514 | |
2515 | domain->updated = false; | |
2516 | } | |
2517 | ||
8bda3092 JR |
2518 | /* |
2519 | * This function fetches the PTE for a given address in the aperture | |
2520 | */ | |
2521 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2522 | unsigned long address) | |
2523 | { | |
384de729 | 2524 | struct aperture_range *aperture; |
8bda3092 JR |
2525 | u64 *pte, *pte_page; |
2526 | ||
384de729 JR |
2527 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2528 | if (!aperture) | |
2529 | return NULL; | |
2530 | ||
2531 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2532 | if (!pte) { |
cbb9d729 | 2533 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2534 | GFP_ATOMIC); |
384de729 JR |
2535 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2536 | } else | |
8c8c143c | 2537 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2538 | |
04bfdd84 | 2539 | update_domain(&dom->domain); |
8bda3092 JR |
2540 | |
2541 | return pte; | |
2542 | } | |
2543 | ||
431b2a20 JR |
2544 | /* |
2545 | * This is the generic map function. It maps one 4kb page at paddr to | |
2546 | * the given address in the DMA address space for the domain. | |
2547 | */ | |
680525e0 | 2548 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2549 | unsigned long address, |
2550 | phys_addr_t paddr, | |
2551 | int direction) | |
2552 | { | |
2553 | u64 *pte, __pte; | |
2554 | ||
2555 | WARN_ON(address > dom->aperture_size); | |
2556 | ||
2557 | paddr &= PAGE_MASK; | |
2558 | ||
8bda3092 | 2559 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2560 | if (!pte) |
8fd524b3 | 2561 | return DMA_ERROR_CODE; |
cb76c322 JR |
2562 | |
2563 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2564 | ||
2565 | if (direction == DMA_TO_DEVICE) | |
2566 | __pte |= IOMMU_PTE_IR; | |
2567 | else if (direction == DMA_FROM_DEVICE) | |
2568 | __pte |= IOMMU_PTE_IW; | |
2569 | else if (direction == DMA_BIDIRECTIONAL) | |
2570 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2571 | ||
2572 | WARN_ON(*pte); | |
2573 | ||
2574 | *pte = __pte; | |
2575 | ||
2576 | return (dma_addr_t)address; | |
2577 | } | |
2578 | ||
431b2a20 JR |
2579 | /* |
2580 | * The generic unmapping function for on page in the DMA address space. | |
2581 | */ | |
680525e0 | 2582 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2583 | unsigned long address) |
2584 | { | |
384de729 | 2585 | struct aperture_range *aperture; |
cb76c322 JR |
2586 | u64 *pte; |
2587 | ||
2588 | if (address >= dom->aperture_size) | |
2589 | return; | |
2590 | ||
384de729 JR |
2591 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2592 | if (!aperture) | |
2593 | return; | |
2594 | ||
2595 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2596 | if (!pte) | |
2597 | return; | |
cb76c322 | 2598 | |
8c8c143c | 2599 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2600 | |
2601 | WARN_ON(!*pte); | |
2602 | ||
2603 | *pte = 0ULL; | |
2604 | } | |
2605 | ||
431b2a20 JR |
2606 | /* |
2607 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2608 | * contiguous memory region into DMA address space. It is used by all |
2609 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2610 | * Must be called with the domain lock held. |
2611 | */ | |
cb76c322 | 2612 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2613 | struct dma_ops_domain *dma_dom, |
2614 | phys_addr_t paddr, | |
2615 | size_t size, | |
6d4f343f | 2616 | int dir, |
832a90c3 JR |
2617 | bool align, |
2618 | u64 dma_mask) | |
cb76c322 JR |
2619 | { |
2620 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2621 | dma_addr_t address, start, ret; |
cb76c322 | 2622 | unsigned int pages; |
6d4f343f | 2623 | unsigned long align_mask = 0; |
cb76c322 JR |
2624 | int i; |
2625 | ||
e3c449f5 | 2626 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2627 | paddr &= PAGE_MASK; |
2628 | ||
8ecaf8f1 JR |
2629 | INC_STATS_COUNTER(total_map_requests); |
2630 | ||
c1858976 JR |
2631 | if (pages > 1) |
2632 | INC_STATS_COUNTER(cross_page); | |
2633 | ||
6d4f343f JR |
2634 | if (align) |
2635 | align_mask = (1UL << get_order(size)) - 1; | |
2636 | ||
11b83888 | 2637 | retry: |
832a90c3 JR |
2638 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2639 | dma_mask); | |
8fd524b3 | 2640 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2641 | /* |
2642 | * setting next_address here will let the address | |
2643 | * allocator only scan the new allocated range in the | |
2644 | * first run. This is a small optimization. | |
2645 | */ | |
2646 | dma_dom->next_address = dma_dom->aperture_size; | |
2647 | ||
576175c2 | 2648 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2649 | goto out; |
2650 | ||
2651 | /* | |
af901ca1 | 2652 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2653 | * allocation again |
2654 | */ | |
2655 | goto retry; | |
2656 | } | |
cb76c322 JR |
2657 | |
2658 | start = address; | |
2659 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2660 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2661 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2662 | goto out_unmap; |
2663 | ||
cb76c322 JR |
2664 | paddr += PAGE_SIZE; |
2665 | start += PAGE_SIZE; | |
2666 | } | |
2667 | address += offset; | |
2668 | ||
5774f7c5 JR |
2669 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2670 | ||
afa9fdc2 | 2671 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2672 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2673 | dma_dom->need_flush = false; |
318afd41 | 2674 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2675 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2676 | |
cb76c322 JR |
2677 | out: |
2678 | return address; | |
53812c11 JR |
2679 | |
2680 | out_unmap: | |
2681 | ||
2682 | for (--i; i >= 0; --i) { | |
2683 | start -= PAGE_SIZE; | |
680525e0 | 2684 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2685 | } |
2686 | ||
2687 | dma_ops_free_addresses(dma_dom, address, pages); | |
2688 | ||
8fd524b3 | 2689 | return DMA_ERROR_CODE; |
cb76c322 JR |
2690 | } |
2691 | ||
431b2a20 JR |
2692 | /* |
2693 | * Does the reverse of the __map_single function. Must be called with | |
2694 | * the domain lock held too | |
2695 | */ | |
cd8c82e8 | 2696 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2697 | dma_addr_t dma_addr, |
2698 | size_t size, | |
2699 | int dir) | |
2700 | { | |
04e0463e | 2701 | dma_addr_t flush_addr; |
cb76c322 JR |
2702 | dma_addr_t i, start; |
2703 | unsigned int pages; | |
2704 | ||
8fd524b3 | 2705 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2706 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2707 | return; |
2708 | ||
04e0463e | 2709 | flush_addr = dma_addr; |
e3c449f5 | 2710 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2711 | dma_addr &= PAGE_MASK; |
2712 | start = dma_addr; | |
2713 | ||
2714 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2715 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2716 | start += PAGE_SIZE; |
2717 | } | |
2718 | ||
5774f7c5 JR |
2719 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2720 | ||
cb76c322 | 2721 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2722 | |
80be308d | 2723 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2724 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2725 | dma_dom->need_flush = false; |
2726 | } | |
cb76c322 JR |
2727 | } |
2728 | ||
431b2a20 JR |
2729 | /* |
2730 | * The exported map_single function for dma_ops. | |
2731 | */ | |
51491367 FT |
2732 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2733 | unsigned long offset, size_t size, | |
2734 | enum dma_data_direction dir, | |
2735 | struct dma_attrs *attrs) | |
4da70b9e JR |
2736 | { |
2737 | unsigned long flags; | |
4da70b9e | 2738 | struct protection_domain *domain; |
4da70b9e | 2739 | dma_addr_t addr; |
832a90c3 | 2740 | u64 dma_mask; |
51491367 | 2741 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2742 | |
0f2a86f2 JR |
2743 | INC_STATS_COUNTER(cnt_map_single); |
2744 | ||
94f6d190 JR |
2745 | domain = get_domain(dev); |
2746 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2747 | return (dma_addr_t)paddr; |
94f6d190 JR |
2748 | else if (IS_ERR(domain)) |
2749 | return DMA_ERROR_CODE; | |
4da70b9e | 2750 | |
f99c0f1c JR |
2751 | dma_mask = *dev->dma_mask; |
2752 | ||
4da70b9e | 2753 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2754 | |
cd8c82e8 | 2755 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2756 | dma_mask); |
8fd524b3 | 2757 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2758 | goto out; |
2759 | ||
17b124bf | 2760 | domain_flush_complete(domain); |
4da70b9e JR |
2761 | |
2762 | out: | |
2763 | spin_unlock_irqrestore(&domain->lock, flags); | |
2764 | ||
2765 | return addr; | |
2766 | } | |
2767 | ||
431b2a20 JR |
2768 | /* |
2769 | * The exported unmap_single function for dma_ops. | |
2770 | */ | |
51491367 FT |
2771 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2772 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2773 | { |
2774 | unsigned long flags; | |
4da70b9e | 2775 | struct protection_domain *domain; |
4da70b9e | 2776 | |
146a6917 JR |
2777 | INC_STATS_COUNTER(cnt_unmap_single); |
2778 | ||
94f6d190 JR |
2779 | domain = get_domain(dev); |
2780 | if (IS_ERR(domain)) | |
5b28df6f JR |
2781 | return; |
2782 | ||
4da70b9e JR |
2783 | spin_lock_irqsave(&domain->lock, flags); |
2784 | ||
cd8c82e8 | 2785 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2786 | |
17b124bf | 2787 | domain_flush_complete(domain); |
4da70b9e JR |
2788 | |
2789 | spin_unlock_irqrestore(&domain->lock, flags); | |
2790 | } | |
2791 | ||
431b2a20 JR |
2792 | /* |
2793 | * This is a special map_sg function which is used if we should map a | |
2794 | * device which is not handled by an AMD IOMMU in the system. | |
2795 | */ | |
65b050ad JR |
2796 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2797 | int nelems, int dir) | |
2798 | { | |
2799 | struct scatterlist *s; | |
2800 | int i; | |
2801 | ||
2802 | for_each_sg(sglist, s, nelems, i) { | |
2803 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2804 | s->dma_length = s->length; | |
2805 | } | |
2806 | ||
2807 | return nelems; | |
2808 | } | |
2809 | ||
431b2a20 JR |
2810 | /* |
2811 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2812 | * lists). | |
2813 | */ | |
65b050ad | 2814 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2815 | int nelems, enum dma_data_direction dir, |
2816 | struct dma_attrs *attrs) | |
65b050ad JR |
2817 | { |
2818 | unsigned long flags; | |
65b050ad | 2819 | struct protection_domain *domain; |
65b050ad JR |
2820 | int i; |
2821 | struct scatterlist *s; | |
2822 | phys_addr_t paddr; | |
2823 | int mapped_elems = 0; | |
832a90c3 | 2824 | u64 dma_mask; |
65b050ad | 2825 | |
d03f067a JR |
2826 | INC_STATS_COUNTER(cnt_map_sg); |
2827 | ||
94f6d190 JR |
2828 | domain = get_domain(dev); |
2829 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2830 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2831 | else if (IS_ERR(domain)) |
2832 | return 0; | |
dbcc112e | 2833 | |
832a90c3 | 2834 | dma_mask = *dev->dma_mask; |
65b050ad | 2835 | |
65b050ad JR |
2836 | spin_lock_irqsave(&domain->lock, flags); |
2837 | ||
2838 | for_each_sg(sglist, s, nelems, i) { | |
2839 | paddr = sg_phys(s); | |
2840 | ||
cd8c82e8 | 2841 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2842 | paddr, s->length, dir, false, |
2843 | dma_mask); | |
65b050ad JR |
2844 | |
2845 | if (s->dma_address) { | |
2846 | s->dma_length = s->length; | |
2847 | mapped_elems++; | |
2848 | } else | |
2849 | goto unmap; | |
65b050ad JR |
2850 | } |
2851 | ||
17b124bf | 2852 | domain_flush_complete(domain); |
65b050ad JR |
2853 | |
2854 | out: | |
2855 | spin_unlock_irqrestore(&domain->lock, flags); | |
2856 | ||
2857 | return mapped_elems; | |
2858 | unmap: | |
2859 | for_each_sg(sglist, s, mapped_elems, i) { | |
2860 | if (s->dma_address) | |
cd8c82e8 | 2861 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2862 | s->dma_length, dir); |
2863 | s->dma_address = s->dma_length = 0; | |
2864 | } | |
2865 | ||
2866 | mapped_elems = 0; | |
2867 | ||
2868 | goto out; | |
2869 | } | |
2870 | ||
431b2a20 JR |
2871 | /* |
2872 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2873 | * lists). | |
2874 | */ | |
65b050ad | 2875 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2876 | int nelems, enum dma_data_direction dir, |
2877 | struct dma_attrs *attrs) | |
65b050ad JR |
2878 | { |
2879 | unsigned long flags; | |
65b050ad JR |
2880 | struct protection_domain *domain; |
2881 | struct scatterlist *s; | |
65b050ad JR |
2882 | int i; |
2883 | ||
55877a6b JR |
2884 | INC_STATS_COUNTER(cnt_unmap_sg); |
2885 | ||
94f6d190 JR |
2886 | domain = get_domain(dev); |
2887 | if (IS_ERR(domain)) | |
5b28df6f JR |
2888 | return; |
2889 | ||
65b050ad JR |
2890 | spin_lock_irqsave(&domain->lock, flags); |
2891 | ||
2892 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2893 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2894 | s->dma_length, dir); |
65b050ad JR |
2895 | s->dma_address = s->dma_length = 0; |
2896 | } | |
2897 | ||
17b124bf | 2898 | domain_flush_complete(domain); |
65b050ad JR |
2899 | |
2900 | spin_unlock_irqrestore(&domain->lock, flags); | |
2901 | } | |
2902 | ||
431b2a20 JR |
2903 | /* |
2904 | * The exported alloc_coherent function for dma_ops. | |
2905 | */ | |
5d8b53cf | 2906 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2907 | dma_addr_t *dma_addr, gfp_t flag, |
2908 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2909 | { |
2910 | unsigned long flags; | |
2911 | void *virt_addr; | |
5d8b53cf | 2912 | struct protection_domain *domain; |
5d8b53cf | 2913 | phys_addr_t paddr; |
832a90c3 | 2914 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2915 | |
c8f0fb36 JR |
2916 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2917 | ||
94f6d190 JR |
2918 | domain = get_domain(dev); |
2919 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2920 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2921 | *dma_addr = __pa(virt_addr); | |
2922 | return virt_addr; | |
94f6d190 JR |
2923 | } else if (IS_ERR(domain)) |
2924 | return NULL; | |
5d8b53cf | 2925 | |
f99c0f1c JR |
2926 | dma_mask = dev->coherent_dma_mask; |
2927 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2928 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2929 | |
2930 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2931 | if (!virt_addr) | |
b25ae679 | 2932 | return NULL; |
5d8b53cf | 2933 | |
5d8b53cf JR |
2934 | paddr = virt_to_phys(virt_addr); |
2935 | ||
832a90c3 JR |
2936 | if (!dma_mask) |
2937 | dma_mask = *dev->dma_mask; | |
2938 | ||
5d8b53cf JR |
2939 | spin_lock_irqsave(&domain->lock, flags); |
2940 | ||
cd8c82e8 | 2941 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2942 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2943 | |
8fd524b3 | 2944 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2945 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2946 | goto out_free; |
367d04c4 | 2947 | } |
5d8b53cf | 2948 | |
17b124bf | 2949 | domain_flush_complete(domain); |
5d8b53cf | 2950 | |
5d8b53cf JR |
2951 | spin_unlock_irqrestore(&domain->lock, flags); |
2952 | ||
2953 | return virt_addr; | |
5b28df6f JR |
2954 | |
2955 | out_free: | |
2956 | ||
2957 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2958 | ||
2959 | return NULL; | |
5d8b53cf JR |
2960 | } |
2961 | ||
431b2a20 JR |
2962 | /* |
2963 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2964 | */ |
5d8b53cf | 2965 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2966 | void *virt_addr, dma_addr_t dma_addr, |
2967 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2968 | { |
2969 | unsigned long flags; | |
5d8b53cf | 2970 | struct protection_domain *domain; |
5d8b53cf | 2971 | |
5d31ee7e JR |
2972 | INC_STATS_COUNTER(cnt_free_coherent); |
2973 | ||
94f6d190 JR |
2974 | domain = get_domain(dev); |
2975 | if (IS_ERR(domain)) | |
5b28df6f JR |
2976 | goto free_mem; |
2977 | ||
5d8b53cf JR |
2978 | spin_lock_irqsave(&domain->lock, flags); |
2979 | ||
cd8c82e8 | 2980 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2981 | |
17b124bf | 2982 | domain_flush_complete(domain); |
5d8b53cf JR |
2983 | |
2984 | spin_unlock_irqrestore(&domain->lock, flags); | |
2985 | ||
2986 | free_mem: | |
2987 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2988 | } | |
2989 | ||
b39ba6ad JR |
2990 | /* |
2991 | * This function is called by the DMA layer to find out if we can handle a | |
2992 | * particular device. It is part of the dma_ops. | |
2993 | */ | |
2994 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2995 | { | |
420aef8a | 2996 | return check_device(dev); |
b39ba6ad JR |
2997 | } |
2998 | ||
c432f3df | 2999 | /* |
431b2a20 JR |
3000 | * The function for pre-allocating protection domains. |
3001 | * | |
c432f3df JR |
3002 | * If the driver core informs the DMA layer if a driver grabs a device |
3003 | * we don't need to preallocate the protection domains anymore. | |
3004 | * For now we have to. | |
3005 | */ | |
943bc7e1 | 3006 | static void __init prealloc_protection_domains(void) |
c432f3df | 3007 | { |
5abcdba4 | 3008 | struct iommu_dev_data *dev_data; |
c432f3df | 3009 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3010 | struct pci_dev *dev = NULL; |
98fc5a69 | 3011 | u16 devid; |
c432f3df | 3012 | |
d18c69d3 | 3013 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3014 | |
3015 | /* Do we handle this device? */ | |
3016 | if (!check_device(&dev->dev)) | |
c432f3df | 3017 | continue; |
98fc5a69 | 3018 | |
5abcdba4 JR |
3019 | dev_data = get_dev_data(&dev->dev); |
3020 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3021 | /* Make sure passthrough domain is allocated */ | |
3022 | alloc_passthrough_domain(); | |
3023 | dev_data->passthrough = true; | |
3024 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3025 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3026 | dev_name(&dev->dev)); |
3027 | } | |
3028 | ||
98fc5a69 | 3029 | /* Is there already any domain for it? */ |
15898bbc | 3030 | if (domain_for_device(&dev->dev)) |
c432f3df | 3031 | continue; |
98fc5a69 JR |
3032 | |
3033 | devid = get_device_id(&dev->dev); | |
3034 | ||
87a64d52 | 3035 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3036 | if (!dma_dom) |
3037 | continue; | |
3038 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3039 | dma_dom->target_dev = devid; |
3040 | ||
15898bbc | 3041 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3042 | |
bd60b735 | 3043 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3044 | } |
3045 | } | |
3046 | ||
160c1d8e | 3047 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3048 | .alloc = alloc_coherent, |
3049 | .free = free_coherent, | |
51491367 FT |
3050 | .map_page = map_page, |
3051 | .unmap_page = unmap_page, | |
6631ee9d JR |
3052 | .map_sg = map_sg, |
3053 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3054 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3055 | }; |
3056 | ||
27c2127a JR |
3057 | static unsigned device_dma_ops_init(void) |
3058 | { | |
5abcdba4 | 3059 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3060 | struct pci_dev *pdev = NULL; |
3061 | unsigned unhandled = 0; | |
3062 | ||
3063 | for_each_pci_dev(pdev) { | |
3064 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3065 | |
3066 | iommu_ignore_device(&pdev->dev); | |
3067 | ||
27c2127a JR |
3068 | unhandled += 1; |
3069 | continue; | |
3070 | } | |
3071 | ||
5abcdba4 JR |
3072 | dev_data = get_dev_data(&pdev->dev); |
3073 | ||
3074 | if (!dev_data->passthrough) | |
3075 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3076 | else | |
3077 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3078 | } |
3079 | ||
3080 | return unhandled; | |
3081 | } | |
3082 | ||
431b2a20 JR |
3083 | /* |
3084 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3085 | */ | |
f5325094 JR |
3086 | |
3087 | void __init amd_iommu_init_api(void) | |
3088 | { | |
2cc21c42 | 3089 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3090 | } |
3091 | ||
6631ee9d JR |
3092 | int __init amd_iommu_init_dma_ops(void) |
3093 | { | |
3094 | struct amd_iommu *iommu; | |
27c2127a | 3095 | int ret, unhandled; |
6631ee9d | 3096 | |
431b2a20 JR |
3097 | /* |
3098 | * first allocate a default protection domain for every IOMMU we | |
3099 | * found in the system. Devices not assigned to any other | |
3100 | * protection domain will be assigned to the default one. | |
3101 | */ | |
3bd22172 | 3102 | for_each_iommu(iommu) { |
87a64d52 | 3103 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3104 | if (iommu->default_dom == NULL) |
3105 | return -ENOMEM; | |
e2dc14a2 | 3106 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3107 | ret = iommu_init_unity_mappings(iommu); |
3108 | if (ret) | |
3109 | goto free_domains; | |
3110 | } | |
3111 | ||
431b2a20 | 3112 | /* |
8793abeb | 3113 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3114 | */ |
8793abeb | 3115 | prealloc_protection_domains(); |
6631ee9d JR |
3116 | |
3117 | iommu_detected = 1; | |
75f1cdf1 | 3118 | swiotlb = 0; |
6631ee9d | 3119 | |
431b2a20 | 3120 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3121 | unhandled = device_dma_ops_init(); |
3122 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3123 | /* There are unhandled devices - initialize swiotlb for them */ | |
3124 | swiotlb = 1; | |
3125 | } | |
6631ee9d | 3126 | |
7f26508b JR |
3127 | amd_iommu_stats_init(); |
3128 | ||
62410eeb JR |
3129 | if (amd_iommu_unmap_flush) |
3130 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3131 | else | |
3132 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3133 | ||
6631ee9d JR |
3134 | return 0; |
3135 | ||
3136 | free_domains: | |
3137 | ||
3bd22172 | 3138 | for_each_iommu(iommu) { |
6631ee9d JR |
3139 | if (iommu->default_dom) |
3140 | dma_ops_domain_free(iommu->default_dom); | |
3141 | } | |
3142 | ||
3143 | return ret; | |
3144 | } | |
6d98cd80 JR |
3145 | |
3146 | /***************************************************************************** | |
3147 | * | |
3148 | * The following functions belong to the exported interface of AMD IOMMU | |
3149 | * | |
3150 | * This interface allows access to lower level functions of the IOMMU | |
3151 | * like protection domain handling and assignement of devices to domains | |
3152 | * which is not possible with the dma_ops interface. | |
3153 | * | |
3154 | *****************************************************************************/ | |
3155 | ||
6d98cd80 JR |
3156 | static void cleanup_domain(struct protection_domain *domain) |
3157 | { | |
492667da | 3158 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 3159 | unsigned long flags; |
6d98cd80 JR |
3160 | |
3161 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3162 | ||
492667da | 3163 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 3164 | __detach_device(dev_data); |
492667da JR |
3165 | atomic_set(&dev_data->bind, 0); |
3166 | } | |
6d98cd80 JR |
3167 | |
3168 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3169 | } | |
3170 | ||
2650815f JR |
3171 | static void protection_domain_free(struct protection_domain *domain) |
3172 | { | |
3173 | if (!domain) | |
3174 | return; | |
3175 | ||
aeb26f55 JR |
3176 | del_domain_from_list(domain); |
3177 | ||
2650815f JR |
3178 | if (domain->id) |
3179 | domain_id_free(domain->id); | |
3180 | ||
3181 | kfree(domain); | |
3182 | } | |
3183 | ||
3184 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3185 | { |
3186 | struct protection_domain *domain; | |
3187 | ||
3188 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3189 | if (!domain) | |
2650815f | 3190 | return NULL; |
c156e347 JR |
3191 | |
3192 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3193 | mutex_init(&domain->api_lock); |
c156e347 JR |
3194 | domain->id = domain_id_alloc(); |
3195 | if (!domain->id) | |
2650815f | 3196 | goto out_err; |
7c392cbe | 3197 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3198 | |
aeb26f55 JR |
3199 | add_domain_to_list(domain); |
3200 | ||
2650815f JR |
3201 | return domain; |
3202 | ||
3203 | out_err: | |
3204 | kfree(domain); | |
3205 | ||
3206 | return NULL; | |
3207 | } | |
3208 | ||
5abcdba4 JR |
3209 | static int __init alloc_passthrough_domain(void) |
3210 | { | |
3211 | if (pt_domain != NULL) | |
3212 | return 0; | |
3213 | ||
3214 | /* allocate passthrough domain */ | |
3215 | pt_domain = protection_domain_alloc(); | |
3216 | if (!pt_domain) | |
3217 | return -ENOMEM; | |
3218 | ||
3219 | pt_domain->mode = PAGE_MODE_NONE; | |
3220 | ||
3221 | return 0; | |
3222 | } | |
2650815f JR |
3223 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3224 | { | |
3225 | struct protection_domain *domain; | |
3226 | ||
3227 | domain = protection_domain_alloc(); | |
3228 | if (!domain) | |
c156e347 | 3229 | goto out_free; |
2650815f JR |
3230 | |
3231 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3232 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3233 | if (!domain->pt_root) | |
3234 | goto out_free; | |
3235 | ||
f3572db8 JR |
3236 | domain->iommu_domain = dom; |
3237 | ||
c156e347 JR |
3238 | dom->priv = domain; |
3239 | ||
0ff64f80 JR |
3240 | dom->geometry.aperture_start = 0; |
3241 | dom->geometry.aperture_end = ~0ULL; | |
3242 | dom->geometry.force_aperture = true; | |
3243 | ||
c156e347 JR |
3244 | return 0; |
3245 | ||
3246 | out_free: | |
2650815f | 3247 | protection_domain_free(domain); |
c156e347 JR |
3248 | |
3249 | return -ENOMEM; | |
3250 | } | |
3251 | ||
98383fc3 JR |
3252 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3253 | { | |
3254 | struct protection_domain *domain = dom->priv; | |
3255 | ||
3256 | if (!domain) | |
3257 | return; | |
3258 | ||
3259 | if (domain->dev_cnt > 0) | |
3260 | cleanup_domain(domain); | |
3261 | ||
3262 | BUG_ON(domain->dev_cnt != 0); | |
3263 | ||
132bd68f JR |
3264 | if (domain->mode != PAGE_MODE_NONE) |
3265 | free_pagetable(domain); | |
98383fc3 | 3266 | |
52815b75 JR |
3267 | if (domain->flags & PD_IOMMUV2_MASK) |
3268 | free_gcr3_table(domain); | |
3269 | ||
8b408fe4 | 3270 | protection_domain_free(domain); |
98383fc3 JR |
3271 | |
3272 | dom->priv = NULL; | |
3273 | } | |
3274 | ||
684f2888 JR |
3275 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3276 | struct device *dev) | |
3277 | { | |
657cbb6b | 3278 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3279 | struct amd_iommu *iommu; |
684f2888 JR |
3280 | u16 devid; |
3281 | ||
98fc5a69 | 3282 | if (!check_device(dev)) |
684f2888 JR |
3283 | return; |
3284 | ||
98fc5a69 | 3285 | devid = get_device_id(dev); |
684f2888 | 3286 | |
657cbb6b | 3287 | if (dev_data->domain != NULL) |
15898bbc | 3288 | detach_device(dev); |
684f2888 JR |
3289 | |
3290 | iommu = amd_iommu_rlookup_table[devid]; | |
3291 | if (!iommu) | |
3292 | return; | |
3293 | ||
684f2888 JR |
3294 | iommu_completion_wait(iommu); |
3295 | } | |
3296 | ||
01106066 JR |
3297 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3298 | struct device *dev) | |
3299 | { | |
3300 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3301 | struct iommu_dev_data *dev_data; |
01106066 | 3302 | struct amd_iommu *iommu; |
15898bbc | 3303 | int ret; |
01106066 | 3304 | |
98fc5a69 | 3305 | if (!check_device(dev)) |
01106066 JR |
3306 | return -EINVAL; |
3307 | ||
657cbb6b JR |
3308 | dev_data = dev->archdata.iommu; |
3309 | ||
f62dda66 | 3310 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3311 | if (!iommu) |
3312 | return -EINVAL; | |
3313 | ||
657cbb6b | 3314 | if (dev_data->domain) |
15898bbc | 3315 | detach_device(dev); |
01106066 | 3316 | |
15898bbc | 3317 | ret = attach_device(dev, domain); |
01106066 JR |
3318 | |
3319 | iommu_completion_wait(iommu); | |
3320 | ||
15898bbc | 3321 | return ret; |
01106066 JR |
3322 | } |
3323 | ||
468e2366 | 3324 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3325 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3326 | { |
3327 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3328 | int prot = 0; |
3329 | int ret; | |
3330 | ||
132bd68f JR |
3331 | if (domain->mode == PAGE_MODE_NONE) |
3332 | return -EINVAL; | |
3333 | ||
c6229ca6 JR |
3334 | if (iommu_prot & IOMMU_READ) |
3335 | prot |= IOMMU_PROT_IR; | |
3336 | if (iommu_prot & IOMMU_WRITE) | |
3337 | prot |= IOMMU_PROT_IW; | |
3338 | ||
5d214fe6 | 3339 | mutex_lock(&domain->api_lock); |
795e74f7 | 3340 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3341 | mutex_unlock(&domain->api_lock); |
3342 | ||
795e74f7 | 3343 | return ret; |
c6229ca6 JR |
3344 | } |
3345 | ||
5009065d OBC |
3346 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3347 | size_t page_size) | |
eb74ff6c | 3348 | { |
eb74ff6c | 3349 | struct protection_domain *domain = dom->priv; |
5009065d | 3350 | size_t unmap_size; |
eb74ff6c | 3351 | |
132bd68f JR |
3352 | if (domain->mode == PAGE_MODE_NONE) |
3353 | return -EINVAL; | |
3354 | ||
5d214fe6 | 3355 | mutex_lock(&domain->api_lock); |
468e2366 | 3356 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3357 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3358 | |
17b124bf | 3359 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3360 | |
5009065d | 3361 | return unmap_size; |
eb74ff6c JR |
3362 | } |
3363 | ||
645c4c8d JR |
3364 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
3365 | unsigned long iova) | |
3366 | { | |
3367 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3368 | unsigned long offset_mask; |
645c4c8d | 3369 | phys_addr_t paddr; |
f03152bb | 3370 | u64 *pte, __pte; |
645c4c8d | 3371 | |
132bd68f JR |
3372 | if (domain->mode == PAGE_MODE_NONE) |
3373 | return iova; | |
3374 | ||
24cd7723 | 3375 | pte = fetch_pte(domain, iova); |
645c4c8d | 3376 | |
a6d41a40 | 3377 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3378 | return 0; |
3379 | ||
f03152bb JR |
3380 | if (PM_PTE_LEVEL(*pte) == 0) |
3381 | offset_mask = PAGE_SIZE - 1; | |
3382 | else | |
3383 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3384 | ||
3385 | __pte = *pte & PM_ADDR_MASK; | |
3386 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3387 | |
3388 | return paddr; | |
3389 | } | |
3390 | ||
dbb9fd86 SY |
3391 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3392 | unsigned long cap) | |
3393 | { | |
80a506b8 JR |
3394 | switch (cap) { |
3395 | case IOMMU_CAP_CACHE_COHERENCY: | |
3396 | return 1; | |
bdddadcb JR |
3397 | case IOMMU_CAP_INTR_REMAP: |
3398 | return irq_remapping_enabled; | |
80a506b8 JR |
3399 | } |
3400 | ||
dbb9fd86 SY |
3401 | return 0; |
3402 | } | |
3403 | ||
26961efe JR |
3404 | static struct iommu_ops amd_iommu_ops = { |
3405 | .domain_init = amd_iommu_domain_init, | |
3406 | .domain_destroy = amd_iommu_domain_destroy, | |
3407 | .attach_dev = amd_iommu_attach_device, | |
3408 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3409 | .map = amd_iommu_map, |
3410 | .unmap = amd_iommu_unmap, | |
26961efe | 3411 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3412 | .domain_has_cap = amd_iommu_domain_has_cap, |
aa3de9c0 | 3413 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3414 | }; |
3415 | ||
0feae533 JR |
3416 | /***************************************************************************** |
3417 | * | |
3418 | * The next functions do a basic initialization of IOMMU for pass through | |
3419 | * mode | |
3420 | * | |
3421 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3422 | * DMA-API translation. | |
3423 | * | |
3424 | *****************************************************************************/ | |
3425 | ||
3426 | int __init amd_iommu_init_passthrough(void) | |
3427 | { | |
5abcdba4 | 3428 | struct iommu_dev_data *dev_data; |
0feae533 | 3429 | struct pci_dev *dev = NULL; |
5abcdba4 | 3430 | struct amd_iommu *iommu; |
15898bbc | 3431 | u16 devid; |
5abcdba4 | 3432 | int ret; |
0feae533 | 3433 | |
5abcdba4 JR |
3434 | ret = alloc_passthrough_domain(); |
3435 | if (ret) | |
3436 | return ret; | |
0feae533 | 3437 | |
6c54aabd | 3438 | for_each_pci_dev(dev) { |
98fc5a69 | 3439 | if (!check_device(&dev->dev)) |
0feae533 JR |
3440 | continue; |
3441 | ||
5abcdba4 JR |
3442 | dev_data = get_dev_data(&dev->dev); |
3443 | dev_data->passthrough = true; | |
3444 | ||
98fc5a69 JR |
3445 | devid = get_device_id(&dev->dev); |
3446 | ||
15898bbc | 3447 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3448 | if (!iommu) |
3449 | continue; | |
3450 | ||
15898bbc | 3451 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3452 | } |
3453 | ||
2655d7a2 JR |
3454 | amd_iommu_stats_init(); |
3455 | ||
0feae533 JR |
3456 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3457 | ||
3458 | return 0; | |
3459 | } | |
72e1dcc4 JR |
3460 | |
3461 | /* IOMMUv2 specific functions */ | |
3462 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3463 | { | |
3464 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3465 | } | |
3466 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3467 | ||
3468 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3469 | { | |
3470 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3471 | } | |
3472 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3473 | |
3474 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3475 | { | |
3476 | struct protection_domain *domain = dom->priv; | |
3477 | unsigned long flags; | |
3478 | ||
3479 | spin_lock_irqsave(&domain->lock, flags); | |
3480 | ||
3481 | /* Update data structure */ | |
3482 | domain->mode = PAGE_MODE_NONE; | |
3483 | domain->updated = true; | |
3484 | ||
3485 | /* Make changes visible to IOMMUs */ | |
3486 | update_domain(domain); | |
3487 | ||
3488 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3489 | free_pagetable(domain); | |
3490 | ||
3491 | spin_unlock_irqrestore(&domain->lock, flags); | |
3492 | } | |
3493 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3494 | |
3495 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3496 | { | |
3497 | struct protection_domain *domain = dom->priv; | |
3498 | unsigned long flags; | |
3499 | int levels, ret; | |
3500 | ||
3501 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3502 | return -EINVAL; | |
3503 | ||
3504 | /* Number of GCR3 table levels required */ | |
3505 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3506 | levels += 1; | |
3507 | ||
3508 | if (levels > amd_iommu_max_glx_val) | |
3509 | return -EINVAL; | |
3510 | ||
3511 | spin_lock_irqsave(&domain->lock, flags); | |
3512 | ||
3513 | /* | |
3514 | * Save us all sanity checks whether devices already in the | |
3515 | * domain support IOMMUv2. Just force that the domain has no | |
3516 | * devices attached when it is switched into IOMMUv2 mode. | |
3517 | */ | |
3518 | ret = -EBUSY; | |
3519 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3520 | goto out; | |
3521 | ||
3522 | ret = -ENOMEM; | |
3523 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3524 | if (domain->gcr3_tbl == NULL) | |
3525 | goto out; | |
3526 | ||
3527 | domain->glx = levels; | |
3528 | domain->flags |= PD_IOMMUV2_MASK; | |
3529 | domain->updated = true; | |
3530 | ||
3531 | update_domain(domain); | |
3532 | ||
3533 | ret = 0; | |
3534 | ||
3535 | out: | |
3536 | spin_unlock_irqrestore(&domain->lock, flags); | |
3537 | ||
3538 | return ret; | |
3539 | } | |
3540 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3541 | |
3542 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3543 | u64 address, bool size) | |
3544 | { | |
3545 | struct iommu_dev_data *dev_data; | |
3546 | struct iommu_cmd cmd; | |
3547 | int i, ret; | |
3548 | ||
3549 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3550 | return -EINVAL; | |
3551 | ||
3552 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3553 | ||
3554 | /* | |
3555 | * IOMMU TLB needs to be flushed before Device TLB to | |
3556 | * prevent device TLB refill from IOMMU TLB | |
3557 | */ | |
3558 | for (i = 0; i < amd_iommus_present; ++i) { | |
3559 | if (domain->dev_iommu[i] == 0) | |
3560 | continue; | |
3561 | ||
3562 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3563 | if (ret != 0) | |
3564 | goto out; | |
3565 | } | |
3566 | ||
3567 | /* Wait until IOMMU TLB flushes are complete */ | |
3568 | domain_flush_complete(domain); | |
3569 | ||
3570 | /* Now flush device TLBs */ | |
3571 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3572 | struct amd_iommu *iommu; | |
3573 | int qdep; | |
3574 | ||
3575 | BUG_ON(!dev_data->ats.enabled); | |
3576 | ||
3577 | qdep = dev_data->ats.qdep; | |
3578 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3579 | ||
3580 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3581 | qdep, address, size); | |
3582 | ||
3583 | ret = iommu_queue_command(iommu, &cmd); | |
3584 | if (ret != 0) | |
3585 | goto out; | |
3586 | } | |
3587 | ||
3588 | /* Wait until all device TLBs are flushed */ | |
3589 | domain_flush_complete(domain); | |
3590 | ||
3591 | ret = 0; | |
3592 | ||
3593 | out: | |
3594 | ||
3595 | return ret; | |
3596 | } | |
3597 | ||
3598 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3599 | u64 address) | |
3600 | { | |
399be2f5 JR |
3601 | INC_STATS_COUNTER(invalidate_iotlb); |
3602 | ||
22e266c7 JR |
3603 | return __flush_pasid(domain, pasid, address, false); |
3604 | } | |
3605 | ||
3606 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3607 | u64 address) | |
3608 | { | |
3609 | struct protection_domain *domain = dom->priv; | |
3610 | unsigned long flags; | |
3611 | int ret; | |
3612 | ||
3613 | spin_lock_irqsave(&domain->lock, flags); | |
3614 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3615 | spin_unlock_irqrestore(&domain->lock, flags); | |
3616 | ||
3617 | return ret; | |
3618 | } | |
3619 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3620 | ||
3621 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3622 | { | |
399be2f5 JR |
3623 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3624 | ||
22e266c7 JR |
3625 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3626 | true); | |
3627 | } | |
3628 | ||
3629 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3630 | { | |
3631 | struct protection_domain *domain = dom->priv; | |
3632 | unsigned long flags; | |
3633 | int ret; | |
3634 | ||
3635 | spin_lock_irqsave(&domain->lock, flags); | |
3636 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3637 | spin_unlock_irqrestore(&domain->lock, flags); | |
3638 | ||
3639 | return ret; | |
3640 | } | |
3641 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3642 | ||
b16137b1 JR |
3643 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3644 | { | |
3645 | int index; | |
3646 | u64 *pte; | |
3647 | ||
3648 | while (true) { | |
3649 | ||
3650 | index = (pasid >> (9 * level)) & 0x1ff; | |
3651 | pte = &root[index]; | |
3652 | ||
3653 | if (level == 0) | |
3654 | break; | |
3655 | ||
3656 | if (!(*pte & GCR3_VALID)) { | |
3657 | if (!alloc) | |
3658 | return NULL; | |
3659 | ||
3660 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3661 | if (root == NULL) | |
3662 | return NULL; | |
3663 | ||
3664 | *pte = __pa(root) | GCR3_VALID; | |
3665 | } | |
3666 | ||
3667 | root = __va(*pte & PAGE_MASK); | |
3668 | ||
3669 | level -= 1; | |
3670 | } | |
3671 | ||
3672 | return pte; | |
3673 | } | |
3674 | ||
3675 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3676 | unsigned long cr3) | |
3677 | { | |
3678 | u64 *pte; | |
3679 | ||
3680 | if (domain->mode != PAGE_MODE_NONE) | |
3681 | return -EINVAL; | |
3682 | ||
3683 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3684 | if (pte == NULL) | |
3685 | return -ENOMEM; | |
3686 | ||
3687 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3688 | ||
3689 | return __amd_iommu_flush_tlb(domain, pasid); | |
3690 | } | |
3691 | ||
3692 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3693 | { | |
3694 | u64 *pte; | |
3695 | ||
3696 | if (domain->mode != PAGE_MODE_NONE) | |
3697 | return -EINVAL; | |
3698 | ||
3699 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3700 | if (pte == NULL) | |
3701 | return 0; | |
3702 | ||
3703 | *pte = 0; | |
3704 | ||
3705 | return __amd_iommu_flush_tlb(domain, pasid); | |
3706 | } | |
3707 | ||
3708 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3709 | unsigned long cr3) | |
3710 | { | |
3711 | struct protection_domain *domain = dom->priv; | |
3712 | unsigned long flags; | |
3713 | int ret; | |
3714 | ||
3715 | spin_lock_irqsave(&domain->lock, flags); | |
3716 | ret = __set_gcr3(domain, pasid, cr3); | |
3717 | spin_unlock_irqrestore(&domain->lock, flags); | |
3718 | ||
3719 | return ret; | |
3720 | } | |
3721 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3722 | ||
3723 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3724 | { | |
3725 | struct protection_domain *domain = dom->priv; | |
3726 | unsigned long flags; | |
3727 | int ret; | |
3728 | ||
3729 | spin_lock_irqsave(&domain->lock, flags); | |
3730 | ret = __clear_gcr3(domain, pasid); | |
3731 | spin_unlock_irqrestore(&domain->lock, flags); | |
3732 | ||
3733 | return ret; | |
3734 | } | |
3735 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3736 | |
3737 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3738 | int status, int tag) | |
3739 | { | |
3740 | struct iommu_dev_data *dev_data; | |
3741 | struct amd_iommu *iommu; | |
3742 | struct iommu_cmd cmd; | |
3743 | ||
399be2f5 JR |
3744 | INC_STATS_COUNTER(complete_ppr); |
3745 | ||
c99afa25 JR |
3746 | dev_data = get_dev_data(&pdev->dev); |
3747 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3748 | ||
3749 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3750 | tag, dev_data->pri_tlp); | |
3751 | ||
3752 | return iommu_queue_command(iommu, &cmd); | |
3753 | } | |
3754 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3755 | |
3756 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3757 | { | |
3758 | struct protection_domain *domain; | |
3759 | ||
3760 | domain = get_domain(&pdev->dev); | |
3761 | if (IS_ERR(domain)) | |
3762 | return NULL; | |
3763 | ||
3764 | /* Only return IOMMUv2 domains */ | |
3765 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3766 | return NULL; | |
3767 | ||
3768 | return domain->iommu_domain; | |
3769 | } | |
3770 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3771 | |
3772 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3773 | { | |
3774 | struct iommu_dev_data *dev_data; | |
3775 | ||
3776 | if (!amd_iommu_v2_supported()) | |
3777 | return; | |
3778 | ||
3779 | dev_data = get_dev_data(&pdev->dev); | |
3780 | dev_data->errata |= (1 << erratum); | |
3781 | } | |
3782 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3783 | |
3784 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3785 | struct amd_iommu_device_info *info) | |
3786 | { | |
3787 | int max_pasids; | |
3788 | int pos; | |
3789 | ||
3790 | if (pdev == NULL || info == NULL) | |
3791 | return -EINVAL; | |
3792 | ||
3793 | if (!amd_iommu_v2_supported()) | |
3794 | return -EINVAL; | |
3795 | ||
3796 | memset(info, 0, sizeof(*info)); | |
3797 | ||
3798 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3799 | if (pos) | |
3800 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3801 | ||
3802 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3803 | if (pos) | |
3804 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3805 | ||
3806 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3807 | if (pos) { | |
3808 | int features; | |
3809 | ||
3810 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3811 | max_pasids = min(max_pasids, (1 << 20)); | |
3812 | ||
3813 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3814 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3815 | ||
3816 | features = pci_pasid_features(pdev); | |
3817 | if (features & PCI_PASID_CAP_EXEC) | |
3818 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3819 | if (features & PCI_PASID_CAP_PRIV) | |
3820 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3821 | } | |
3822 | ||
3823 | return 0; | |
3824 | } | |
3825 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3826 | |
3827 | #ifdef CONFIG_IRQ_REMAP | |
3828 | ||
3829 | /***************************************************************************** | |
3830 | * | |
3831 | * Interrupt Remapping Implementation | |
3832 | * | |
3833 | *****************************************************************************/ | |
3834 | ||
3835 | union irte { | |
3836 | u32 val; | |
3837 | struct { | |
3838 | u32 valid : 1, | |
3839 | no_fault : 1, | |
3840 | int_type : 3, | |
3841 | rq_eoi : 1, | |
3842 | dm : 1, | |
3843 | rsvd_1 : 1, | |
3844 | destination : 8, | |
3845 | vector : 8, | |
3846 | rsvd_2 : 8; | |
3847 | } fields; | |
3848 | }; | |
3849 | ||
3850 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3851 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3852 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3853 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3854 | ||
3855 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3856 | { | |
3857 | u64 dte; | |
3858 | ||
3859 | dte = amd_iommu_dev_table[devid].data[2]; | |
3860 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3861 | dte |= virt_to_phys(table->table); | |
3862 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3863 | dte |= DTE_IRQ_TABLE_LEN; | |
3864 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3865 | ||
3866 | amd_iommu_dev_table[devid].data[2] = dte; | |
3867 | } | |
3868 | ||
3869 | #define IRTE_ALLOCATED (~1U) | |
3870 | ||
3871 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3872 | { | |
3873 | struct irq_remap_table *table = NULL; | |
3874 | struct amd_iommu *iommu; | |
3875 | unsigned long flags; | |
3876 | u16 alias; | |
3877 | ||
3878 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3879 | ||
3880 | iommu = amd_iommu_rlookup_table[devid]; | |
3881 | if (!iommu) | |
3882 | goto out_unlock; | |
3883 | ||
3884 | table = irq_lookup_table[devid]; | |
3885 | if (table) | |
3886 | goto out; | |
3887 | ||
3888 | alias = amd_iommu_alias_table[devid]; | |
3889 | table = irq_lookup_table[alias]; | |
3890 | if (table) { | |
3891 | irq_lookup_table[devid] = table; | |
3892 | set_dte_irq_entry(devid, table); | |
3893 | iommu_flush_dte(iommu, devid); | |
3894 | goto out; | |
3895 | } | |
3896 | ||
3897 | /* Nothing there yet, allocate new irq remapping table */ | |
3898 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3899 | if (!table) | |
3900 | goto out; | |
3901 | ||
3902 | if (ioapic) | |
3903 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3904 | table->min_index = 32; | |
3905 | ||
3906 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3907 | if (!table->table) { | |
3908 | kfree(table); | |
821f0f68 | 3909 | table = NULL; |
2b324506 JR |
3910 | goto out; |
3911 | } | |
3912 | ||
3913 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3914 | ||
3915 | if (ioapic) { | |
3916 | int i; | |
3917 | ||
3918 | for (i = 0; i < 32; ++i) | |
3919 | table->table[i] = IRTE_ALLOCATED; | |
3920 | } | |
3921 | ||
3922 | irq_lookup_table[devid] = table; | |
3923 | set_dte_irq_entry(devid, table); | |
3924 | iommu_flush_dte(iommu, devid); | |
3925 | if (devid != alias) { | |
3926 | irq_lookup_table[alias] = table; | |
3927 | set_dte_irq_entry(devid, table); | |
3928 | iommu_flush_dte(iommu, alias); | |
3929 | } | |
3930 | ||
3931 | out: | |
3932 | iommu_completion_wait(iommu); | |
3933 | ||
3934 | out_unlock: | |
3935 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3936 | ||
3937 | return table; | |
3938 | } | |
3939 | ||
3940 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3941 | { | |
3942 | struct irq_remap_table *table; | |
3943 | unsigned long flags; | |
3944 | int index, c; | |
3945 | ||
3946 | table = get_irq_table(devid, false); | |
3947 | if (!table) | |
3948 | return -ENODEV; | |
3949 | ||
3950 | spin_lock_irqsave(&table->lock, flags); | |
3951 | ||
3952 | /* Scan table for free entries */ | |
3953 | for (c = 0, index = table->min_index; | |
3954 | index < MAX_IRQS_PER_TABLE; | |
3955 | ++index) { | |
3956 | if (table->table[index] == 0) | |
3957 | c += 1; | |
3958 | else | |
3959 | c = 0; | |
3960 | ||
3961 | if (c == count) { | |
3962 | struct irq_2_iommu *irte_info; | |
3963 | ||
3964 | for (; c != 0; --c) | |
3965 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3966 | ||
3967 | index -= count - 1; | |
3968 | ||
3969 | irte_info = &cfg->irq_2_iommu; | |
3970 | irte_info->sub_handle = devid; | |
3971 | irte_info->irte_index = index; | |
3972 | irte_info->iommu = (void *)cfg; | |
3973 | ||
3974 | goto out; | |
3975 | } | |
3976 | } | |
3977 | ||
3978 | index = -ENOSPC; | |
3979 | ||
3980 | out: | |
3981 | spin_unlock_irqrestore(&table->lock, flags); | |
3982 | ||
3983 | return index; | |
3984 | } | |
3985 | ||
3986 | static int get_irte(u16 devid, int index, union irte *irte) | |
3987 | { | |
3988 | struct irq_remap_table *table; | |
3989 | unsigned long flags; | |
3990 | ||
3991 | table = get_irq_table(devid, false); | |
3992 | if (!table) | |
3993 | return -ENOMEM; | |
3994 | ||
3995 | spin_lock_irqsave(&table->lock, flags); | |
3996 | irte->val = table->table[index]; | |
3997 | spin_unlock_irqrestore(&table->lock, flags); | |
3998 | ||
3999 | return 0; | |
4000 | } | |
4001 | ||
4002 | static int modify_irte(u16 devid, int index, union irte irte) | |
4003 | { | |
4004 | struct irq_remap_table *table; | |
4005 | struct amd_iommu *iommu; | |
4006 | unsigned long flags; | |
4007 | ||
4008 | iommu = amd_iommu_rlookup_table[devid]; | |
4009 | if (iommu == NULL) | |
4010 | return -EINVAL; | |
4011 | ||
4012 | table = get_irq_table(devid, false); | |
4013 | if (!table) | |
4014 | return -ENOMEM; | |
4015 | ||
4016 | spin_lock_irqsave(&table->lock, flags); | |
4017 | table->table[index] = irte.val; | |
4018 | spin_unlock_irqrestore(&table->lock, flags); | |
4019 | ||
4020 | iommu_flush_irt(iommu, devid); | |
4021 | iommu_completion_wait(iommu); | |
4022 | ||
4023 | return 0; | |
4024 | } | |
4025 | ||
4026 | static void free_irte(u16 devid, int index) | |
4027 | { | |
4028 | struct irq_remap_table *table; | |
4029 | struct amd_iommu *iommu; | |
4030 | unsigned long flags; | |
4031 | ||
4032 | iommu = amd_iommu_rlookup_table[devid]; | |
4033 | if (iommu == NULL) | |
4034 | return; | |
4035 | ||
4036 | table = get_irq_table(devid, false); | |
4037 | if (!table) | |
4038 | return; | |
4039 | ||
4040 | spin_lock_irqsave(&table->lock, flags); | |
4041 | table->table[index] = 0; | |
4042 | spin_unlock_irqrestore(&table->lock, flags); | |
4043 | ||
4044 | iommu_flush_irt(iommu, devid); | |
4045 | iommu_completion_wait(iommu); | |
4046 | } | |
4047 | ||
5527de74 JR |
4048 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4049 | unsigned int destination, int vector, | |
4050 | struct io_apic_irq_attr *attr) | |
4051 | { | |
4052 | struct irq_remap_table *table; | |
4053 | struct irq_2_iommu *irte_info; | |
4054 | struct irq_cfg *cfg; | |
4055 | union irte irte; | |
4056 | int ioapic_id; | |
4057 | int index; | |
4058 | int devid; | |
4059 | int ret; | |
4060 | ||
4061 | cfg = irq_get_chip_data(irq); | |
4062 | if (!cfg) | |
4063 | return -EINVAL; | |
4064 | ||
4065 | irte_info = &cfg->irq_2_iommu; | |
4066 | ioapic_id = mpc_ioapic_id(attr->ioapic); | |
4067 | devid = get_ioapic_devid(ioapic_id); | |
4068 | ||
4069 | if (devid < 0) | |
4070 | return devid; | |
4071 | ||
4072 | table = get_irq_table(devid, true); | |
4073 | if (table == NULL) | |
4074 | return -ENOMEM; | |
4075 | ||
4076 | index = attr->ioapic_pin; | |
4077 | ||
4078 | /* Setup IRQ remapping info */ | |
4079 | irte_info->sub_handle = devid; | |
4080 | irte_info->irte_index = index; | |
4081 | irte_info->iommu = (void *)cfg; | |
4082 | ||
4083 | /* Setup IRTE for IOMMU */ | |
4084 | irte.val = 0; | |
4085 | irte.fields.vector = vector; | |
4086 | irte.fields.int_type = apic->irq_delivery_mode; | |
4087 | irte.fields.destination = destination; | |
4088 | irte.fields.dm = apic->irq_dest_mode; | |
4089 | irte.fields.valid = 1; | |
4090 | ||
4091 | ret = modify_irte(devid, index, irte); | |
4092 | if (ret) | |
4093 | return ret; | |
4094 | ||
4095 | /* Setup IOAPIC entry */ | |
4096 | memset(entry, 0, sizeof(*entry)); | |
4097 | ||
4098 | entry->vector = index; | |
4099 | entry->mask = 0; | |
4100 | entry->trigger = attr->trigger; | |
4101 | entry->polarity = attr->polarity; | |
4102 | ||
4103 | /* | |
4104 | * Mask level triggered irqs. | |
5527de74 JR |
4105 | */ |
4106 | if (attr->trigger) | |
4107 | entry->mask = 1; | |
4108 | ||
4109 | return 0; | |
4110 | } | |
4111 | ||
4112 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4113 | bool force) | |
4114 | { | |
4115 | struct irq_2_iommu *irte_info; | |
4116 | unsigned int dest, irq; | |
4117 | struct irq_cfg *cfg; | |
4118 | union irte irte; | |
4119 | int err; | |
4120 | ||
4121 | if (!config_enabled(CONFIG_SMP)) | |
4122 | return -1; | |
4123 | ||
4124 | cfg = data->chip_data; | |
4125 | irq = data->irq; | |
4126 | irte_info = &cfg->irq_2_iommu; | |
4127 | ||
4128 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4129 | return -EINVAL; | |
4130 | ||
4131 | if (get_irte(irte_info->sub_handle, irte_info->irte_index, &irte)) | |
4132 | return -EBUSY; | |
4133 | ||
4134 | if (assign_irq_vector(irq, cfg, mask)) | |
4135 | return -EBUSY; | |
4136 | ||
4137 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4138 | if (err) { | |
4139 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4140 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4141 | return err; | |
4142 | } | |
4143 | ||
4144 | irte.fields.vector = cfg->vector; | |
4145 | irte.fields.destination = dest; | |
4146 | ||
4147 | modify_irte(irte_info->sub_handle, irte_info->irte_index, irte); | |
4148 | ||
4149 | if (cfg->move_in_progress) | |
4150 | send_cleanup_vector(cfg); | |
4151 | ||
4152 | cpumask_copy(data->affinity, mask); | |
4153 | ||
4154 | return 0; | |
4155 | } | |
4156 | ||
4157 | static int free_irq(int irq) | |
4158 | { | |
4159 | struct irq_2_iommu *irte_info; | |
4160 | struct irq_cfg *cfg; | |
4161 | ||
4162 | cfg = irq_get_chip_data(irq); | |
4163 | if (!cfg) | |
4164 | return -EINVAL; | |
4165 | ||
4166 | irte_info = &cfg->irq_2_iommu; | |
4167 | ||
4168 | free_irte(irte_info->sub_handle, irte_info->irte_index); | |
4169 | ||
4170 | return 0; | |
4171 | } | |
4172 | ||
0b4d48cb JR |
4173 | static void compose_msi_msg(struct pci_dev *pdev, |
4174 | unsigned int irq, unsigned int dest, | |
4175 | struct msi_msg *msg, u8 hpet_id) | |
4176 | { | |
4177 | struct irq_2_iommu *irte_info; | |
4178 | struct irq_cfg *cfg; | |
4179 | union irte irte; | |
4180 | ||
4181 | cfg = irq_get_chip_data(irq); | |
4182 | if (!cfg) | |
4183 | return; | |
4184 | ||
4185 | irte_info = &cfg->irq_2_iommu; | |
4186 | ||
4187 | irte.val = 0; | |
4188 | irte.fields.vector = cfg->vector; | |
4189 | irte.fields.int_type = apic->irq_delivery_mode; | |
4190 | irte.fields.destination = dest; | |
4191 | irte.fields.dm = apic->irq_dest_mode; | |
4192 | irte.fields.valid = 1; | |
4193 | ||
4194 | modify_irte(irte_info->sub_handle, irte_info->irte_index, irte); | |
4195 | ||
4196 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4197 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4198 | msg->data = irte_info->irte_index; | |
4199 | } | |
4200 | ||
4201 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4202 | { | |
4203 | struct irq_cfg *cfg; | |
4204 | int index; | |
4205 | u16 devid; | |
4206 | ||
4207 | if (!pdev) | |
4208 | return -EINVAL; | |
4209 | ||
4210 | cfg = irq_get_chip_data(irq); | |
4211 | if (!cfg) | |
4212 | return -EINVAL; | |
4213 | ||
4214 | devid = get_device_id(&pdev->dev); | |
4215 | index = alloc_irq_index(cfg, devid, nvec); | |
4216 | ||
4217 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4218 | } | |
4219 | ||
4220 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4221 | int index, int offset) | |
4222 | { | |
4223 | struct irq_2_iommu *irte_info; | |
4224 | struct irq_cfg *cfg; | |
4225 | u16 devid; | |
4226 | ||
4227 | if (!pdev) | |
4228 | return -EINVAL; | |
4229 | ||
4230 | cfg = irq_get_chip_data(irq); | |
4231 | if (!cfg) | |
4232 | return -EINVAL; | |
4233 | ||
4234 | if (index >= MAX_IRQS_PER_TABLE) | |
4235 | return 0; | |
4236 | ||
4237 | devid = get_device_id(&pdev->dev); | |
4238 | irte_info = &cfg->irq_2_iommu; | |
4239 | ||
4240 | irte_info->sub_handle = devid; | |
4241 | irte_info->irte_index = index + offset; | |
4242 | irte_info->iommu = (void *)cfg; | |
4243 | ||
4244 | return 0; | |
4245 | } | |
4246 | ||
d976195c JR |
4247 | static int setup_hpet_msi(unsigned int irq, unsigned int id) |
4248 | { | |
4249 | struct irq_2_iommu *irte_info; | |
4250 | struct irq_cfg *cfg; | |
4251 | int index, devid; | |
4252 | ||
4253 | cfg = irq_get_chip_data(irq); | |
4254 | if (!cfg) | |
4255 | return -EINVAL; | |
4256 | ||
4257 | irte_info = &cfg->irq_2_iommu; | |
4258 | devid = get_hpet_devid(id); | |
4259 | if (devid < 0) | |
4260 | return devid; | |
4261 | ||
4262 | index = alloc_irq_index(cfg, devid, 1); | |
4263 | if (index < 0) | |
4264 | return index; | |
4265 | ||
4266 | irte_info->sub_handle = devid; | |
4267 | irte_info->irte_index = index; | |
4268 | irte_info->iommu = (void *)cfg; | |
4269 | ||
4270 | return 0; | |
4271 | } | |
4272 | ||
6b474b82 JR |
4273 | struct irq_remap_ops amd_iommu_irq_ops = { |
4274 | .supported = amd_iommu_supported, | |
4275 | .prepare = amd_iommu_prepare, | |
4276 | .enable = amd_iommu_enable, | |
4277 | .disable = amd_iommu_disable, | |
4278 | .reenable = amd_iommu_reenable, | |
4279 | .enable_faulting = amd_iommu_enable_faulting, | |
4280 | .setup_ioapic_entry = setup_ioapic_entry, | |
4281 | .set_affinity = set_affinity, | |
4282 | .free_irq = free_irq, | |
4283 | .compose_msi_msg = compose_msi_msg, | |
4284 | .msi_alloc_irq = msi_alloc_irq, | |
4285 | .msi_setup_irq = msi_setup_irq, | |
4286 | .setup_hpet_msi = setup_hpet_msi, | |
4287 | }; | |
2b324506 | 4288 | #endif |