projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iommu/amd: Add support for contiguous dma allocator
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
CommitLineData
b6c02715 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <jroedel@suse.de>
b6c02715
JR		 4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
72e1dcc4 20#include <linux/ratelimit.h>
b6c02715 21#include <linux/pci.h>
cb41ed85 22#include <linux/pci-ats.h>
a66022c4 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
7f26508b 25#include <linux/debugfs.h>
b6c02715 26#include <linux/scatterlist.h>
51491367 27#include <linux/dma-mapping.h>
b6c02715 28#include <linux/iommu-helper.h>
c156e347 29#include <linux/iommu.h>
815b33fd 30#include <linux/delay.h>
403f81d8 31#include <linux/amd-iommu.h>
72e1dcc4
JR		 32#include <linux/notifier.h>
33#include <linux/export.h>
2b324506
JR		 34#include <linux/irq.h>
35#include <linux/msi.h>
3b839a57 36#include <linux/dma-contiguous.h>
2b324506
JR		 37#include <asm/irq_remapping.h>
38#include <asm/io_apic.h>
39#include <asm/apic.h>
40#include <asm/hw_irq.h>
17f5b569 41#include <asm/msidef.h>
b6c02715 42#include <asm/proto.h>
46a7fa27 43#include <asm/iommu.h>
1d9b16d1 44#include <asm/gart.h>
27c2127a 45#include <asm/dma.h>
403f81d8
JR		 46
47#include "amd_iommu_proto.h"
48#include "amd_iommu_types.h"
6b474b82 49#include "irq_remapping.h"
b6c02715
JR		 50
51#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
815b33fd 53#define LOOP_TIMEOUT 100000
136f78a1 54
aa3de9c0
OBC		 55/*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
954e3dd8 61 * 512GB Pages are not supported due to a hardware bug
aa3de9c0 62 */
954e3dd8 63#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
aa3de9c0 64
b6c02715
JR		 65static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
bd60b735
JR		 67/* A list of preallocated protection domains */
68static LIST_HEAD(iommu_pd_list);
69static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
8fa5f802
JR		 71/* List of all available dev_data structures */
72static LIST_HEAD(dev_data_list);
73static DEFINE_SPINLOCK(dev_data_list_lock);
74
6efed63b
JR		 75LIST_HEAD(ioapic_map);
76LIST_HEAD(hpet_map);
77
0feae533
JR		 78/*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82static struct protection_domain *pt_domain;
83
b22f6434 84static const struct iommu_ops amd_iommu_ops;
26961efe 85
72e1dcc4 86static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
52815b75 87int amd_iommu_max_glx_val = -1;
72e1dcc4 88
ac1534a5
JR		 89static struct dma_map_ops amd_iommu_dma_ops;
90
50917e26
JR		 91/*
92 * This struct contains device specific data for the IOMMU
93 */
94struct iommu_dev_data {
95 struct list_head list; /* For domain->dev_list */
96 struct list_head dev_data_list; /* For global dev_data_list */
f251e187 97 struct list_head alias_list; /* Link alias-groups together */
50917e26
JR		 98 struct iommu_dev_data *alias_data;/* The alias dev_data */
99 struct protection_domain *domain; /* Domain the device is bound to */
50917e26
JR		 100 u16 devid; /* PCI Device ID */
101 bool iommu_v2; /* Device can make use of IOMMUv2 */
102 bool passthrough; /* Default for device is pt_domain */
103 struct {
104 bool enabled;
105 int qdep;
106 } ats; /* ATS state */
107 bool pri_tlp; /* PASID TLB required for
108 PPR completions */
109 u32 errata; /* Bitmap for errata to apply */
110};
111
431b2a20
JR		 112/*
113 * general struct to manage commands send to an IOMMU
114 */
d6449536 115struct iommu_cmd {
b6c02715
JR		 116 u32 data[4];
117};
118
05152a04
JR		 119struct kmem_cache *amd_iommu_irq_cache;
120
04bfdd84 121static void update_domain(struct protection_domain *domain);
5abcdba4 122static int __init alloc_passthrough_domain(void);
c1eee67b 123
15898bbc
JR		 124/****************************************************************************
125 *
126 * Helper functions
127 *
128 ****************************************************************************/
129
f62dda66 130static struct iommu_dev_data *alloc_dev_data(u16 devid)
8fa5f802
JR		 131{
132 struct iommu_dev_data *dev_data;
133 unsigned long flags;
134
135 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
136 if (!dev_data)
137 return NULL;
138
f251e187
JR		 139 INIT_LIST_HEAD(&dev_data->alias_list);
140
f62dda66 141 dev_data->devid = devid;
8fa5f802
JR		 142
143 spin_lock_irqsave(&dev_data_list_lock, flags);
144 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
145 spin_unlock_irqrestore(&dev_data_list_lock, flags);
146
147 return dev_data;
148}
149
150static void free_dev_data(struct iommu_dev_data *dev_data)
151{
152 unsigned long flags;
153
154 spin_lock_irqsave(&dev_data_list_lock, flags);
155 list_del(&dev_data->dev_data_list);
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 kfree(dev_data);
159}
160
3b03bb74
JR		 161static struct iommu_dev_data *search_dev_data(u16 devid)
162{
163 struct iommu_dev_data *dev_data;
164 unsigned long flags;
165
166 spin_lock_irqsave(&dev_data_list_lock, flags);
167 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
168 if (dev_data->devid == devid)
169 goto out_unlock;
170 }
171
172 dev_data = NULL;
173
174out_unlock:
175 spin_unlock_irqrestore(&dev_data_list_lock, flags);
176
177 return dev_data;
178}
179
180static struct iommu_dev_data *find_dev_data(u16 devid)
181{
182 struct iommu_dev_data *dev_data;
183
184 dev_data = search_dev_data(devid);
185
186 if (dev_data == NULL)
187 dev_data = alloc_dev_data(devid);
188
189 return dev_data;
190}
191
15898bbc
JR		 192static inline u16 get_device_id(struct device *dev)
193{
194 struct pci_dev *pdev = to_pci_dev(dev);
195
6f2729ba 196 return PCI_DEVID(pdev->bus->number, pdev->devfn);
15898bbc
JR		 197}
198
657cbb6b
JR		 199static struct iommu_dev_data *get_dev_data(struct device *dev)
200{
201 return dev->archdata.iommu;
202}
203
5abcdba4
JR		 204static bool pci_iommuv2_capable(struct pci_dev *pdev)
205{
206 static const int caps[] = {
207 PCI_EXT_CAP_ID_ATS,
46277b75
JR		 208 PCI_EXT_CAP_ID_PRI,
209 PCI_EXT_CAP_ID_PASID,
5abcdba4
JR		 210 };
211 int i, pos;
212
213 for (i = 0; i < 3; ++i) {
214 pos = pci_find_ext_capability(pdev, caps[i]);
215 if (pos == 0)
216 return false;
217 }
218
219 return true;
220}
221
6a113ddc
JR		 222static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
223{
224 struct iommu_dev_data *dev_data;
225
226 dev_data = get_dev_data(&pdev->dev);
227
228 return dev_data->errata & (1 << erratum) ? true : false;
229}
230
71c70984
JR		 231/*
232 * In this function the list of preallocated protection domains is traversed to
233 * find the domain for a specific device
234 */
235static struct dma_ops_domain *find_protection_domain(u16 devid)
236{
237 struct dma_ops_domain *entry, *ret = NULL;
238 unsigned long flags;
239 u16 alias = amd_iommu_alias_table[devid];
240
241 if (list_empty(&iommu_pd_list))
242 return NULL;
243
244 spin_lock_irqsave(&iommu_pd_list_lock, flags);
245
246 list_for_each_entry(entry, &iommu_pd_list, list) {
247 if (entry->target_dev == devid ||
248 entry->target_dev == alias) {
249 ret = entry;
250 break;
251 }
252 }
253
254 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
255
256 return ret;
257}
258
98fc5a69
JR		 259/*
260 * This function checks if the driver got a valid device from the caller to
261 * avoid dereferencing invalid pointers.
262 */
263static bool check_device(struct device *dev)
264{
265 u16 devid;
266
267 if (!dev || !dev->dma_mask)
268 return false;
269
b82a2272
YW		 270 /* No PCI device */
271 if (!dev_is_pci(dev))
98fc5a69
JR		 272 return false;
273
274 devid = get_device_id(dev);
275
276 /* Out of our scope? */
277 if (devid > amd_iommu_last_bdf)
278 return false;
279
280 if (amd_iommu_rlookup_table[devid] == NULL)
281 return false;
282
283 return true;
284}
285
25b11ce2 286static void init_iommu_group(struct device *dev)
2851db21 287{
2851db21 288 struct iommu_group *group;
2851db21 289
65d5352f 290 group = iommu_group_get_for_dev(dev);
25b11ce2
AW		 291 if (!IS_ERR(group))
292 iommu_group_put(group);
eb9c9527
AW		 293}
294
c1931090
AW		 295static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
296{
297 *(u16 *)data = alias;
298 return 0;
299}
300
301static u16 get_alias(struct device *dev)
302{
303 struct pci_dev *pdev = to_pci_dev(dev);
304 u16 devid, ivrs_alias, pci_alias;
305
306 devid = get_device_id(dev);
307 ivrs_alias = amd_iommu_alias_table[devid];
308 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
309
310 if (ivrs_alias == pci_alias)
311 return ivrs_alias;
312
313 /*
314 * DMA alias showdown
315 *
316 * The IVRS is fairly reliable in telling us about aliases, but it
317 * can't know about every screwy device. If we don't have an IVRS
318 * reported alias, use the PCI reported alias. In that case we may
319 * still need to initialize the rlookup and dev_table entries if the
320 * alias is to a non-existent device.
321 */
322 if (ivrs_alias == devid) {
323 if (!amd_iommu_rlookup_table[pci_alias]) {
324 amd_iommu_rlookup_table[pci_alias] =
325 amd_iommu_rlookup_table[devid];
326 memcpy(amd_iommu_dev_table[pci_alias].data,
327 amd_iommu_dev_table[devid].data,
328 sizeof(amd_iommu_dev_table[pci_alias].data));
329 }
330
331 return pci_alias;
332 }
333
334 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
335 "for device %s[%04x:%04x], kernel reported alias "
336 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
337 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
338 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
339 PCI_FUNC(pci_alias));
340
341 /*
342 * If we don't have a PCI DMA alias and the IVRS alias is on the same
343 * bus, then the IVRS table may know about a quirk that we don't.
344 */
345 if (pci_alias == devid &&
346 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
347 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
348 pdev->dma_alias_devfn = ivrs_alias & 0xff;
349 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
350 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
351 dev_name(dev));
352 }
353
354 return ivrs_alias;
355}
356
eb9c9527
AW		 357static int iommu_init_device(struct device *dev)
358{
359 struct pci_dev *pdev = to_pci_dev(dev);
360 struct iommu_dev_data *dev_data;
361 u16 alias;
eb9c9527
AW		 362
363 if (dev->archdata.iommu)
364 return 0;
365
366 dev_data = find_dev_data(get_device_id(dev));
367 if (!dev_data)
368 return -ENOMEM;
369
c1931090
AW		 370 alias = get_alias(dev);
371
eb9c9527
AW		 372 if (alias != dev_data->devid) {
373 struct iommu_dev_data *alias_data;
374
375 alias_data = find_dev_data(alias);
376 if (alias_data == NULL) {
377 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
378 dev_name(dev));
379 free_dev_data(dev_data);
380 return -ENOTSUPP;
381 }
382 dev_data->alias_data = alias_data;
eb9c9527 383
f251e187
JR		 384 /* Add device to the alias_list */
385 list_add(&dev_data->alias_list, &alias_data->alias_list);
e644a013 386 }
9dcd6130 387
5abcdba4
JR		 388 if (pci_iommuv2_capable(pdev)) {
389 struct amd_iommu *iommu;
390
391 iommu = amd_iommu_rlookup_table[dev_data->devid];
392 dev_data->iommu_v2 = iommu->is_iommu_v2;
393 }
394
657cbb6b
JR		 395 dev->archdata.iommu = dev_data;
396
066f2e98
AW		 397 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
398 dev);
399
657cbb6b
JR		 400 return 0;
401}
402
26018874
JR		 403static void iommu_ignore_device(struct device *dev)
404{
405 u16 devid, alias;
406
407 devid = get_device_id(dev);
408 alias = amd_iommu_alias_table[devid];
409
410 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
411 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
412
413 amd_iommu_rlookup_table[devid] = NULL;
414 amd_iommu_rlookup_table[alias] = NULL;
415}
416
657cbb6b
JR		 417static void iommu_uninit_device(struct device *dev)
418{
c1931090
AW		 419 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
420
421 if (!dev_data)
422 return;
423
066f2e98
AW		 424 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
425 dev);
426
9dcd6130
AW		 427 iommu_group_remove_device(dev);
428
c1931090
AW		 429 /* Unlink from alias, it may change if another device is re-plugged */
430 dev_data->alias_data = NULL;
431
8fa5f802 432 /*
c1931090
AW		 433 * We keep dev_data around for unplugged devices and reuse it when the
434 * device is re-plugged - not doing so would introduce a ton of races.
8fa5f802 435 */
657cbb6b 436}
b7cc9554
JR		 437
438void __init amd_iommu_uninit_devices(void)
439{
8fa5f802 440 struct iommu_dev_data *dev_data, *n;
b7cc9554
JR		 441 struct pci_dev *pdev = NULL;
442
443 for_each_pci_dev(pdev) {
444
445 if (!check_device(&pdev->dev))
446 continue;
447
448 iommu_uninit_device(&pdev->dev);
449 }
8fa5f802
JR		 450
451 /* Free all of our dev_data structures */
452 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
453 free_dev_data(dev_data);
b7cc9554
JR		 454}
455
456int __init amd_iommu_init_devices(void)
457{
458 struct pci_dev *pdev = NULL;
459 int ret = 0;
460
461 for_each_pci_dev(pdev) {
462
463 if (!check_device(&pdev->dev))
464 continue;
465
466 ret = iommu_init_device(&pdev->dev);
26018874
JR		 467 if (ret == -ENOTSUPP)
468 iommu_ignore_device(&pdev->dev);
469 else if (ret)
b7cc9554
JR		 470 goto out_free;
471 }
472
25b11ce2
AW		 473 /*
474 * Initialize IOMMU groups only after iommu_init_device() has
475 * had a chance to populate any IVRS defined aliases.
476 */
477 for_each_pci_dev(pdev) {
478 if (check_device(&pdev->dev))
479 init_iommu_group(&pdev->dev);
480 }
481
b7cc9554
JR		 482 return 0;
483
484out_free:
485
486 amd_iommu_uninit_devices();
487
488 return ret;
489}
7f26508b
JR		 490#ifdef CONFIG_AMD_IOMMU_STATS
491
492/*
493 * Initialization code for statistics collection
494 */
495
da49f6df 496DECLARE_STATS_COUNTER(compl_wait);
0f2a86f2 497DECLARE_STATS_COUNTER(cnt_map_single);
146a6917 498DECLARE_STATS_COUNTER(cnt_unmap_single);
d03f067a 499DECLARE_STATS_COUNTER(cnt_map_sg);
55877a6b 500DECLARE_STATS_COUNTER(cnt_unmap_sg);
c8f0fb36 501DECLARE_STATS_COUNTER(cnt_alloc_coherent);
5d31ee7e 502DECLARE_STATS_COUNTER(cnt_free_coherent);
c1858976 503DECLARE_STATS_COUNTER(cross_page);
f57d98ae 504DECLARE_STATS_COUNTER(domain_flush_single);
18811f55 505DECLARE_STATS_COUNTER(domain_flush_all);
5774f7c5 506DECLARE_STATS_COUNTER(alloced_io_mem);
8ecaf8f1 507DECLARE_STATS_COUNTER(total_map_requests);
399be2f5
JR		 508DECLARE_STATS_COUNTER(complete_ppr);
509DECLARE_STATS_COUNTER(invalidate_iotlb);
510DECLARE_STATS_COUNTER(invalidate_iotlb_all);
511DECLARE_STATS_COUNTER(pri_requests);
512
7f26508b 513static struct dentry *stats_dir;
7f26508b
JR		 514static struct dentry *de_fflush;
515
516static void amd_iommu_stats_add(struct __iommu_counter *cnt)
517{
518 if (stats_dir == NULL)
519 return;
520
521 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
522 &cnt->value);
523}
524
525static void amd_iommu_stats_init(void)
526{
527 stats_dir = debugfs_create_dir("amd-iommu", NULL);
528 if (stats_dir == NULL)
529 return;
530
7f26508b 531 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
3775d481 532 &amd_iommu_unmap_flush);
da49f6df
JR		 533
534 amd_iommu_stats_add(&compl_wait);
0f2a86f2 535 amd_iommu_stats_add(&cnt_map_single);
146a6917 536 amd_iommu_stats_add(&cnt_unmap_single);
d03f067a 537 amd_iommu_stats_add(&cnt_map_sg);
55877a6b 538 amd_iommu_stats_add(&cnt_unmap_sg);
c8f0fb36 539 amd_iommu_stats_add(&cnt_alloc_coherent);
5d31ee7e 540 amd_iommu_stats_add(&cnt_free_coherent);
c1858976 541 amd_iommu_stats_add(&cross_page);
f57d98ae 542 amd_iommu_stats_add(&domain_flush_single);
18811f55 543 amd_iommu_stats_add(&domain_flush_all);
5774f7c5 544 amd_iommu_stats_add(&alloced_io_mem);
8ecaf8f1 545 amd_iommu_stats_add(&total_map_requests);
399be2f5
JR		 546 amd_iommu_stats_add(&complete_ppr);
547 amd_iommu_stats_add(&invalidate_iotlb);
548 amd_iommu_stats_add(&invalidate_iotlb_all);
549 amd_iommu_stats_add(&pri_requests);
7f26508b
JR		 550}
551
552#endif
553
a80dc3e0
JR		 554/****************************************************************************
555 *
556 * Interrupt handling functions
557 *
558 ****************************************************************************/
559
e3e59876
JR		 560static void dump_dte_entry(u16 devid)
561{
562 int i;
563
ee6c2868
JR		 564 for (i = 0; i < 4; ++i)
565 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
e3e59876
JR		 566 amd_iommu_dev_table[devid].data[i]);
567}
568
945b4ac4
JR		 569static void dump_command(unsigned long phys_addr)
570{
571 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
572 int i;
573
574 for (i = 0; i < 4; ++i)
575 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
576}
577
a345b23b 578static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
90008ee4 579{
3d06fca8
JR		 580 int type, devid, domid, flags;
581 volatile u32 *event = __evt;
582 int count = 0;
583 u64 address;
584
585retry:
586 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
587 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
588 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
589 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
590 address = (u64)(((u64)event[3]) << 32) | event[2];
591
592 if (type == 0) {
593 /* Did we hit the erratum? */
594 if (++count == LOOP_TIMEOUT) {
595 pr_err("AMD-Vi: No event written to event log\n");
596 return;
597 }
598 udelay(1);
599 goto retry;
600 }
90008ee4 601
4c6f40d4 602 printk(KERN_ERR "AMD-Vi: Event logged [");
90008ee4
JR		 603
604 switch (type) {
605 case EVENT_TYPE_ILL_DEV:
606 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
607 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 608 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4 609 address, flags);
e3e59876 610 dump_dte_entry(devid);
90008ee4
JR		 611 break;
612 case EVENT_TYPE_IO_FAULT:
613 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
614 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
c5081cd7 615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 616 domid, address, flags);
617 break;
618 case EVENT_TYPE_DEV_TAB_ERR:
619 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
620 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 621 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 622 address, flags);
623 break;
624 case EVENT_TYPE_PAGE_TAB_ERR:
625 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
626 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
c5081cd7 627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 628 domid, address, flags);
629 break;
630 case EVENT_TYPE_ILL_CMD:
631 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
945b4ac4 632 dump_command(address);
90008ee4
JR		 633 break;
634 case EVENT_TYPE_CMD_HARD_ERR:
635 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
636 "flags=0x%04x]\n", address, flags);
637 break;
638 case EVENT_TYPE_IOTLB_INV_TO:
639 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
640 "address=0x%016llx]\n",
c5081cd7 641 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 642 address);
643 break;
644 case EVENT_TYPE_INV_DEV_REQ:
645 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
646 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 648 address, flags);
649 break;
650 default:
651 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
652 }
3d06fca8
JR		 653
654 memset(__evt, 0, 4 * sizeof(u32));
90008ee4
JR		 655}
656
657static void iommu_poll_events(struct amd_iommu *iommu)
658{
659 u32 head, tail;
90008ee4
JR		 660
661 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
662 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
663
664 while (head != tail) {
a345b23b 665 iommu_print_event(iommu, iommu->evt_buf + head);
90008ee4
JR		 666 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
667 }
668
669 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
90008ee4
JR		 670}
671
eee53537 672static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
72e1dcc4
JR		 673{
674 struct amd_iommu_fault fault;
72e1dcc4 675
399be2f5
JR		 676 INC_STATS_COUNTER(pri_requests);
677
72e1dcc4
JR		 678 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
679 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
680 return;
681 }
682
683 fault.address = raw[1];
684 fault.pasid = PPR_PASID(raw[0]);
685 fault.device_id = PPR_DEVID(raw[0]);
686 fault.tag = PPR_TAG(raw[0]);
687 fault.flags = PPR_FLAGS(raw[0]);
688
72e1dcc4
JR		 689 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
690}
691
692static void iommu_poll_ppr_log(struct amd_iommu *iommu)
693{
72e1dcc4
JR		 694 u32 head, tail;
695
696 if (iommu->ppr_log == NULL)
697 return;
698
72e1dcc4
JR		 699 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
701
702 while (head != tail) {
eee53537
JR		 703 volatile u64 *raw;
704 u64 entry[2];
705 int i;
706
707 raw = (u64 *)(iommu->ppr_log + head);
708
709 /*
710 * Hardware bug: Interrupt may arrive before the entry is
711 * written to memory. If this happens we need to wait for the
712 * entry to arrive.
713 */
714 for (i = 0; i < LOOP_TIMEOUT; ++i) {
715 if (PPR_REQ_TYPE(raw[0]) != 0)
716 break;
717 udelay(1);
718 }
72e1dcc4 719
eee53537
JR		 720 /* Avoid memcpy function-call overhead */
721 entry[0] = raw[0];
722 entry[1] = raw[1];
72e1dcc4 723
eee53537
JR		 724 /*
725 * To detect the hardware bug we need to clear the entry
726 * back to zero.
727 */
728 raw[0] = raw[1] = 0UL;
729
730 /* Update head pointer of hardware ring-buffer */
72e1dcc4
JR		 731 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
732 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
eee53537 733
eee53537
JR		 734 /* Handle PPR entry */
735 iommu_handle_ppr_entry(iommu, entry);
736
eee53537
JR		 737 /* Refresh ring-buffer information */
738 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
72e1dcc4
JR		 739 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
740 }
72e1dcc4
JR		 741}
742
72fe00f0 743irqreturn_t amd_iommu_int_thread(int irq, void *data)
a80dc3e0 744{
3f398bc7
SS		 745 struct amd_iommu *iommu = (struct amd_iommu *) data;
746 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 747
3f398bc7
SS		 748 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
749 /* Enable EVT and PPR interrupts again */
750 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
751 iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 752
3f398bc7
SS		 753 if (status & MMIO_STATUS_EVT_INT_MASK) {
754 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
755 iommu_poll_events(iommu);
756 }
90008ee4 757
3f398bc7
SS		 758 if (status & MMIO_STATUS_PPR_INT_MASK) {
759 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
760 iommu_poll_ppr_log(iommu);
761 }
90008ee4 762
3f398bc7
SS		 763 /*
764 * Hardware bug: ERBT1312
765 * When re-enabling interrupt (by writing 1
766 * to clear the bit), the hardware might also try to set
767 * the interrupt bit in the event status register.
768 * In this scenario, the bit will be set, and disable
769 * subsequent interrupts.
770 *
771 * Workaround: The IOMMU driver should read back the
772 * status register and check if the interrupt bits are cleared.
773 * If not, driver will need to go through the interrupt handler
774 * again and re-clear the bits
775 */
776 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
777 }
90008ee4 778 return IRQ_HANDLED;
a80dc3e0
JR		 779}
780
72fe00f0
JR		 781irqreturn_t amd_iommu_int_handler(int irq, void *data)
782{
783 return IRQ_WAKE_THREAD;
784}
785
431b2a20
JR		 786/****************************************************************************
787 *
788 * IOMMU command queuing functions
789 *
790 ****************************************************************************/
791
ac0ea6e9
JR		 792static int wait_on_sem(volatile u64 *sem)
793{
794 int i = 0;
795
796 while (*sem == 0 && i < LOOP_TIMEOUT) {
797 udelay(1);
798 i += 1;
799 }
800
801 if (i == LOOP_TIMEOUT) {
802 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
803 return -EIO;
804 }
805
806 return 0;
807}
808
809static void copy_cmd_to_buffer(struct amd_iommu *iommu,
810 struct iommu_cmd *cmd,
811 u32 tail)
a19ae1ec 812{
a19ae1ec
JR		 813 u8 *target;
814
8a7c5ef3 815 target = iommu->cmd_buf + tail;
ac0ea6e9
JR		 816 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
817
818 /* Copy command to buffer */
819 memcpy(target, cmd, sizeof(*cmd));
820
821 /* Tell the IOMMU about it */
a19ae1ec 822 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
ac0ea6e9 823}
a19ae1ec 824
815b33fd 825static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
ded46737 826{
815b33fd
JR		 827 WARN_ON(address & 0x7ULL);
828
ded46737 829 memset(cmd, 0, sizeof(*cmd));
815b33fd
JR		 830 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
831 cmd->data[1] = upper_32_bits(__pa(address));
832 cmd->data[2] = 1;
ded46737
JR		 833 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
834}
835
94fe79e2
JR		 836static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
837{
838 memset(cmd, 0, sizeof(*cmd));
839 cmd->data[0] = devid;
840 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
841}
842
11b6402c
JR		 843static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
844 size_t size, u16 domid, int pde)
845{
846 u64 pages;
ae0cbbb1 847 bool s;
11b6402c
JR		 848
849 pages = iommu_num_pages(address, size, PAGE_SIZE);
ae0cbbb1 850 s = false;
11b6402c
JR		 851
852 if (pages > 1) {
853 /*
854 * If we have to flush more than one page, flush all
855 * TLB entries for this domain
856 */
857 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
ae0cbbb1 858 s = true;
11b6402c
JR		 859 }
860
861 address &= PAGE_MASK;
862
863 memset(cmd, 0, sizeof(*cmd));
864 cmd->data[1] |= domid;
865 cmd->data[2] = lower_32_bits(address);
866 cmd->data[3] = upper_32_bits(address);
867 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
868 if (s) /* size bit - we flush more than one 4kb page */
869 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
df805abb 870 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
11b6402c
JR		 871 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
872}
873
cb41ed85
JR		 874static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
875 u64 address, size_t size)
876{
877 u64 pages;
ae0cbbb1 878 bool s;
cb41ed85
JR		 879
880 pages = iommu_num_pages(address, size, PAGE_SIZE);
ae0cbbb1 881 s = false;
cb41ed85
JR		 882
883 if (pages > 1) {
884 /*
885 * If we have to flush more than one page, flush all
886 * TLB entries for this domain
887 */
888 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
ae0cbbb1 889 s = true;
cb41ed85
JR		 890 }
891
892 address &= PAGE_MASK;
893
894 memset(cmd, 0, sizeof(*cmd));
895 cmd->data[0] = devid;
896 cmd->data[0] |= (qdep & 0xff) << 24;
897 cmd->data[1] = devid;
898 cmd->data[2] = lower_32_bits(address);
899 cmd->data[3] = upper_32_bits(address);
900 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
901 if (s)
902 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
903}
904
22e266c7
JR		 905static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
906 u64 address, bool size)
907{
908 memset(cmd, 0, sizeof(*cmd));
909
910 address &= ~(0xfffULL);
911
a919a018 912 cmd->data[0] = pasid;
22e266c7
JR		 913 cmd->data[1] = domid;
914 cmd->data[2] = lower_32_bits(address);
915 cmd->data[3] = upper_32_bits(address);
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
918 if (size)
919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
920 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
921}
922
923static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
924 int qdep, u64 address, bool size)
925{
926 memset(cmd, 0, sizeof(*cmd));
927
928 address &= ~(0xfffULL);
929
930 cmd->data[0] = devid;
e8d2d82d 931 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
22e266c7
JR		 932 cmd->data[0] |= (qdep & 0xff) << 24;
933 cmd->data[1] = devid;
e8d2d82d 934 cmd->data[1] |= (pasid & 0xff) << 16;
22e266c7
JR		 935 cmd->data[2] = lower_32_bits(address);
936 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
937 cmd->data[3] = upper_32_bits(address);
938 if (size)
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
940 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
941}
942
c99afa25
JR		 943static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
944 int status, int tag, bool gn)
945{
946 memset(cmd, 0, sizeof(*cmd));
947
948 cmd->data[0] = devid;
949 if (gn) {
a919a018 950 cmd->data[1] = pasid;
c99afa25
JR		 951 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
952 }
953 cmd->data[3] = tag & 0x1ff;
954 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
955
956 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
957}
958
58fc7f14
JR		 959static void build_inv_all(struct iommu_cmd *cmd)
960{
961 memset(cmd, 0, sizeof(*cmd));
962 CMD_SET_TYPE(cmd, CMD_INV_ALL);
a19ae1ec
JR		 963}
964
7ef2798d
JR		 965static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
966{
967 memset(cmd, 0, sizeof(*cmd));
968 cmd->data[0] = devid;
969 CMD_SET_TYPE(cmd, CMD_INV_IRT);
970}
971
431b2a20 972/*
431b2a20 973 * Writes the command to the IOMMUs command buffer and informs the
ac0ea6e9 974 * hardware about the new command.
431b2a20 975 */
f1ca1512
JR		 976static int iommu_queue_command_sync(struct amd_iommu *iommu,
977 struct iommu_cmd *cmd,
978 bool sync)
a19ae1ec 979{
ac0ea6e9 980 u32 left, tail, head, next_tail;
a19ae1ec 981 unsigned long flags;
a19ae1ec 982
549c90dc 983 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
ac0ea6e9
JR		 984
985again:
a19ae1ec 986 spin_lock_irqsave(&iommu->lock, flags);
a19ae1ec 987
ac0ea6e9
JR		 988 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
989 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
990 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
991 left = (head - next_tail) % iommu->cmd_buf_size;
a19ae1ec 992
ac0ea6e9
JR		 993 if (left <= 2) {
994 struct iommu_cmd sync_cmd;
995 volatile u64 sem = 0;
996 int ret;
8d201968 997
ac0ea6e9
JR		 998 build_completion_wait(&sync_cmd, (u64)&sem);
999 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
da49f6df 1000
ac0ea6e9
JR		 1001 spin_unlock_irqrestore(&iommu->lock, flags);
1002
1003 if ((ret = wait_on_sem(&sem)) != 0)
1004 return ret;
1005
1006 goto again;
8d201968
JR		 1007 }
1008
ac0ea6e9
JR		 1009 copy_cmd_to_buffer(iommu, cmd, tail);
1010
1011 /* We need to sync now to make sure all commands are processed */
f1ca1512 1012 iommu->need_sync = sync;
ac0ea6e9 1013
a19ae1ec 1014 spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 1015
815b33fd 1016 return 0;
8d201968
JR		 1017}
1018
f1ca1512
JR		 1019static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1020{
1021 return iommu_queue_command_sync(iommu, cmd, true);
1022}
1023
8d201968
JR		 1024/*
1025 * This function queues a completion wait command into the command
1026 * buffer of an IOMMU
1027 */
a19ae1ec 1028static int iommu_completion_wait(struct amd_iommu *iommu)
8d201968
JR		 1029{
1030 struct iommu_cmd cmd;
815b33fd 1031 volatile u64 sem = 0;
ac0ea6e9 1032 int ret;
8d201968 1033
09ee17eb 1034 if (!iommu->need_sync)
815b33fd 1035 return 0;
09ee17eb 1036
815b33fd 1037 build_completion_wait(&cmd, (u64)&sem);
a19ae1ec 1038
f1ca1512 1039 ret = iommu_queue_command_sync(iommu, &cmd, false);
a19ae1ec 1040 if (ret)
815b33fd 1041 return ret;
8d201968 1042
ac0ea6e9 1043 return wait_on_sem(&sem);
8d201968
JR		 1044}
1045
d8c13085 1046static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
a19ae1ec 1047{
d8c13085 1048 struct iommu_cmd cmd;
a19ae1ec 1049
d8c13085 1050 build_inv_dte(&cmd, devid);
7e4f88da 1051
d8c13085
JR		 1052 return iommu_queue_command(iommu, &cmd);
1053}
09ee17eb 1054
7d0c5cc5
JR		 1055static void iommu_flush_dte_all(struct amd_iommu *iommu)
1056{
1057 u32 devid;
09ee17eb 1058
7d0c5cc5
JR		 1059 for (devid = 0; devid <= 0xffff; ++devid)
1060 iommu_flush_dte(iommu, devid);
a19ae1ec 1061
7d0c5cc5
JR		 1062 iommu_completion_wait(iommu);
1063}
84df8175 1064
7d0c5cc5
JR		 1065/*
1066 * This function uses heavy locking and may disable irqs for some time. But
1067 * this is no issue because it is only called during resume.
1068 */
1069static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1070{
1071 u32 dom_id;
a19ae1ec 1072
7d0c5cc5
JR		 1073 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1074 struct iommu_cmd cmd;
1075 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1076 dom_id, 1);
1077 iommu_queue_command(iommu, &cmd);
1078 }
8eed9833 1079
7d0c5cc5 1080 iommu_completion_wait(iommu);
a19ae1ec
JR		 1081}
1082
58fc7f14 1083static void iommu_flush_all(struct amd_iommu *iommu)
0518a3a4 1084{
58fc7f14 1085 struct iommu_cmd cmd;
0518a3a4 1086
58fc7f14 1087 build_inv_all(&cmd);
0518a3a4 1088
58fc7f14
JR		 1089 iommu_queue_command(iommu, &cmd);
1090 iommu_completion_wait(iommu);
1091}
1092
7ef2798d
JR		 1093static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1094{
1095 struct iommu_cmd cmd;
1096
1097 build_inv_irt(&cmd, devid);
1098
1099 iommu_queue_command(iommu, &cmd);
1100}
1101
1102static void iommu_flush_irt_all(struct amd_iommu *iommu)
1103{
1104 u32 devid;
1105
1106 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1107 iommu_flush_irt(iommu, devid);
1108
1109 iommu_completion_wait(iommu);
1110}
1111
7d0c5cc5
JR		 1112void iommu_flush_all_caches(struct amd_iommu *iommu)
1113{
58fc7f14
JR		 1114 if (iommu_feature(iommu, FEATURE_IA)) {
1115 iommu_flush_all(iommu);
1116 } else {
1117 iommu_flush_dte_all(iommu);
7ef2798d 1118 iommu_flush_irt_all(iommu);
58fc7f14 1119 iommu_flush_tlb_all(iommu);
0518a3a4
JR		 1120 }
1121}
1122
431b2a20 1123/*
cb41ed85 1124 * Command send function for flushing on-device TLB
431b2a20 1125 */
6c542047
JR		 1126static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1127 u64 address, size_t size)
3fa43655
JR		 1128{
1129 struct amd_iommu *iommu;
b00d3bcf 1130 struct iommu_cmd cmd;
cb41ed85 1131 int qdep;
3fa43655 1132
ea61cddb
JR		 1133 qdep = dev_data->ats.qdep;
1134 iommu = amd_iommu_rlookup_table[dev_data->devid];
3fa43655 1135
ea61cddb 1136 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
b00d3bcf
JR		 1137
1138 return iommu_queue_command(iommu, &cmd);
3fa43655
JR		 1139}
1140
431b2a20 1141/*
431b2a20 1142 * Command send function for invalidating a device table entry
431b2a20 1143 */
6c542047 1144static int device_flush_dte(struct iommu_dev_data *dev_data)
a19ae1ec 1145{
3fa43655 1146 struct amd_iommu *iommu;
ee2fa743 1147 int ret;
a19ae1ec 1148
6c542047 1149 iommu = amd_iommu_rlookup_table[dev_data->devid];
a19ae1ec 1150
f62dda66 1151 ret = iommu_flush_dte(iommu, dev_data->devid);
cb41ed85
JR		 1152 if (ret)
1153 return ret;
1154
ea61cddb 1155 if (dev_data->ats.enabled)
6c542047 1156 ret = device_flush_iotlb(dev_data, 0, ~0UL);
ee2fa743 1157
ee2fa743 1158 return ret;
a19ae1ec
JR		 1159}
1160
431b2a20
JR		 1161/*
1162 * TLB invalidation function which is called from the mapping functions.
1163 * It invalidates a single PTE if the range to flush is within a single
1164 * page. Otherwise it flushes the whole TLB of the IOMMU.
1165 */
17b124bf
JR		 1166static void __domain_flush_pages(struct protection_domain *domain,
1167 u64 address, size_t size, int pde)
a19ae1ec 1168{
cb41ed85 1169 struct iommu_dev_data *dev_data;
11b6402c
JR		 1170 struct iommu_cmd cmd;
1171 int ret = 0, i;
a19ae1ec 1172
11b6402c 1173 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
999ba417 1174
6de8ad9b
JR		 1175 for (i = 0; i < amd_iommus_present; ++i) {
1176 if (!domain->dev_iommu[i])
1177 continue;
1178
1179 /*
1180 * Devices of this domain are behind this IOMMU
1181 * We need a TLB flush
1182 */
11b6402c 1183 ret |= iommu_queue_command(amd_iommus[i], &cmd);
6de8ad9b
JR		 1184 }
1185
cb41ed85 1186 list_for_each_entry(dev_data, &domain->dev_list, list) {
cb41ed85 1187
ea61cddb 1188 if (!dev_data->ats.enabled)
cb41ed85
JR		 1189 continue;
1190
6c542047 1191 ret |= device_flush_iotlb(dev_data, address, size);
cb41ed85
JR		 1192 }
1193
11b6402c 1194 WARN_ON(ret);
6de8ad9b
JR		 1195}
1196
17b124bf
JR		 1197static void domain_flush_pages(struct protection_domain *domain,
1198 u64 address, size_t size)
6de8ad9b 1199{
17b124bf 1200 __domain_flush_pages(domain, address, size, 0);
a19ae1ec 1201}
b6c02715 1202
1c655773 1203/* Flush the whole IO/TLB for a given protection domain */
17b124bf 1204static void domain_flush_tlb(struct protection_domain *domain)
1c655773 1205{
17b124bf 1206 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1c655773
JR		 1207}
1208
42a49f96 1209/* Flush the whole IO/TLB for a given protection domain - including PDE */
17b124bf 1210static void domain_flush_tlb_pde(struct protection_domain *domain)
42a49f96 1211{
17b124bf 1212 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
42a49f96
CW		 1213}
1214
17b124bf 1215static void domain_flush_complete(struct protection_domain *domain)
b00d3bcf 1216{
17b124bf 1217 int i;
18811f55 1218
17b124bf
JR		 1219 for (i = 0; i < amd_iommus_present; ++i) {
1220 if (!domain->dev_iommu[i])
1221 continue;
bfd1be18 1222
17b124bf
JR		 1223 /*
1224 * Devices of this domain are behind this IOMMU
1225 * We need to wait for completion of all commands.
1226 */
1227 iommu_completion_wait(amd_iommus[i]);
bfd1be18 1228 }
e394d72a
JR		 1229}
1230
b00d3bcf 1231
09b42804 1232/*
b00d3bcf 1233 * This function flushes the DTEs for all devices in domain
09b42804 1234 */
17b124bf 1235static void domain_flush_devices(struct protection_domain *domain)
e394d72a 1236{
b00d3bcf 1237 struct iommu_dev_data *dev_data;
b26e81b8 1238
b00d3bcf 1239 list_for_each_entry(dev_data, &domain->dev_list, list)
6c542047 1240 device_flush_dte(dev_data);
a345b23b
JR		 1241}
1242
431b2a20
JR		 1243/****************************************************************************
1244 *
1245 * The functions below are used the create the page table mappings for
1246 * unity mapped regions.
1247 *
1248 ****************************************************************************/
1249
308973d3
JR		 1250/*
1251 * This function is used to add another level to an IO page table. Adding
1252 * another level increases the size of the address space by 9 bits to a size up
1253 * to 64 bits.
1254 */
1255static bool increase_address_space(struct protection_domain *domain,
1256 gfp_t gfp)
1257{
1258 u64 *pte;
1259
1260 if (domain->mode == PAGE_MODE_6_LEVEL)
1261 /* address space already 64 bit large */
1262 return false;
1263
1264 pte = (void *)get_zeroed_page(gfp);
1265 if (!pte)
1266 return false;
1267
1268 *pte = PM_LEVEL_PDE(domain->mode,
1269 virt_to_phys(domain->pt_root));
1270 domain->pt_root = pte;
1271 domain->mode += 1;
1272 domain->updated = true;
1273
1274 return true;
1275}
1276
1277static u64 *alloc_pte(struct protection_domain *domain,
1278 unsigned long address,
cbb9d729 1279 unsigned long page_size,
308973d3
JR		 1280 u64 **pte_page,
1281 gfp_t gfp)
1282{
cbb9d729 1283 int level, end_lvl;
308973d3 1284 u64 *pte, *page;
cbb9d729
JR		 1285
1286 BUG_ON(!is_power_of_2(page_size));
308973d3
JR		 1287
1288 while (address > PM_LEVEL_SIZE(domain->mode))
1289 increase_address_space(domain, gfp);
1290
cbb9d729
JR		 1291 level = domain->mode - 1;
1292 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1293 address = PAGE_SIZE_ALIGN(address, page_size);
1294 end_lvl = PAGE_SIZE_LEVEL(page_size);
308973d3
JR		 1295
1296 while (level > end_lvl) {
1297 if (!IOMMU_PTE_PRESENT(*pte)) {
1298 page = (u64 *)get_zeroed_page(gfp);
1299 if (!page)
1300 return NULL;
1301 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1302 }
1303
cbb9d729
JR		 1304 /* No level skipping support yet */
1305 if (PM_PTE_LEVEL(*pte) != level)
1306 return NULL;
1307
308973d3
JR		 1308 level -= 1;
1309
1310 pte = IOMMU_PTE_PAGE(*pte);
1311
1312 if (pte_page && level == end_lvl)
1313 *pte_page = pte;
1314
1315 pte = &pte[PM_LEVEL_INDEX(level, address)];
1316 }
1317
1318 return pte;
1319}
1320
1321/*
1322 * This function checks if there is a PTE for a given dma address. If
1323 * there is one, it returns the pointer to it.
1324 */
24cd7723 1325static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
308973d3
JR		 1326{
1327 int level;
1328 u64 *pte;
1329
24cd7723
JR		 1330 if (address > PM_LEVEL_SIZE(domain->mode))
1331 return NULL;
1332
1333 level = domain->mode - 1;
1334 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
308973d3 1335
24cd7723
JR		 1336 while (level > 0) {
1337
1338 /* Not Present */
308973d3
JR		 1339 if (!IOMMU_PTE_PRESENT(*pte))
1340 return NULL;
1341
24cd7723
JR		 1342 /* Large PTE */
1343 if (PM_PTE_LEVEL(*pte) == 0x07) {
1344 unsigned long pte_mask, __pte;
1345
1346 /*
1347 * If we have a series of large PTEs, make
1348 * sure to return a pointer to the first one.
1349 */
1350 pte_mask = PTE_PAGE_SIZE(*pte);
1351 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1352 __pte = ((unsigned long)pte) & pte_mask;
1353
1354 return (u64 *)__pte;
1355 }
1356
1357 /* No level skipping support yet */
1358 if (PM_PTE_LEVEL(*pte) != level)
1359 return NULL;
1360
308973d3
JR		 1361 level -= 1;
1362
24cd7723 1363 /* Walk to the next level */
308973d3
JR		 1364 pte = IOMMU_PTE_PAGE(*pte);
1365 pte = &pte[PM_LEVEL_INDEX(level, address)];
308973d3
JR		 1366 }
1367
1368 return pte;
1369}
1370
431b2a20
JR		 1371/*
1372 * Generic mapping functions. It maps a physical address into a DMA
1373 * address space. It allocates the page table pages if necessary.
1374 * In the future it can be extended to a generic mapping function
1375 * supporting all features of AMD IOMMU page tables like level skipping
1376 * and full 64 bit address spaces.
1377 */
38e817fe
JR		 1378static int iommu_map_page(struct protection_domain *dom,
1379 unsigned long bus_addr,
1380 unsigned long phys_addr,
abdc5eb3 1381 int prot,
cbb9d729 1382 unsigned long page_size)
bd0e5211 1383{
8bda3092 1384 u64 __pte, *pte;
cbb9d729 1385 int i, count;
abdc5eb3 1386
bad1cac2 1387 if (!(prot & IOMMU_PROT_MASK))
bd0e5211
JR		 1388 return -EINVAL;
1389
cbb9d729
JR		 1390 bus_addr = PAGE_ALIGN(bus_addr);
1391 phys_addr = PAGE_ALIGN(phys_addr);
1392 count = PAGE_SIZE_PTE_COUNT(page_size);
1393 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1394
63eaa75e
ML		 1395 if (!pte)
1396 return -ENOMEM;
1397
cbb9d729
JR		 1398 for (i = 0; i < count; ++i)
1399 if (IOMMU_PTE_PRESENT(pte[i]))
1400 return -EBUSY;
bd0e5211 1401
cbb9d729
JR		 1402 if (page_size > PAGE_SIZE) {
1403 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1404 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1405 } else
1406 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
bd0e5211 1407
bd0e5211
JR		 1408 if (prot & IOMMU_PROT_IR)
1409 __pte |= IOMMU_PTE_IR;
1410 if (prot & IOMMU_PROT_IW)
1411 __pte |= IOMMU_PTE_IW;
1412
cbb9d729
JR		 1413 for (i = 0; i < count; ++i)
1414 pte[i] = __pte;
bd0e5211 1415
04bfdd84
JR		 1416 update_domain(dom);
1417
bd0e5211
JR		 1418 return 0;
1419}
1420
24cd7723
JR		 1421static unsigned long iommu_unmap_page(struct protection_domain *dom,
1422 unsigned long bus_addr,
1423 unsigned long page_size)
eb74ff6c 1424{
24cd7723
JR		 1425 unsigned long long unmap_size, unmapped;
1426 u64 *pte;
1427
1428 BUG_ON(!is_power_of_2(page_size));
1429
1430 unmapped = 0;
eb74ff6c 1431
24cd7723
JR		 1432 while (unmapped < page_size) {
1433
1434 pte = fetch_pte(dom, bus_addr);
1435
1436 if (!pte) {
1437 /*
1438 * No PTE for this address
1439 * move forward in 4kb steps
1440 */
1441 unmap_size = PAGE_SIZE;
1442 } else if (PM_PTE_LEVEL(*pte) == 0) {
1443 /* 4kb PTE found for this address */
1444 unmap_size = PAGE_SIZE;
1445 *pte = 0ULL;
1446 } else {
1447 int count, i;
1448
1449 /* Large PTE found which maps this address */
1450 unmap_size = PTE_PAGE_SIZE(*pte);
60d0ca3c
AW		 1451
1452 /* Only unmap from the first pte in the page */
1453 if ((unmap_size - 1) & bus_addr)
1454 break;
24cd7723
JR		 1455 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1456 for (i = 0; i < count; i++)
1457 pte[i] = 0ULL;
1458 }
1459
1460 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1461 unmapped += unmap_size;
1462 }
1463
60d0ca3c 1464 BUG_ON(unmapped && !is_power_of_2(unmapped));
eb74ff6c 1465
24cd7723 1466 return unmapped;
eb74ff6c 1467}
eb74ff6c 1468
431b2a20
JR		 1469/*
1470 * This function checks if a specific unity mapping entry is needed for
1471 * this specific IOMMU.
1472 */
bd0e5211
JR		 1473static int iommu_for_unity_map(struct amd_iommu *iommu,
1474 struct unity_map_entry *entry)
1475{
1476 u16 bdf, i;
1477
1478 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1479 bdf = amd_iommu_alias_table[i];
1480 if (amd_iommu_rlookup_table[bdf] == iommu)
1481 return 1;
1482 }
1483
1484 return 0;
1485}
1486
431b2a20
JR		 1487/*
1488 * This function actually applies the mapping to the page table of the
1489 * dma_ops domain.
1490 */
bd0e5211
JR		 1491static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1492 struct unity_map_entry *e)
1493{
1494 u64 addr;
1495 int ret;
1496
1497 for (addr = e->address_start; addr < e->address_end;
1498 addr += PAGE_SIZE) {
abdc5eb3 1499 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
cbb9d729 1500 PAGE_SIZE);
bd0e5211
JR		 1501 if (ret)
1502 return ret;
1503 /*
1504 * if unity mapping is in aperture range mark the page
1505 * as allocated in the aperture
1506 */
1507 if (addr < dma_dom->aperture_size)
c3239567 1508 __set_bit(addr >> PAGE_SHIFT,
384de729 1509 dma_dom->aperture[0]->bitmap);
bd0e5211
JR		 1510 }
1511
1512 return 0;
1513}
1514
171e7b37
JR		 1515/*
1516 * Init the unity mappings for a specific IOMMU in the system
1517 *
1518 * Basically iterates over all unity mapping entries and applies them to
1519 * the default domain DMA of that IOMMU if necessary.
1520 */
1521static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1522{
1523 struct unity_map_entry *entry;
1524 int ret;
1525
1526 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1527 if (!iommu_for_unity_map(iommu, entry))
1528 continue;
1529 ret = dma_ops_unity_map(iommu->default_dom, entry);
1530 if (ret)
1531 return ret;
1532 }
1533
1534 return 0;
1535}
1536
431b2a20
JR		 1537/*
1538 * Inits the unity mappings required for a specific device
1539 */
bd0e5211
JR		 1540static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1541 u16 devid)
1542{
1543 struct unity_map_entry *e;
1544 int ret;
1545
1546 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1547 if (!(devid >= e->devid_start && devid <= e->devid_end))
1548 continue;
1549 ret = dma_ops_unity_map(dma_dom, e);
1550 if (ret)
1551 return ret;
1552 }
1553
1554 return 0;
1555}
1556
431b2a20
JR		 1557/****************************************************************************
1558 *
1559 * The next functions belong to the address allocator for the dma_ops
1560 * interface functions. They work like the allocators in the other IOMMU
1561 * drivers. Its basically a bitmap which marks the allocated pages in
1562 * the aperture. Maybe it could be enhanced in the future to a more
1563 * efficient allocator.
1564 *
1565 ****************************************************************************/
d3086444 1566
431b2a20 1567/*
384de729 1568 * The address allocator core functions.
431b2a20
JR		 1569 *
1570 * called with domain->lock held
1571 */
384de729 1572
171e7b37
JR		 1573/*
1574 * Used to reserve address ranges in the aperture (e.g. for exclusion
1575 * ranges.
1576 */
1577static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1578 unsigned long start_page,
1579 unsigned int pages)
1580{
1581 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1582
1583 if (start_page + pages > last_page)
1584 pages = last_page - start_page;
1585
1586 for (i = start_page; i < start_page + pages; ++i) {
1587 int index = i / APERTURE_RANGE_PAGES;
1588 int page = i % APERTURE_RANGE_PAGES;
1589 __set_bit(page, dom->aperture[index]->bitmap);
1590 }
1591}
1592
9cabe89b
JR		 1593/*
1594 * This function is used to add a new aperture range to an existing
1595 * aperture in case of dma_ops domain allocation or address allocation
1596 * failure.
1597 */
576175c2 1598static int alloc_new_range(struct dma_ops_domain *dma_dom,
9cabe89b
JR		 1599 bool populate, gfp_t gfp)
1600{
1601 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
576175c2 1602 struct amd_iommu *iommu;
17f5b569 1603 unsigned long i, old_size;
9cabe89b 1604
f5e9705c
JR		 1605#ifdef CONFIG_IOMMU_STRESS
1606 populate = false;
1607#endif
1608
9cabe89b
JR		 1609 if (index >= APERTURE_MAX_RANGES)
1610 return -ENOMEM;
1611
1612 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1613 if (!dma_dom->aperture[index])
1614 return -ENOMEM;
1615
1616 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1617 if (!dma_dom->aperture[index]->bitmap)
1618 goto out_free;
1619
1620 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1621
1622 if (populate) {
1623 unsigned long address = dma_dom->aperture_size;
1624 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1625 u64 *pte, *pte_page;
1626
1627 for (i = 0; i < num_ptes; ++i) {
cbb9d729 1628 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
9cabe89b
JR		 1629 &pte_page, gfp);
1630 if (!pte)
1631 goto out_free;
1632
1633 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1634
1635 address += APERTURE_RANGE_SIZE / 64;
1636 }
1637 }
1638
17f5b569 1639 old_size = dma_dom->aperture_size;
9cabe89b
JR		 1640 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1641
17f5b569
JR		 1642 /* Reserve address range used for MSI messages */
1643 if (old_size < MSI_ADDR_BASE_LO &&
1644 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1645 unsigned long spage;
1646 int pages;
1647
1648 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1649 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1650
1651 dma_ops_reserve_addresses(dma_dom, spage, pages);
1652 }
1653
b595076a 1654 /* Initialize the exclusion range if necessary */
576175c2
JR		 1655 for_each_iommu(iommu) {
1656 if (iommu->exclusion_start &&
1657 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1658 && iommu->exclusion_start < dma_dom->aperture_size) {
1659 unsigned long startpage;
1660 int pages = iommu_num_pages(iommu->exclusion_start,
1661 iommu->exclusion_length,
1662 PAGE_SIZE);
1663 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1664 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1665 }
00cd122a
JR		 1666 }
1667
1668 /*
1669 * Check for areas already mapped as present in the new aperture
1670 * range and mark those pages as reserved in the allocator. Such
1671 * mappings may already exist as a result of requested unity
1672 * mappings for devices.
1673 */
1674 for (i = dma_dom->aperture[index]->offset;
1675 i < dma_dom->aperture_size;
1676 i += PAGE_SIZE) {
24cd7723 1677 u64 *pte = fetch_pte(&dma_dom->domain, i);
00cd122a
JR		 1678 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1679 continue;
1680
fcd0861d 1681 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
00cd122a
JR		 1682 }
1683
04bfdd84
JR		 1684 update_domain(&dma_dom->domain);
1685
9cabe89b
JR		 1686 return 0;
1687
1688out_free:
04bfdd84
JR		 1689 update_domain(&dma_dom->domain);
1690
9cabe89b
JR		 1691 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1692
1693 kfree(dma_dom->aperture[index]);
1694 dma_dom->aperture[index] = NULL;
1695
1696 return -ENOMEM;
1697}
1698
384de729
JR		 1699static unsigned long dma_ops_area_alloc(struct device *dev,
1700 struct dma_ops_domain *dom,
1701 unsigned int pages,
1702 unsigned long align_mask,
1703 u64 dma_mask,
1704 unsigned long start)
1705{
803b8cb4 1706 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
384de729
JR		 1707 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1708 int i = start >> APERTURE_RANGE_SHIFT;
1709 unsigned long boundary_size;
1710 unsigned long address = -1;
1711 unsigned long limit;
1712
803b8cb4
JR		 1713 next_bit >>= PAGE_SHIFT;
1714
384de729
JR		 1715 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1716 PAGE_SIZE) >> PAGE_SHIFT;
1717
1718 for (;i < max_index; ++i) {
1719 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1720
1721 if (dom->aperture[i]->offset >= dma_mask)
1722 break;
1723
1724 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1725 dma_mask >> PAGE_SHIFT);
1726
1727 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1728 limit, next_bit, pages, 0,
1729 boundary_size, align_mask);
1730 if (address != -1) {
1731 address = dom->aperture[i]->offset +
1732 (address << PAGE_SHIFT);
803b8cb4 1733 dom->next_address = address + (pages << PAGE_SHIFT);
384de729
JR		 1734 break;
1735 }
1736
1737 next_bit = 0;
1738 }
1739
1740 return address;
1741}
1742
d3086444
JR		 1743static unsigned long dma_ops_alloc_addresses(struct device *dev,
1744 struct dma_ops_domain *dom,
6d4f343f 1745 unsigned int pages,
832a90c3
JR		 1746 unsigned long align_mask,
1747 u64 dma_mask)
d3086444 1748{
d3086444 1749 unsigned long address;
d3086444 1750
fe16f088
JR		 1751#ifdef CONFIG_IOMMU_STRESS
1752 dom->next_address = 0;
1753 dom->need_flush = true;
1754#endif
d3086444 1755
384de729 1756 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
803b8cb4 1757 dma_mask, dom->next_address);
d3086444 1758
1c655773 1759 if (address == -1) {
803b8cb4 1760 dom->next_address = 0;
384de729
JR		 1761 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1762 dma_mask, 0);
1c655773
JR		 1763 dom->need_flush = true;
1764 }
d3086444 1765
384de729 1766 if (unlikely(address == -1))
8fd524b3 1767 address = DMA_ERROR_CODE;
d3086444
JR		 1768
1769 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1770
1771 return address;
1772}
1773
431b2a20
JR		 1774/*
1775 * The address free function.
1776 *
1777 * called with domain->lock held
1778 */
d3086444
JR		 1779static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1780 unsigned long address,
1781 unsigned int pages)
1782{
384de729
JR		 1783 unsigned i = address >> APERTURE_RANGE_SHIFT;
1784 struct aperture_range *range = dom->aperture[i];
80be308d 1785
384de729
JR		 1786 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1787
47bccd6b
JR		 1788#ifdef CONFIG_IOMMU_STRESS
1789 if (i < 4)
1790 return;
1791#endif
80be308d 1792
803b8cb4 1793 if (address >= dom->next_address)
80be308d 1794 dom->need_flush = true;
384de729
JR		 1795
1796 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
803b8cb4 1797
a66022c4 1798 bitmap_clear(range->bitmap, address, pages);
384de729 1799
d3086444
JR		 1800}
1801
431b2a20
JR		 1802/****************************************************************************
1803 *
1804 * The next functions belong to the domain allocation. A domain is
1805 * allocated for every IOMMU as the default domain. If device isolation
1806 * is enabled, every device get its own domain. The most important thing
1807 * about domains is the page table mapping the DMA address space they
1808 * contain.
1809 *
1810 ****************************************************************************/
1811
aeb26f55
JR		 1812/*
1813 * This function adds a protection domain to the global protection domain list
1814 */
1815static void add_domain_to_list(struct protection_domain *domain)
1816{
1817 unsigned long flags;
1818
1819 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1820 list_add(&domain->list, &amd_iommu_pd_list);
1821 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1822}
1823
1824/*
1825 * This function removes a protection domain to the global
1826 * protection domain list
1827 */
1828static void del_domain_from_list(struct protection_domain *domain)
1829{
1830 unsigned long flags;
1831
1832 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1833 list_del(&domain->list);
1834 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1835}
1836
ec487d1a
JR		 1837static u16 domain_id_alloc(void)
1838{
1839 unsigned long flags;
1840 int id;
1841
1842 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1843 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1844 BUG_ON(id == 0);
1845 if (id > 0 && id < MAX_DOMAIN_ID)
1846 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1847 else
1848 id = 0;
1849 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1850
1851 return id;
1852}
1853
a2acfb75
JR		 1854static void domain_id_free(int id)
1855{
1856 unsigned long flags;
1857
1858 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1859 if (id > 0 && id < MAX_DOMAIN_ID)
1860 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1861 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1862}
a2acfb75 1863
5c34c403
JR		 1864#define DEFINE_FREE_PT_FN(LVL, FN) \
1865static void free_pt_##LVL (unsigned long __pt) \
1866{ \
1867 unsigned long p; \
1868 u64 *pt; \
1869 int i; \
1870 \
1871 pt = (u64 *)__pt; \
1872 \
1873 for (i = 0; i < 512; ++i) { \
1874 if (!IOMMU_PTE_PRESENT(pt[i])) \
1875 continue; \
1876 \
1877 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1878 FN(p); \
1879 } \
1880 free_page((unsigned long)pt); \
1881}
1882
1883DEFINE_FREE_PT_FN(l2, free_page)
1884DEFINE_FREE_PT_FN(l3, free_pt_l2)
1885DEFINE_FREE_PT_FN(l4, free_pt_l3)
1886DEFINE_FREE_PT_FN(l5, free_pt_l4)
1887DEFINE_FREE_PT_FN(l6, free_pt_l5)
1888
86db2e5d 1889static void free_pagetable(struct protection_domain *domain)
ec487d1a 1890{
5c34c403 1891 unsigned long root = (unsigned long)domain->pt_root;
ec487d1a 1892
5c34c403
JR		 1893 switch (domain->mode) {
1894 case PAGE_MODE_NONE:
1895 break;
1896 case PAGE_MODE_1_LEVEL:
1897 free_page(root);
1898 break;
1899 case PAGE_MODE_2_LEVEL:
1900 free_pt_l2(root);
1901 break;
1902 case PAGE_MODE_3_LEVEL:
1903 free_pt_l3(root);
1904 break;
1905 case PAGE_MODE_4_LEVEL:
1906 free_pt_l4(root);
1907 break;
1908 case PAGE_MODE_5_LEVEL:
1909 free_pt_l5(root);
1910 break;
1911 case PAGE_MODE_6_LEVEL:
1912 free_pt_l6(root);
1913 break;
1914 default:
1915 BUG();
ec487d1a 1916 }
ec487d1a
JR		 1917}
1918
b16137b1
JR		 1919static void free_gcr3_tbl_level1(u64 *tbl)
1920{
1921 u64 *ptr;
1922 int i;
1923
1924 for (i = 0; i < 512; ++i) {
1925 if (!(tbl[i] & GCR3_VALID))
1926 continue;
1927
1928 ptr = __va(tbl[i] & PAGE_MASK);
1929
1930 free_page((unsigned long)ptr);
1931 }
1932}
1933
1934static void free_gcr3_tbl_level2(u64 *tbl)
1935{
1936 u64 *ptr;
1937 int i;
1938
1939 for (i = 0; i < 512; ++i) {
1940 if (!(tbl[i] & GCR3_VALID))
1941 continue;
1942
1943 ptr = __va(tbl[i] & PAGE_MASK);
1944
1945 free_gcr3_tbl_level1(ptr);
1946 }
1947}
1948
52815b75
JR		 1949static void free_gcr3_table(struct protection_domain *domain)
1950{
b16137b1
JR		 1951 if (domain->glx == 2)
1952 free_gcr3_tbl_level2(domain->gcr3_tbl);
1953 else if (domain->glx == 1)
1954 free_gcr3_tbl_level1(domain->gcr3_tbl);
1955 else if (domain->glx != 0)
1956 BUG();
1957
52815b75
JR		 1958 free_page((unsigned long)domain->gcr3_tbl);
1959}
1960
431b2a20
JR		 1961/*
1962 * Free a domain, only used if something went wrong in the
1963 * allocation path and we need to free an already allocated page table
1964 */
ec487d1a
JR		 1965static void dma_ops_domain_free(struct dma_ops_domain *dom)
1966{
384de729
JR		 1967 int i;
1968
ec487d1a
JR		 1969 if (!dom)
1970 return;
1971
aeb26f55
JR		 1972 del_domain_from_list(&dom->domain);
1973
86db2e5d 1974 free_pagetable(&dom->domain);
ec487d1a 1975
384de729
JR		 1976 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1977 if (!dom->aperture[i])
1978 continue;
1979 free_page((unsigned long)dom->aperture[i]->bitmap);
1980 kfree(dom->aperture[i]);
1981 }
ec487d1a
JR		 1982
1983 kfree(dom);
1984}
1985
431b2a20
JR		 1986/*
1987 * Allocates a new protection domain usable for the dma_ops functions.
b595076a 1988 * It also initializes the page table and the address allocator data
431b2a20
JR		 1989 * structures required for the dma_ops interface
1990 */
87a64d52 1991static struct dma_ops_domain *dma_ops_domain_alloc(void)
ec487d1a
JR		 1992{
1993 struct dma_ops_domain *dma_dom;
ec487d1a
JR		 1994
1995 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1996 if (!dma_dom)
1997 return NULL;
1998
1999 spin_lock_init(&dma_dom->domain.lock);
2000
2001 dma_dom->domain.id = domain_id_alloc();
2002 if (dma_dom->domain.id == 0)
2003 goto free_dma_dom;
7c392cbe 2004 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
8f7a017c 2005 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
ec487d1a 2006 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
9fdb19d6 2007 dma_dom->domain.flags = PD_DMA_OPS_MASK;
ec487d1a
JR		 2008 dma_dom->domain.priv = dma_dom;
2009 if (!dma_dom->domain.pt_root)
2010 goto free_dma_dom;
ec487d1a 2011
1c655773 2012 dma_dom->need_flush = false;
bd60b735 2013 dma_dom->target_dev = 0xffff;
1c655773 2014
aeb26f55
JR		 2015 add_domain_to_list(&dma_dom->domain);
2016
576175c2 2017 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
ec487d1a 2018 goto free_dma_dom;
ec487d1a 2019
431b2a20 2020 /*
ec487d1a
JR		 2021 * mark the first page as allocated so we never return 0 as
2022 * a valid dma-address. So we can use 0 as error value
431b2a20 2023 */
384de729 2024 dma_dom->aperture[0]->bitmap[0] = 1;
803b8cb4 2025 dma_dom->next_address = 0;
ec487d1a 2026
ec487d1a
JR		 2027
2028 return dma_dom;
2029
2030free_dma_dom:
2031 dma_ops_domain_free(dma_dom);
2032
2033 return NULL;
2034}
2035
5b28df6f
JR		 2036/*
2037 * little helper function to check whether a given protection domain is a
2038 * dma_ops domain
2039 */
2040static bool dma_ops_domain(struct protection_domain *domain)
2041{
2042 return domain->flags & PD_DMA_OPS_MASK;
2043}
2044
fd7b5535 2045static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
b20ac0d4 2046{
132bd68f 2047 u64 pte_root = 0;
ee6c2868 2048 u64 flags = 0;
863c74eb 2049
132bd68f
JR		 2050 if (domain->mode != PAGE_MODE_NONE)
2051 pte_root = virt_to_phys(domain->pt_root);
2052
38ddf41b
JR		 2053 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2054 << DEV_ENTRY_MODE_SHIFT;
2055 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
b20ac0d4 2056
ee6c2868
JR		 2057 flags = amd_iommu_dev_table[devid].data[1];
2058
fd7b5535
JR		 2059 if (ats)
2060 flags |= DTE_FLAG_IOTLB;
2061
52815b75
JR		 2062 if (domain->flags & PD_IOMMUV2_MASK) {
2063 u64 gcr3 = __pa(domain->gcr3_tbl);
2064 u64 glx = domain->glx;
2065 u64 tmp;
2066
2067 pte_root |= DTE_FLAG_GV;
2068 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2069
2070 /* First mask out possible old values for GCR3 table */
2071 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2072 flags &= ~tmp;
2073
2074 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2075 flags &= ~tmp;
2076
2077 /* Encode GCR3 table into DTE */
2078 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2079 pte_root |= tmp;
2080
2081 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2082 flags |= tmp;
2083
2084 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2085 flags |= tmp;
2086 }
2087
ee6c2868
JR		 2088 flags &= ~(0xffffUL);
2089 flags |= domain->id;
2090
2091 amd_iommu_dev_table[devid].data[1] = flags;
2092 amd_iommu_dev_table[devid].data[0] = pte_root;
15898bbc
JR		 2093}
2094
2095static void clear_dte_entry(u16 devid)
2096{
15898bbc
JR		 2097 /* remove entry from the device table seen by the hardware */
2098 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2099 amd_iommu_dev_table[devid].data[1] = 0;
15898bbc
JR		 2100
2101 amd_iommu_apply_erratum_63(devid);
7f760ddd
JR		 2102}
2103
ec9e79ef
JR		 2104static void do_attach(struct iommu_dev_data *dev_data,
2105 struct protection_domain *domain)
7f760ddd 2106{
7f760ddd 2107 struct amd_iommu *iommu;
ec9e79ef 2108 bool ats;
fd7b5535 2109
ec9e79ef
JR		 2110 iommu = amd_iommu_rlookup_table[dev_data->devid];
2111 ats = dev_data->ats.enabled;
7f760ddd
JR		 2112
2113 /* Update data structures */
2114 dev_data->domain = domain;
2115 list_add(&dev_data->list, &domain->dev_list);
f62dda66 2116 set_dte_entry(dev_data->devid, domain, ats);
7f760ddd
JR		 2117
2118 /* Do reference counting */
2119 domain->dev_iommu[iommu->index] += 1;
2120 domain->dev_cnt += 1;
2121
2122 /* Flush the DTE entry */
6c542047 2123 device_flush_dte(dev_data);
7f760ddd
JR		 2124}
2125
ec9e79ef 2126static void do_detach(struct iommu_dev_data *dev_data)
7f760ddd 2127{
7f760ddd 2128 struct amd_iommu *iommu;
7f760ddd 2129
ec9e79ef 2130 iommu = amd_iommu_rlookup_table[dev_data->devid];
15898bbc
JR		 2131
2132 /* decrease reference counters */
7f760ddd
JR		 2133 dev_data->domain->dev_iommu[iommu->index] -= 1;
2134 dev_data->domain->dev_cnt -= 1;
2135
2136 /* Update data structures */
2137 dev_data->domain = NULL;
2138 list_del(&dev_data->list);
f62dda66 2139 clear_dte_entry(dev_data->devid);
15898bbc 2140
7f760ddd 2141 /* Flush the DTE entry */
6c542047 2142 device_flush_dte(dev_data);
2b681faf
JR		 2143}
2144
2145/*
2146 * If a device is not yet associated with a domain, this function does
2147 * assigns it visible for the hardware
2148 */
ec9e79ef 2149static int __attach_device(struct iommu_dev_data *dev_data,
15898bbc 2150 struct protection_domain *domain)
2b681faf 2151{
397111ab 2152 struct iommu_dev_data *head, *entry;
84fe6c19 2153 int ret;
657cbb6b 2154
2b681faf
JR		 2155 /* lock domain */
2156 spin_lock(&domain->lock);
2157
397111ab 2158 head = dev_data;
15898bbc 2159
397111ab
JR		 2160 if (head->alias_data != NULL)
2161 head = head->alias_data;
eba6ac60 2162
397111ab 2163 /* Now we have the root of the alias group, if any */
15898bbc 2164
397111ab
JR		 2165 ret = -EBUSY;
2166 if (head->domain != NULL)
2167 goto out_unlock;
15898bbc 2168
397111ab
JR		 2169 /* Attach alias group root */
2170 do_attach(head, domain);
eba6ac60 2171
397111ab
JR		 2172 /* Attach other devices in the alias group */
2173 list_for_each_entry(entry, &head->alias_list, alias_list)
2174 do_attach(entry, domain);
24100055 2175
84fe6c19
JL		 2176 ret = 0;
2177
2178out_unlock:
2179
eba6ac60
JR		 2180 /* ready */
2181 spin_unlock(&domain->lock);
15898bbc 2182
84fe6c19 2183 return ret;
0feae533 2184}
b20ac0d4 2185
52815b75
JR		 2186
2187static void pdev_iommuv2_disable(struct pci_dev *pdev)
2188{
2189 pci_disable_ats(pdev);
2190 pci_disable_pri(pdev);
2191 pci_disable_pasid(pdev);
2192}
2193
6a113ddc
JR		 2194/* FIXME: Change generic reset-function to do the same */
2195static int pri_reset_while_enabled(struct pci_dev *pdev)
2196{
2197 u16 control;
2198 int pos;
2199
46277b75 2200 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
6a113ddc
JR		 2201 if (!pos)
2202 return -EINVAL;
2203
46277b75
JR		 2204 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2205 control |= PCI_PRI_CTRL_RESET;
2206 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
6a113ddc
JR		 2207
2208 return 0;
2209}
2210
52815b75
JR		 2211static int pdev_iommuv2_enable(struct pci_dev *pdev)
2212{
6a113ddc
JR		 2213 bool reset_enable;
2214 int reqs, ret;
2215
2216 /* FIXME: Hardcode number of outstanding requests for now */
2217 reqs = 32;
2218 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2219 reqs = 1;
2220 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
52815b75
JR		 2221
2222 /* Only allow access to user-accessible pages */
2223 ret = pci_enable_pasid(pdev, 0);
2224 if (ret)
2225 goto out_err;
2226
2227 /* First reset the PRI state of the device */
2228 ret = pci_reset_pri(pdev);
2229 if (ret)
2230 goto out_err;
2231
6a113ddc
JR		 2232 /* Enable PRI */
2233 ret = pci_enable_pri(pdev, reqs);
52815b75
JR		 2234 if (ret)
2235 goto out_err;
2236
6a113ddc
JR		 2237 if (reset_enable) {
2238 ret = pri_reset_while_enabled(pdev);
2239 if (ret)
2240 goto out_err;
2241 }
2242
52815b75
JR		 2243 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2244 if (ret)
2245 goto out_err;
2246
2247 return 0;
2248
2249out_err:
2250 pci_disable_pri(pdev);
2251 pci_disable_pasid(pdev);
2252
2253 return ret;
2254}
2255
c99afa25 2256/* FIXME: Move this to PCI code */
a3b93121 2257#define PCI_PRI_TLP_OFF (1 << 15)
c99afa25 2258
98f1ad25 2259static bool pci_pri_tlp_required(struct pci_dev *pdev)
c99afa25 2260{
a3b93121 2261 u16 status;
c99afa25
JR		 2262 int pos;
2263
46277b75 2264 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c99afa25
JR		 2265 if (!pos)
2266 return false;
2267
a3b93121 2268 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
c99afa25 2269
a3b93121 2270 return (status & PCI_PRI_TLP_OFF) ? true : false;
c99afa25
JR		 2271}
2272
407d733e 2273/*
df805abb 2274 * If a device is not yet associated with a domain, this function
407d733e
JR		 2275 * assigns it visible for the hardware
2276 */
15898bbc
JR		 2277static int attach_device(struct device *dev,
2278 struct protection_domain *domain)
0feae533 2279{
fd7b5535 2280 struct pci_dev *pdev = to_pci_dev(dev);
ea61cddb 2281 struct iommu_dev_data *dev_data;
eba6ac60 2282 unsigned long flags;
15898bbc 2283 int ret;
eba6ac60 2284
ea61cddb
JR		 2285 dev_data = get_dev_data(dev);
2286
52815b75
JR		 2287 if (domain->flags & PD_IOMMUV2_MASK) {
2288 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2289 return -EINVAL;
2290
2291 if (pdev_iommuv2_enable(pdev) != 0)
2292 return -EINVAL;
2293
2294 dev_data->ats.enabled = true;
2295 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
c99afa25 2296 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
52815b75
JR		 2297 } else if (amd_iommu_iotlb_sup &&
2298 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
ea61cddb
JR		 2299 dev_data->ats.enabled = true;
2300 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2301 }
fd7b5535 2302
eba6ac60 2303 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2304 ret = __attach_device(dev_data, domain);
b20ac0d4
JR		 2305 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2306
0feae533
JR		 2307 /*
2308 * We might boot into a crash-kernel here. The crashed kernel
2309 * left the caches in the IOMMU dirty. So we have to flush
2310 * here to evict all dirty stuff.
2311 */
17b124bf 2312 domain_flush_tlb_pde(domain);
15898bbc
JR		 2313
2314 return ret;
b20ac0d4
JR		 2315}
2316
355bf553
JR		 2317/*
2318 * Removes a device from a protection domain (unlocked)
2319 */
ec9e79ef 2320static void __detach_device(struct iommu_dev_data *dev_data)
355bf553 2321{
397111ab 2322 struct iommu_dev_data *head, *entry;
2ca76279 2323 struct protection_domain *domain;
7c392cbe 2324 unsigned long flags;
c4596114 2325
7f760ddd 2326 BUG_ON(!dev_data->domain);
355bf553 2327
2ca76279
JR		 2328 domain = dev_data->domain;
2329
2330 spin_lock_irqsave(&domain->lock, flags);
24100055 2331
397111ab
JR		 2332 head = dev_data;
2333 if (head->alias_data != NULL)
2334 head = head->alias_data;
71f77580 2335
397111ab
JR		 2336 list_for_each_entry(entry, &head->alias_list, alias_list)
2337 do_detach(entry);
24100055 2338
397111ab 2339 do_detach(head);
7f760ddd 2340
2ca76279 2341 spin_unlock_irqrestore(&domain->lock, flags);
21129f78
JR		 2342
2343 /*
2344 * If we run in passthrough mode the device must be assigned to the
d3ad9373
JR		 2345 * passthrough domain if it is detached from any other domain.
2346 * Make sure we can deassign from the pt_domain itself.
21129f78 2347 */
5abcdba4 2348 if (dev_data->passthrough &&
d3ad9373 2349 (dev_data->domain == NULL && domain != pt_domain))
ec9e79ef 2350 __attach_device(dev_data, pt_domain);
355bf553
JR		 2351}
2352
2353/*
2354 * Removes a device from a protection domain (with devtable_lock held)
2355 */
15898bbc 2356static void detach_device(struct device *dev)
355bf553 2357{
52815b75 2358 struct protection_domain *domain;
ea61cddb 2359 struct iommu_dev_data *dev_data;
355bf553
JR		 2360 unsigned long flags;
2361
ec9e79ef 2362 dev_data = get_dev_data(dev);
52815b75 2363 domain = dev_data->domain;
ec9e79ef 2364
355bf553
JR		 2365 /* lock device table */
2366 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2367 __detach_device(dev_data);
355bf553 2368 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
fd7b5535 2369
52815b75
JR		 2370 if (domain->flags & PD_IOMMUV2_MASK)
2371 pdev_iommuv2_disable(to_pci_dev(dev));
2372 else if (dev_data->ats.enabled)
ea61cddb 2373 pci_disable_ats(to_pci_dev(dev));
52815b75
JR		 2374
2375 dev_data->ats.enabled = false;
355bf553 2376}
e275a2a0 2377
15898bbc
JR		 2378/*
2379 * Find out the protection domain structure for a given PCI device. This
2380 * will give us the pointer to the page table root for example.
2381 */
2382static struct protection_domain *domain_for_device(struct device *dev)
2383{
71f77580 2384 struct iommu_dev_data *dev_data;
2b02b091 2385 struct protection_domain *dom = NULL;
15898bbc 2386 unsigned long flags;
15898bbc 2387
657cbb6b 2388 dev_data = get_dev_data(dev);
15898bbc 2389
2b02b091
JR		 2390 if (dev_data->domain)
2391 return dev_data->domain;
15898bbc 2392
71f77580
JR		 2393 if (dev_data->alias_data != NULL) {
2394 struct iommu_dev_data *alias_data = dev_data->alias_data;
2b02b091
JR		 2395
2396 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2397 if (alias_data->domain != NULL) {
2398 __attach_device(dev_data, alias_data->domain);
2399 dom = alias_data->domain;
2400 }
2401 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2402 }
15898bbc
JR		 2403
2404 return dom;
2405}
2406
e275a2a0
JR		 2407static int device_change_notifier(struct notifier_block *nb,
2408 unsigned long action, void *data)
2409{
e275a2a0 2410 struct dma_ops_domain *dma_domain;
5abcdba4
JR		 2411 struct protection_domain *domain;
2412 struct iommu_dev_data *dev_data;
2413 struct device *dev = data;
e275a2a0 2414 struct amd_iommu *iommu;
1ac4cbbc 2415 unsigned long flags;
5abcdba4 2416 u16 devid;
e275a2a0 2417
98fc5a69
JR		 2418 if (!check_device(dev))
2419 return 0;
e275a2a0 2420
5abcdba4
JR		 2421 devid = get_device_id(dev);
2422 iommu = amd_iommu_rlookup_table[devid];
2423 dev_data = get_dev_data(dev);
e275a2a0
JR		 2424
2425 switch (action) {
1ac4cbbc 2426 case BUS_NOTIFY_ADD_DEVICE:
657cbb6b
JR		 2427
2428 iommu_init_device(dev);
25b11ce2 2429 init_iommu_group(dev);
657cbb6b 2430
2c9195e9
JR		 2431 /*
2432 * dev_data is still NULL and
2433 * got initialized in iommu_init_device
2434 */
2435 dev_data = get_dev_data(dev);
2436
2437 if (iommu_pass_through || dev_data->iommu_v2) {
2438 dev_data->passthrough = true;
2439 attach_device(dev, pt_domain);
2440 break;
2441 }
2442
657cbb6b
JR		 2443 domain = domain_for_device(dev);
2444
1ac4cbbc
JR		 2445 /* allocate a protection domain if a device is added */
2446 dma_domain = find_protection_domain(devid);
c2a2876e
JR		 2447 if (!dma_domain) {
2448 dma_domain = dma_ops_domain_alloc();
2449 if (!dma_domain)
2450 goto out;
2451 dma_domain->target_dev = devid;
2452
2453 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2454 list_add_tail(&dma_domain->list, &iommu_pd_list);
2455 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2456 }
ac1534a5 2457
2c9195e9 2458 dev->archdata.dma_ops = &amd_iommu_dma_ops;
ac1534a5 2459
e275a2a0 2460 break;
6c5cc801 2461 case BUS_NOTIFY_REMOVED_DEVICE:
657cbb6b
JR		 2462
2463 iommu_uninit_device(dev);
2464
e275a2a0
JR		 2465 default:
2466 goto out;
2467 }
2468
e275a2a0
JR		 2469 iommu_completion_wait(iommu);
2470
2471out:
2472 return 0;
2473}
2474
b25ae679 2475static struct notifier_block device_nb = {
e275a2a0
JR		 2476 .notifier_call = device_change_notifier,
2477};
355bf553 2478
8638c491
JR		 2479void amd_iommu_init_notifier(void)
2480{
2481 bus_register_notifier(&pci_bus_type, &device_nb);
2482}
2483
431b2a20
JR		 2484/*****************************************************************************
2485 *
2486 * The next functions belong to the dma_ops mapping/unmapping code.
2487 *
2488 *****************************************************************************/
2489
2490/*
2491 * In the dma_ops path we only have the struct device. This function
2492 * finds the corresponding IOMMU, the protection domain and the
2493 * requestor id for a given device.
2494 * If the device is not yet associated with a domain this is also done
2495 * in this function.
2496 */
94f6d190 2497static struct protection_domain *get_domain(struct device *dev)
b20ac0d4 2498{
94f6d190 2499 struct protection_domain *domain;
b20ac0d4 2500 struct dma_ops_domain *dma_dom;
94f6d190 2501 u16 devid = get_device_id(dev);
b20ac0d4 2502
f99c0f1c 2503 if (!check_device(dev))
94f6d190 2504 return ERR_PTR(-EINVAL);
b20ac0d4 2505
94f6d190
JR		 2506 domain = domain_for_device(dev);
2507 if (domain != NULL && !dma_ops_domain(domain))
2508 return ERR_PTR(-EBUSY);
f99c0f1c 2509
94f6d190
JR		 2510 if (domain != NULL)
2511 return domain;
b20ac0d4 2512
df805abb 2513 /* Device not bound yet - bind it */
94f6d190 2514 dma_dom = find_protection_domain(devid);
15898bbc 2515 if (!dma_dom)
94f6d190
JR		 2516 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2517 attach_device(dev, &dma_dom->domain);
15898bbc 2518 DUMP_printk("Using protection domain %d for device %s\n",
94f6d190 2519 dma_dom->domain.id, dev_name(dev));
f91ba190 2520
94f6d190 2521 return &dma_dom->domain;
b20ac0d4
JR		 2522}
2523
04bfdd84
JR		 2524static void update_device_table(struct protection_domain *domain)
2525{
492667da 2526 struct iommu_dev_data *dev_data;
04bfdd84 2527
ea61cddb
JR		 2528 list_for_each_entry(dev_data, &domain->dev_list, list)
2529 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
04bfdd84
JR		 2530}
2531
2532static void update_domain(struct protection_domain *domain)
2533{
2534 if (!domain->updated)
2535 return;
2536
2537 update_device_table(domain);
17b124bf
JR		 2538
2539 domain_flush_devices(domain);
2540 domain_flush_tlb_pde(domain);
04bfdd84
JR		 2541
2542 domain->updated = false;
2543}
2544
8bda3092
JR		 2545/*
2546 * This function fetches the PTE for a given address in the aperture
2547 */
2548static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2549 unsigned long address)
2550{
384de729 2551 struct aperture_range *aperture;
8bda3092
JR		 2552 u64 *pte, *pte_page;
2553
384de729
JR		 2554 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2555 if (!aperture)
2556 return NULL;
2557
2558 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
8bda3092 2559 if (!pte) {
cbb9d729 2560 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
abdc5eb3 2561 GFP_ATOMIC);
384de729
JR		 2562 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2563 } else
8c8c143c 2564 pte += PM_LEVEL_INDEX(0, address);
8bda3092 2565
04bfdd84 2566 update_domain(&dom->domain);
8bda3092
JR		 2567
2568 return pte;
2569}
2570
431b2a20
JR		 2571/*
2572 * This is the generic map function. It maps one 4kb page at paddr to
2573 * the given address in the DMA address space for the domain.
2574 */
680525e0 2575static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
cb76c322
JR		 2576 unsigned long address,
2577 phys_addr_t paddr,
2578 int direction)
2579{
2580 u64 *pte, __pte;
2581
2582 WARN_ON(address > dom->aperture_size);
2583
2584 paddr &= PAGE_MASK;
2585
8bda3092 2586 pte = dma_ops_get_pte(dom, address);
53812c11 2587 if (!pte)
8fd524b3 2588 return DMA_ERROR_CODE;
cb76c322
JR		 2589
2590 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2591
2592 if (direction == DMA_TO_DEVICE)
2593 __pte |= IOMMU_PTE_IR;
2594 else if (direction == DMA_FROM_DEVICE)
2595 __pte |= IOMMU_PTE_IW;
2596 else if (direction == DMA_BIDIRECTIONAL)
2597 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2598
2599 WARN_ON(*pte);
2600
2601 *pte = __pte;
2602
2603 return (dma_addr_t)address;
2604}
2605
431b2a20
JR		 2606/*
2607 * The generic unmapping function for on page in the DMA address space.
2608 */
680525e0 2609static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
cb76c322
JR		 2610 unsigned long address)
2611{
384de729 2612 struct aperture_range *aperture;
cb76c322
JR		 2613 u64 *pte;
2614
2615 if (address >= dom->aperture_size)
2616 return;
2617
384de729
JR		 2618 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2619 if (!aperture)
2620 return;
2621
2622 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2623 if (!pte)
2624 return;
cb76c322 2625
8c8c143c 2626 pte += PM_LEVEL_INDEX(0, address);
cb76c322
JR		 2627
2628 WARN_ON(!*pte);
2629
2630 *pte = 0ULL;
2631}
2632
431b2a20
JR		 2633/*
2634 * This function contains common code for mapping of a physically
24f81160
JR		 2635 * contiguous memory region into DMA address space. It is used by all
2636 * mapping functions provided with this IOMMU driver.
431b2a20
JR		 2637 * Must be called with the domain lock held.
2638 */
cb76c322 2639static dma_addr_t __map_single(struct device *dev,
cb76c322
JR		 2640 struct dma_ops_domain *dma_dom,
2641 phys_addr_t paddr,
2642 size_t size,
6d4f343f 2643 int dir,
832a90c3
JR		 2644 bool align,
2645 u64 dma_mask)
cb76c322
JR		 2646{
2647 dma_addr_t offset = paddr & ~PAGE_MASK;
53812c11 2648 dma_addr_t address, start, ret;
cb76c322 2649 unsigned int pages;
6d4f343f 2650 unsigned long align_mask = 0;
cb76c322
JR		 2651 int i;
2652
e3c449f5 2653 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
cb76c322
JR		 2654 paddr &= PAGE_MASK;
2655
8ecaf8f1
JR		 2656 INC_STATS_COUNTER(total_map_requests);
2657
c1858976
JR		 2658 if (pages > 1)
2659 INC_STATS_COUNTER(cross_page);
2660
6d4f343f
JR		 2661 if (align)
2662 align_mask = (1UL << get_order(size)) - 1;
2663
11b83888 2664retry:
832a90c3
JR		 2665 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2666 dma_mask);
8fd524b3 2667 if (unlikely(address == DMA_ERROR_CODE)) {
11b83888
JR		 2668 /*
2669 * setting next_address here will let the address
2670 * allocator only scan the new allocated range in the
2671 * first run. This is a small optimization.
2672 */
2673 dma_dom->next_address = dma_dom->aperture_size;
2674
576175c2 2675 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
11b83888
JR		 2676 goto out;
2677
2678 /*
af901ca1 2679 * aperture was successfully enlarged by 128 MB, try
11b83888
JR		 2680 * allocation again
2681 */
2682 goto retry;
2683 }
cb76c322
JR		 2684
2685 start = address;
2686 for (i = 0; i < pages; ++i) {
680525e0 2687 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
8fd524b3 2688 if (ret == DMA_ERROR_CODE)
53812c11
JR		 2689 goto out_unmap;
2690
cb76c322
JR		 2691 paddr += PAGE_SIZE;
2692 start += PAGE_SIZE;
2693 }
2694 address += offset;
2695
5774f7c5
JR		 2696 ADD_STATS_COUNTER(alloced_io_mem, size);
2697
afa9fdc2 2698 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
17b124bf 2699 domain_flush_tlb(&dma_dom->domain);
1c655773 2700 dma_dom->need_flush = false;
318afd41 2701 } else if (unlikely(amd_iommu_np_cache))
17b124bf 2702 domain_flush_pages(&dma_dom->domain, address, size);
270cab24 2703
cb76c322
JR		 2704out:
2705 return address;
53812c11
JR		 2706
2707out_unmap:
2708
2709 for (--i; i >= 0; --i) {
2710 start -= PAGE_SIZE;
680525e0 2711 dma_ops_domain_unmap(dma_dom, start);
53812c11
JR		 2712 }
2713
2714 dma_ops_free_addresses(dma_dom, address, pages);
2715
8fd524b3 2716 return DMA_ERROR_CODE;
cb76c322
JR		 2717}
2718
431b2a20
JR		 2719/*
2720 * Does the reverse of the __map_single function. Must be called with
2721 * the domain lock held too
2722 */
cd8c82e8 2723static void __unmap_single(struct dma_ops_domain *dma_dom,
cb76c322
JR		 2724 dma_addr_t dma_addr,
2725 size_t size,
2726 int dir)
2727{
04e0463e 2728 dma_addr_t flush_addr;
cb76c322
JR		 2729 dma_addr_t i, start;
2730 unsigned int pages;
2731
8fd524b3 2732 if ((dma_addr == DMA_ERROR_CODE) ||
b8d9905d 2733 (dma_addr + size > dma_dom->aperture_size))
cb76c322
JR		 2734 return;
2735
04e0463e 2736 flush_addr = dma_addr;
e3c449f5 2737 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
cb76c322
JR		 2738 dma_addr &= PAGE_MASK;
2739 start = dma_addr;
2740
2741 for (i = 0; i < pages; ++i) {
680525e0 2742 dma_ops_domain_unmap(dma_dom, start);
cb76c322
JR		 2743 start += PAGE_SIZE;
2744 }
2745
5774f7c5
JR		 2746 SUB_STATS_COUNTER(alloced_io_mem, size);
2747
cb76c322 2748 dma_ops_free_addresses(dma_dom, dma_addr, pages);
270cab24 2749
80be308d 2750 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
17b124bf 2751 domain_flush_pages(&dma_dom->domain, flush_addr, size);
80be308d
JR		 2752 dma_dom->need_flush = false;
2753 }
cb76c322
JR		 2754}
2755
431b2a20
JR		 2756/*
2757 * The exported map_single function for dma_ops.
2758 */
51491367
FT		 2759static dma_addr_t map_page(struct device *dev, struct page *page,
2760 unsigned long offset, size_t size,
2761 enum dma_data_direction dir,
2762 struct dma_attrs *attrs)
4da70b9e
JR		 2763{
2764 unsigned long flags;
4da70b9e 2765 struct protection_domain *domain;
4da70b9e 2766 dma_addr_t addr;
832a90c3 2767 u64 dma_mask;
51491367 2768 phys_addr_t paddr = page_to_phys(page) + offset;
4da70b9e 2769
0f2a86f2
JR		 2770 INC_STATS_COUNTER(cnt_map_single);
2771
94f6d190
JR		 2772 domain = get_domain(dev);
2773 if (PTR_ERR(domain) == -EINVAL)
4da70b9e 2774 return (dma_addr_t)paddr;
94f6d190
JR		 2775 else if (IS_ERR(domain))
2776 return DMA_ERROR_CODE;
4da70b9e 2777
f99c0f1c
JR		 2778 dma_mask = *dev->dma_mask;
2779
4da70b9e 2780 spin_lock_irqsave(&domain->lock, flags);
94f6d190 2781
cd8c82e8 2782 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
832a90c3 2783 dma_mask);
8fd524b3 2784 if (addr == DMA_ERROR_CODE)
4da70b9e
JR		 2785 goto out;
2786
17b124bf 2787 domain_flush_complete(domain);
4da70b9e
JR		 2788
2789out:
2790 spin_unlock_irqrestore(&domain->lock, flags);
2791
2792 return addr;
2793}
2794
431b2a20
JR		 2795/*
2796 * The exported unmap_single function for dma_ops.
2797 */
51491367
FT		 2798static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2799 enum dma_data_direction dir, struct dma_attrs *attrs)
4da70b9e
JR		 2800{
2801 unsigned long flags;
4da70b9e 2802 struct protection_domain *domain;
4da70b9e 2803
146a6917
JR		 2804 INC_STATS_COUNTER(cnt_unmap_single);
2805
94f6d190
JR		 2806 domain = get_domain(dev);
2807 if (IS_ERR(domain))
5b28df6f
JR		 2808 return;
2809
4da70b9e
JR		 2810 spin_lock_irqsave(&domain->lock, flags);
2811
cd8c82e8 2812 __unmap_single(domain->priv, dma_addr, size, dir);
4da70b9e 2813
17b124bf 2814 domain_flush_complete(domain);
4da70b9e
JR		 2815
2816 spin_unlock_irqrestore(&domain->lock, flags);
2817}
2818
431b2a20
JR		 2819/*
2820 * The exported map_sg function for dma_ops (handles scatter-gather
2821 * lists).
2822 */
65b050ad 2823static int map_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2824 int nelems, enum dma_data_direction dir,
2825 struct dma_attrs *attrs)
65b050ad
JR		 2826{
2827 unsigned long flags;
65b050ad 2828 struct protection_domain *domain;
65b050ad
JR		 2829 int i;
2830 struct scatterlist *s;
2831 phys_addr_t paddr;
2832 int mapped_elems = 0;
832a90c3 2833 u64 dma_mask;
65b050ad 2834
d03f067a
JR		 2835 INC_STATS_COUNTER(cnt_map_sg);
2836
94f6d190 2837 domain = get_domain(dev);
a0e191b2 2838 if (IS_ERR(domain))
94f6d190 2839 return 0;
dbcc112e 2840
832a90c3 2841 dma_mask = *dev->dma_mask;
65b050ad 2842
65b050ad
JR		 2843 spin_lock_irqsave(&domain->lock, flags);
2844
2845 for_each_sg(sglist, s, nelems, i) {
2846 paddr = sg_phys(s);
2847
cd8c82e8 2848 s->dma_address = __map_single(dev, domain->priv,
832a90c3
JR		 2849 paddr, s->length, dir, false,
2850 dma_mask);
65b050ad
JR		 2851
2852 if (s->dma_address) {
2853 s->dma_length = s->length;
2854 mapped_elems++;
2855 } else
2856 goto unmap;
65b050ad
JR		 2857 }
2858
17b124bf 2859 domain_flush_complete(domain);
65b050ad
JR		 2860
2861out:
2862 spin_unlock_irqrestore(&domain->lock, flags);
2863
2864 return mapped_elems;
2865unmap:
2866 for_each_sg(sglist, s, mapped_elems, i) {
2867 if (s->dma_address)
cd8c82e8 2868 __unmap_single(domain->priv, s->dma_address,
65b050ad
JR		 2869 s->dma_length, dir);
2870 s->dma_address = s->dma_length = 0;
2871 }
2872
2873 mapped_elems = 0;
2874
2875 goto out;
2876}
2877
431b2a20
JR		 2878/*
2879 * The exported map_sg function for dma_ops (handles scatter-gather
2880 * lists).
2881 */
65b050ad 2882static void unmap_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2883 int nelems, enum dma_data_direction dir,
2884 struct dma_attrs *attrs)
65b050ad
JR		 2885{
2886 unsigned long flags;
65b050ad
JR		 2887 struct protection_domain *domain;
2888 struct scatterlist *s;
65b050ad
JR		 2889 int i;
2890
55877a6b
JR		 2891 INC_STATS_COUNTER(cnt_unmap_sg);
2892
94f6d190
JR		 2893 domain = get_domain(dev);
2894 if (IS_ERR(domain))
5b28df6f
JR		 2895 return;
2896
65b050ad
JR		 2897 spin_lock_irqsave(&domain->lock, flags);
2898
2899 for_each_sg(sglist, s, nelems, i) {
cd8c82e8 2900 __unmap_single(domain->priv, s->dma_address,
65b050ad 2901 s->dma_length, dir);
65b050ad
JR		 2902 s->dma_address = s->dma_length = 0;
2903 }
2904
17b124bf 2905 domain_flush_complete(domain);
65b050ad
JR		 2906
2907 spin_unlock_irqrestore(&domain->lock, flags);
2908}
2909
431b2a20
JR		 2910/*
2911 * The exported alloc_coherent function for dma_ops.
2912 */
5d8b53cf 2913static void *alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 2914 dma_addr_t *dma_addr, gfp_t flag,
2915 struct dma_attrs *attrs)
5d8b53cf 2916{
832a90c3 2917 u64 dma_mask = dev->coherent_dma_mask;
3b839a57
JR		 2918 struct protection_domain *domain;
2919 unsigned long flags;
2920 struct page *page;
5d8b53cf 2921
c8f0fb36
JR		 2922 INC_STATS_COUNTER(cnt_alloc_coherent);
2923
94f6d190
JR		 2924 domain = get_domain(dev);
2925 if (PTR_ERR(domain) == -EINVAL) {
3b839a57
JR		 2926 page = alloc_pages(flag, get_order(size));
2927 *dma_addr = page_to_phys(page);
2928 return page_address(page);
94f6d190
JR		 2929 } else if (IS_ERR(domain))
2930 return NULL;
5d8b53cf 2931
3b839a57 2932 size = PAGE_ALIGN(size);
f99c0f1c
JR		 2933 dma_mask = dev->coherent_dma_mask;
2934 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
5d8b53cf 2935
3b839a57
JR		 2936 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2937 if (!page) {
2938 if (!(flag & __GFP_WAIT))
2939 return NULL;
5d8b53cf 2940
3b839a57
JR		 2941 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2942 get_order(size));
2943 if (!page)
2944 return NULL;
2945 }
5d8b53cf 2946
832a90c3
JR		 2947 if (!dma_mask)
2948 dma_mask = *dev->dma_mask;
2949
5d8b53cf
JR		 2950 spin_lock_irqsave(&domain->lock, flags);
2951
3b839a57 2952 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
832a90c3 2953 size, DMA_BIDIRECTIONAL, true, dma_mask);
5d8b53cf 2954
8fd524b3 2955 if (*dma_addr == DMA_ERROR_CODE) {
367d04c4 2956 spin_unlock_irqrestore(&domain->lock, flags);
5b28df6f 2957 goto out_free;
367d04c4 2958 }
5d8b53cf 2959
17b124bf 2960 domain_flush_complete(domain);
5d8b53cf 2961
5d8b53cf
JR		 2962 spin_unlock_irqrestore(&domain->lock, flags);
2963
3b839a57 2964 return page_address(page);
5b28df6f
JR		 2965
2966out_free:
2967
3b839a57
JR		 2968 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2969 __free_pages(page, get_order(size));
5b28df6f
JR		 2970
2971 return NULL;
5d8b53cf
JR		 2972}
2973
431b2a20
JR		 2974/*
2975 * The exported free_coherent function for dma_ops.
431b2a20 2976 */
5d8b53cf 2977static void free_coherent(struct device *dev, size_t size,
baa676fc
AP		 2978 void *virt_addr, dma_addr_t dma_addr,
2979 struct dma_attrs *attrs)
5d8b53cf 2980{
5d8b53cf 2981 struct protection_domain *domain;
3b839a57
JR		 2982 unsigned long flags;
2983 struct page *page;
5d8b53cf 2984
5d31ee7e
JR		 2985 INC_STATS_COUNTER(cnt_free_coherent);
2986
3b839a57
JR		 2987 page = virt_to_page(virt_addr);
2988 size = PAGE_ALIGN(size);
2989
94f6d190
JR		 2990 domain = get_domain(dev);
2991 if (IS_ERR(domain))
5b28df6f
JR		 2992 goto free_mem;
2993
5d8b53cf
JR		 2994 spin_lock_irqsave(&domain->lock, flags);
2995
cd8c82e8 2996 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
5d8b53cf 2997
17b124bf 2998 domain_flush_complete(domain);
5d8b53cf
JR		 2999
3000 spin_unlock_irqrestore(&domain->lock, flags);
3001
3002free_mem:
3b839a57
JR		 3003 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3004 __free_pages(page, get_order(size));
5d8b53cf
JR		 3005}
3006
b39ba6ad
JR		 3007/*
3008 * This function is called by the DMA layer to find out if we can handle a
3009 * particular device. It is part of the dma_ops.
3010 */
3011static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3012{
420aef8a 3013 return check_device(dev);
b39ba6ad
JR		 3014}
3015
c432f3df 3016/*
431b2a20
JR		 3017 * The function for pre-allocating protection domains.
3018 *
c432f3df
JR		 3019 * If the driver core informs the DMA layer if a driver grabs a device
3020 * we don't need to preallocate the protection domains anymore.
3021 * For now we have to.
3022 */
943bc7e1 3023static void __init prealloc_protection_domains(void)
c432f3df 3024{
5abcdba4 3025 struct iommu_dev_data *dev_data;
c432f3df 3026 struct dma_ops_domain *dma_dom;
5abcdba4 3027 struct pci_dev *dev = NULL;
98fc5a69 3028 u16 devid;
c432f3df 3029
d18c69d3 3030 for_each_pci_dev(dev) {
98fc5a69
JR		 3031
3032 /* Do we handle this device? */
3033 if (!check_device(&dev->dev))
c432f3df 3034 continue;
98fc5a69 3035
5abcdba4
JR		 3036 dev_data = get_dev_data(&dev->dev);
3037 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3038 /* Make sure passthrough domain is allocated */
3039 alloc_passthrough_domain();
3040 dev_data->passthrough = true;
3041 attach_device(&dev->dev, pt_domain);
df805abb 3042 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
5abcdba4
JR		 3043 dev_name(&dev->dev));
3044 }
3045
98fc5a69 3046 /* Is there already any domain for it? */
15898bbc 3047 if (domain_for_device(&dev->dev))
c432f3df 3048 continue;
98fc5a69
JR		 3049
3050 devid = get_device_id(&dev->dev);
3051
87a64d52 3052 dma_dom = dma_ops_domain_alloc();
c432f3df
JR		 3053 if (!dma_dom)
3054 continue;
3055 init_unity_mappings_for_device(dma_dom, devid);
bd60b735
JR		 3056 dma_dom->target_dev = devid;
3057
15898bbc 3058 attach_device(&dev->dev, &dma_dom->domain);
be831297 3059
bd60b735 3060 list_add_tail(&dma_dom->list, &iommu_pd_list);
c432f3df
JR		 3061 }
3062}
3063
160c1d8e 3064static struct dma_map_ops amd_iommu_dma_ops = {
baa676fc
AP		 3065 .alloc = alloc_coherent,
3066 .free = free_coherent,
51491367
FT		 3067 .map_page = map_page,
3068 .unmap_page = unmap_page,
6631ee9d
JR		 3069 .map_sg = map_sg,
3070 .unmap_sg = unmap_sg,
b39ba6ad 3071 .dma_supported = amd_iommu_dma_supported,
6631ee9d
JR		 3072};
3073
27c2127a
JR		 3074static unsigned device_dma_ops_init(void)
3075{
5abcdba4 3076 struct iommu_dev_data *dev_data;
27c2127a
JR		 3077 struct pci_dev *pdev = NULL;
3078 unsigned unhandled = 0;
3079
3080 for_each_pci_dev(pdev) {
3081 if (!check_device(&pdev->dev)) {
af1be049
JR		 3082
3083 iommu_ignore_device(&pdev->dev);
3084
27c2127a
JR		 3085 unhandled += 1;
3086 continue;
3087 }
3088
5abcdba4
JR		 3089 dev_data = get_dev_data(&pdev->dev);
3090
3091 if (!dev_data->passthrough)
3092 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3093 else
3094 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
27c2127a
JR		 3095 }
3096
3097 return unhandled;
3098}
3099
431b2a20
JR		 3100/*
3101 * The function which clues the AMD IOMMU driver into dma_ops.
3102 */
f5325094
JR		 3103
3104void __init amd_iommu_init_api(void)
3105{
2cc21c42 3106 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
f5325094
JR		 3107}
3108
6631ee9d
JR		 3109int __init amd_iommu_init_dma_ops(void)
3110{
3111 struct amd_iommu *iommu;
27c2127a 3112 int ret, unhandled;
6631ee9d 3113
431b2a20
JR		 3114 /*
3115 * first allocate a default protection domain for every IOMMU we
3116 * found in the system. Devices not assigned to any other
3117 * protection domain will be assigned to the default one.
3118 */
3bd22172 3119 for_each_iommu(iommu) {
87a64d52 3120 iommu->default_dom = dma_ops_domain_alloc();
6631ee9d
JR		 3121 if (iommu->default_dom == NULL)
3122 return -ENOMEM;
e2dc14a2 3123 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
6631ee9d
JR		 3124 ret = iommu_init_unity_mappings(iommu);
3125 if (ret)
3126 goto free_domains;
3127 }
3128
431b2a20 3129 /*
8793abeb 3130 * Pre-allocate the protection domains for each device.
431b2a20 3131 */
8793abeb 3132 prealloc_protection_domains();
6631ee9d
JR		 3133
3134 iommu_detected = 1;
75f1cdf1 3135 swiotlb = 0;
6631ee9d 3136
431b2a20 3137 /* Make the driver finally visible to the drivers */
27c2127a
JR		 3138 unhandled = device_dma_ops_init();
3139 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3140 /* There are unhandled devices - initialize swiotlb for them */
3141 swiotlb = 1;
3142 }
6631ee9d 3143
7f26508b
JR		 3144 amd_iommu_stats_init();
3145
62410eeb
JR		 3146 if (amd_iommu_unmap_flush)
3147 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3148 else
3149 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3150
6631ee9d
JR		 3151 return 0;
3152
3153free_domains:
3154
3bd22172 3155 for_each_iommu(iommu) {
91457df7 3156 dma_ops_domain_free(iommu->default_dom);
6631ee9d
JR		 3157 }
3158
3159 return ret;
3160}
6d98cd80
JR		 3161
3162/*****************************************************************************
3163 *
3164 * The following functions belong to the exported interface of AMD IOMMU
3165 *
3166 * This interface allows access to lower level functions of the IOMMU
3167 * like protection domain handling and assignement of devices to domains
3168 * which is not possible with the dma_ops interface.
3169 *
3170 *****************************************************************************/
3171
6d98cd80
JR		 3172static void cleanup_domain(struct protection_domain *domain)
3173{
9b29d3c6 3174 struct iommu_dev_data *entry;
6d98cd80 3175 unsigned long flags;
6d98cd80
JR		 3176
3177 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3178
9b29d3c6
JR		 3179 while (!list_empty(&domain->dev_list)) {
3180 entry = list_first_entry(&domain->dev_list,
3181 struct iommu_dev_data, list);
3182 __detach_device(entry);
492667da 3183 }
6d98cd80
JR		 3184
3185 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3186}
3187
2650815f
JR		 3188static void protection_domain_free(struct protection_domain *domain)
3189{
3190 if (!domain)
3191 return;
3192
aeb26f55
JR		 3193 del_domain_from_list(domain);
3194
2650815f
JR		 3195 if (domain->id)
3196 domain_id_free(domain->id);
3197
3198 kfree(domain);
3199}
3200
3201static struct protection_domain *protection_domain_alloc(void)
c156e347
JR		 3202{
3203 struct protection_domain *domain;
3204
3205 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3206 if (!domain)
2650815f 3207 return NULL;
c156e347
JR		 3208
3209 spin_lock_init(&domain->lock);
5d214fe6 3210 mutex_init(&domain->api_lock);
c156e347
JR		 3211 domain->id = domain_id_alloc();
3212 if (!domain->id)
2650815f 3213 goto out_err;
7c392cbe 3214 INIT_LIST_HEAD(&domain->dev_list);
2650815f 3215
aeb26f55
JR		 3216 add_domain_to_list(domain);
3217
2650815f
JR		 3218 return domain;
3219
3220out_err:
3221 kfree(domain);
3222
3223 return NULL;
3224}
3225
5abcdba4
JR		 3226static int __init alloc_passthrough_domain(void)
3227{
3228 if (pt_domain != NULL)
3229 return 0;
3230
3231 /* allocate passthrough domain */
3232 pt_domain = protection_domain_alloc();
3233 if (!pt_domain)
3234 return -ENOMEM;
3235
3236 pt_domain->mode = PAGE_MODE_NONE;
3237
3238 return 0;
3239}
2650815f
JR		 3240static int amd_iommu_domain_init(struct iommu_domain *dom)
3241{
3242 struct protection_domain *domain;
3243
3244 domain = protection_domain_alloc();
3245 if (!domain)
c156e347 3246 goto out_free;
2650815f
JR		 3247
3248 domain->mode = PAGE_MODE_3_LEVEL;
c156e347
JR		 3249 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3250 if (!domain->pt_root)
3251 goto out_free;
3252
f3572db8
JR		 3253 domain->iommu_domain = dom;
3254
c156e347
JR		 3255 dom->priv = domain;
3256
0ff64f80
JR		 3257 dom->geometry.aperture_start = 0;
3258 dom->geometry.aperture_end = ~0ULL;
3259 dom->geometry.force_aperture = true;
3260
c156e347
JR		 3261 return 0;
3262
3263out_free:
2650815f 3264 protection_domain_free(domain);
c156e347
JR		 3265
3266 return -ENOMEM;
3267}
3268
98383fc3
JR		 3269static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3270{
3271 struct protection_domain *domain = dom->priv;
3272
3273 if (!domain)
3274 return;
3275
3276 if (domain->dev_cnt > 0)
3277 cleanup_domain(domain);
3278
3279 BUG_ON(domain->dev_cnt != 0);
3280
132bd68f
JR		 3281 if (domain->mode != PAGE_MODE_NONE)
3282 free_pagetable(domain);
98383fc3 3283
52815b75
JR		 3284 if (domain->flags & PD_IOMMUV2_MASK)
3285 free_gcr3_table(domain);
3286
8b408fe4 3287 protection_domain_free(domain);
98383fc3
JR		 3288
3289 dom->priv = NULL;
3290}
3291
684f2888
JR		 3292static void amd_iommu_detach_device(struct iommu_domain *dom,
3293 struct device *dev)
3294{
657cbb6b 3295 struct iommu_dev_data *dev_data = dev->archdata.iommu;
684f2888 3296 struct amd_iommu *iommu;
684f2888
JR		 3297 u16 devid;
3298
98fc5a69 3299 if (!check_device(dev))
684f2888
JR		 3300 return;
3301
98fc5a69 3302 devid = get_device_id(dev);
684f2888 3303
657cbb6b 3304 if (dev_data->domain != NULL)
15898bbc 3305 detach_device(dev);
684f2888
JR		 3306
3307 iommu = amd_iommu_rlookup_table[devid];
3308 if (!iommu)
3309 return;
3310
684f2888
JR		 3311 iommu_completion_wait(iommu);
3312}
3313
01106066
JR		 3314static int amd_iommu_attach_device(struct iommu_domain *dom,
3315 struct device *dev)
3316{
3317 struct protection_domain *domain = dom->priv;
657cbb6b 3318 struct iommu_dev_data *dev_data;
01106066 3319 struct amd_iommu *iommu;
15898bbc 3320 int ret;
01106066 3321
98fc5a69 3322 if (!check_device(dev))
01106066
JR		 3323 return -EINVAL;
3324
657cbb6b
JR		 3325 dev_data = dev->archdata.iommu;
3326
f62dda66 3327 iommu = amd_iommu_rlookup_table[dev_data->devid];
01106066
JR		 3328 if (!iommu)
3329 return -EINVAL;
3330
657cbb6b 3331 if (dev_data->domain)
15898bbc 3332 detach_device(dev);
01106066 3333
15898bbc 3334 ret = attach_device(dev, domain);
01106066
JR		 3335
3336 iommu_completion_wait(iommu);
3337
15898bbc 3338 return ret;
01106066
JR		 3339}
3340
468e2366 3341static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
5009065d 3342 phys_addr_t paddr, size_t page_size, int iommu_prot)
c6229ca6
JR		 3343{
3344 struct protection_domain *domain = dom->priv;
c6229ca6
JR		 3345 int prot = 0;
3346 int ret;
3347
132bd68f
JR		 3348 if (domain->mode == PAGE_MODE_NONE)
3349 return -EINVAL;
3350
c6229ca6
JR		 3351 if (iommu_prot & IOMMU_READ)
3352 prot |= IOMMU_PROT_IR;
3353 if (iommu_prot & IOMMU_WRITE)
3354 prot |= IOMMU_PROT_IW;
3355
5d214fe6 3356 mutex_lock(&domain->api_lock);
795e74f7 3357 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
5d214fe6
JR		 3358 mutex_unlock(&domain->api_lock);
3359
795e74f7 3360 return ret;
c6229ca6
JR		 3361}
3362
5009065d
OBC		 3363static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3364 size_t page_size)
eb74ff6c 3365{
eb74ff6c 3366 struct protection_domain *domain = dom->priv;
5009065d 3367 size_t unmap_size;
eb74ff6c 3368
132bd68f
JR		 3369 if (domain->mode == PAGE_MODE_NONE)
3370 return -EINVAL;
3371
5d214fe6 3372 mutex_lock(&domain->api_lock);
468e2366 3373 unmap_size = iommu_unmap_page(domain, iova, page_size);
795e74f7 3374 mutex_unlock(&domain->api_lock);
eb74ff6c 3375
17b124bf 3376 domain_flush_tlb_pde(domain);
5d214fe6 3377
5009065d 3378 return unmap_size;
eb74ff6c
JR		 3379}
3380
645c4c8d 3381static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
bb5547ac 3382 dma_addr_t iova)
645c4c8d
JR		 3383{
3384 struct protection_domain *domain = dom->priv;
f03152bb 3385 unsigned long offset_mask;
645c4c8d 3386 phys_addr_t paddr;
f03152bb 3387 u64 *pte, __pte;
645c4c8d 3388
132bd68f
JR		 3389 if (domain->mode == PAGE_MODE_NONE)
3390 return iova;
3391
24cd7723 3392 pte = fetch_pte(domain, iova);
645c4c8d 3393
a6d41a40 3394 if (!pte || !IOMMU_PTE_PRESENT(*pte))
645c4c8d
JR		 3395 return 0;
3396
f03152bb
JR		 3397 if (PM_PTE_LEVEL(*pte) == 0)
3398 offset_mask = PAGE_SIZE - 1;
3399 else
3400 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3401
3402 __pte = *pte & PM_ADDR_MASK;
3403 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
645c4c8d
JR		 3404
3405 return paddr;
3406}
3407
ab636481 3408static bool amd_iommu_capable(enum iommu_cap cap)
dbb9fd86 3409{
80a506b8
JR		 3410 switch (cap) {
3411 case IOMMU_CAP_CACHE_COHERENCY:
ab636481 3412 return true;
bdddadcb 3413 case IOMMU_CAP_INTR_REMAP:
ab636481 3414 return (irq_remapping_enabled == 1);
cfdeec22
WD		 3415 case IOMMU_CAP_NOEXEC:
3416 return false;
80a506b8
JR		 3417 }
3418
ab636481 3419 return false;
dbb9fd86
SY		 3420}
3421
b22f6434 3422static const struct iommu_ops amd_iommu_ops = {
ab636481 3423 .capable = amd_iommu_capable,
26961efe
JR		 3424 .domain_init = amd_iommu_domain_init,
3425 .domain_destroy = amd_iommu_domain_destroy,
3426 .attach_dev = amd_iommu_attach_device,
3427 .detach_dev = amd_iommu_detach_device,
468e2366
JR		 3428 .map = amd_iommu_map,
3429 .unmap = amd_iommu_unmap,
315786eb 3430 .map_sg = default_iommu_map_sg,
26961efe 3431 .iova_to_phys = amd_iommu_iova_to_phys,
aa3de9c0 3432 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
26961efe
JR		 3433};
3434
0feae533
JR		 3435/*****************************************************************************
3436 *
3437 * The next functions do a basic initialization of IOMMU for pass through
3438 * mode
3439 *
3440 * In passthrough mode the IOMMU is initialized and enabled but not used for
3441 * DMA-API translation.
3442 *
3443 *****************************************************************************/
3444
3445int __init amd_iommu_init_passthrough(void)
3446{
5abcdba4 3447 struct iommu_dev_data *dev_data;
0feae533 3448 struct pci_dev *dev = NULL;
5abcdba4 3449 int ret;
0feae533 3450
5abcdba4
JR		 3451 ret = alloc_passthrough_domain();
3452 if (ret)
3453 return ret;
0feae533 3454
6c54aabd 3455 for_each_pci_dev(dev) {
98fc5a69 3456 if (!check_device(&dev->dev))
0feae533
JR		 3457 continue;
3458
5abcdba4
JR		 3459 dev_data = get_dev_data(&dev->dev);
3460 dev_data->passthrough = true;
3461
15898bbc 3462 attach_device(&dev->dev, pt_domain);
0feae533
JR		 3463 }
3464
2655d7a2
JR		 3465 amd_iommu_stats_init();
3466
0feae533
JR		 3467 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3468
3469 return 0;
3470}
72e1dcc4
JR		 3471
3472/* IOMMUv2 specific functions */
3473int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3474{
3475 return atomic_notifier_chain_register(&ppr_notifier, nb);
3476}
3477EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3478
3479int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3480{
3481 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3482}
3483EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
132bd68f
JR		 3484
3485void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3486{
3487 struct protection_domain *domain = dom->priv;
3488 unsigned long flags;
3489
3490 spin_lock_irqsave(&domain->lock, flags);
3491
3492 /* Update data structure */
3493 domain->mode = PAGE_MODE_NONE;
3494 domain->updated = true;
3495
3496 /* Make changes visible to IOMMUs */
3497 update_domain(domain);
3498
3499 /* Page-table is not visible to IOMMU anymore, so free it */
3500 free_pagetable(domain);
3501
3502 spin_unlock_irqrestore(&domain->lock, flags);
3503}
3504EXPORT_SYMBOL(amd_iommu_domain_direct_map);
52815b75
JR		 3505
3506int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3507{
3508 struct protection_domain *domain = dom->priv;
3509 unsigned long flags;
3510 int levels, ret;
3511
3512 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3513 return -EINVAL;
3514
3515 /* Number of GCR3 table levels required */
3516 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3517 levels += 1;
3518
3519 if (levels > amd_iommu_max_glx_val)
3520 return -EINVAL;
3521
3522 spin_lock_irqsave(&domain->lock, flags);
3523
3524 /*
3525 * Save us all sanity checks whether devices already in the
3526 * domain support IOMMUv2. Just force that the domain has no
3527 * devices attached when it is switched into IOMMUv2 mode.
3528 */
3529 ret = -EBUSY;
3530 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3531 goto out;
3532
3533 ret = -ENOMEM;
3534 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3535 if (domain->gcr3_tbl == NULL)
3536 goto out;
3537
3538 domain->glx = levels;
3539 domain->flags |= PD_IOMMUV2_MASK;
3540 domain->updated = true;
3541
3542 update_domain(domain);
3543
3544 ret = 0;
3545
3546out:
3547 spin_unlock_irqrestore(&domain->lock, flags);
3548
3549 return ret;
3550}
3551EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
22e266c7
JR		 3552
3553static int __flush_pasid(struct protection_domain *domain, int pasid,
3554 u64 address, bool size)
3555{
3556 struct iommu_dev_data *dev_data;
3557 struct iommu_cmd cmd;
3558 int i, ret;
3559
3560 if (!(domain->flags & PD_IOMMUV2_MASK))
3561 return -EINVAL;
3562
3563 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3564
3565 /*
3566 * IOMMU TLB needs to be flushed before Device TLB to
3567 * prevent device TLB refill from IOMMU TLB
3568 */
3569 for (i = 0; i < amd_iommus_present; ++i) {
3570 if (domain->dev_iommu[i] == 0)
3571 continue;
3572
3573 ret = iommu_queue_command(amd_iommus[i], &cmd);
3574 if (ret != 0)
3575 goto out;
3576 }
3577
3578 /* Wait until IOMMU TLB flushes are complete */
3579 domain_flush_complete(domain);
3580
3581 /* Now flush device TLBs */
3582 list_for_each_entry(dev_data, &domain->dev_list, list) {
3583 struct amd_iommu *iommu;
3584 int qdep;
3585
3586 BUG_ON(!dev_data->ats.enabled);
3587
3588 qdep = dev_data->ats.qdep;
3589 iommu = amd_iommu_rlookup_table[dev_data->devid];
3590
3591 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3592 qdep, address, size);
3593
3594 ret = iommu_queue_command(iommu, &cmd);
3595 if (ret != 0)
3596 goto out;
3597 }
3598
3599 /* Wait until all device TLBs are flushed */
3600 domain_flush_complete(domain);
3601
3602 ret = 0;
3603
3604out:
3605
3606 return ret;
3607}
3608
3609static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3610 u64 address)
3611{
399be2f5
JR		 3612 INC_STATS_COUNTER(invalidate_iotlb);
3613
22e266c7
JR		 3614 return __flush_pasid(domain, pasid, address, false);
3615}
3616
3617int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3618 u64 address)
3619{
3620 struct protection_domain *domain = dom->priv;
3621 unsigned long flags;
3622 int ret;
3623
3624 spin_lock_irqsave(&domain->lock, flags);
3625 ret = __amd_iommu_flush_page(domain, pasid, address);
3626 spin_unlock_irqrestore(&domain->lock, flags);
3627
3628 return ret;
3629}
3630EXPORT_SYMBOL(amd_iommu_flush_page);
3631
3632static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3633{
399be2f5
JR		 3634 INC_STATS_COUNTER(invalidate_iotlb_all);
3635
22e266c7
JR		 3636 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3637 true);
3638}
3639
3640int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3641{
3642 struct protection_domain *domain = dom->priv;
3643 unsigned long flags;
3644 int ret;
3645
3646 spin_lock_irqsave(&domain->lock, flags);
3647 ret = __amd_iommu_flush_tlb(domain, pasid);
3648 spin_unlock_irqrestore(&domain->lock, flags);
3649
3650 return ret;
3651}
3652EXPORT_SYMBOL(amd_iommu_flush_tlb);
3653
b16137b1
JR		 3654static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3655{
3656 int index;
3657 u64 *pte;
3658
3659 while (true) {
3660
3661 index = (pasid >> (9 * level)) & 0x1ff;
3662 pte = &root[index];
3663
3664 if (level == 0)
3665 break;
3666
3667 if (!(*pte & GCR3_VALID)) {
3668 if (!alloc)
3669 return NULL;
3670
3671 root = (void *)get_zeroed_page(GFP_ATOMIC);
3672 if (root == NULL)
3673 return NULL;
3674
3675 *pte = __pa(root) | GCR3_VALID;
3676 }
3677
3678 root = __va(*pte & PAGE_MASK);
3679
3680 level -= 1;
3681 }
3682
3683 return pte;
3684}
3685
3686static int __set_gcr3(struct protection_domain *domain, int pasid,
3687 unsigned long cr3)
3688{
3689 u64 *pte;
3690
3691 if (domain->mode != PAGE_MODE_NONE)
3692 return -EINVAL;
3693
3694 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3695 if (pte == NULL)
3696 return -ENOMEM;
3697
3698 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3699
3700 return __amd_iommu_flush_tlb(domain, pasid);
3701}
3702
3703static int __clear_gcr3(struct protection_domain *domain, int pasid)
3704{
3705 u64 *pte;
3706
3707 if (domain->mode != PAGE_MODE_NONE)
3708 return -EINVAL;
3709
3710 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3711 if (pte == NULL)
3712 return 0;
3713
3714 *pte = 0;
3715
3716 return __amd_iommu_flush_tlb(domain, pasid);
3717}
3718
3719int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3720 unsigned long cr3)
3721{
3722 struct protection_domain *domain = dom->priv;
3723 unsigned long flags;
3724 int ret;
3725
3726 spin_lock_irqsave(&domain->lock, flags);
3727 ret = __set_gcr3(domain, pasid, cr3);
3728 spin_unlock_irqrestore(&domain->lock, flags);
3729
3730 return ret;
3731}
3732EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3733
3734int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3735{
3736 struct protection_domain *domain = dom->priv;
3737 unsigned long flags;
3738 int ret;
3739
3740 spin_lock_irqsave(&domain->lock, flags);
3741 ret = __clear_gcr3(domain, pasid);
3742 spin_unlock_irqrestore(&domain->lock, flags);
3743
3744 return ret;
3745}
3746EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
c99afa25
JR		 3747
3748int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3749 int status, int tag)
3750{
3751 struct iommu_dev_data *dev_data;
3752 struct amd_iommu *iommu;
3753 struct iommu_cmd cmd;
3754
399be2f5
JR		 3755 INC_STATS_COUNTER(complete_ppr);
3756
c99afa25
JR		 3757 dev_data = get_dev_data(&pdev->dev);
3758 iommu = amd_iommu_rlookup_table[dev_data->devid];
3759
3760 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3761 tag, dev_data->pri_tlp);
3762
3763 return iommu_queue_command(iommu, &cmd);
3764}
3765EXPORT_SYMBOL(amd_iommu_complete_ppr);
f3572db8
JR		 3766
3767struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3768{
3769 struct protection_domain *domain;
3770
3771 domain = get_domain(&pdev->dev);
3772 if (IS_ERR(domain))
3773 return NULL;
3774
3775 /* Only return IOMMUv2 domains */
3776 if (!(domain->flags & PD_IOMMUV2_MASK))
3777 return NULL;
3778
3779 return domain->iommu_domain;
3780}
3781EXPORT_SYMBOL(amd_iommu_get_v2_domain);
6a113ddc
JR		 3782
3783void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3784{
3785 struct iommu_dev_data *dev_data;
3786
3787 if (!amd_iommu_v2_supported())
3788 return;
3789
3790 dev_data = get_dev_data(&pdev->dev);
3791 dev_data->errata |= (1 << erratum);
3792}
3793EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
52efdb89
JR		 3794
3795int amd_iommu_device_info(struct pci_dev *pdev,
3796 struct amd_iommu_device_info *info)
3797{
3798 int max_pasids;
3799 int pos;
3800
3801 if (pdev == NULL || info == NULL)
3802 return -EINVAL;
3803
3804 if (!amd_iommu_v2_supported())
3805 return -EINVAL;
3806
3807 memset(info, 0, sizeof(*info));
3808
3809 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3810 if (pos)
3811 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3812
3813 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3814 if (pos)
3815 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3816
3817 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3818 if (pos) {
3819 int features;
3820
3821 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3822 max_pasids = min(max_pasids, (1 << 20));
3823
3824 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3825 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3826
3827 features = pci_pasid_features(pdev);
3828 if (features & PCI_PASID_CAP_EXEC)
3829 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3830 if (features & PCI_PASID_CAP_PRIV)
3831 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3832 }
3833
3834 return 0;
3835}
3836EXPORT_SYMBOL(amd_iommu_device_info);
2b324506
JR		 3837
3838#ifdef CONFIG_IRQ_REMAP
3839
3840/*****************************************************************************
3841 *
3842 * Interrupt Remapping Implementation
3843 *
3844 *****************************************************************************/
3845
3846union irte {
3847 u32 val;
3848 struct {
3849 u32 valid : 1,
3850 no_fault : 1,
3851 int_type : 3,
3852 rq_eoi : 1,
3853 dm : 1,
3854 rsvd_1 : 1,
3855 destination : 8,
3856 vector : 8,
3857 rsvd_2 : 8;
3858 } fields;
3859};
3860
3861#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3862#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3863#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3864#define DTE_IRQ_REMAP_ENABLE 1ULL
3865
3866static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3867{
3868 u64 dte;
3869
3870 dte = amd_iommu_dev_table[devid].data[2];
3871 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3872 dte |= virt_to_phys(table->table);
3873 dte |= DTE_IRQ_REMAP_INTCTL;
3874 dte |= DTE_IRQ_TABLE_LEN;
3875 dte |= DTE_IRQ_REMAP_ENABLE;
3876
3877 amd_iommu_dev_table[devid].data[2] = dte;
3878}
3879
3880#define IRTE_ALLOCATED (~1U)
3881
3882static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3883{
3884 struct irq_remap_table *table = NULL;
3885 struct amd_iommu *iommu;
3886 unsigned long flags;
3887 u16 alias;
3888
3889 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3890
3891 iommu = amd_iommu_rlookup_table[devid];
3892 if (!iommu)
3893 goto out_unlock;
3894
3895 table = irq_lookup_table[devid];
3896 if (table)
3897 goto out;
3898
3899 alias = amd_iommu_alias_table[devid];
3900 table = irq_lookup_table[alias];
3901 if (table) {
3902 irq_lookup_table[devid] = table;
3903 set_dte_irq_entry(devid, table);
3904 iommu_flush_dte(iommu, devid);
3905 goto out;
3906 }
3907
3908 /* Nothing there yet, allocate new irq remapping table */
3909 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3910 if (!table)
3911 goto out;
3912
197887f0
JR		 3913 /* Initialize table spin-lock */
3914 spin_lock_init(&table->lock);
3915
2b324506
JR		 3916 if (ioapic)
3917 /* Keep the first 32 indexes free for IOAPIC interrupts */
3918 table->min_index = 32;
3919
3920 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3921 if (!table->table) {
3922 kfree(table);
821f0f68 3923 table = NULL;
2b324506
JR		 3924 goto out;
3925 }
3926
3927 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3928
3929 if (ioapic) {
3930 int i;
3931
3932 for (i = 0; i < 32; ++i)
3933 table->table[i] = IRTE_ALLOCATED;
3934 }
3935
3936 irq_lookup_table[devid] = table;
3937 set_dte_irq_entry(devid, table);
3938 iommu_flush_dte(iommu, devid);
3939 if (devid != alias) {
3940 irq_lookup_table[alias] = table;
e028a9e6 3941 set_dte_irq_entry(alias, table);
2b324506
JR		 3942 iommu_flush_dte(iommu, alias);
3943 }
3944
3945out:
3946 iommu_completion_wait(iommu);
3947
3948out_unlock:
3949 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3950
3951 return table;
3952}
3953
3954static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3955{
3956 struct irq_remap_table *table;
3957 unsigned long flags;
3958 int index, c;
3959
3960 table = get_irq_table(devid, false);
3961 if (!table)
3962 return -ENODEV;
3963
3964 spin_lock_irqsave(&table->lock, flags);
3965
3966 /* Scan table for free entries */
3967 for (c = 0, index = table->min_index;
3968 index < MAX_IRQS_PER_TABLE;
3969 ++index) {
3970 if (table->table[index] == 0)
3971 c += 1;
3972 else
3973 c = 0;
3974
3975 if (c == count) {
0dfedd61 3976 struct irq_2_irte *irte_info;
2b324506
JR		 3977
3978 for (; c != 0; --c)
3979 table->table[index - c + 1] = IRTE_ALLOCATED;
3980
3981 index -= count - 1;
3982
9b1b0e42 3983 cfg->remapped = 1;
0dfedd61
JR		 3984 irte_info = &cfg->irq_2_irte;
3985 irte_info->devid = devid;
3986 irte_info->index = index;
2b324506
JR		 3987
3988 goto out;
3989 }
3990 }
3991
3992 index = -ENOSPC;
3993
3994out:
3995 spin_unlock_irqrestore(&table->lock, flags);
3996
3997 return index;
3998}
3999
4000static int get_irte(u16 devid, int index, union irte *irte)
4001{
4002 struct irq_remap_table *table;
4003 unsigned long flags;
4004
4005 table = get_irq_table(devid, false);
4006 if (!table)
4007 return -ENOMEM;
4008
4009 spin_lock_irqsave(&table->lock, flags);
4010 irte->val = table->table[index];
4011 spin_unlock_irqrestore(&table->lock, flags);
4012
4013 return 0;
4014}
4015
4016static int modify_irte(u16 devid, int index, union irte irte)
4017{
4018 struct irq_remap_table *table;
4019 struct amd_iommu *iommu;
4020 unsigned long flags;
4021
4022 iommu = amd_iommu_rlookup_table[devid];
4023 if (iommu == NULL)
4024 return -EINVAL;
4025
4026 table = get_irq_table(devid, false);
4027 if (!table)
4028 return -ENOMEM;
4029
4030 spin_lock_irqsave(&table->lock, flags);
4031 table->table[index] = irte.val;
4032 spin_unlock_irqrestore(&table->lock, flags);
4033
4034 iommu_flush_irt(iommu, devid);
4035 iommu_completion_wait(iommu);
4036
4037 return 0;
4038}
4039
4040static void free_irte(u16 devid, int index)
4041{
4042 struct irq_remap_table *table;
4043 struct amd_iommu *iommu;
4044 unsigned long flags;
4045
4046 iommu = amd_iommu_rlookup_table[devid];
4047 if (iommu == NULL)
4048 return;
4049
4050 table = get_irq_table(devid, false);
4051 if (!table)
4052 return;
4053
4054 spin_lock_irqsave(&table->lock, flags);
4055 table->table[index] = 0;
4056 spin_unlock_irqrestore(&table->lock, flags);
4057
4058 iommu_flush_irt(iommu, devid);
4059 iommu_completion_wait(iommu);
4060}
4061
5527de74
JR		 4062static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4063 unsigned int destination, int vector,
4064 struct io_apic_irq_attr *attr)
4065{
4066 struct irq_remap_table *table;
0dfedd61 4067 struct irq_2_irte *irte_info;
5527de74
JR		 4068 struct irq_cfg *cfg;
4069 union irte irte;
4070 int ioapic_id;
4071 int index;
4072 int devid;
4073 int ret;
4074
719b530c 4075 cfg = irq_cfg(irq);
5527de74
JR		 4076 if (!cfg)
4077 return -EINVAL;
4078
0dfedd61 4079 irte_info = &cfg->irq_2_irte;
5527de74
JR		 4080 ioapic_id = mpc_ioapic_id(attr->ioapic);
4081 devid = get_ioapic_devid(ioapic_id);
4082
4083 if (devid < 0)
4084 return devid;
4085
4086 table = get_irq_table(devid, true);
4087 if (table == NULL)
4088 return -ENOMEM;
4089
4090 index = attr->ioapic_pin;
4091
4092 /* Setup IRQ remapping info */
9b1b0e42 4093 cfg->remapped = 1;
0dfedd61
JR		 4094 irte_info->devid = devid;
4095 irte_info->index = index;
5527de74
JR		 4096
4097 /* Setup IRTE for IOMMU */
4098 irte.val = 0;
4099 irte.fields.vector = vector;
4100 irte.fields.int_type = apic->irq_delivery_mode;
4101 irte.fields.destination = destination;
4102 irte.fields.dm = apic->irq_dest_mode;
4103 irte.fields.valid = 1;
4104
4105 ret = modify_irte(devid, index, irte);
4106 if (ret)
4107 return ret;
4108
4109 /* Setup IOAPIC entry */
4110 memset(entry, 0, sizeof(*entry));
4111
4112 entry->vector = index;
4113 entry->mask = 0;
4114 entry->trigger = attr->trigger;
4115 entry->polarity = attr->polarity;
4116
4117 /*
4118 * Mask level triggered irqs.
5527de74
JR		 4119 */
4120 if (attr->trigger)
4121 entry->mask = 1;
4122
4123 return 0;
4124}
4125
4126static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4127 bool force)
4128{
0dfedd61 4129 struct irq_2_irte *irte_info;
5527de74
JR		 4130 unsigned int dest, irq;
4131 struct irq_cfg *cfg;
4132 union irte irte;
4133 int err;
4134
4135 if (!config_enabled(CONFIG_SMP))
4136 return -1;
4137
719b530c 4138 cfg = irqd_cfg(data);
5527de74 4139 irq = data->irq;
0dfedd61 4140 irte_info = &cfg->irq_2_irte;
5527de74
JR		 4141
4142 if (!cpumask_intersects(mask, cpu_online_mask))
4143 return -EINVAL;
4144
0dfedd61 4145 if (get_irte(irte_info->devid, irte_info->index, &irte))
5527de74
JR		 4146 return -EBUSY;
4147
4148 if (assign_irq_vector(irq, cfg, mask))
4149 return -EBUSY;
4150
4151 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4152 if (err) {
4153 if (assign_irq_vector(irq, cfg, data->affinity))
4154 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4155 return err;
4156 }
4157
4158 irte.fields.vector = cfg->vector;
4159 irte.fields.destination = dest;
4160
0dfedd61 4161 modify_irte(irte_info->devid, irte_info->index, irte);
5527de74
JR		 4162
4163 if (cfg->move_in_progress)
4164 send_cleanup_vector(cfg);
4165
4166 cpumask_copy(data->affinity, mask);
4167
4168 return 0;
4169}
4170
4171static int free_irq(int irq)
4172{
0dfedd61 4173 struct irq_2_irte *irte_info;
5527de74
JR		 4174 struct irq_cfg *cfg;
4175
719b530c 4176 cfg = irq_cfg(irq);
5527de74
JR		 4177 if (!cfg)
4178 return -EINVAL;
4179
0dfedd61 4180 irte_info = &cfg->irq_2_irte;
5527de74 4181
0dfedd61 4182 free_irte(irte_info->devid, irte_info->index);
5527de74
JR		 4183
4184 return 0;
4185}
4186
0b4d48cb
JR		 4187static void compose_msi_msg(struct pci_dev *pdev,
4188 unsigned int irq, unsigned int dest,
4189 struct msi_msg *msg, u8 hpet_id)
4190{
0dfedd61 4191 struct irq_2_irte *irte_info;
0b4d48cb
JR		 4192 struct irq_cfg *cfg;
4193 union irte irte;
4194
719b530c 4195 cfg = irq_cfg(irq);
0b4d48cb
JR		 4196 if (!cfg)
4197 return;
4198
0dfedd61 4199 irte_info = &cfg->irq_2_irte;
0b4d48cb
JR		 4200
4201 irte.val = 0;
4202 irte.fields.vector = cfg->vector;
4203 irte.fields.int_type = apic->irq_delivery_mode;
4204 irte.fields.destination = dest;
4205 irte.fields.dm = apic->irq_dest_mode;
4206 irte.fields.valid = 1;
4207
0dfedd61 4208 modify_irte(irte_info->devid, irte_info->index, irte);
0b4d48cb
JR		 4209
4210 msg->address_hi = MSI_ADDR_BASE_HI;
4211 msg->address_lo = MSI_ADDR_BASE_LO;
0dfedd61 4212 msg->data = irte_info->index;
0b4d48cb
JR		 4213}
4214
4215static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4216{
4217 struct irq_cfg *cfg;
4218 int index;
4219 u16 devid;
4220
4221 if (!pdev)
4222 return -EINVAL;
4223
719b530c 4224 cfg = irq_cfg(irq);
0b4d48cb
JR		 4225 if (!cfg)
4226 return -EINVAL;
4227
4228 devid = get_device_id(&pdev->dev);
4229 index = alloc_irq_index(cfg, devid, nvec);
4230
4231 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4232}
4233
4234static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4235 int index, int offset)
4236{
0dfedd61 4237 struct irq_2_irte *irte_info;
0b4d48cb
JR		 4238 struct irq_cfg *cfg;
4239 u16 devid;
4240
4241 if (!pdev)
4242 return -EINVAL;
4243
719b530c 4244 cfg = irq_cfg(irq);
0b4d48cb
JR		 4245 if (!cfg)
4246 return -EINVAL;
4247
4248 if (index >= MAX_IRQS_PER_TABLE)
4249 return 0;
4250
4251 devid = get_device_id(&pdev->dev);
0dfedd61 4252 irte_info = &cfg->irq_2_irte;
0b4d48cb 4253
9b1b0e42 4254 cfg->remapped = 1;
0dfedd61
JR		 4255 irte_info->devid = devid;
4256 irte_info->index = index + offset;
0b4d48cb
JR		 4257
4258 return 0;
4259}
4260
5fc24d8c 4261static int alloc_hpet_msi(unsigned int irq, unsigned int id)
d976195c 4262{
0dfedd61 4263 struct irq_2_irte *irte_info;
d976195c
JR		 4264 struct irq_cfg *cfg;
4265 int index, devid;
4266
719b530c 4267 cfg = irq_cfg(irq);
d976195c
JR		 4268 if (!cfg)
4269 return -EINVAL;
4270
0dfedd61 4271 irte_info = &cfg->irq_2_irte;
d976195c
JR		 4272 devid = get_hpet_devid(id);
4273 if (devid < 0)
4274 return devid;
4275
4276 index = alloc_irq_index(cfg, devid, 1);
4277 if (index < 0)
4278 return index;
4279
9b1b0e42 4280 cfg->remapped = 1;
0dfedd61
JR		 4281 irte_info->devid = devid;
4282 irte_info->index = index;
d976195c
JR		 4283
4284 return 0;
4285}
4286
6b474b82 4287struct irq_remap_ops amd_iommu_irq_ops = {
6b474b82
JR		 4288 .prepare = amd_iommu_prepare,
4289 .enable = amd_iommu_enable,
4290 .disable = amd_iommu_disable,
4291 .reenable = amd_iommu_reenable,
4292 .enable_faulting = amd_iommu_enable_faulting,
4293 .setup_ioapic_entry = setup_ioapic_entry,
4294 .set_affinity = set_affinity,
4295 .free_irq = free_irq,
4296 .compose_msi_msg = compose_msi_msg,
4297 .msi_alloc_irq = msi_alloc_irq,
4298 .msi_setup_irq = msi_setup_irq,
5fc24d8c 4299 .alloc_hpet_msi = alloc_hpet_msi,
6b474b82 4300};
2b324506 4301#endif
Linux kernel - Deliverables
This page took 0.813279 seconds and 5 git commands to generate.