Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
2b324506 JR |
37 | #include <asm/irq_remapping.h> |
38 | #include <asm/io_apic.h> | |
39 | #include <asm/apic.h> | |
40 | #include <asm/hw_irq.h> | |
17f5b569 | 41 | #include <asm/msidef.h> |
b6c02715 | 42 | #include <asm/proto.h> |
46a7fa27 | 43 | #include <asm/iommu.h> |
1d9b16d1 | 44 | #include <asm/gart.h> |
27c2127a | 45 | #include <asm/dma.h> |
403f81d8 JR |
46 | |
47 | #include "amd_iommu_proto.h" | |
48 | #include "amd_iommu_types.h" | |
6b474b82 | 49 | #include "irq_remapping.h" |
b6c02715 JR |
50 | |
51 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
52 | ||
815b33fd | 53 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 54 | |
aa3de9c0 OBC |
55 | /* |
56 | * This bitmap is used to advertise the page sizes our hardware support | |
57 | * to the IOMMU core, which will then use this information to split | |
58 | * physically contiguous memory regions it is mapping into page sizes | |
59 | * that we support. | |
60 | * | |
954e3dd8 | 61 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 62 | */ |
954e3dd8 | 63 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 64 | |
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
6efed63b JR |
75 | LIST_HEAD(ioapic_map); |
76 | LIST_HEAD(hpet_map); | |
77 | ||
0feae533 JR |
78 | /* |
79 | * Domain for untranslated devices - only allocated | |
80 | * if iommu=pt passed on kernel cmd line. | |
81 | */ | |
82 | static struct protection_domain *pt_domain; | |
83 | ||
b22f6434 | 84 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 85 | |
72e1dcc4 | 86 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 87 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 88 | |
ac1534a5 JR |
89 | static struct dma_map_ops amd_iommu_dma_ops; |
90 | ||
50917e26 JR |
91 | /* |
92 | * This struct contains device specific data for the IOMMU | |
93 | */ | |
94 | struct iommu_dev_data { | |
95 | struct list_head list; /* For domain->dev_list */ | |
96 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 97 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
98 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
99 | struct protection_domain *domain; /* Domain the device is bound to */ | |
50917e26 JR |
100 | u16 devid; /* PCI Device ID */ |
101 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
102 | bool passthrough; /* Default for device is pt_domain */ | |
103 | struct { | |
104 | bool enabled; | |
105 | int qdep; | |
106 | } ats; /* ATS state */ | |
107 | bool pri_tlp; /* PASID TLB required for | |
108 | PPR completions */ | |
109 | u32 errata; /* Bitmap for errata to apply */ | |
110 | }; | |
111 | ||
431b2a20 JR |
112 | /* |
113 | * general struct to manage commands send to an IOMMU | |
114 | */ | |
d6449536 | 115 | struct iommu_cmd { |
b6c02715 JR |
116 | u32 data[4]; |
117 | }; | |
118 | ||
05152a04 JR |
119 | struct kmem_cache *amd_iommu_irq_cache; |
120 | ||
04bfdd84 | 121 | static void update_domain(struct protection_domain *domain); |
aafd8ba0 | 122 | static int alloc_passthrough_domain(void); |
c1eee67b | 123 | |
15898bbc JR |
124 | /**************************************************************************** |
125 | * | |
126 | * Helper functions | |
127 | * | |
128 | ****************************************************************************/ | |
129 | ||
3f4b87b9 JR |
130 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
131 | { | |
132 | return container_of(dom, struct protection_domain, domain); | |
133 | } | |
134 | ||
f62dda66 | 135 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
136 | { |
137 | struct iommu_dev_data *dev_data; | |
138 | unsigned long flags; | |
139 | ||
140 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
141 | if (!dev_data) | |
142 | return NULL; | |
143 | ||
f251e187 JR |
144 | INIT_LIST_HEAD(&dev_data->alias_list); |
145 | ||
f62dda66 | 146 | dev_data->devid = devid; |
8fa5f802 JR |
147 | |
148 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
149 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
150 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
151 | ||
152 | return dev_data; | |
153 | } | |
154 | ||
155 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
156 | { | |
157 | unsigned long flags; | |
158 | ||
159 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
160 | list_del(&dev_data->dev_data_list); | |
161 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
162 | ||
163 | kfree(dev_data); | |
164 | } | |
165 | ||
3b03bb74 JR |
166 | static struct iommu_dev_data *search_dev_data(u16 devid) |
167 | { | |
168 | struct iommu_dev_data *dev_data; | |
169 | unsigned long flags; | |
170 | ||
171 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
172 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
173 | if (dev_data->devid == devid) | |
174 | goto out_unlock; | |
175 | } | |
176 | ||
177 | dev_data = NULL; | |
178 | ||
179 | out_unlock: | |
180 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
181 | ||
182 | return dev_data; | |
183 | } | |
184 | ||
185 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
186 | { | |
187 | struct iommu_dev_data *dev_data; | |
188 | ||
189 | dev_data = search_dev_data(devid); | |
190 | ||
191 | if (dev_data == NULL) | |
192 | dev_data = alloc_dev_data(devid); | |
193 | ||
194 | return dev_data; | |
195 | } | |
196 | ||
15898bbc JR |
197 | static inline u16 get_device_id(struct device *dev) |
198 | { | |
199 | struct pci_dev *pdev = to_pci_dev(dev); | |
200 | ||
6f2729ba | 201 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
202 | } |
203 | ||
657cbb6b JR |
204 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
205 | { | |
206 | return dev->archdata.iommu; | |
207 | } | |
208 | ||
5abcdba4 JR |
209 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
210 | { | |
211 | static const int caps[] = { | |
212 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
213 | PCI_EXT_CAP_ID_PRI, |
214 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
215 | }; |
216 | int i, pos; | |
217 | ||
218 | for (i = 0; i < 3; ++i) { | |
219 | pos = pci_find_ext_capability(pdev, caps[i]); | |
220 | if (pos == 0) | |
221 | return false; | |
222 | } | |
223 | ||
224 | return true; | |
225 | } | |
226 | ||
6a113ddc JR |
227 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
228 | { | |
229 | struct iommu_dev_data *dev_data; | |
230 | ||
231 | dev_data = get_dev_data(&pdev->dev); | |
232 | ||
233 | return dev_data->errata & (1 << erratum) ? true : false; | |
234 | } | |
235 | ||
71c70984 JR |
236 | /* |
237 | * In this function the list of preallocated protection domains is traversed to | |
238 | * find the domain for a specific device | |
239 | */ | |
240 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
241 | { | |
242 | struct dma_ops_domain *entry, *ret = NULL; | |
243 | unsigned long flags; | |
244 | u16 alias = amd_iommu_alias_table[devid]; | |
245 | ||
246 | if (list_empty(&iommu_pd_list)) | |
247 | return NULL; | |
248 | ||
249 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
250 | ||
251 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
252 | if (entry->target_dev == devid || | |
253 | entry->target_dev == alias) { | |
254 | ret = entry; | |
255 | break; | |
256 | } | |
257 | } | |
258 | ||
259 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
260 | ||
261 | return ret; | |
262 | } | |
263 | ||
98fc5a69 JR |
264 | /* |
265 | * This function checks if the driver got a valid device from the caller to | |
266 | * avoid dereferencing invalid pointers. | |
267 | */ | |
268 | static bool check_device(struct device *dev) | |
269 | { | |
270 | u16 devid; | |
271 | ||
272 | if (!dev || !dev->dma_mask) | |
273 | return false; | |
274 | ||
b82a2272 YW |
275 | /* No PCI device */ |
276 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
277 | return false; |
278 | ||
279 | devid = get_device_id(dev); | |
280 | ||
281 | /* Out of our scope? */ | |
282 | if (devid > amd_iommu_last_bdf) | |
283 | return false; | |
284 | ||
285 | if (amd_iommu_rlookup_table[devid] == NULL) | |
286 | return false; | |
287 | ||
288 | return true; | |
289 | } | |
290 | ||
25b11ce2 | 291 | static void init_iommu_group(struct device *dev) |
2851db21 | 292 | { |
2851db21 | 293 | struct iommu_group *group; |
2851db21 | 294 | |
65d5352f | 295 | group = iommu_group_get_for_dev(dev); |
25b11ce2 AW |
296 | if (!IS_ERR(group)) |
297 | iommu_group_put(group); | |
eb9c9527 AW |
298 | } |
299 | ||
c1931090 AW |
300 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
301 | { | |
302 | *(u16 *)data = alias; | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static u16 get_alias(struct device *dev) | |
307 | { | |
308 | struct pci_dev *pdev = to_pci_dev(dev); | |
309 | u16 devid, ivrs_alias, pci_alias; | |
310 | ||
311 | devid = get_device_id(dev); | |
312 | ivrs_alias = amd_iommu_alias_table[devid]; | |
313 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
314 | ||
315 | if (ivrs_alias == pci_alias) | |
316 | return ivrs_alias; | |
317 | ||
318 | /* | |
319 | * DMA alias showdown | |
320 | * | |
321 | * The IVRS is fairly reliable in telling us about aliases, but it | |
322 | * can't know about every screwy device. If we don't have an IVRS | |
323 | * reported alias, use the PCI reported alias. In that case we may | |
324 | * still need to initialize the rlookup and dev_table entries if the | |
325 | * alias is to a non-existent device. | |
326 | */ | |
327 | if (ivrs_alias == devid) { | |
328 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
329 | amd_iommu_rlookup_table[pci_alias] = | |
330 | amd_iommu_rlookup_table[devid]; | |
331 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
332 | amd_iommu_dev_table[devid].data, | |
333 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
334 | } | |
335 | ||
336 | return pci_alias; | |
337 | } | |
338 | ||
339 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
340 | "for device %s[%04x:%04x], kernel reported alias " | |
341 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
342 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
343 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
344 | PCI_FUNC(pci_alias)); | |
345 | ||
346 | /* | |
347 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
348 | * bus, then the IVRS table may know about a quirk that we don't. | |
349 | */ | |
350 | if (pci_alias == devid && | |
351 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
352 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
353 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
354 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
355 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
356 | dev_name(dev)); | |
357 | } | |
358 | ||
359 | return ivrs_alias; | |
360 | } | |
361 | ||
eb9c9527 AW |
362 | static int iommu_init_device(struct device *dev) |
363 | { | |
364 | struct pci_dev *pdev = to_pci_dev(dev); | |
365 | struct iommu_dev_data *dev_data; | |
366 | u16 alias; | |
eb9c9527 AW |
367 | |
368 | if (dev->archdata.iommu) | |
369 | return 0; | |
370 | ||
371 | dev_data = find_dev_data(get_device_id(dev)); | |
372 | if (!dev_data) | |
373 | return -ENOMEM; | |
374 | ||
c1931090 AW |
375 | alias = get_alias(dev); |
376 | ||
eb9c9527 AW |
377 | if (alias != dev_data->devid) { |
378 | struct iommu_dev_data *alias_data; | |
379 | ||
380 | alias_data = find_dev_data(alias); | |
381 | if (alias_data == NULL) { | |
382 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
383 | dev_name(dev)); | |
384 | free_dev_data(dev_data); | |
385 | return -ENOTSUPP; | |
386 | } | |
387 | dev_data->alias_data = alias_data; | |
eb9c9527 | 388 | |
f251e187 JR |
389 | /* Add device to the alias_list */ |
390 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
e644a013 | 391 | } |
9dcd6130 | 392 | |
5abcdba4 JR |
393 | if (pci_iommuv2_capable(pdev)) { |
394 | struct amd_iommu *iommu; | |
395 | ||
396 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
397 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
398 | } | |
399 | ||
657cbb6b JR |
400 | dev->archdata.iommu = dev_data; |
401 | ||
066f2e98 AW |
402 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
403 | dev); | |
404 | ||
657cbb6b JR |
405 | return 0; |
406 | } | |
407 | ||
26018874 JR |
408 | static void iommu_ignore_device(struct device *dev) |
409 | { | |
410 | u16 devid, alias; | |
411 | ||
412 | devid = get_device_id(dev); | |
413 | alias = amd_iommu_alias_table[devid]; | |
414 | ||
415 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
416 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
417 | ||
418 | amd_iommu_rlookup_table[devid] = NULL; | |
419 | amd_iommu_rlookup_table[alias] = NULL; | |
420 | } | |
421 | ||
657cbb6b JR |
422 | static void iommu_uninit_device(struct device *dev) |
423 | { | |
c1931090 AW |
424 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
425 | ||
426 | if (!dev_data) | |
427 | return; | |
428 | ||
066f2e98 AW |
429 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
430 | dev); | |
431 | ||
9dcd6130 AW |
432 | iommu_group_remove_device(dev); |
433 | ||
c1931090 AW |
434 | /* Unlink from alias, it may change if another device is re-plugged */ |
435 | dev_data->alias_data = NULL; | |
436 | ||
aafd8ba0 JR |
437 | /* Remove dma-ops */ |
438 | dev->archdata.dma_ops = NULL; | |
439 | ||
8fa5f802 | 440 | /* |
c1931090 AW |
441 | * We keep dev_data around for unplugged devices and reuse it when the |
442 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 443 | */ |
657cbb6b | 444 | } |
b7cc9554 | 445 | |
7f26508b JR |
446 | #ifdef CONFIG_AMD_IOMMU_STATS |
447 | ||
448 | /* | |
449 | * Initialization code for statistics collection | |
450 | */ | |
451 | ||
da49f6df | 452 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 453 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 454 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 455 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 456 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 457 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 458 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 459 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 460 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 461 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 462 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 463 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
464 | DECLARE_STATS_COUNTER(complete_ppr); |
465 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
466 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
467 | DECLARE_STATS_COUNTER(pri_requests); | |
468 | ||
7f26508b | 469 | static struct dentry *stats_dir; |
7f26508b JR |
470 | static struct dentry *de_fflush; |
471 | ||
472 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
473 | { | |
474 | if (stats_dir == NULL) | |
475 | return; | |
476 | ||
477 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
478 | &cnt->value); | |
479 | } | |
480 | ||
481 | static void amd_iommu_stats_init(void) | |
482 | { | |
483 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
484 | if (stats_dir == NULL) | |
485 | return; | |
486 | ||
7f26508b | 487 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 488 | &amd_iommu_unmap_flush); |
da49f6df JR |
489 | |
490 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 491 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 492 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 493 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 494 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 495 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 496 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 497 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 498 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 499 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 500 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 501 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
502 | amd_iommu_stats_add(&complete_ppr); |
503 | amd_iommu_stats_add(&invalidate_iotlb); | |
504 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
505 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
506 | } |
507 | ||
508 | #endif | |
509 | ||
a80dc3e0 JR |
510 | /**************************************************************************** |
511 | * | |
512 | * Interrupt handling functions | |
513 | * | |
514 | ****************************************************************************/ | |
515 | ||
e3e59876 JR |
516 | static void dump_dte_entry(u16 devid) |
517 | { | |
518 | int i; | |
519 | ||
ee6c2868 JR |
520 | for (i = 0; i < 4; ++i) |
521 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
522 | amd_iommu_dev_table[devid].data[i]); |
523 | } | |
524 | ||
945b4ac4 JR |
525 | static void dump_command(unsigned long phys_addr) |
526 | { | |
527 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
528 | int i; | |
529 | ||
530 | for (i = 0; i < 4; ++i) | |
531 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
532 | } | |
533 | ||
a345b23b | 534 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 535 | { |
3d06fca8 JR |
536 | int type, devid, domid, flags; |
537 | volatile u32 *event = __evt; | |
538 | int count = 0; | |
539 | u64 address; | |
540 | ||
541 | retry: | |
542 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
543 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
544 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
545 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
546 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
547 | ||
548 | if (type == 0) { | |
549 | /* Did we hit the erratum? */ | |
550 | if (++count == LOOP_TIMEOUT) { | |
551 | pr_err("AMD-Vi: No event written to event log\n"); | |
552 | return; | |
553 | } | |
554 | udelay(1); | |
555 | goto retry; | |
556 | } | |
90008ee4 | 557 | |
4c6f40d4 | 558 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
559 | |
560 | switch (type) { | |
561 | case EVENT_TYPE_ILL_DEV: | |
562 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
563 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 564 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 565 | address, flags); |
e3e59876 | 566 | dump_dte_entry(devid); |
90008ee4 JR |
567 | break; |
568 | case EVENT_TYPE_IO_FAULT: | |
569 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
570 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 571 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
572 | domid, address, flags); |
573 | break; | |
574 | case EVENT_TYPE_DEV_TAB_ERR: | |
575 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
576 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 577 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
578 | address, flags); |
579 | break; | |
580 | case EVENT_TYPE_PAGE_TAB_ERR: | |
581 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
582 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 583 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
584 | domid, address, flags); |
585 | break; | |
586 | case EVENT_TYPE_ILL_CMD: | |
587 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 588 | dump_command(address); |
90008ee4 JR |
589 | break; |
590 | case EVENT_TYPE_CMD_HARD_ERR: | |
591 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
592 | "flags=0x%04x]\n", address, flags); | |
593 | break; | |
594 | case EVENT_TYPE_IOTLB_INV_TO: | |
595 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
596 | "address=0x%016llx]\n", | |
c5081cd7 | 597 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
598 | address); |
599 | break; | |
600 | case EVENT_TYPE_INV_DEV_REQ: | |
601 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
602 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 603 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
604 | address, flags); |
605 | break; | |
606 | default: | |
607 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
608 | } | |
3d06fca8 JR |
609 | |
610 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
611 | } |
612 | ||
613 | static void iommu_poll_events(struct amd_iommu *iommu) | |
614 | { | |
615 | u32 head, tail; | |
90008ee4 JR |
616 | |
617 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
618 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
619 | ||
620 | while (head != tail) { | |
a345b23b | 621 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
622 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
623 | } | |
624 | ||
625 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
626 | } |
627 | ||
eee53537 | 628 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
629 | { |
630 | struct amd_iommu_fault fault; | |
72e1dcc4 | 631 | |
399be2f5 JR |
632 | INC_STATS_COUNTER(pri_requests); |
633 | ||
72e1dcc4 JR |
634 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
635 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
636 | return; | |
637 | } | |
638 | ||
639 | fault.address = raw[1]; | |
640 | fault.pasid = PPR_PASID(raw[0]); | |
641 | fault.device_id = PPR_DEVID(raw[0]); | |
642 | fault.tag = PPR_TAG(raw[0]); | |
643 | fault.flags = PPR_FLAGS(raw[0]); | |
644 | ||
72e1dcc4 JR |
645 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
646 | } | |
647 | ||
648 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
649 | { | |
72e1dcc4 JR |
650 | u32 head, tail; |
651 | ||
652 | if (iommu->ppr_log == NULL) | |
653 | return; | |
654 | ||
72e1dcc4 JR |
655 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
656 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
657 | ||
658 | while (head != tail) { | |
eee53537 JR |
659 | volatile u64 *raw; |
660 | u64 entry[2]; | |
661 | int i; | |
662 | ||
663 | raw = (u64 *)(iommu->ppr_log + head); | |
664 | ||
665 | /* | |
666 | * Hardware bug: Interrupt may arrive before the entry is | |
667 | * written to memory. If this happens we need to wait for the | |
668 | * entry to arrive. | |
669 | */ | |
670 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
671 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
672 | break; | |
673 | udelay(1); | |
674 | } | |
72e1dcc4 | 675 | |
eee53537 JR |
676 | /* Avoid memcpy function-call overhead */ |
677 | entry[0] = raw[0]; | |
678 | entry[1] = raw[1]; | |
72e1dcc4 | 679 | |
eee53537 JR |
680 | /* |
681 | * To detect the hardware bug we need to clear the entry | |
682 | * back to zero. | |
683 | */ | |
684 | raw[0] = raw[1] = 0UL; | |
685 | ||
686 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
687 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
688 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 689 | |
eee53537 JR |
690 | /* Handle PPR entry */ |
691 | iommu_handle_ppr_entry(iommu, entry); | |
692 | ||
eee53537 JR |
693 | /* Refresh ring-buffer information */ |
694 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
695 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
696 | } | |
72e1dcc4 JR |
697 | } |
698 | ||
72fe00f0 | 699 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 700 | { |
3f398bc7 SS |
701 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
702 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 703 | |
3f398bc7 SS |
704 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
705 | /* Enable EVT and PPR interrupts again */ | |
706 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
707 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 708 | |
3f398bc7 SS |
709 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
710 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
711 | iommu_poll_events(iommu); | |
712 | } | |
90008ee4 | 713 | |
3f398bc7 SS |
714 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
715 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
716 | iommu_poll_ppr_log(iommu); | |
717 | } | |
90008ee4 | 718 | |
3f398bc7 SS |
719 | /* |
720 | * Hardware bug: ERBT1312 | |
721 | * When re-enabling interrupt (by writing 1 | |
722 | * to clear the bit), the hardware might also try to set | |
723 | * the interrupt bit in the event status register. | |
724 | * In this scenario, the bit will be set, and disable | |
725 | * subsequent interrupts. | |
726 | * | |
727 | * Workaround: The IOMMU driver should read back the | |
728 | * status register and check if the interrupt bits are cleared. | |
729 | * If not, driver will need to go through the interrupt handler | |
730 | * again and re-clear the bits | |
731 | */ | |
732 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
733 | } | |
90008ee4 | 734 | return IRQ_HANDLED; |
a80dc3e0 JR |
735 | } |
736 | ||
72fe00f0 JR |
737 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
738 | { | |
739 | return IRQ_WAKE_THREAD; | |
740 | } | |
741 | ||
431b2a20 JR |
742 | /**************************************************************************** |
743 | * | |
744 | * IOMMU command queuing functions | |
745 | * | |
746 | ****************************************************************************/ | |
747 | ||
ac0ea6e9 JR |
748 | static int wait_on_sem(volatile u64 *sem) |
749 | { | |
750 | int i = 0; | |
751 | ||
752 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
753 | udelay(1); | |
754 | i += 1; | |
755 | } | |
756 | ||
757 | if (i == LOOP_TIMEOUT) { | |
758 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
759 | return -EIO; | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
766 | struct iommu_cmd *cmd, | |
767 | u32 tail) | |
a19ae1ec | 768 | { |
a19ae1ec JR |
769 | u8 *target; |
770 | ||
8a7c5ef3 | 771 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
772 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
773 | ||
774 | /* Copy command to buffer */ | |
775 | memcpy(target, cmd, sizeof(*cmd)); | |
776 | ||
777 | /* Tell the IOMMU about it */ | |
a19ae1ec | 778 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 779 | } |
a19ae1ec | 780 | |
815b33fd | 781 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 782 | { |
815b33fd JR |
783 | WARN_ON(address & 0x7ULL); |
784 | ||
ded46737 | 785 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
786 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
787 | cmd->data[1] = upper_32_bits(__pa(address)); | |
788 | cmd->data[2] = 1; | |
ded46737 JR |
789 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
790 | } | |
791 | ||
94fe79e2 JR |
792 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
793 | { | |
794 | memset(cmd, 0, sizeof(*cmd)); | |
795 | cmd->data[0] = devid; | |
796 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
797 | } | |
798 | ||
11b6402c JR |
799 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
800 | size_t size, u16 domid, int pde) | |
801 | { | |
802 | u64 pages; | |
ae0cbbb1 | 803 | bool s; |
11b6402c JR |
804 | |
805 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 806 | s = false; |
11b6402c JR |
807 | |
808 | if (pages > 1) { | |
809 | /* | |
810 | * If we have to flush more than one page, flush all | |
811 | * TLB entries for this domain | |
812 | */ | |
813 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 814 | s = true; |
11b6402c JR |
815 | } |
816 | ||
817 | address &= PAGE_MASK; | |
818 | ||
819 | memset(cmd, 0, sizeof(*cmd)); | |
820 | cmd->data[1] |= domid; | |
821 | cmd->data[2] = lower_32_bits(address); | |
822 | cmd->data[3] = upper_32_bits(address); | |
823 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
824 | if (s) /* size bit - we flush more than one 4kb page */ | |
825 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 826 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
827 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
828 | } | |
829 | ||
cb41ed85 JR |
830 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
831 | u64 address, size_t size) | |
832 | { | |
833 | u64 pages; | |
ae0cbbb1 | 834 | bool s; |
cb41ed85 JR |
835 | |
836 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 837 | s = false; |
cb41ed85 JR |
838 | |
839 | if (pages > 1) { | |
840 | /* | |
841 | * If we have to flush more than one page, flush all | |
842 | * TLB entries for this domain | |
843 | */ | |
844 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 845 | s = true; |
cb41ed85 JR |
846 | } |
847 | ||
848 | address &= PAGE_MASK; | |
849 | ||
850 | memset(cmd, 0, sizeof(*cmd)); | |
851 | cmd->data[0] = devid; | |
852 | cmd->data[0] |= (qdep & 0xff) << 24; | |
853 | cmd->data[1] = devid; | |
854 | cmd->data[2] = lower_32_bits(address); | |
855 | cmd->data[3] = upper_32_bits(address); | |
856 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
857 | if (s) | |
858 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
859 | } | |
860 | ||
22e266c7 JR |
861 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
862 | u64 address, bool size) | |
863 | { | |
864 | memset(cmd, 0, sizeof(*cmd)); | |
865 | ||
866 | address &= ~(0xfffULL); | |
867 | ||
a919a018 | 868 | cmd->data[0] = pasid; |
22e266c7 JR |
869 | cmd->data[1] = domid; |
870 | cmd->data[2] = lower_32_bits(address); | |
871 | cmd->data[3] = upper_32_bits(address); | |
872 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
873 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
874 | if (size) | |
875 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
876 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
877 | } | |
878 | ||
879 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
880 | int qdep, u64 address, bool size) | |
881 | { | |
882 | memset(cmd, 0, sizeof(*cmd)); | |
883 | ||
884 | address &= ~(0xfffULL); | |
885 | ||
886 | cmd->data[0] = devid; | |
e8d2d82d | 887 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
888 | cmd->data[0] |= (qdep & 0xff) << 24; |
889 | cmd->data[1] = devid; | |
e8d2d82d | 890 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
891 | cmd->data[2] = lower_32_bits(address); |
892 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
893 | cmd->data[3] = upper_32_bits(address); | |
894 | if (size) | |
895 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
896 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
897 | } | |
898 | ||
c99afa25 JR |
899 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
900 | int status, int tag, bool gn) | |
901 | { | |
902 | memset(cmd, 0, sizeof(*cmd)); | |
903 | ||
904 | cmd->data[0] = devid; | |
905 | if (gn) { | |
a919a018 | 906 | cmd->data[1] = pasid; |
c99afa25 JR |
907 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
908 | } | |
909 | cmd->data[3] = tag & 0x1ff; | |
910 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
911 | ||
912 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
913 | } | |
914 | ||
58fc7f14 JR |
915 | static void build_inv_all(struct iommu_cmd *cmd) |
916 | { | |
917 | memset(cmd, 0, sizeof(*cmd)); | |
918 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
919 | } |
920 | ||
7ef2798d JR |
921 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
922 | { | |
923 | memset(cmd, 0, sizeof(*cmd)); | |
924 | cmd->data[0] = devid; | |
925 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
926 | } | |
927 | ||
431b2a20 | 928 | /* |
431b2a20 | 929 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 930 | * hardware about the new command. |
431b2a20 | 931 | */ |
f1ca1512 JR |
932 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
933 | struct iommu_cmd *cmd, | |
934 | bool sync) | |
a19ae1ec | 935 | { |
ac0ea6e9 | 936 | u32 left, tail, head, next_tail; |
a19ae1ec | 937 | unsigned long flags; |
a19ae1ec | 938 | |
549c90dc | 939 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
940 | |
941 | again: | |
a19ae1ec | 942 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 943 | |
ac0ea6e9 JR |
944 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
945 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
946 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
947 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 948 | |
ac0ea6e9 JR |
949 | if (left <= 2) { |
950 | struct iommu_cmd sync_cmd; | |
951 | volatile u64 sem = 0; | |
952 | int ret; | |
8d201968 | 953 | |
ac0ea6e9 JR |
954 | build_completion_wait(&sync_cmd, (u64)&sem); |
955 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 956 | |
ac0ea6e9 JR |
957 | spin_unlock_irqrestore(&iommu->lock, flags); |
958 | ||
959 | if ((ret = wait_on_sem(&sem)) != 0) | |
960 | return ret; | |
961 | ||
962 | goto again; | |
8d201968 JR |
963 | } |
964 | ||
ac0ea6e9 JR |
965 | copy_cmd_to_buffer(iommu, cmd, tail); |
966 | ||
967 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 968 | iommu->need_sync = sync; |
ac0ea6e9 | 969 | |
a19ae1ec | 970 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 971 | |
815b33fd | 972 | return 0; |
8d201968 JR |
973 | } |
974 | ||
f1ca1512 JR |
975 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
976 | { | |
977 | return iommu_queue_command_sync(iommu, cmd, true); | |
978 | } | |
979 | ||
8d201968 JR |
980 | /* |
981 | * This function queues a completion wait command into the command | |
982 | * buffer of an IOMMU | |
983 | */ | |
a19ae1ec | 984 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
985 | { |
986 | struct iommu_cmd cmd; | |
815b33fd | 987 | volatile u64 sem = 0; |
ac0ea6e9 | 988 | int ret; |
8d201968 | 989 | |
09ee17eb | 990 | if (!iommu->need_sync) |
815b33fd | 991 | return 0; |
09ee17eb | 992 | |
815b33fd | 993 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 994 | |
f1ca1512 | 995 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 996 | if (ret) |
815b33fd | 997 | return ret; |
8d201968 | 998 | |
ac0ea6e9 | 999 | return wait_on_sem(&sem); |
8d201968 JR |
1000 | } |
1001 | ||
d8c13085 | 1002 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1003 | { |
d8c13085 | 1004 | struct iommu_cmd cmd; |
a19ae1ec | 1005 | |
d8c13085 | 1006 | build_inv_dte(&cmd, devid); |
7e4f88da | 1007 | |
d8c13085 JR |
1008 | return iommu_queue_command(iommu, &cmd); |
1009 | } | |
09ee17eb | 1010 | |
7d0c5cc5 JR |
1011 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1012 | { | |
1013 | u32 devid; | |
09ee17eb | 1014 | |
7d0c5cc5 JR |
1015 | for (devid = 0; devid <= 0xffff; ++devid) |
1016 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1017 | |
7d0c5cc5 JR |
1018 | iommu_completion_wait(iommu); |
1019 | } | |
84df8175 | 1020 | |
7d0c5cc5 JR |
1021 | /* |
1022 | * This function uses heavy locking and may disable irqs for some time. But | |
1023 | * this is no issue because it is only called during resume. | |
1024 | */ | |
1025 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1026 | { | |
1027 | u32 dom_id; | |
a19ae1ec | 1028 | |
7d0c5cc5 JR |
1029 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1030 | struct iommu_cmd cmd; | |
1031 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1032 | dom_id, 1); | |
1033 | iommu_queue_command(iommu, &cmd); | |
1034 | } | |
8eed9833 | 1035 | |
7d0c5cc5 | 1036 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1037 | } |
1038 | ||
58fc7f14 | 1039 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1040 | { |
58fc7f14 | 1041 | struct iommu_cmd cmd; |
0518a3a4 | 1042 | |
58fc7f14 | 1043 | build_inv_all(&cmd); |
0518a3a4 | 1044 | |
58fc7f14 JR |
1045 | iommu_queue_command(iommu, &cmd); |
1046 | iommu_completion_wait(iommu); | |
1047 | } | |
1048 | ||
7ef2798d JR |
1049 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1050 | { | |
1051 | struct iommu_cmd cmd; | |
1052 | ||
1053 | build_inv_irt(&cmd, devid); | |
1054 | ||
1055 | iommu_queue_command(iommu, &cmd); | |
1056 | } | |
1057 | ||
1058 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1059 | { | |
1060 | u32 devid; | |
1061 | ||
1062 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1063 | iommu_flush_irt(iommu, devid); | |
1064 | ||
1065 | iommu_completion_wait(iommu); | |
1066 | } | |
1067 | ||
7d0c5cc5 JR |
1068 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1069 | { | |
58fc7f14 JR |
1070 | if (iommu_feature(iommu, FEATURE_IA)) { |
1071 | iommu_flush_all(iommu); | |
1072 | } else { | |
1073 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1074 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1075 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1076 | } |
1077 | } | |
1078 | ||
431b2a20 | 1079 | /* |
cb41ed85 | 1080 | * Command send function for flushing on-device TLB |
431b2a20 | 1081 | */ |
6c542047 JR |
1082 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1083 | u64 address, size_t size) | |
3fa43655 JR |
1084 | { |
1085 | struct amd_iommu *iommu; | |
b00d3bcf | 1086 | struct iommu_cmd cmd; |
cb41ed85 | 1087 | int qdep; |
3fa43655 | 1088 | |
ea61cddb JR |
1089 | qdep = dev_data->ats.qdep; |
1090 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1091 | |
ea61cddb | 1092 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1093 | |
1094 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1095 | } |
1096 | ||
431b2a20 | 1097 | /* |
431b2a20 | 1098 | * Command send function for invalidating a device table entry |
431b2a20 | 1099 | */ |
6c542047 | 1100 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1101 | { |
3fa43655 | 1102 | struct amd_iommu *iommu; |
ee2fa743 | 1103 | int ret; |
a19ae1ec | 1104 | |
6c542047 | 1105 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1106 | |
f62dda66 | 1107 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1108 | if (ret) |
1109 | return ret; | |
1110 | ||
ea61cddb | 1111 | if (dev_data->ats.enabled) |
6c542047 | 1112 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1113 | |
ee2fa743 | 1114 | return ret; |
a19ae1ec JR |
1115 | } |
1116 | ||
431b2a20 JR |
1117 | /* |
1118 | * TLB invalidation function which is called from the mapping functions. | |
1119 | * It invalidates a single PTE if the range to flush is within a single | |
1120 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1121 | */ | |
17b124bf JR |
1122 | static void __domain_flush_pages(struct protection_domain *domain, |
1123 | u64 address, size_t size, int pde) | |
a19ae1ec | 1124 | { |
cb41ed85 | 1125 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1126 | struct iommu_cmd cmd; |
1127 | int ret = 0, i; | |
a19ae1ec | 1128 | |
11b6402c | 1129 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1130 | |
6de8ad9b JR |
1131 | for (i = 0; i < amd_iommus_present; ++i) { |
1132 | if (!domain->dev_iommu[i]) | |
1133 | continue; | |
1134 | ||
1135 | /* | |
1136 | * Devices of this domain are behind this IOMMU | |
1137 | * We need a TLB flush | |
1138 | */ | |
11b6402c | 1139 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1140 | } |
1141 | ||
cb41ed85 | 1142 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1143 | |
ea61cddb | 1144 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1145 | continue; |
1146 | ||
6c542047 | 1147 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1148 | } |
1149 | ||
11b6402c | 1150 | WARN_ON(ret); |
6de8ad9b JR |
1151 | } |
1152 | ||
17b124bf JR |
1153 | static void domain_flush_pages(struct protection_domain *domain, |
1154 | u64 address, size_t size) | |
6de8ad9b | 1155 | { |
17b124bf | 1156 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1157 | } |
b6c02715 | 1158 | |
1c655773 | 1159 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1160 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1161 | { |
17b124bf | 1162 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1163 | } |
1164 | ||
42a49f96 | 1165 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1166 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1167 | { |
17b124bf | 1168 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1169 | } |
1170 | ||
17b124bf | 1171 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1172 | { |
17b124bf | 1173 | int i; |
18811f55 | 1174 | |
17b124bf JR |
1175 | for (i = 0; i < amd_iommus_present; ++i) { |
1176 | if (!domain->dev_iommu[i]) | |
1177 | continue; | |
bfd1be18 | 1178 | |
17b124bf JR |
1179 | /* |
1180 | * Devices of this domain are behind this IOMMU | |
1181 | * We need to wait for completion of all commands. | |
1182 | */ | |
1183 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1184 | } |
e394d72a JR |
1185 | } |
1186 | ||
b00d3bcf | 1187 | |
09b42804 | 1188 | /* |
b00d3bcf | 1189 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1190 | */ |
17b124bf | 1191 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1192 | { |
b00d3bcf | 1193 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1194 | |
b00d3bcf | 1195 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1196 | device_flush_dte(dev_data); |
a345b23b JR |
1197 | } |
1198 | ||
431b2a20 JR |
1199 | /**************************************************************************** |
1200 | * | |
1201 | * The functions below are used the create the page table mappings for | |
1202 | * unity mapped regions. | |
1203 | * | |
1204 | ****************************************************************************/ | |
1205 | ||
308973d3 JR |
1206 | /* |
1207 | * This function is used to add another level to an IO page table. Adding | |
1208 | * another level increases the size of the address space by 9 bits to a size up | |
1209 | * to 64 bits. | |
1210 | */ | |
1211 | static bool increase_address_space(struct protection_domain *domain, | |
1212 | gfp_t gfp) | |
1213 | { | |
1214 | u64 *pte; | |
1215 | ||
1216 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1217 | /* address space already 64 bit large */ | |
1218 | return false; | |
1219 | ||
1220 | pte = (void *)get_zeroed_page(gfp); | |
1221 | if (!pte) | |
1222 | return false; | |
1223 | ||
1224 | *pte = PM_LEVEL_PDE(domain->mode, | |
1225 | virt_to_phys(domain->pt_root)); | |
1226 | domain->pt_root = pte; | |
1227 | domain->mode += 1; | |
1228 | domain->updated = true; | |
1229 | ||
1230 | return true; | |
1231 | } | |
1232 | ||
1233 | static u64 *alloc_pte(struct protection_domain *domain, | |
1234 | unsigned long address, | |
cbb9d729 | 1235 | unsigned long page_size, |
308973d3 JR |
1236 | u64 **pte_page, |
1237 | gfp_t gfp) | |
1238 | { | |
cbb9d729 | 1239 | int level, end_lvl; |
308973d3 | 1240 | u64 *pte, *page; |
cbb9d729 JR |
1241 | |
1242 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1243 | |
1244 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1245 | increase_address_space(domain, gfp); | |
1246 | ||
cbb9d729 JR |
1247 | level = domain->mode - 1; |
1248 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1249 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1250 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1251 | |
1252 | while (level > end_lvl) { | |
1253 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1254 | page = (u64 *)get_zeroed_page(gfp); | |
1255 | if (!page) | |
1256 | return NULL; | |
1257 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1258 | } | |
1259 | ||
cbb9d729 JR |
1260 | /* No level skipping support yet */ |
1261 | if (PM_PTE_LEVEL(*pte) != level) | |
1262 | return NULL; | |
1263 | ||
308973d3 JR |
1264 | level -= 1; |
1265 | ||
1266 | pte = IOMMU_PTE_PAGE(*pte); | |
1267 | ||
1268 | if (pte_page && level == end_lvl) | |
1269 | *pte_page = pte; | |
1270 | ||
1271 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1272 | } | |
1273 | ||
1274 | return pte; | |
1275 | } | |
1276 | ||
1277 | /* | |
1278 | * This function checks if there is a PTE for a given dma address. If | |
1279 | * there is one, it returns the pointer to it. | |
1280 | */ | |
3039ca1b JR |
1281 | static u64 *fetch_pte(struct protection_domain *domain, |
1282 | unsigned long address, | |
1283 | unsigned long *page_size) | |
308973d3 JR |
1284 | { |
1285 | int level; | |
1286 | u64 *pte; | |
1287 | ||
24cd7723 JR |
1288 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1289 | return NULL; | |
1290 | ||
3039ca1b JR |
1291 | level = domain->mode - 1; |
1292 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1293 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1294 | |
24cd7723 JR |
1295 | while (level > 0) { |
1296 | ||
1297 | /* Not Present */ | |
308973d3 JR |
1298 | if (!IOMMU_PTE_PRESENT(*pte)) |
1299 | return NULL; | |
1300 | ||
24cd7723 | 1301 | /* Large PTE */ |
3039ca1b JR |
1302 | if (PM_PTE_LEVEL(*pte) == 7 || |
1303 | PM_PTE_LEVEL(*pte) == 0) | |
1304 | break; | |
24cd7723 JR |
1305 | |
1306 | /* No level skipping support yet */ | |
1307 | if (PM_PTE_LEVEL(*pte) != level) | |
1308 | return NULL; | |
1309 | ||
308973d3 JR |
1310 | level -= 1; |
1311 | ||
24cd7723 | 1312 | /* Walk to the next level */ |
3039ca1b JR |
1313 | pte = IOMMU_PTE_PAGE(*pte); |
1314 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1315 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1316 | } | |
1317 | ||
1318 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1319 | unsigned long pte_mask; | |
1320 | ||
1321 | /* | |
1322 | * If we have a series of large PTEs, make | |
1323 | * sure to return a pointer to the first one. | |
1324 | */ | |
1325 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1326 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1327 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1328 | } |
1329 | ||
1330 | return pte; | |
1331 | } | |
1332 | ||
431b2a20 JR |
1333 | /* |
1334 | * Generic mapping functions. It maps a physical address into a DMA | |
1335 | * address space. It allocates the page table pages if necessary. | |
1336 | * In the future it can be extended to a generic mapping function | |
1337 | * supporting all features of AMD IOMMU page tables like level skipping | |
1338 | * and full 64 bit address spaces. | |
1339 | */ | |
38e817fe JR |
1340 | static int iommu_map_page(struct protection_domain *dom, |
1341 | unsigned long bus_addr, | |
1342 | unsigned long phys_addr, | |
abdc5eb3 | 1343 | int prot, |
cbb9d729 | 1344 | unsigned long page_size) |
bd0e5211 | 1345 | { |
8bda3092 | 1346 | u64 __pte, *pte; |
cbb9d729 | 1347 | int i, count; |
abdc5eb3 | 1348 | |
d4b03664 JR |
1349 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1350 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1351 | ||
bad1cac2 | 1352 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1353 | return -EINVAL; |
1354 | ||
d4b03664 JR |
1355 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1356 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1357 | |
63eaa75e ML |
1358 | if (!pte) |
1359 | return -ENOMEM; | |
1360 | ||
cbb9d729 JR |
1361 | for (i = 0; i < count; ++i) |
1362 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1363 | return -EBUSY; | |
bd0e5211 | 1364 | |
d4b03664 | 1365 | if (count > 1) { |
cbb9d729 JR |
1366 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1367 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1368 | } else | |
1369 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1370 | |
bd0e5211 JR |
1371 | if (prot & IOMMU_PROT_IR) |
1372 | __pte |= IOMMU_PTE_IR; | |
1373 | if (prot & IOMMU_PROT_IW) | |
1374 | __pte |= IOMMU_PTE_IW; | |
1375 | ||
cbb9d729 JR |
1376 | for (i = 0; i < count; ++i) |
1377 | pte[i] = __pte; | |
bd0e5211 | 1378 | |
04bfdd84 JR |
1379 | update_domain(dom); |
1380 | ||
bd0e5211 JR |
1381 | return 0; |
1382 | } | |
1383 | ||
24cd7723 JR |
1384 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1385 | unsigned long bus_addr, | |
1386 | unsigned long page_size) | |
eb74ff6c | 1387 | { |
71b390e9 JR |
1388 | unsigned long long unmapped; |
1389 | unsigned long unmap_size; | |
24cd7723 JR |
1390 | u64 *pte; |
1391 | ||
1392 | BUG_ON(!is_power_of_2(page_size)); | |
1393 | ||
1394 | unmapped = 0; | |
eb74ff6c | 1395 | |
24cd7723 JR |
1396 | while (unmapped < page_size) { |
1397 | ||
71b390e9 JR |
1398 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1399 | ||
1400 | if (pte) { | |
1401 | int i, count; | |
1402 | ||
1403 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1404 | for (i = 0; i < count; i++) |
1405 | pte[i] = 0ULL; | |
1406 | } | |
1407 | ||
1408 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1409 | unmapped += unmap_size; | |
1410 | } | |
1411 | ||
60d0ca3c | 1412 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1413 | |
24cd7723 | 1414 | return unmapped; |
eb74ff6c | 1415 | } |
eb74ff6c | 1416 | |
431b2a20 JR |
1417 | /* |
1418 | * This function checks if a specific unity mapping entry is needed for | |
1419 | * this specific IOMMU. | |
1420 | */ | |
bd0e5211 JR |
1421 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1422 | struct unity_map_entry *entry) | |
1423 | { | |
1424 | u16 bdf, i; | |
1425 | ||
1426 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1427 | bdf = amd_iommu_alias_table[i]; | |
1428 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1429 | return 1; | |
1430 | } | |
1431 | ||
1432 | return 0; | |
1433 | } | |
1434 | ||
431b2a20 JR |
1435 | /* |
1436 | * This function actually applies the mapping to the page table of the | |
1437 | * dma_ops domain. | |
1438 | */ | |
bd0e5211 JR |
1439 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1440 | struct unity_map_entry *e) | |
1441 | { | |
1442 | u64 addr; | |
1443 | int ret; | |
1444 | ||
1445 | for (addr = e->address_start; addr < e->address_end; | |
1446 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1447 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1448 | PAGE_SIZE); |
bd0e5211 JR |
1449 | if (ret) |
1450 | return ret; | |
1451 | /* | |
1452 | * if unity mapping is in aperture range mark the page | |
1453 | * as allocated in the aperture | |
1454 | */ | |
1455 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1456 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1457 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1458 | } |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
171e7b37 JR |
1463 | /* |
1464 | * Init the unity mappings for a specific IOMMU in the system | |
1465 | * | |
1466 | * Basically iterates over all unity mapping entries and applies them to | |
1467 | * the default domain DMA of that IOMMU if necessary. | |
1468 | */ | |
1469 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1470 | { | |
1471 | struct unity_map_entry *entry; | |
1472 | int ret; | |
1473 | ||
1474 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1475 | if (!iommu_for_unity_map(iommu, entry)) | |
1476 | continue; | |
1477 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1478 | if (ret) | |
1479 | return ret; | |
1480 | } | |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
431b2a20 JR |
1485 | /* |
1486 | * Inits the unity mappings required for a specific device | |
1487 | */ | |
bd0e5211 JR |
1488 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1489 | u16 devid) | |
1490 | { | |
1491 | struct unity_map_entry *e; | |
1492 | int ret; | |
1493 | ||
1494 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1495 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1496 | continue; | |
1497 | ret = dma_ops_unity_map(dma_dom, e); | |
1498 | if (ret) | |
1499 | return ret; | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
431b2a20 JR |
1505 | /**************************************************************************** |
1506 | * | |
1507 | * The next functions belong to the address allocator for the dma_ops | |
1508 | * interface functions. They work like the allocators in the other IOMMU | |
1509 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1510 | * the aperture. Maybe it could be enhanced in the future to a more | |
1511 | * efficient allocator. | |
1512 | * | |
1513 | ****************************************************************************/ | |
d3086444 | 1514 | |
431b2a20 | 1515 | /* |
384de729 | 1516 | * The address allocator core functions. |
431b2a20 JR |
1517 | * |
1518 | * called with domain->lock held | |
1519 | */ | |
384de729 | 1520 | |
171e7b37 JR |
1521 | /* |
1522 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1523 | * ranges. | |
1524 | */ | |
1525 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1526 | unsigned long start_page, | |
1527 | unsigned int pages) | |
1528 | { | |
1529 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1530 | ||
1531 | if (start_page + pages > last_page) | |
1532 | pages = last_page - start_page; | |
1533 | ||
1534 | for (i = start_page; i < start_page + pages; ++i) { | |
1535 | int index = i / APERTURE_RANGE_PAGES; | |
1536 | int page = i % APERTURE_RANGE_PAGES; | |
1537 | __set_bit(page, dom->aperture[index]->bitmap); | |
1538 | } | |
1539 | } | |
1540 | ||
9cabe89b JR |
1541 | /* |
1542 | * This function is used to add a new aperture range to an existing | |
1543 | * aperture in case of dma_ops domain allocation or address allocation | |
1544 | * failure. | |
1545 | */ | |
576175c2 | 1546 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1547 | bool populate, gfp_t gfp) |
1548 | { | |
1549 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1550 | struct amd_iommu *iommu; |
5d7c94c3 | 1551 | unsigned long i, old_size, pte_pgsize; |
9cabe89b | 1552 | |
f5e9705c JR |
1553 | #ifdef CONFIG_IOMMU_STRESS |
1554 | populate = false; | |
1555 | #endif | |
1556 | ||
9cabe89b JR |
1557 | if (index >= APERTURE_MAX_RANGES) |
1558 | return -ENOMEM; | |
1559 | ||
1560 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1561 | if (!dma_dom->aperture[index]) | |
1562 | return -ENOMEM; | |
1563 | ||
1564 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1565 | if (!dma_dom->aperture[index]->bitmap) | |
1566 | goto out_free; | |
1567 | ||
1568 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1569 | ||
1570 | if (populate) { | |
1571 | unsigned long address = dma_dom->aperture_size; | |
1572 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1573 | u64 *pte, *pte_page; | |
1574 | ||
1575 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1576 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1577 | &pte_page, gfp); |
1578 | if (!pte) | |
1579 | goto out_free; | |
1580 | ||
1581 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1582 | ||
1583 | address += APERTURE_RANGE_SIZE / 64; | |
1584 | } | |
1585 | } | |
1586 | ||
17f5b569 | 1587 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1588 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1589 | ||
17f5b569 JR |
1590 | /* Reserve address range used for MSI messages */ |
1591 | if (old_size < MSI_ADDR_BASE_LO && | |
1592 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1593 | unsigned long spage; | |
1594 | int pages; | |
1595 | ||
1596 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1597 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1598 | ||
1599 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1600 | } | |
1601 | ||
b595076a | 1602 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1603 | for_each_iommu(iommu) { |
1604 | if (iommu->exclusion_start && | |
1605 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1606 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1607 | unsigned long startpage; | |
1608 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1609 | iommu->exclusion_length, | |
1610 | PAGE_SIZE); | |
1611 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1612 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1613 | } | |
00cd122a JR |
1614 | } |
1615 | ||
1616 | /* | |
1617 | * Check for areas already mapped as present in the new aperture | |
1618 | * range and mark those pages as reserved in the allocator. Such | |
1619 | * mappings may already exist as a result of requested unity | |
1620 | * mappings for devices. | |
1621 | */ | |
1622 | for (i = dma_dom->aperture[index]->offset; | |
1623 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1624 | i += pte_pgsize) { |
3039ca1b | 1625 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1626 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1627 | continue; | |
1628 | ||
5d7c94c3 JR |
1629 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1630 | pte_pgsize >> 12); | |
00cd122a JR |
1631 | } |
1632 | ||
04bfdd84 JR |
1633 | update_domain(&dma_dom->domain); |
1634 | ||
9cabe89b JR |
1635 | return 0; |
1636 | ||
1637 | out_free: | |
04bfdd84 JR |
1638 | update_domain(&dma_dom->domain); |
1639 | ||
9cabe89b JR |
1640 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1641 | ||
1642 | kfree(dma_dom->aperture[index]); | |
1643 | dma_dom->aperture[index] = NULL; | |
1644 | ||
1645 | return -ENOMEM; | |
1646 | } | |
1647 | ||
384de729 JR |
1648 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1649 | struct dma_ops_domain *dom, | |
1650 | unsigned int pages, | |
1651 | unsigned long align_mask, | |
1652 | u64 dma_mask, | |
1653 | unsigned long start) | |
1654 | { | |
803b8cb4 | 1655 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1656 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1657 | int i = start >> APERTURE_RANGE_SHIFT; | |
1658 | unsigned long boundary_size; | |
1659 | unsigned long address = -1; | |
1660 | unsigned long limit; | |
1661 | ||
803b8cb4 JR |
1662 | next_bit >>= PAGE_SHIFT; |
1663 | ||
384de729 JR |
1664 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1665 | PAGE_SIZE) >> PAGE_SHIFT; | |
1666 | ||
1667 | for (;i < max_index; ++i) { | |
1668 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1669 | ||
1670 | if (dom->aperture[i]->offset >= dma_mask) | |
1671 | break; | |
1672 | ||
1673 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1674 | dma_mask >> PAGE_SHIFT); | |
1675 | ||
1676 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1677 | limit, next_bit, pages, 0, | |
1678 | boundary_size, align_mask); | |
1679 | if (address != -1) { | |
1680 | address = dom->aperture[i]->offset + | |
1681 | (address << PAGE_SHIFT); | |
803b8cb4 | 1682 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1683 | break; |
1684 | } | |
1685 | ||
1686 | next_bit = 0; | |
1687 | } | |
1688 | ||
1689 | return address; | |
1690 | } | |
1691 | ||
d3086444 JR |
1692 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1693 | struct dma_ops_domain *dom, | |
6d4f343f | 1694 | unsigned int pages, |
832a90c3 JR |
1695 | unsigned long align_mask, |
1696 | u64 dma_mask) | |
d3086444 | 1697 | { |
d3086444 | 1698 | unsigned long address; |
d3086444 | 1699 | |
fe16f088 JR |
1700 | #ifdef CONFIG_IOMMU_STRESS |
1701 | dom->next_address = 0; | |
1702 | dom->need_flush = true; | |
1703 | #endif | |
d3086444 | 1704 | |
384de729 | 1705 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1706 | dma_mask, dom->next_address); |
d3086444 | 1707 | |
1c655773 | 1708 | if (address == -1) { |
803b8cb4 | 1709 | dom->next_address = 0; |
384de729 JR |
1710 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1711 | dma_mask, 0); | |
1c655773 JR |
1712 | dom->need_flush = true; |
1713 | } | |
d3086444 | 1714 | |
384de729 | 1715 | if (unlikely(address == -1)) |
8fd524b3 | 1716 | address = DMA_ERROR_CODE; |
d3086444 JR |
1717 | |
1718 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1719 | ||
1720 | return address; | |
1721 | } | |
1722 | ||
431b2a20 JR |
1723 | /* |
1724 | * The address free function. | |
1725 | * | |
1726 | * called with domain->lock held | |
1727 | */ | |
d3086444 JR |
1728 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1729 | unsigned long address, | |
1730 | unsigned int pages) | |
1731 | { | |
384de729 JR |
1732 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1733 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1734 | |
384de729 JR |
1735 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1736 | ||
47bccd6b JR |
1737 | #ifdef CONFIG_IOMMU_STRESS |
1738 | if (i < 4) | |
1739 | return; | |
1740 | #endif | |
80be308d | 1741 | |
803b8cb4 | 1742 | if (address >= dom->next_address) |
80be308d | 1743 | dom->need_flush = true; |
384de729 JR |
1744 | |
1745 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1746 | |
a66022c4 | 1747 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1748 | |
d3086444 JR |
1749 | } |
1750 | ||
431b2a20 JR |
1751 | /**************************************************************************** |
1752 | * | |
1753 | * The next functions belong to the domain allocation. A domain is | |
1754 | * allocated for every IOMMU as the default domain. If device isolation | |
1755 | * is enabled, every device get its own domain. The most important thing | |
1756 | * about domains is the page table mapping the DMA address space they | |
1757 | * contain. | |
1758 | * | |
1759 | ****************************************************************************/ | |
1760 | ||
aeb26f55 JR |
1761 | /* |
1762 | * This function adds a protection domain to the global protection domain list | |
1763 | */ | |
1764 | static void add_domain_to_list(struct protection_domain *domain) | |
1765 | { | |
1766 | unsigned long flags; | |
1767 | ||
1768 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1769 | list_add(&domain->list, &amd_iommu_pd_list); | |
1770 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1771 | } | |
1772 | ||
1773 | /* | |
1774 | * This function removes a protection domain to the global | |
1775 | * protection domain list | |
1776 | */ | |
1777 | static void del_domain_from_list(struct protection_domain *domain) | |
1778 | { | |
1779 | unsigned long flags; | |
1780 | ||
1781 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1782 | list_del(&domain->list); | |
1783 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1784 | } | |
1785 | ||
ec487d1a JR |
1786 | static u16 domain_id_alloc(void) |
1787 | { | |
1788 | unsigned long flags; | |
1789 | int id; | |
1790 | ||
1791 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1792 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1793 | BUG_ON(id == 0); | |
1794 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1795 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1796 | else | |
1797 | id = 0; | |
1798 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1799 | ||
1800 | return id; | |
1801 | } | |
1802 | ||
a2acfb75 JR |
1803 | static void domain_id_free(int id) |
1804 | { | |
1805 | unsigned long flags; | |
1806 | ||
1807 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1808 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1809 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1810 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1811 | } | |
a2acfb75 | 1812 | |
5c34c403 JR |
1813 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1814 | static void free_pt_##LVL (unsigned long __pt) \ | |
1815 | { \ | |
1816 | unsigned long p; \ | |
1817 | u64 *pt; \ | |
1818 | int i; \ | |
1819 | \ | |
1820 | pt = (u64 *)__pt; \ | |
1821 | \ | |
1822 | for (i = 0; i < 512; ++i) { \ | |
1823 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1824 | continue; \ | |
1825 | \ | |
1826 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1827 | FN(p); \ | |
1828 | } \ | |
1829 | free_page((unsigned long)pt); \ | |
1830 | } | |
1831 | ||
1832 | DEFINE_FREE_PT_FN(l2, free_page) | |
1833 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1834 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1835 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1836 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1837 | ||
86db2e5d | 1838 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1839 | { |
5c34c403 | 1840 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1841 | |
5c34c403 JR |
1842 | switch (domain->mode) { |
1843 | case PAGE_MODE_NONE: | |
1844 | break; | |
1845 | case PAGE_MODE_1_LEVEL: | |
1846 | free_page(root); | |
1847 | break; | |
1848 | case PAGE_MODE_2_LEVEL: | |
1849 | free_pt_l2(root); | |
1850 | break; | |
1851 | case PAGE_MODE_3_LEVEL: | |
1852 | free_pt_l3(root); | |
1853 | break; | |
1854 | case PAGE_MODE_4_LEVEL: | |
1855 | free_pt_l4(root); | |
1856 | break; | |
1857 | case PAGE_MODE_5_LEVEL: | |
1858 | free_pt_l5(root); | |
1859 | break; | |
1860 | case PAGE_MODE_6_LEVEL: | |
1861 | free_pt_l6(root); | |
1862 | break; | |
1863 | default: | |
1864 | BUG(); | |
ec487d1a | 1865 | } |
ec487d1a JR |
1866 | } |
1867 | ||
b16137b1 JR |
1868 | static void free_gcr3_tbl_level1(u64 *tbl) |
1869 | { | |
1870 | u64 *ptr; | |
1871 | int i; | |
1872 | ||
1873 | for (i = 0; i < 512; ++i) { | |
1874 | if (!(tbl[i] & GCR3_VALID)) | |
1875 | continue; | |
1876 | ||
1877 | ptr = __va(tbl[i] & PAGE_MASK); | |
1878 | ||
1879 | free_page((unsigned long)ptr); | |
1880 | } | |
1881 | } | |
1882 | ||
1883 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1884 | { | |
1885 | u64 *ptr; | |
1886 | int i; | |
1887 | ||
1888 | for (i = 0; i < 512; ++i) { | |
1889 | if (!(tbl[i] & GCR3_VALID)) | |
1890 | continue; | |
1891 | ||
1892 | ptr = __va(tbl[i] & PAGE_MASK); | |
1893 | ||
1894 | free_gcr3_tbl_level1(ptr); | |
1895 | } | |
1896 | } | |
1897 | ||
52815b75 JR |
1898 | static void free_gcr3_table(struct protection_domain *domain) |
1899 | { | |
b16137b1 JR |
1900 | if (domain->glx == 2) |
1901 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1902 | else if (domain->glx == 1) | |
1903 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1904 | else if (domain->glx != 0) | |
1905 | BUG(); | |
1906 | ||
52815b75 JR |
1907 | free_page((unsigned long)domain->gcr3_tbl); |
1908 | } | |
1909 | ||
431b2a20 JR |
1910 | /* |
1911 | * Free a domain, only used if something went wrong in the | |
1912 | * allocation path and we need to free an already allocated page table | |
1913 | */ | |
ec487d1a JR |
1914 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1915 | { | |
384de729 JR |
1916 | int i; |
1917 | ||
ec487d1a JR |
1918 | if (!dom) |
1919 | return; | |
1920 | ||
aeb26f55 JR |
1921 | del_domain_from_list(&dom->domain); |
1922 | ||
86db2e5d | 1923 | free_pagetable(&dom->domain); |
ec487d1a | 1924 | |
384de729 JR |
1925 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1926 | if (!dom->aperture[i]) | |
1927 | continue; | |
1928 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1929 | kfree(dom->aperture[i]); | |
1930 | } | |
ec487d1a JR |
1931 | |
1932 | kfree(dom); | |
1933 | } | |
1934 | ||
431b2a20 JR |
1935 | /* |
1936 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1937 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1938 | * structures required for the dma_ops interface |
1939 | */ | |
87a64d52 | 1940 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1941 | { |
1942 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1943 | |
1944 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1945 | if (!dma_dom) | |
1946 | return NULL; | |
1947 | ||
1948 | spin_lock_init(&dma_dom->domain.lock); | |
1949 | ||
1950 | dma_dom->domain.id = domain_id_alloc(); | |
1951 | if (dma_dom->domain.id == 0) | |
1952 | goto free_dma_dom; | |
7c392cbe | 1953 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1954 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1955 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1956 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1957 | dma_dom->domain.priv = dma_dom; |
1958 | if (!dma_dom->domain.pt_root) | |
1959 | goto free_dma_dom; | |
ec487d1a | 1960 | |
1c655773 | 1961 | dma_dom->need_flush = false; |
bd60b735 | 1962 | dma_dom->target_dev = 0xffff; |
1c655773 | 1963 | |
aeb26f55 JR |
1964 | add_domain_to_list(&dma_dom->domain); |
1965 | ||
576175c2 | 1966 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1967 | goto free_dma_dom; |
ec487d1a | 1968 | |
431b2a20 | 1969 | /* |
ec487d1a JR |
1970 | * mark the first page as allocated so we never return 0 as |
1971 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1972 | */ |
384de729 | 1973 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1974 | dma_dom->next_address = 0; |
ec487d1a | 1975 | |
ec487d1a JR |
1976 | |
1977 | return dma_dom; | |
1978 | ||
1979 | free_dma_dom: | |
1980 | dma_ops_domain_free(dma_dom); | |
1981 | ||
1982 | return NULL; | |
1983 | } | |
1984 | ||
5b28df6f JR |
1985 | /* |
1986 | * little helper function to check whether a given protection domain is a | |
1987 | * dma_ops domain | |
1988 | */ | |
1989 | static bool dma_ops_domain(struct protection_domain *domain) | |
1990 | { | |
1991 | return domain->flags & PD_DMA_OPS_MASK; | |
1992 | } | |
1993 | ||
fd7b5535 | 1994 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1995 | { |
132bd68f | 1996 | u64 pte_root = 0; |
ee6c2868 | 1997 | u64 flags = 0; |
863c74eb | 1998 | |
132bd68f JR |
1999 | if (domain->mode != PAGE_MODE_NONE) |
2000 | pte_root = virt_to_phys(domain->pt_root); | |
2001 | ||
38ddf41b JR |
2002 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2003 | << DEV_ENTRY_MODE_SHIFT; | |
2004 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2005 | |
ee6c2868 JR |
2006 | flags = amd_iommu_dev_table[devid].data[1]; |
2007 | ||
fd7b5535 JR |
2008 | if (ats) |
2009 | flags |= DTE_FLAG_IOTLB; | |
2010 | ||
52815b75 JR |
2011 | if (domain->flags & PD_IOMMUV2_MASK) { |
2012 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2013 | u64 glx = domain->glx; | |
2014 | u64 tmp; | |
2015 | ||
2016 | pte_root |= DTE_FLAG_GV; | |
2017 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2018 | ||
2019 | /* First mask out possible old values for GCR3 table */ | |
2020 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2021 | flags &= ~tmp; | |
2022 | ||
2023 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2024 | flags &= ~tmp; | |
2025 | ||
2026 | /* Encode GCR3 table into DTE */ | |
2027 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2028 | pte_root |= tmp; | |
2029 | ||
2030 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2031 | flags |= tmp; | |
2032 | ||
2033 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2034 | flags |= tmp; | |
2035 | } | |
2036 | ||
ee6c2868 JR |
2037 | flags &= ~(0xffffUL); |
2038 | flags |= domain->id; | |
2039 | ||
2040 | amd_iommu_dev_table[devid].data[1] = flags; | |
2041 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2042 | } |
2043 | ||
2044 | static void clear_dte_entry(u16 devid) | |
2045 | { | |
15898bbc JR |
2046 | /* remove entry from the device table seen by the hardware */ |
2047 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2048 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2049 | |
2050 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2051 | } |
2052 | ||
ec9e79ef JR |
2053 | static void do_attach(struct iommu_dev_data *dev_data, |
2054 | struct protection_domain *domain) | |
7f760ddd | 2055 | { |
7f760ddd | 2056 | struct amd_iommu *iommu; |
ec9e79ef | 2057 | bool ats; |
fd7b5535 | 2058 | |
ec9e79ef JR |
2059 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2060 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2061 | |
2062 | /* Update data structures */ | |
2063 | dev_data->domain = domain; | |
2064 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2065 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2066 | |
2067 | /* Do reference counting */ | |
2068 | domain->dev_iommu[iommu->index] += 1; | |
2069 | domain->dev_cnt += 1; | |
2070 | ||
2071 | /* Flush the DTE entry */ | |
6c542047 | 2072 | device_flush_dte(dev_data); |
7f760ddd JR |
2073 | } |
2074 | ||
ec9e79ef | 2075 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2076 | { |
7f760ddd | 2077 | struct amd_iommu *iommu; |
7f760ddd | 2078 | |
ec9e79ef | 2079 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2080 | |
2081 | /* decrease reference counters */ | |
7f760ddd JR |
2082 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2083 | dev_data->domain->dev_cnt -= 1; | |
2084 | ||
2085 | /* Update data structures */ | |
2086 | dev_data->domain = NULL; | |
2087 | list_del(&dev_data->list); | |
f62dda66 | 2088 | clear_dte_entry(dev_data->devid); |
15898bbc | 2089 | |
7f760ddd | 2090 | /* Flush the DTE entry */ |
6c542047 | 2091 | device_flush_dte(dev_data); |
2b681faf JR |
2092 | } |
2093 | ||
2094 | /* | |
2095 | * If a device is not yet associated with a domain, this function does | |
2096 | * assigns it visible for the hardware | |
2097 | */ | |
ec9e79ef | 2098 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2099 | struct protection_domain *domain) |
2b681faf | 2100 | { |
397111ab | 2101 | struct iommu_dev_data *head, *entry; |
84fe6c19 | 2102 | int ret; |
657cbb6b | 2103 | |
2b681faf JR |
2104 | /* lock domain */ |
2105 | spin_lock(&domain->lock); | |
2106 | ||
397111ab | 2107 | head = dev_data; |
15898bbc | 2108 | |
397111ab JR |
2109 | if (head->alias_data != NULL) |
2110 | head = head->alias_data; | |
eba6ac60 | 2111 | |
397111ab | 2112 | /* Now we have the root of the alias group, if any */ |
15898bbc | 2113 | |
397111ab JR |
2114 | ret = -EBUSY; |
2115 | if (head->domain != NULL) | |
2116 | goto out_unlock; | |
15898bbc | 2117 | |
397111ab JR |
2118 | /* Attach alias group root */ |
2119 | do_attach(head, domain); | |
eba6ac60 | 2120 | |
397111ab JR |
2121 | /* Attach other devices in the alias group */ |
2122 | list_for_each_entry(entry, &head->alias_list, alias_list) | |
2123 | do_attach(entry, domain); | |
24100055 | 2124 | |
84fe6c19 JL |
2125 | ret = 0; |
2126 | ||
2127 | out_unlock: | |
2128 | ||
eba6ac60 JR |
2129 | /* ready */ |
2130 | spin_unlock(&domain->lock); | |
15898bbc | 2131 | |
84fe6c19 | 2132 | return ret; |
0feae533 | 2133 | } |
b20ac0d4 | 2134 | |
52815b75 JR |
2135 | |
2136 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2137 | { | |
2138 | pci_disable_ats(pdev); | |
2139 | pci_disable_pri(pdev); | |
2140 | pci_disable_pasid(pdev); | |
2141 | } | |
2142 | ||
6a113ddc JR |
2143 | /* FIXME: Change generic reset-function to do the same */ |
2144 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2145 | { | |
2146 | u16 control; | |
2147 | int pos; | |
2148 | ||
46277b75 | 2149 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2150 | if (!pos) |
2151 | return -EINVAL; | |
2152 | ||
46277b75 JR |
2153 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2154 | control |= PCI_PRI_CTRL_RESET; | |
2155 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2156 | |
2157 | return 0; | |
2158 | } | |
2159 | ||
52815b75 JR |
2160 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2161 | { | |
6a113ddc JR |
2162 | bool reset_enable; |
2163 | int reqs, ret; | |
2164 | ||
2165 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2166 | reqs = 32; | |
2167 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2168 | reqs = 1; | |
2169 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2170 | |
2171 | /* Only allow access to user-accessible pages */ | |
2172 | ret = pci_enable_pasid(pdev, 0); | |
2173 | if (ret) | |
2174 | goto out_err; | |
2175 | ||
2176 | /* First reset the PRI state of the device */ | |
2177 | ret = pci_reset_pri(pdev); | |
2178 | if (ret) | |
2179 | goto out_err; | |
2180 | ||
6a113ddc JR |
2181 | /* Enable PRI */ |
2182 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2183 | if (ret) |
2184 | goto out_err; | |
2185 | ||
6a113ddc JR |
2186 | if (reset_enable) { |
2187 | ret = pri_reset_while_enabled(pdev); | |
2188 | if (ret) | |
2189 | goto out_err; | |
2190 | } | |
2191 | ||
52815b75 JR |
2192 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2193 | if (ret) | |
2194 | goto out_err; | |
2195 | ||
2196 | return 0; | |
2197 | ||
2198 | out_err: | |
2199 | pci_disable_pri(pdev); | |
2200 | pci_disable_pasid(pdev); | |
2201 | ||
2202 | return ret; | |
2203 | } | |
2204 | ||
c99afa25 | 2205 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2206 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2207 | |
98f1ad25 | 2208 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2209 | { |
a3b93121 | 2210 | u16 status; |
c99afa25 JR |
2211 | int pos; |
2212 | ||
46277b75 | 2213 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2214 | if (!pos) |
2215 | return false; | |
2216 | ||
a3b93121 | 2217 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2218 | |
a3b93121 | 2219 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2220 | } |
2221 | ||
407d733e | 2222 | /* |
df805abb | 2223 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2224 | * assigns it visible for the hardware |
2225 | */ | |
15898bbc JR |
2226 | static int attach_device(struct device *dev, |
2227 | struct protection_domain *domain) | |
0feae533 | 2228 | { |
fd7b5535 | 2229 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2230 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2231 | unsigned long flags; |
15898bbc | 2232 | int ret; |
eba6ac60 | 2233 | |
ea61cddb JR |
2234 | dev_data = get_dev_data(dev); |
2235 | ||
52815b75 JR |
2236 | if (domain->flags & PD_IOMMUV2_MASK) { |
2237 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2238 | return -EINVAL; | |
2239 | ||
2240 | if (pdev_iommuv2_enable(pdev) != 0) | |
2241 | return -EINVAL; | |
2242 | ||
2243 | dev_data->ats.enabled = true; | |
2244 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2245 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2246 | } else if (amd_iommu_iotlb_sup && |
2247 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2248 | dev_data->ats.enabled = true; |
2249 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2250 | } | |
fd7b5535 | 2251 | |
eba6ac60 | 2252 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2253 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2254 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2255 | ||
0feae533 JR |
2256 | /* |
2257 | * We might boot into a crash-kernel here. The crashed kernel | |
2258 | * left the caches in the IOMMU dirty. So we have to flush | |
2259 | * here to evict all dirty stuff. | |
2260 | */ | |
17b124bf | 2261 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2262 | |
2263 | return ret; | |
b20ac0d4 JR |
2264 | } |
2265 | ||
355bf553 JR |
2266 | /* |
2267 | * Removes a device from a protection domain (unlocked) | |
2268 | */ | |
ec9e79ef | 2269 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2270 | { |
397111ab | 2271 | struct iommu_dev_data *head, *entry; |
2ca76279 | 2272 | struct protection_domain *domain; |
7c392cbe | 2273 | unsigned long flags; |
c4596114 | 2274 | |
7f760ddd | 2275 | BUG_ON(!dev_data->domain); |
355bf553 | 2276 | |
2ca76279 JR |
2277 | domain = dev_data->domain; |
2278 | ||
2279 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2280 | |
397111ab JR |
2281 | head = dev_data; |
2282 | if (head->alias_data != NULL) | |
2283 | head = head->alias_data; | |
71f77580 | 2284 | |
397111ab JR |
2285 | list_for_each_entry(entry, &head->alias_list, alias_list) |
2286 | do_detach(entry); | |
24100055 | 2287 | |
397111ab | 2288 | do_detach(head); |
7f760ddd | 2289 | |
2ca76279 | 2290 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2291 | |
2292 | /* | |
2293 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2294 | * passthrough domain if it is detached from any other domain. |
2295 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2296 | */ |
5abcdba4 | 2297 | if (dev_data->passthrough && |
d3ad9373 | 2298 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2299 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2300 | } |
2301 | ||
2302 | /* | |
2303 | * Removes a device from a protection domain (with devtable_lock held) | |
2304 | */ | |
15898bbc | 2305 | static void detach_device(struct device *dev) |
355bf553 | 2306 | { |
52815b75 | 2307 | struct protection_domain *domain; |
ea61cddb | 2308 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2309 | unsigned long flags; |
2310 | ||
ec9e79ef | 2311 | dev_data = get_dev_data(dev); |
52815b75 | 2312 | domain = dev_data->domain; |
ec9e79ef | 2313 | |
355bf553 JR |
2314 | /* lock device table */ |
2315 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2316 | __detach_device(dev_data); |
355bf553 | 2317 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2318 | |
52815b75 JR |
2319 | if (domain->flags & PD_IOMMUV2_MASK) |
2320 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2321 | else if (dev_data->ats.enabled) | |
ea61cddb | 2322 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2323 | |
2324 | dev_data->ats.enabled = false; | |
355bf553 | 2325 | } |
e275a2a0 | 2326 | |
15898bbc JR |
2327 | /* |
2328 | * Find out the protection domain structure for a given PCI device. This | |
2329 | * will give us the pointer to the page table root for example. | |
2330 | */ | |
2331 | static struct protection_domain *domain_for_device(struct device *dev) | |
2332 | { | |
71f77580 | 2333 | struct iommu_dev_data *dev_data; |
2b02b091 | 2334 | struct protection_domain *dom = NULL; |
15898bbc | 2335 | unsigned long flags; |
15898bbc | 2336 | |
657cbb6b | 2337 | dev_data = get_dev_data(dev); |
15898bbc | 2338 | |
2b02b091 JR |
2339 | if (dev_data->domain) |
2340 | return dev_data->domain; | |
15898bbc | 2341 | |
71f77580 JR |
2342 | if (dev_data->alias_data != NULL) { |
2343 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2344 | |
2345 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2346 | if (alias_data->domain != NULL) { | |
2347 | __attach_device(dev_data, alias_data->domain); | |
2348 | dom = alias_data->domain; | |
2349 | } | |
2350 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2351 | } | |
15898bbc JR |
2352 | |
2353 | return dom; | |
2354 | } | |
2355 | ||
aafd8ba0 | 2356 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2357 | { |
e275a2a0 | 2358 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2359 | struct protection_domain *domain; |
2360 | struct iommu_dev_data *dev_data; | |
e275a2a0 | 2361 | struct amd_iommu *iommu; |
1ac4cbbc | 2362 | unsigned long flags; |
5abcdba4 | 2363 | u16 devid; |
aafd8ba0 | 2364 | int ret; |
e275a2a0 | 2365 | |
aafd8ba0 | 2366 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2367 | return 0; |
e275a2a0 | 2368 | |
aafd8ba0 JR |
2369 | devid = get_device_id(dev); |
2370 | iommu = amd_iommu_rlookup_table[devid]; | |
657cbb6b | 2371 | |
aafd8ba0 JR |
2372 | ret = iommu_init_device(dev); |
2373 | if (ret == -ENOTSUPP) { | |
2374 | iommu_ignore_device(dev); | |
2375 | goto out; | |
2376 | } | |
2377 | init_iommu_group(dev); | |
2c9195e9 | 2378 | |
aafd8ba0 | 2379 | dev_data = get_dev_data(dev); |
2c9195e9 | 2380 | |
aafd8ba0 JR |
2381 | if (iommu_pass_through || dev_data->iommu_v2) { |
2382 | /* Make sure passthrough domain is allocated */ | |
2383 | alloc_passthrough_domain(); | |
2384 | dev_data->passthrough = true; | |
2385 | attach_device(dev, pt_domain); | |
2386 | goto out; | |
2387 | } | |
657cbb6b | 2388 | |
aafd8ba0 | 2389 | domain = domain_for_device(dev); |
c2a2876e | 2390 | |
aafd8ba0 JR |
2391 | /* allocate a protection domain if a device is added */ |
2392 | dma_domain = find_protection_domain(devid); | |
2393 | if (!dma_domain) { | |
2394 | dma_domain = dma_ops_domain_alloc(); | |
2395 | if (!dma_domain) | |
2396 | goto out; | |
2397 | dma_domain->target_dev = devid; | |
ac1534a5 | 2398 | |
aafd8ba0 | 2399 | init_unity_mappings_for_device(dma_domain, devid); |
ac1534a5 | 2400 | |
aafd8ba0 JR |
2401 | spin_lock_irqsave(&iommu_pd_list_lock, flags); |
2402 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2403 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2404 | } | |
657cbb6b | 2405 | |
aafd8ba0 | 2406 | attach_device(dev, &dma_domain->domain); |
657cbb6b | 2407 | |
aafd8ba0 | 2408 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2409 | |
aafd8ba0 | 2410 | out: |
e275a2a0 JR |
2411 | iommu_completion_wait(iommu); |
2412 | ||
e275a2a0 JR |
2413 | return 0; |
2414 | } | |
2415 | ||
aafd8ba0 | 2416 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2417 | { |
aafd8ba0 JR |
2418 | struct amd_iommu *iommu; |
2419 | u16 devid; | |
2420 | ||
2421 | if (!check_device(dev)) | |
2422 | return; | |
2423 | ||
2424 | devid = get_device_id(dev); | |
2425 | iommu = amd_iommu_rlookup_table[devid]; | |
2426 | ||
2427 | iommu_uninit_device(dev); | |
2428 | iommu_completion_wait(iommu); | |
8638c491 JR |
2429 | } |
2430 | ||
431b2a20 JR |
2431 | /***************************************************************************** |
2432 | * | |
2433 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2434 | * | |
2435 | *****************************************************************************/ | |
2436 | ||
2437 | /* | |
2438 | * In the dma_ops path we only have the struct device. This function | |
2439 | * finds the corresponding IOMMU, the protection domain and the | |
2440 | * requestor id for a given device. | |
2441 | * If the device is not yet associated with a domain this is also done | |
2442 | * in this function. | |
2443 | */ | |
94f6d190 | 2444 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2445 | { |
94f6d190 | 2446 | struct protection_domain *domain; |
063071df | 2447 | struct iommu_domain *io_domain; |
b20ac0d4 | 2448 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2449 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2450 | |
f99c0f1c | 2451 | if (!check_device(dev)) |
94f6d190 | 2452 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2453 | |
063071df JR |
2454 | io_domain = iommu_get_domain_for_dev(dev); |
2455 | if (io_domain) { | |
2456 | domain = to_pdomain(io_domain); | |
2457 | return domain; | |
2458 | } | |
2459 | ||
94f6d190 JR |
2460 | domain = domain_for_device(dev); |
2461 | if (domain != NULL && !dma_ops_domain(domain)) | |
2462 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2463 | |
94f6d190 JR |
2464 | if (domain != NULL) |
2465 | return domain; | |
b20ac0d4 | 2466 | |
df805abb | 2467 | /* Device not bound yet - bind it */ |
94f6d190 | 2468 | dma_dom = find_protection_domain(devid); |
15898bbc | 2469 | if (!dma_dom) |
94f6d190 JR |
2470 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2471 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2472 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2473 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2474 | |
94f6d190 | 2475 | return &dma_dom->domain; |
b20ac0d4 JR |
2476 | } |
2477 | ||
04bfdd84 JR |
2478 | static void update_device_table(struct protection_domain *domain) |
2479 | { | |
492667da | 2480 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2481 | |
ea61cddb JR |
2482 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2483 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2484 | } |
2485 | ||
2486 | static void update_domain(struct protection_domain *domain) | |
2487 | { | |
2488 | if (!domain->updated) | |
2489 | return; | |
2490 | ||
2491 | update_device_table(domain); | |
17b124bf JR |
2492 | |
2493 | domain_flush_devices(domain); | |
2494 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2495 | |
2496 | domain->updated = false; | |
2497 | } | |
2498 | ||
8bda3092 JR |
2499 | /* |
2500 | * This function fetches the PTE for a given address in the aperture | |
2501 | */ | |
2502 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2503 | unsigned long address) | |
2504 | { | |
384de729 | 2505 | struct aperture_range *aperture; |
8bda3092 JR |
2506 | u64 *pte, *pte_page; |
2507 | ||
384de729 JR |
2508 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2509 | if (!aperture) | |
2510 | return NULL; | |
2511 | ||
2512 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2513 | if (!pte) { |
cbb9d729 | 2514 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2515 | GFP_ATOMIC); |
384de729 JR |
2516 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2517 | } else | |
8c8c143c | 2518 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2519 | |
04bfdd84 | 2520 | update_domain(&dom->domain); |
8bda3092 JR |
2521 | |
2522 | return pte; | |
2523 | } | |
2524 | ||
431b2a20 JR |
2525 | /* |
2526 | * This is the generic map function. It maps one 4kb page at paddr to | |
2527 | * the given address in the DMA address space for the domain. | |
2528 | */ | |
680525e0 | 2529 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2530 | unsigned long address, |
2531 | phys_addr_t paddr, | |
2532 | int direction) | |
2533 | { | |
2534 | u64 *pte, __pte; | |
2535 | ||
2536 | WARN_ON(address > dom->aperture_size); | |
2537 | ||
2538 | paddr &= PAGE_MASK; | |
2539 | ||
8bda3092 | 2540 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2541 | if (!pte) |
8fd524b3 | 2542 | return DMA_ERROR_CODE; |
cb76c322 JR |
2543 | |
2544 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2545 | ||
2546 | if (direction == DMA_TO_DEVICE) | |
2547 | __pte |= IOMMU_PTE_IR; | |
2548 | else if (direction == DMA_FROM_DEVICE) | |
2549 | __pte |= IOMMU_PTE_IW; | |
2550 | else if (direction == DMA_BIDIRECTIONAL) | |
2551 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2552 | ||
2553 | WARN_ON(*pte); | |
2554 | ||
2555 | *pte = __pte; | |
2556 | ||
2557 | return (dma_addr_t)address; | |
2558 | } | |
2559 | ||
431b2a20 JR |
2560 | /* |
2561 | * The generic unmapping function for on page in the DMA address space. | |
2562 | */ | |
680525e0 | 2563 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2564 | unsigned long address) |
2565 | { | |
384de729 | 2566 | struct aperture_range *aperture; |
cb76c322 JR |
2567 | u64 *pte; |
2568 | ||
2569 | if (address >= dom->aperture_size) | |
2570 | return; | |
2571 | ||
384de729 JR |
2572 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2573 | if (!aperture) | |
2574 | return; | |
2575 | ||
2576 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2577 | if (!pte) | |
2578 | return; | |
cb76c322 | 2579 | |
8c8c143c | 2580 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2581 | |
2582 | WARN_ON(!*pte); | |
2583 | ||
2584 | *pte = 0ULL; | |
2585 | } | |
2586 | ||
431b2a20 JR |
2587 | /* |
2588 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2589 | * contiguous memory region into DMA address space. It is used by all |
2590 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2591 | * Must be called with the domain lock held. |
2592 | */ | |
cb76c322 | 2593 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2594 | struct dma_ops_domain *dma_dom, |
2595 | phys_addr_t paddr, | |
2596 | size_t size, | |
6d4f343f | 2597 | int dir, |
832a90c3 JR |
2598 | bool align, |
2599 | u64 dma_mask) | |
cb76c322 JR |
2600 | { |
2601 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2602 | dma_addr_t address, start, ret; |
cb76c322 | 2603 | unsigned int pages; |
6d4f343f | 2604 | unsigned long align_mask = 0; |
cb76c322 JR |
2605 | int i; |
2606 | ||
e3c449f5 | 2607 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2608 | paddr &= PAGE_MASK; |
2609 | ||
8ecaf8f1 JR |
2610 | INC_STATS_COUNTER(total_map_requests); |
2611 | ||
c1858976 JR |
2612 | if (pages > 1) |
2613 | INC_STATS_COUNTER(cross_page); | |
2614 | ||
6d4f343f JR |
2615 | if (align) |
2616 | align_mask = (1UL << get_order(size)) - 1; | |
2617 | ||
11b83888 | 2618 | retry: |
832a90c3 JR |
2619 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2620 | dma_mask); | |
8fd524b3 | 2621 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2622 | /* |
2623 | * setting next_address here will let the address | |
2624 | * allocator only scan the new allocated range in the | |
2625 | * first run. This is a small optimization. | |
2626 | */ | |
2627 | dma_dom->next_address = dma_dom->aperture_size; | |
2628 | ||
576175c2 | 2629 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2630 | goto out; |
2631 | ||
2632 | /* | |
af901ca1 | 2633 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2634 | * allocation again |
2635 | */ | |
2636 | goto retry; | |
2637 | } | |
cb76c322 JR |
2638 | |
2639 | start = address; | |
2640 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2641 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2642 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2643 | goto out_unmap; |
2644 | ||
cb76c322 JR |
2645 | paddr += PAGE_SIZE; |
2646 | start += PAGE_SIZE; | |
2647 | } | |
2648 | address += offset; | |
2649 | ||
5774f7c5 JR |
2650 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2651 | ||
afa9fdc2 | 2652 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2653 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2654 | dma_dom->need_flush = false; |
318afd41 | 2655 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2656 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2657 | |
cb76c322 JR |
2658 | out: |
2659 | return address; | |
53812c11 JR |
2660 | |
2661 | out_unmap: | |
2662 | ||
2663 | for (--i; i >= 0; --i) { | |
2664 | start -= PAGE_SIZE; | |
680525e0 | 2665 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2666 | } |
2667 | ||
2668 | dma_ops_free_addresses(dma_dom, address, pages); | |
2669 | ||
8fd524b3 | 2670 | return DMA_ERROR_CODE; |
cb76c322 JR |
2671 | } |
2672 | ||
431b2a20 JR |
2673 | /* |
2674 | * Does the reverse of the __map_single function. Must be called with | |
2675 | * the domain lock held too | |
2676 | */ | |
cd8c82e8 | 2677 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2678 | dma_addr_t dma_addr, |
2679 | size_t size, | |
2680 | int dir) | |
2681 | { | |
04e0463e | 2682 | dma_addr_t flush_addr; |
cb76c322 JR |
2683 | dma_addr_t i, start; |
2684 | unsigned int pages; | |
2685 | ||
8fd524b3 | 2686 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2687 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2688 | return; |
2689 | ||
04e0463e | 2690 | flush_addr = dma_addr; |
e3c449f5 | 2691 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2692 | dma_addr &= PAGE_MASK; |
2693 | start = dma_addr; | |
2694 | ||
2695 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2696 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2697 | start += PAGE_SIZE; |
2698 | } | |
2699 | ||
5774f7c5 JR |
2700 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2701 | ||
cb76c322 | 2702 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2703 | |
80be308d | 2704 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2705 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2706 | dma_dom->need_flush = false; |
2707 | } | |
cb76c322 JR |
2708 | } |
2709 | ||
431b2a20 JR |
2710 | /* |
2711 | * The exported map_single function for dma_ops. | |
2712 | */ | |
51491367 FT |
2713 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2714 | unsigned long offset, size_t size, | |
2715 | enum dma_data_direction dir, | |
2716 | struct dma_attrs *attrs) | |
4da70b9e JR |
2717 | { |
2718 | unsigned long flags; | |
4da70b9e | 2719 | struct protection_domain *domain; |
4da70b9e | 2720 | dma_addr_t addr; |
832a90c3 | 2721 | u64 dma_mask; |
51491367 | 2722 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2723 | |
0f2a86f2 JR |
2724 | INC_STATS_COUNTER(cnt_map_single); |
2725 | ||
94f6d190 JR |
2726 | domain = get_domain(dev); |
2727 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2728 | return (dma_addr_t)paddr; |
94f6d190 JR |
2729 | else if (IS_ERR(domain)) |
2730 | return DMA_ERROR_CODE; | |
4da70b9e | 2731 | |
f99c0f1c JR |
2732 | dma_mask = *dev->dma_mask; |
2733 | ||
4da70b9e | 2734 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2735 | |
cd8c82e8 | 2736 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2737 | dma_mask); |
8fd524b3 | 2738 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2739 | goto out; |
2740 | ||
17b124bf | 2741 | domain_flush_complete(domain); |
4da70b9e JR |
2742 | |
2743 | out: | |
2744 | spin_unlock_irqrestore(&domain->lock, flags); | |
2745 | ||
2746 | return addr; | |
2747 | } | |
2748 | ||
431b2a20 JR |
2749 | /* |
2750 | * The exported unmap_single function for dma_ops. | |
2751 | */ | |
51491367 FT |
2752 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2753 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2754 | { |
2755 | unsigned long flags; | |
4da70b9e | 2756 | struct protection_domain *domain; |
4da70b9e | 2757 | |
146a6917 JR |
2758 | INC_STATS_COUNTER(cnt_unmap_single); |
2759 | ||
94f6d190 JR |
2760 | domain = get_domain(dev); |
2761 | if (IS_ERR(domain)) | |
5b28df6f JR |
2762 | return; |
2763 | ||
4da70b9e JR |
2764 | spin_lock_irqsave(&domain->lock, flags); |
2765 | ||
cd8c82e8 | 2766 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2767 | |
17b124bf | 2768 | domain_flush_complete(domain); |
4da70b9e JR |
2769 | |
2770 | spin_unlock_irqrestore(&domain->lock, flags); | |
2771 | } | |
2772 | ||
431b2a20 JR |
2773 | /* |
2774 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2775 | * lists). | |
2776 | */ | |
65b050ad | 2777 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2778 | int nelems, enum dma_data_direction dir, |
2779 | struct dma_attrs *attrs) | |
65b050ad JR |
2780 | { |
2781 | unsigned long flags; | |
65b050ad | 2782 | struct protection_domain *domain; |
65b050ad JR |
2783 | int i; |
2784 | struct scatterlist *s; | |
2785 | phys_addr_t paddr; | |
2786 | int mapped_elems = 0; | |
832a90c3 | 2787 | u64 dma_mask; |
65b050ad | 2788 | |
d03f067a JR |
2789 | INC_STATS_COUNTER(cnt_map_sg); |
2790 | ||
94f6d190 | 2791 | domain = get_domain(dev); |
a0e191b2 | 2792 | if (IS_ERR(domain)) |
94f6d190 | 2793 | return 0; |
dbcc112e | 2794 | |
832a90c3 | 2795 | dma_mask = *dev->dma_mask; |
65b050ad | 2796 | |
65b050ad JR |
2797 | spin_lock_irqsave(&domain->lock, flags); |
2798 | ||
2799 | for_each_sg(sglist, s, nelems, i) { | |
2800 | paddr = sg_phys(s); | |
2801 | ||
cd8c82e8 | 2802 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2803 | paddr, s->length, dir, false, |
2804 | dma_mask); | |
65b050ad JR |
2805 | |
2806 | if (s->dma_address) { | |
2807 | s->dma_length = s->length; | |
2808 | mapped_elems++; | |
2809 | } else | |
2810 | goto unmap; | |
65b050ad JR |
2811 | } |
2812 | ||
17b124bf | 2813 | domain_flush_complete(domain); |
65b050ad JR |
2814 | |
2815 | out: | |
2816 | spin_unlock_irqrestore(&domain->lock, flags); | |
2817 | ||
2818 | return mapped_elems; | |
2819 | unmap: | |
2820 | for_each_sg(sglist, s, mapped_elems, i) { | |
2821 | if (s->dma_address) | |
cd8c82e8 | 2822 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2823 | s->dma_length, dir); |
2824 | s->dma_address = s->dma_length = 0; | |
2825 | } | |
2826 | ||
2827 | mapped_elems = 0; | |
2828 | ||
2829 | goto out; | |
2830 | } | |
2831 | ||
431b2a20 JR |
2832 | /* |
2833 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2834 | * lists). | |
2835 | */ | |
65b050ad | 2836 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2837 | int nelems, enum dma_data_direction dir, |
2838 | struct dma_attrs *attrs) | |
65b050ad JR |
2839 | { |
2840 | unsigned long flags; | |
65b050ad JR |
2841 | struct protection_domain *domain; |
2842 | struct scatterlist *s; | |
65b050ad JR |
2843 | int i; |
2844 | ||
55877a6b JR |
2845 | INC_STATS_COUNTER(cnt_unmap_sg); |
2846 | ||
94f6d190 JR |
2847 | domain = get_domain(dev); |
2848 | if (IS_ERR(domain)) | |
5b28df6f JR |
2849 | return; |
2850 | ||
65b050ad JR |
2851 | spin_lock_irqsave(&domain->lock, flags); |
2852 | ||
2853 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2854 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2855 | s->dma_length, dir); |
65b050ad JR |
2856 | s->dma_address = s->dma_length = 0; |
2857 | } | |
2858 | ||
17b124bf | 2859 | domain_flush_complete(domain); |
65b050ad JR |
2860 | |
2861 | spin_unlock_irqrestore(&domain->lock, flags); | |
2862 | } | |
2863 | ||
431b2a20 JR |
2864 | /* |
2865 | * The exported alloc_coherent function for dma_ops. | |
2866 | */ | |
5d8b53cf | 2867 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2868 | dma_addr_t *dma_addr, gfp_t flag, |
2869 | struct dma_attrs *attrs) | |
5d8b53cf | 2870 | { |
832a90c3 | 2871 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 JR |
2872 | struct protection_domain *domain; |
2873 | unsigned long flags; | |
2874 | struct page *page; | |
5d8b53cf | 2875 | |
c8f0fb36 JR |
2876 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2877 | ||
94f6d190 JR |
2878 | domain = get_domain(dev); |
2879 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2880 | page = alloc_pages(flag, get_order(size)); |
2881 | *dma_addr = page_to_phys(page); | |
2882 | return page_address(page); | |
94f6d190 JR |
2883 | } else if (IS_ERR(domain)) |
2884 | return NULL; | |
5d8b53cf | 2885 | |
3b839a57 | 2886 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2887 | dma_mask = dev->coherent_dma_mask; |
2888 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 2889 | |
3b839a57 JR |
2890 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2891 | if (!page) { | |
2892 | if (!(flag & __GFP_WAIT)) | |
2893 | return NULL; | |
5d8b53cf | 2894 | |
3b839a57 JR |
2895 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2896 | get_order(size)); | |
2897 | if (!page) | |
2898 | return NULL; | |
2899 | } | |
5d8b53cf | 2900 | |
832a90c3 JR |
2901 | if (!dma_mask) |
2902 | dma_mask = *dev->dma_mask; | |
2903 | ||
5d8b53cf JR |
2904 | spin_lock_irqsave(&domain->lock, flags); |
2905 | ||
3b839a57 | 2906 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2907 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2908 | |
8fd524b3 | 2909 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2910 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2911 | goto out_free; |
367d04c4 | 2912 | } |
5d8b53cf | 2913 | |
17b124bf | 2914 | domain_flush_complete(domain); |
5d8b53cf | 2915 | |
5d8b53cf JR |
2916 | spin_unlock_irqrestore(&domain->lock, flags); |
2917 | ||
3b839a57 | 2918 | return page_address(page); |
5b28df6f JR |
2919 | |
2920 | out_free: | |
2921 | ||
3b839a57 JR |
2922 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2923 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2924 | |
2925 | return NULL; | |
5d8b53cf JR |
2926 | } |
2927 | ||
431b2a20 JR |
2928 | /* |
2929 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2930 | */ |
5d8b53cf | 2931 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2932 | void *virt_addr, dma_addr_t dma_addr, |
2933 | struct dma_attrs *attrs) | |
5d8b53cf | 2934 | { |
5d8b53cf | 2935 | struct protection_domain *domain; |
3b839a57 JR |
2936 | unsigned long flags; |
2937 | struct page *page; | |
5d8b53cf | 2938 | |
5d31ee7e JR |
2939 | INC_STATS_COUNTER(cnt_free_coherent); |
2940 | ||
3b839a57 JR |
2941 | page = virt_to_page(virt_addr); |
2942 | size = PAGE_ALIGN(size); | |
2943 | ||
94f6d190 JR |
2944 | domain = get_domain(dev); |
2945 | if (IS_ERR(domain)) | |
5b28df6f JR |
2946 | goto free_mem; |
2947 | ||
5d8b53cf JR |
2948 | spin_lock_irqsave(&domain->lock, flags); |
2949 | ||
cd8c82e8 | 2950 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2951 | |
17b124bf | 2952 | domain_flush_complete(domain); |
5d8b53cf JR |
2953 | |
2954 | spin_unlock_irqrestore(&domain->lock, flags); | |
2955 | ||
2956 | free_mem: | |
3b839a57 JR |
2957 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2958 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2959 | } |
2960 | ||
b39ba6ad JR |
2961 | /* |
2962 | * This function is called by the DMA layer to find out if we can handle a | |
2963 | * particular device. It is part of the dma_ops. | |
2964 | */ | |
2965 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2966 | { | |
420aef8a | 2967 | return check_device(dev); |
b39ba6ad JR |
2968 | } |
2969 | ||
160c1d8e | 2970 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
2971 | .alloc = alloc_coherent, |
2972 | .free = free_coherent, | |
51491367 FT |
2973 | .map_page = map_page, |
2974 | .unmap_page = unmap_page, | |
6631ee9d JR |
2975 | .map_sg = map_sg, |
2976 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2977 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2978 | }; |
2979 | ||
27c2127a JR |
2980 | static unsigned device_dma_ops_init(void) |
2981 | { | |
5abcdba4 | 2982 | struct iommu_dev_data *dev_data; |
27c2127a JR |
2983 | struct pci_dev *pdev = NULL; |
2984 | unsigned unhandled = 0; | |
2985 | ||
2986 | for_each_pci_dev(pdev) { | |
2987 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
2988 | |
2989 | iommu_ignore_device(&pdev->dev); | |
2990 | ||
27c2127a JR |
2991 | unhandled += 1; |
2992 | continue; | |
2993 | } | |
2994 | ||
5abcdba4 JR |
2995 | dev_data = get_dev_data(&pdev->dev); |
2996 | ||
2997 | if (!dev_data->passthrough) | |
2998 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2999 | else | |
3000 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3001 | } |
3002 | ||
3003 | return unhandled; | |
3004 | } | |
3005 | ||
431b2a20 JR |
3006 | /* |
3007 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3008 | */ | |
f5325094 JR |
3009 | |
3010 | void __init amd_iommu_init_api(void) | |
3011 | { | |
2cc21c42 | 3012 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3013 | } |
3014 | ||
6631ee9d JR |
3015 | int __init amd_iommu_init_dma_ops(void) |
3016 | { | |
3017 | struct amd_iommu *iommu; | |
27c2127a | 3018 | int ret, unhandled; |
6631ee9d | 3019 | |
431b2a20 JR |
3020 | /* |
3021 | * first allocate a default protection domain for every IOMMU we | |
3022 | * found in the system. Devices not assigned to any other | |
3023 | * protection domain will be assigned to the default one. | |
3024 | */ | |
3bd22172 | 3025 | for_each_iommu(iommu) { |
87a64d52 | 3026 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3027 | if (iommu->default_dom == NULL) |
3028 | return -ENOMEM; | |
e2dc14a2 | 3029 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3030 | ret = iommu_init_unity_mappings(iommu); |
3031 | if (ret) | |
3032 | goto free_domains; | |
3033 | } | |
3034 | ||
6631ee9d | 3035 | iommu_detected = 1; |
75f1cdf1 | 3036 | swiotlb = 0; |
6631ee9d | 3037 | |
431b2a20 | 3038 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3039 | unhandled = device_dma_ops_init(); |
3040 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3041 | /* There are unhandled devices - initialize swiotlb for them */ | |
3042 | swiotlb = 1; | |
3043 | } | |
6631ee9d | 3044 | |
7f26508b JR |
3045 | amd_iommu_stats_init(); |
3046 | ||
62410eeb JR |
3047 | if (amd_iommu_unmap_flush) |
3048 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3049 | else | |
3050 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3051 | ||
6631ee9d JR |
3052 | return 0; |
3053 | ||
3054 | free_domains: | |
3055 | ||
3bd22172 | 3056 | for_each_iommu(iommu) { |
91457df7 | 3057 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3058 | } |
3059 | ||
3060 | return ret; | |
3061 | } | |
6d98cd80 JR |
3062 | |
3063 | /***************************************************************************** | |
3064 | * | |
3065 | * The following functions belong to the exported interface of AMD IOMMU | |
3066 | * | |
3067 | * This interface allows access to lower level functions of the IOMMU | |
3068 | * like protection domain handling and assignement of devices to domains | |
3069 | * which is not possible with the dma_ops interface. | |
3070 | * | |
3071 | *****************************************************************************/ | |
3072 | ||
6d98cd80 JR |
3073 | static void cleanup_domain(struct protection_domain *domain) |
3074 | { | |
9b29d3c6 | 3075 | struct iommu_dev_data *entry; |
6d98cd80 | 3076 | unsigned long flags; |
6d98cd80 JR |
3077 | |
3078 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3079 | ||
9b29d3c6 JR |
3080 | while (!list_empty(&domain->dev_list)) { |
3081 | entry = list_first_entry(&domain->dev_list, | |
3082 | struct iommu_dev_data, list); | |
3083 | __detach_device(entry); | |
492667da | 3084 | } |
6d98cd80 JR |
3085 | |
3086 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3087 | } | |
3088 | ||
2650815f JR |
3089 | static void protection_domain_free(struct protection_domain *domain) |
3090 | { | |
3091 | if (!domain) | |
3092 | return; | |
3093 | ||
aeb26f55 JR |
3094 | del_domain_from_list(domain); |
3095 | ||
2650815f JR |
3096 | if (domain->id) |
3097 | domain_id_free(domain->id); | |
3098 | ||
3099 | kfree(domain); | |
3100 | } | |
3101 | ||
3102 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3103 | { |
3104 | struct protection_domain *domain; | |
3105 | ||
3106 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3107 | if (!domain) | |
2650815f | 3108 | return NULL; |
c156e347 JR |
3109 | |
3110 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3111 | mutex_init(&domain->api_lock); |
c156e347 JR |
3112 | domain->id = domain_id_alloc(); |
3113 | if (!domain->id) | |
2650815f | 3114 | goto out_err; |
7c392cbe | 3115 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3116 | |
aeb26f55 JR |
3117 | add_domain_to_list(domain); |
3118 | ||
2650815f JR |
3119 | return domain; |
3120 | ||
3121 | out_err: | |
3122 | kfree(domain); | |
3123 | ||
3124 | return NULL; | |
3125 | } | |
3126 | ||
aafd8ba0 | 3127 | static int alloc_passthrough_domain(void) |
5abcdba4 JR |
3128 | { |
3129 | if (pt_domain != NULL) | |
3130 | return 0; | |
3131 | ||
3132 | /* allocate passthrough domain */ | |
3133 | pt_domain = protection_domain_alloc(); | |
3134 | if (!pt_domain) | |
3135 | return -ENOMEM; | |
3136 | ||
3137 | pt_domain->mode = PAGE_MODE_NONE; | |
3138 | ||
3139 | return 0; | |
3140 | } | |
3f4b87b9 JR |
3141 | |
3142 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) | |
2650815f | 3143 | { |
3f4b87b9 | 3144 | struct protection_domain *pdomain; |
2650815f | 3145 | |
3f4b87b9 JR |
3146 | /* We only support unmanaged domains for now */ |
3147 | if (type != IOMMU_DOMAIN_UNMANAGED) | |
3148 | return NULL; | |
2650815f | 3149 | |
3f4b87b9 JR |
3150 | pdomain = protection_domain_alloc(); |
3151 | if (!pdomain) | |
c156e347 JR |
3152 | goto out_free; |
3153 | ||
3f4b87b9 JR |
3154 | pdomain->mode = PAGE_MODE_3_LEVEL; |
3155 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3156 | if (!pdomain->pt_root) | |
3157 | goto out_free; | |
c156e347 | 3158 | |
3f4b87b9 JR |
3159 | pdomain->domain.geometry.aperture_start = 0; |
3160 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3161 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 3162 | |
3f4b87b9 | 3163 | return &pdomain->domain; |
c156e347 JR |
3164 | |
3165 | out_free: | |
3f4b87b9 | 3166 | protection_domain_free(pdomain); |
c156e347 | 3167 | |
3f4b87b9 | 3168 | return NULL; |
c156e347 JR |
3169 | } |
3170 | ||
3f4b87b9 | 3171 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3172 | { |
3f4b87b9 | 3173 | struct protection_domain *domain; |
98383fc3 | 3174 | |
3f4b87b9 | 3175 | if (!dom) |
98383fc3 JR |
3176 | return; |
3177 | ||
3f4b87b9 JR |
3178 | domain = to_pdomain(dom); |
3179 | ||
98383fc3 JR |
3180 | if (domain->dev_cnt > 0) |
3181 | cleanup_domain(domain); | |
3182 | ||
3183 | BUG_ON(domain->dev_cnt != 0); | |
3184 | ||
132bd68f JR |
3185 | if (domain->mode != PAGE_MODE_NONE) |
3186 | free_pagetable(domain); | |
98383fc3 | 3187 | |
52815b75 JR |
3188 | if (domain->flags & PD_IOMMUV2_MASK) |
3189 | free_gcr3_table(domain); | |
3190 | ||
8b408fe4 | 3191 | protection_domain_free(domain); |
98383fc3 JR |
3192 | } |
3193 | ||
684f2888 JR |
3194 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3195 | struct device *dev) | |
3196 | { | |
657cbb6b | 3197 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3198 | struct amd_iommu *iommu; |
684f2888 JR |
3199 | u16 devid; |
3200 | ||
98fc5a69 | 3201 | if (!check_device(dev)) |
684f2888 JR |
3202 | return; |
3203 | ||
98fc5a69 | 3204 | devid = get_device_id(dev); |
684f2888 | 3205 | |
657cbb6b | 3206 | if (dev_data->domain != NULL) |
15898bbc | 3207 | detach_device(dev); |
684f2888 JR |
3208 | |
3209 | iommu = amd_iommu_rlookup_table[devid]; | |
3210 | if (!iommu) | |
3211 | return; | |
3212 | ||
684f2888 JR |
3213 | iommu_completion_wait(iommu); |
3214 | } | |
3215 | ||
01106066 JR |
3216 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3217 | struct device *dev) | |
3218 | { | |
3f4b87b9 | 3219 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3220 | struct iommu_dev_data *dev_data; |
01106066 | 3221 | struct amd_iommu *iommu; |
15898bbc | 3222 | int ret; |
01106066 | 3223 | |
98fc5a69 | 3224 | if (!check_device(dev)) |
01106066 JR |
3225 | return -EINVAL; |
3226 | ||
657cbb6b JR |
3227 | dev_data = dev->archdata.iommu; |
3228 | ||
f62dda66 | 3229 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3230 | if (!iommu) |
3231 | return -EINVAL; | |
3232 | ||
657cbb6b | 3233 | if (dev_data->domain) |
15898bbc | 3234 | detach_device(dev); |
01106066 | 3235 | |
15898bbc | 3236 | ret = attach_device(dev, domain); |
01106066 JR |
3237 | |
3238 | iommu_completion_wait(iommu); | |
3239 | ||
15898bbc | 3240 | return ret; |
01106066 JR |
3241 | } |
3242 | ||
468e2366 | 3243 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3244 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3245 | { |
3f4b87b9 | 3246 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3247 | int prot = 0; |
3248 | int ret; | |
3249 | ||
132bd68f JR |
3250 | if (domain->mode == PAGE_MODE_NONE) |
3251 | return -EINVAL; | |
3252 | ||
c6229ca6 JR |
3253 | if (iommu_prot & IOMMU_READ) |
3254 | prot |= IOMMU_PROT_IR; | |
3255 | if (iommu_prot & IOMMU_WRITE) | |
3256 | prot |= IOMMU_PROT_IW; | |
3257 | ||
5d214fe6 | 3258 | mutex_lock(&domain->api_lock); |
795e74f7 | 3259 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3260 | mutex_unlock(&domain->api_lock); |
3261 | ||
795e74f7 | 3262 | return ret; |
c6229ca6 JR |
3263 | } |
3264 | ||
5009065d OBC |
3265 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3266 | size_t page_size) | |
eb74ff6c | 3267 | { |
3f4b87b9 | 3268 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3269 | size_t unmap_size; |
eb74ff6c | 3270 | |
132bd68f JR |
3271 | if (domain->mode == PAGE_MODE_NONE) |
3272 | return -EINVAL; | |
3273 | ||
5d214fe6 | 3274 | mutex_lock(&domain->api_lock); |
468e2366 | 3275 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3276 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3277 | |
17b124bf | 3278 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3279 | |
5009065d | 3280 | return unmap_size; |
eb74ff6c JR |
3281 | } |
3282 | ||
645c4c8d | 3283 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3284 | dma_addr_t iova) |
645c4c8d | 3285 | { |
3f4b87b9 | 3286 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3287 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3288 | u64 *pte, __pte; |
645c4c8d | 3289 | |
132bd68f JR |
3290 | if (domain->mode == PAGE_MODE_NONE) |
3291 | return iova; | |
3292 | ||
3039ca1b | 3293 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3294 | |
a6d41a40 | 3295 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3296 | return 0; |
3297 | ||
b24b1b63 JR |
3298 | offset_mask = pte_pgsize - 1; |
3299 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3300 | |
b24b1b63 | 3301 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3302 | } |
3303 | ||
ab636481 | 3304 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3305 | { |
80a506b8 JR |
3306 | switch (cap) { |
3307 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3308 | return true; |
bdddadcb | 3309 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3310 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3311 | case IOMMU_CAP_NOEXEC: |
3312 | return false; | |
80a506b8 JR |
3313 | } |
3314 | ||
ab636481 | 3315 | return false; |
dbb9fd86 SY |
3316 | } |
3317 | ||
35cf248f JR |
3318 | static void amd_iommu_get_dm_regions(struct device *dev, |
3319 | struct list_head *head) | |
3320 | { | |
3321 | struct unity_map_entry *entry; | |
3322 | u16 devid; | |
3323 | ||
3324 | devid = get_device_id(dev); | |
3325 | ||
3326 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3327 | struct iommu_dm_region *region; | |
3328 | ||
3329 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3330 | continue; | |
3331 | ||
3332 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3333 | if (!region) { | |
3334 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3335 | dev_name(dev)); | |
3336 | return; | |
3337 | } | |
3338 | ||
3339 | region->start = entry->address_start; | |
3340 | region->length = entry->address_end - entry->address_start; | |
3341 | if (entry->prot & IOMMU_PROT_IR) | |
3342 | region->prot |= IOMMU_READ; | |
3343 | if (entry->prot & IOMMU_PROT_IW) | |
3344 | region->prot |= IOMMU_WRITE; | |
3345 | ||
3346 | list_add_tail(®ion->list, head); | |
3347 | } | |
3348 | } | |
3349 | ||
3350 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3351 | struct list_head *head) | |
3352 | { | |
3353 | struct iommu_dm_region *entry, *next; | |
3354 | ||
3355 | list_for_each_entry_safe(entry, next, head, list) | |
3356 | kfree(entry); | |
3357 | } | |
3358 | ||
b22f6434 | 3359 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3360 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3361 | .domain_alloc = amd_iommu_domain_alloc, |
3362 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3363 | .attach_dev = amd_iommu_attach_device, |
3364 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3365 | .map = amd_iommu_map, |
3366 | .unmap = amd_iommu_unmap, | |
315786eb | 3367 | .map_sg = default_iommu_map_sg, |
26961efe | 3368 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3369 | .add_device = amd_iommu_add_device, |
3370 | .remove_device = amd_iommu_remove_device, | |
35cf248f JR |
3371 | .get_dm_regions = amd_iommu_get_dm_regions, |
3372 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3373 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3374 | }; |
3375 | ||
0feae533 JR |
3376 | /***************************************************************************** |
3377 | * | |
3378 | * The next functions do a basic initialization of IOMMU for pass through | |
3379 | * mode | |
3380 | * | |
3381 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3382 | * DMA-API translation. | |
3383 | * | |
3384 | *****************************************************************************/ | |
3385 | ||
3386 | int __init amd_iommu_init_passthrough(void) | |
3387 | { | |
5abcdba4 | 3388 | struct iommu_dev_data *dev_data; |
0feae533 | 3389 | struct pci_dev *dev = NULL; |
5abcdba4 | 3390 | int ret; |
0feae533 | 3391 | |
5abcdba4 JR |
3392 | ret = alloc_passthrough_domain(); |
3393 | if (ret) | |
3394 | return ret; | |
0feae533 | 3395 | |
6c54aabd | 3396 | for_each_pci_dev(dev) { |
98fc5a69 | 3397 | if (!check_device(&dev->dev)) |
0feae533 JR |
3398 | continue; |
3399 | ||
5abcdba4 JR |
3400 | dev_data = get_dev_data(&dev->dev); |
3401 | dev_data->passthrough = true; | |
3402 | ||
15898bbc | 3403 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3404 | } |
3405 | ||
2655d7a2 JR |
3406 | amd_iommu_stats_init(); |
3407 | ||
0feae533 JR |
3408 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3409 | ||
3410 | return 0; | |
3411 | } | |
72e1dcc4 JR |
3412 | |
3413 | /* IOMMUv2 specific functions */ | |
3414 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3415 | { | |
3416 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3417 | } | |
3418 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3419 | ||
3420 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3421 | { | |
3422 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3423 | } | |
3424 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3425 | |
3426 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3427 | { | |
3f4b87b9 | 3428 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3429 | unsigned long flags; |
3430 | ||
3431 | spin_lock_irqsave(&domain->lock, flags); | |
3432 | ||
3433 | /* Update data structure */ | |
3434 | domain->mode = PAGE_MODE_NONE; | |
3435 | domain->updated = true; | |
3436 | ||
3437 | /* Make changes visible to IOMMUs */ | |
3438 | update_domain(domain); | |
3439 | ||
3440 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3441 | free_pagetable(domain); | |
3442 | ||
3443 | spin_unlock_irqrestore(&domain->lock, flags); | |
3444 | } | |
3445 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3446 | |
3447 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3448 | { | |
3f4b87b9 | 3449 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3450 | unsigned long flags; |
3451 | int levels, ret; | |
3452 | ||
3453 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3454 | return -EINVAL; | |
3455 | ||
3456 | /* Number of GCR3 table levels required */ | |
3457 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3458 | levels += 1; | |
3459 | ||
3460 | if (levels > amd_iommu_max_glx_val) | |
3461 | return -EINVAL; | |
3462 | ||
3463 | spin_lock_irqsave(&domain->lock, flags); | |
3464 | ||
3465 | /* | |
3466 | * Save us all sanity checks whether devices already in the | |
3467 | * domain support IOMMUv2. Just force that the domain has no | |
3468 | * devices attached when it is switched into IOMMUv2 mode. | |
3469 | */ | |
3470 | ret = -EBUSY; | |
3471 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3472 | goto out; | |
3473 | ||
3474 | ret = -ENOMEM; | |
3475 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3476 | if (domain->gcr3_tbl == NULL) | |
3477 | goto out; | |
3478 | ||
3479 | domain->glx = levels; | |
3480 | domain->flags |= PD_IOMMUV2_MASK; | |
3481 | domain->updated = true; | |
3482 | ||
3483 | update_domain(domain); | |
3484 | ||
3485 | ret = 0; | |
3486 | ||
3487 | out: | |
3488 | spin_unlock_irqrestore(&domain->lock, flags); | |
3489 | ||
3490 | return ret; | |
3491 | } | |
3492 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3493 | |
3494 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3495 | u64 address, bool size) | |
3496 | { | |
3497 | struct iommu_dev_data *dev_data; | |
3498 | struct iommu_cmd cmd; | |
3499 | int i, ret; | |
3500 | ||
3501 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3502 | return -EINVAL; | |
3503 | ||
3504 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3505 | ||
3506 | /* | |
3507 | * IOMMU TLB needs to be flushed before Device TLB to | |
3508 | * prevent device TLB refill from IOMMU TLB | |
3509 | */ | |
3510 | for (i = 0; i < amd_iommus_present; ++i) { | |
3511 | if (domain->dev_iommu[i] == 0) | |
3512 | continue; | |
3513 | ||
3514 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3515 | if (ret != 0) | |
3516 | goto out; | |
3517 | } | |
3518 | ||
3519 | /* Wait until IOMMU TLB flushes are complete */ | |
3520 | domain_flush_complete(domain); | |
3521 | ||
3522 | /* Now flush device TLBs */ | |
3523 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3524 | struct amd_iommu *iommu; | |
3525 | int qdep; | |
3526 | ||
3527 | BUG_ON(!dev_data->ats.enabled); | |
3528 | ||
3529 | qdep = dev_data->ats.qdep; | |
3530 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3531 | ||
3532 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3533 | qdep, address, size); | |
3534 | ||
3535 | ret = iommu_queue_command(iommu, &cmd); | |
3536 | if (ret != 0) | |
3537 | goto out; | |
3538 | } | |
3539 | ||
3540 | /* Wait until all device TLBs are flushed */ | |
3541 | domain_flush_complete(domain); | |
3542 | ||
3543 | ret = 0; | |
3544 | ||
3545 | out: | |
3546 | ||
3547 | return ret; | |
3548 | } | |
3549 | ||
3550 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3551 | u64 address) | |
3552 | { | |
399be2f5 JR |
3553 | INC_STATS_COUNTER(invalidate_iotlb); |
3554 | ||
22e266c7 JR |
3555 | return __flush_pasid(domain, pasid, address, false); |
3556 | } | |
3557 | ||
3558 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3559 | u64 address) | |
3560 | { | |
3f4b87b9 | 3561 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3562 | unsigned long flags; |
3563 | int ret; | |
3564 | ||
3565 | spin_lock_irqsave(&domain->lock, flags); | |
3566 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3567 | spin_unlock_irqrestore(&domain->lock, flags); | |
3568 | ||
3569 | return ret; | |
3570 | } | |
3571 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3572 | ||
3573 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3574 | { | |
399be2f5 JR |
3575 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3576 | ||
22e266c7 JR |
3577 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3578 | true); | |
3579 | } | |
3580 | ||
3581 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3582 | { | |
3f4b87b9 | 3583 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3584 | unsigned long flags; |
3585 | int ret; | |
3586 | ||
3587 | spin_lock_irqsave(&domain->lock, flags); | |
3588 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3589 | spin_unlock_irqrestore(&domain->lock, flags); | |
3590 | ||
3591 | return ret; | |
3592 | } | |
3593 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3594 | ||
b16137b1 JR |
3595 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3596 | { | |
3597 | int index; | |
3598 | u64 *pte; | |
3599 | ||
3600 | while (true) { | |
3601 | ||
3602 | index = (pasid >> (9 * level)) & 0x1ff; | |
3603 | pte = &root[index]; | |
3604 | ||
3605 | if (level == 0) | |
3606 | break; | |
3607 | ||
3608 | if (!(*pte & GCR3_VALID)) { | |
3609 | if (!alloc) | |
3610 | return NULL; | |
3611 | ||
3612 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3613 | if (root == NULL) | |
3614 | return NULL; | |
3615 | ||
3616 | *pte = __pa(root) | GCR3_VALID; | |
3617 | } | |
3618 | ||
3619 | root = __va(*pte & PAGE_MASK); | |
3620 | ||
3621 | level -= 1; | |
3622 | } | |
3623 | ||
3624 | return pte; | |
3625 | } | |
3626 | ||
3627 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3628 | unsigned long cr3) | |
3629 | { | |
3630 | u64 *pte; | |
3631 | ||
3632 | if (domain->mode != PAGE_MODE_NONE) | |
3633 | return -EINVAL; | |
3634 | ||
3635 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3636 | if (pte == NULL) | |
3637 | return -ENOMEM; | |
3638 | ||
3639 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3640 | ||
3641 | return __amd_iommu_flush_tlb(domain, pasid); | |
3642 | } | |
3643 | ||
3644 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3645 | { | |
3646 | u64 *pte; | |
3647 | ||
3648 | if (domain->mode != PAGE_MODE_NONE) | |
3649 | return -EINVAL; | |
3650 | ||
3651 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3652 | if (pte == NULL) | |
3653 | return 0; | |
3654 | ||
3655 | *pte = 0; | |
3656 | ||
3657 | return __amd_iommu_flush_tlb(domain, pasid); | |
3658 | } | |
3659 | ||
3660 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3661 | unsigned long cr3) | |
3662 | { | |
3f4b87b9 | 3663 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3664 | unsigned long flags; |
3665 | int ret; | |
3666 | ||
3667 | spin_lock_irqsave(&domain->lock, flags); | |
3668 | ret = __set_gcr3(domain, pasid, cr3); | |
3669 | spin_unlock_irqrestore(&domain->lock, flags); | |
3670 | ||
3671 | return ret; | |
3672 | } | |
3673 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3674 | ||
3675 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3676 | { | |
3f4b87b9 | 3677 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3678 | unsigned long flags; |
3679 | int ret; | |
3680 | ||
3681 | spin_lock_irqsave(&domain->lock, flags); | |
3682 | ret = __clear_gcr3(domain, pasid); | |
3683 | spin_unlock_irqrestore(&domain->lock, flags); | |
3684 | ||
3685 | return ret; | |
3686 | } | |
3687 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3688 | |
3689 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3690 | int status, int tag) | |
3691 | { | |
3692 | struct iommu_dev_data *dev_data; | |
3693 | struct amd_iommu *iommu; | |
3694 | struct iommu_cmd cmd; | |
3695 | ||
399be2f5 JR |
3696 | INC_STATS_COUNTER(complete_ppr); |
3697 | ||
c99afa25 JR |
3698 | dev_data = get_dev_data(&pdev->dev); |
3699 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3700 | ||
3701 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3702 | tag, dev_data->pri_tlp); | |
3703 | ||
3704 | return iommu_queue_command(iommu, &cmd); | |
3705 | } | |
3706 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3707 | |
3708 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3709 | { | |
3f4b87b9 | 3710 | struct protection_domain *pdomain; |
f3572db8 | 3711 | |
3f4b87b9 JR |
3712 | pdomain = get_domain(&pdev->dev); |
3713 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3714 | return NULL; |
3715 | ||
3716 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3717 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3718 | return NULL; |
3719 | ||
3f4b87b9 | 3720 | return &pdomain->domain; |
f3572db8 JR |
3721 | } |
3722 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3723 | |
3724 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3725 | { | |
3726 | struct iommu_dev_data *dev_data; | |
3727 | ||
3728 | if (!amd_iommu_v2_supported()) | |
3729 | return; | |
3730 | ||
3731 | dev_data = get_dev_data(&pdev->dev); | |
3732 | dev_data->errata |= (1 << erratum); | |
3733 | } | |
3734 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3735 | |
3736 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3737 | struct amd_iommu_device_info *info) | |
3738 | { | |
3739 | int max_pasids; | |
3740 | int pos; | |
3741 | ||
3742 | if (pdev == NULL || info == NULL) | |
3743 | return -EINVAL; | |
3744 | ||
3745 | if (!amd_iommu_v2_supported()) | |
3746 | return -EINVAL; | |
3747 | ||
3748 | memset(info, 0, sizeof(*info)); | |
3749 | ||
3750 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3751 | if (pos) | |
3752 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3753 | ||
3754 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3755 | if (pos) | |
3756 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3757 | ||
3758 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3759 | if (pos) { | |
3760 | int features; | |
3761 | ||
3762 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3763 | max_pasids = min(max_pasids, (1 << 20)); | |
3764 | ||
3765 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3766 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3767 | ||
3768 | features = pci_pasid_features(pdev); | |
3769 | if (features & PCI_PASID_CAP_EXEC) | |
3770 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3771 | if (features & PCI_PASID_CAP_PRIV) | |
3772 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3773 | } | |
3774 | ||
3775 | return 0; | |
3776 | } | |
3777 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3778 | |
3779 | #ifdef CONFIG_IRQ_REMAP | |
3780 | ||
3781 | /***************************************************************************** | |
3782 | * | |
3783 | * Interrupt Remapping Implementation | |
3784 | * | |
3785 | *****************************************************************************/ | |
3786 | ||
3787 | union irte { | |
3788 | u32 val; | |
3789 | struct { | |
3790 | u32 valid : 1, | |
3791 | no_fault : 1, | |
3792 | int_type : 3, | |
3793 | rq_eoi : 1, | |
3794 | dm : 1, | |
3795 | rsvd_1 : 1, | |
3796 | destination : 8, | |
3797 | vector : 8, | |
3798 | rsvd_2 : 8; | |
3799 | } fields; | |
3800 | }; | |
3801 | ||
3802 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3803 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3804 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3805 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3806 | ||
3807 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3808 | { | |
3809 | u64 dte; | |
3810 | ||
3811 | dte = amd_iommu_dev_table[devid].data[2]; | |
3812 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3813 | dte |= virt_to_phys(table->table); | |
3814 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3815 | dte |= DTE_IRQ_TABLE_LEN; | |
3816 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3817 | ||
3818 | amd_iommu_dev_table[devid].data[2] = dte; | |
3819 | } | |
3820 | ||
3821 | #define IRTE_ALLOCATED (~1U) | |
3822 | ||
3823 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3824 | { | |
3825 | struct irq_remap_table *table = NULL; | |
3826 | struct amd_iommu *iommu; | |
3827 | unsigned long flags; | |
3828 | u16 alias; | |
3829 | ||
3830 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3831 | ||
3832 | iommu = amd_iommu_rlookup_table[devid]; | |
3833 | if (!iommu) | |
3834 | goto out_unlock; | |
3835 | ||
3836 | table = irq_lookup_table[devid]; | |
3837 | if (table) | |
3838 | goto out; | |
3839 | ||
3840 | alias = amd_iommu_alias_table[devid]; | |
3841 | table = irq_lookup_table[alias]; | |
3842 | if (table) { | |
3843 | irq_lookup_table[devid] = table; | |
3844 | set_dte_irq_entry(devid, table); | |
3845 | iommu_flush_dte(iommu, devid); | |
3846 | goto out; | |
3847 | } | |
3848 | ||
3849 | /* Nothing there yet, allocate new irq remapping table */ | |
3850 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3851 | if (!table) | |
3852 | goto out; | |
3853 | ||
197887f0 JR |
3854 | /* Initialize table spin-lock */ |
3855 | spin_lock_init(&table->lock); | |
3856 | ||
2b324506 JR |
3857 | if (ioapic) |
3858 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3859 | table->min_index = 32; | |
3860 | ||
3861 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3862 | if (!table->table) { | |
3863 | kfree(table); | |
821f0f68 | 3864 | table = NULL; |
2b324506 JR |
3865 | goto out; |
3866 | } | |
3867 | ||
3868 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3869 | ||
3870 | if (ioapic) { | |
3871 | int i; | |
3872 | ||
3873 | for (i = 0; i < 32; ++i) | |
3874 | table->table[i] = IRTE_ALLOCATED; | |
3875 | } | |
3876 | ||
3877 | irq_lookup_table[devid] = table; | |
3878 | set_dte_irq_entry(devid, table); | |
3879 | iommu_flush_dte(iommu, devid); | |
3880 | if (devid != alias) { | |
3881 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3882 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3883 | iommu_flush_dte(iommu, alias); |
3884 | } | |
3885 | ||
3886 | out: | |
3887 | iommu_completion_wait(iommu); | |
3888 | ||
3889 | out_unlock: | |
3890 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3891 | ||
3892 | return table; | |
3893 | } | |
3894 | ||
3895 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3896 | { | |
3897 | struct irq_remap_table *table; | |
3898 | unsigned long flags; | |
3899 | int index, c; | |
3900 | ||
3901 | table = get_irq_table(devid, false); | |
3902 | if (!table) | |
3903 | return -ENODEV; | |
3904 | ||
3905 | spin_lock_irqsave(&table->lock, flags); | |
3906 | ||
3907 | /* Scan table for free entries */ | |
3908 | for (c = 0, index = table->min_index; | |
3909 | index < MAX_IRQS_PER_TABLE; | |
3910 | ++index) { | |
3911 | if (table->table[index] == 0) | |
3912 | c += 1; | |
3913 | else | |
3914 | c = 0; | |
3915 | ||
3916 | if (c == count) { | |
0dfedd61 | 3917 | struct irq_2_irte *irte_info; |
2b324506 JR |
3918 | |
3919 | for (; c != 0; --c) | |
3920 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3921 | ||
3922 | index -= count - 1; | |
3923 | ||
9b1b0e42 | 3924 | cfg->remapped = 1; |
0dfedd61 JR |
3925 | irte_info = &cfg->irq_2_irte; |
3926 | irte_info->devid = devid; | |
3927 | irte_info->index = index; | |
2b324506 JR |
3928 | |
3929 | goto out; | |
3930 | } | |
3931 | } | |
3932 | ||
3933 | index = -ENOSPC; | |
3934 | ||
3935 | out: | |
3936 | spin_unlock_irqrestore(&table->lock, flags); | |
3937 | ||
3938 | return index; | |
3939 | } | |
3940 | ||
3941 | static int get_irte(u16 devid, int index, union irte *irte) | |
3942 | { | |
3943 | struct irq_remap_table *table; | |
3944 | unsigned long flags; | |
3945 | ||
3946 | table = get_irq_table(devid, false); | |
3947 | if (!table) | |
3948 | return -ENOMEM; | |
3949 | ||
3950 | spin_lock_irqsave(&table->lock, flags); | |
3951 | irte->val = table->table[index]; | |
3952 | spin_unlock_irqrestore(&table->lock, flags); | |
3953 | ||
3954 | return 0; | |
3955 | } | |
3956 | ||
3957 | static int modify_irte(u16 devid, int index, union irte irte) | |
3958 | { | |
3959 | struct irq_remap_table *table; | |
3960 | struct amd_iommu *iommu; | |
3961 | unsigned long flags; | |
3962 | ||
3963 | iommu = amd_iommu_rlookup_table[devid]; | |
3964 | if (iommu == NULL) | |
3965 | return -EINVAL; | |
3966 | ||
3967 | table = get_irq_table(devid, false); | |
3968 | if (!table) | |
3969 | return -ENOMEM; | |
3970 | ||
3971 | spin_lock_irqsave(&table->lock, flags); | |
3972 | table->table[index] = irte.val; | |
3973 | spin_unlock_irqrestore(&table->lock, flags); | |
3974 | ||
3975 | iommu_flush_irt(iommu, devid); | |
3976 | iommu_completion_wait(iommu); | |
3977 | ||
3978 | return 0; | |
3979 | } | |
3980 | ||
3981 | static void free_irte(u16 devid, int index) | |
3982 | { | |
3983 | struct irq_remap_table *table; | |
3984 | struct amd_iommu *iommu; | |
3985 | unsigned long flags; | |
3986 | ||
3987 | iommu = amd_iommu_rlookup_table[devid]; | |
3988 | if (iommu == NULL) | |
3989 | return; | |
3990 | ||
3991 | table = get_irq_table(devid, false); | |
3992 | if (!table) | |
3993 | return; | |
3994 | ||
3995 | spin_lock_irqsave(&table->lock, flags); | |
3996 | table->table[index] = 0; | |
3997 | spin_unlock_irqrestore(&table->lock, flags); | |
3998 | ||
3999 | iommu_flush_irt(iommu, devid); | |
4000 | iommu_completion_wait(iommu); | |
4001 | } | |
4002 | ||
5527de74 JR |
4003 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4004 | unsigned int destination, int vector, | |
4005 | struct io_apic_irq_attr *attr) | |
4006 | { | |
4007 | struct irq_remap_table *table; | |
0dfedd61 | 4008 | struct irq_2_irte *irte_info; |
5527de74 JR |
4009 | struct irq_cfg *cfg; |
4010 | union irte irte; | |
4011 | int ioapic_id; | |
4012 | int index; | |
4013 | int devid; | |
4014 | int ret; | |
4015 | ||
719b530c | 4016 | cfg = irq_cfg(irq); |
5527de74 JR |
4017 | if (!cfg) |
4018 | return -EINVAL; | |
4019 | ||
0dfedd61 | 4020 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4021 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
4022 | devid = get_ioapic_devid(ioapic_id); | |
4023 | ||
4024 | if (devid < 0) | |
4025 | return devid; | |
4026 | ||
4027 | table = get_irq_table(devid, true); | |
4028 | if (table == NULL) | |
4029 | return -ENOMEM; | |
4030 | ||
4031 | index = attr->ioapic_pin; | |
4032 | ||
4033 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 4034 | cfg->remapped = 1; |
0dfedd61 JR |
4035 | irte_info->devid = devid; |
4036 | irte_info->index = index; | |
5527de74 JR |
4037 | |
4038 | /* Setup IRTE for IOMMU */ | |
4039 | irte.val = 0; | |
4040 | irte.fields.vector = vector; | |
4041 | irte.fields.int_type = apic->irq_delivery_mode; | |
4042 | irte.fields.destination = destination; | |
4043 | irte.fields.dm = apic->irq_dest_mode; | |
4044 | irte.fields.valid = 1; | |
4045 | ||
4046 | ret = modify_irte(devid, index, irte); | |
4047 | if (ret) | |
4048 | return ret; | |
4049 | ||
4050 | /* Setup IOAPIC entry */ | |
4051 | memset(entry, 0, sizeof(*entry)); | |
4052 | ||
4053 | entry->vector = index; | |
4054 | entry->mask = 0; | |
4055 | entry->trigger = attr->trigger; | |
4056 | entry->polarity = attr->polarity; | |
4057 | ||
4058 | /* | |
4059 | * Mask level triggered irqs. | |
5527de74 JR |
4060 | */ |
4061 | if (attr->trigger) | |
4062 | entry->mask = 1; | |
4063 | ||
4064 | return 0; | |
4065 | } | |
4066 | ||
4067 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4068 | bool force) | |
4069 | { | |
0dfedd61 | 4070 | struct irq_2_irte *irte_info; |
5527de74 JR |
4071 | unsigned int dest, irq; |
4072 | struct irq_cfg *cfg; | |
4073 | union irte irte; | |
4074 | int err; | |
4075 | ||
4076 | if (!config_enabled(CONFIG_SMP)) | |
4077 | return -1; | |
4078 | ||
719b530c | 4079 | cfg = irqd_cfg(data); |
5527de74 | 4080 | irq = data->irq; |
0dfedd61 | 4081 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4082 | |
4083 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4084 | return -EINVAL; | |
4085 | ||
0dfedd61 | 4086 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
4087 | return -EBUSY; |
4088 | ||
4089 | if (assign_irq_vector(irq, cfg, mask)) | |
4090 | return -EBUSY; | |
4091 | ||
4092 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4093 | if (err) { | |
4094 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4095 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4096 | return err; | |
4097 | } | |
4098 | ||
4099 | irte.fields.vector = cfg->vector; | |
4100 | irte.fields.destination = dest; | |
4101 | ||
0dfedd61 | 4102 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
4103 | |
4104 | if (cfg->move_in_progress) | |
4105 | send_cleanup_vector(cfg); | |
4106 | ||
4107 | cpumask_copy(data->affinity, mask); | |
4108 | ||
4109 | return 0; | |
4110 | } | |
4111 | ||
4112 | static int free_irq(int irq) | |
4113 | { | |
0dfedd61 | 4114 | struct irq_2_irte *irte_info; |
5527de74 JR |
4115 | struct irq_cfg *cfg; |
4116 | ||
719b530c | 4117 | cfg = irq_cfg(irq); |
5527de74 JR |
4118 | if (!cfg) |
4119 | return -EINVAL; | |
4120 | ||
0dfedd61 | 4121 | irte_info = &cfg->irq_2_irte; |
5527de74 | 4122 | |
0dfedd61 | 4123 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
4124 | |
4125 | return 0; | |
4126 | } | |
4127 | ||
0b4d48cb JR |
4128 | static void compose_msi_msg(struct pci_dev *pdev, |
4129 | unsigned int irq, unsigned int dest, | |
4130 | struct msi_msg *msg, u8 hpet_id) | |
4131 | { | |
0dfedd61 | 4132 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4133 | struct irq_cfg *cfg; |
4134 | union irte irte; | |
4135 | ||
719b530c | 4136 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4137 | if (!cfg) |
4138 | return; | |
4139 | ||
0dfedd61 | 4140 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
4141 | |
4142 | irte.val = 0; | |
4143 | irte.fields.vector = cfg->vector; | |
4144 | irte.fields.int_type = apic->irq_delivery_mode; | |
4145 | irte.fields.destination = dest; | |
4146 | irte.fields.dm = apic->irq_dest_mode; | |
4147 | irte.fields.valid = 1; | |
4148 | ||
0dfedd61 | 4149 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
4150 | |
4151 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4152 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 4153 | msg->data = irte_info->index; |
0b4d48cb JR |
4154 | } |
4155 | ||
4156 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4157 | { | |
4158 | struct irq_cfg *cfg; | |
4159 | int index; | |
4160 | u16 devid; | |
4161 | ||
4162 | if (!pdev) | |
4163 | return -EINVAL; | |
4164 | ||
719b530c | 4165 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4166 | if (!cfg) |
4167 | return -EINVAL; | |
4168 | ||
4169 | devid = get_device_id(&pdev->dev); | |
4170 | index = alloc_irq_index(cfg, devid, nvec); | |
4171 | ||
4172 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4173 | } | |
4174 | ||
4175 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4176 | int index, int offset) | |
4177 | { | |
0dfedd61 | 4178 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4179 | struct irq_cfg *cfg; |
4180 | u16 devid; | |
4181 | ||
4182 | if (!pdev) | |
4183 | return -EINVAL; | |
4184 | ||
719b530c | 4185 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4186 | if (!cfg) |
4187 | return -EINVAL; | |
4188 | ||
4189 | if (index >= MAX_IRQS_PER_TABLE) | |
4190 | return 0; | |
4191 | ||
4192 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4193 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4194 | |
9b1b0e42 | 4195 | cfg->remapped = 1; |
0dfedd61 JR |
4196 | irte_info->devid = devid; |
4197 | irte_info->index = index + offset; | |
0b4d48cb JR |
4198 | |
4199 | return 0; | |
4200 | } | |
4201 | ||
5fc24d8c | 4202 | static int alloc_hpet_msi(unsigned int irq, unsigned int id) |
d976195c | 4203 | { |
0dfedd61 | 4204 | struct irq_2_irte *irte_info; |
d976195c JR |
4205 | struct irq_cfg *cfg; |
4206 | int index, devid; | |
4207 | ||
719b530c | 4208 | cfg = irq_cfg(irq); |
d976195c JR |
4209 | if (!cfg) |
4210 | return -EINVAL; | |
4211 | ||
0dfedd61 | 4212 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4213 | devid = get_hpet_devid(id); |
4214 | if (devid < 0) | |
4215 | return devid; | |
4216 | ||
4217 | index = alloc_irq_index(cfg, devid, 1); | |
4218 | if (index < 0) | |
4219 | return index; | |
4220 | ||
9b1b0e42 | 4221 | cfg->remapped = 1; |
0dfedd61 JR |
4222 | irte_info->devid = devid; |
4223 | irte_info->index = index; | |
d976195c JR |
4224 | |
4225 | return 0; | |
4226 | } | |
4227 | ||
6b474b82 | 4228 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4229 | .prepare = amd_iommu_prepare, |
4230 | .enable = amd_iommu_enable, | |
4231 | .disable = amd_iommu_disable, | |
4232 | .reenable = amd_iommu_reenable, | |
4233 | .enable_faulting = amd_iommu_enable_faulting, | |
4234 | .setup_ioapic_entry = setup_ioapic_entry, | |
4235 | .set_affinity = set_affinity, | |
4236 | .free_irq = free_irq, | |
4237 | .compose_msi_msg = compose_msi_msg, | |
4238 | .msi_alloc_irq = msi_alloc_irq, | |
4239 | .msi_setup_irq = msi_setup_irq, | |
5fc24d8c | 4240 | .alloc_hpet_msi = alloc_hpet_msi, |
6b474b82 | 4241 | }; |
2b324506 | 4242 | #endif |