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iommu/amd: Remove device binding reference count
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
CommitLineData
b6c02715 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
b6c02715
JR		 3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
72e1dcc4 20#include <linux/ratelimit.h>
b6c02715 21#include <linux/pci.h>
cb41ed85 22#include <linux/pci-ats.h>
a66022c4 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
7f26508b 25#include <linux/debugfs.h>
b6c02715 26#include <linux/scatterlist.h>
51491367 27#include <linux/dma-mapping.h>
b6c02715 28#include <linux/iommu-helper.h>
c156e347 29#include <linux/iommu.h>
815b33fd 30#include <linux/delay.h>
403f81d8 31#include <linux/amd-iommu.h>
72e1dcc4
JR		 32#include <linux/notifier.h>
33#include <linux/export.h>
2b324506
JR		 34#include <linux/irq.h>
35#include <linux/msi.h>
36#include <asm/irq_remapping.h>
37#include <asm/io_apic.h>
38#include <asm/apic.h>
39#include <asm/hw_irq.h>
17f5b569 40#include <asm/msidef.h>
b6c02715 41#include <asm/proto.h>
46a7fa27 42#include <asm/iommu.h>
1d9b16d1 43#include <asm/gart.h>
27c2127a 44#include <asm/dma.h>
403f81d8
JR		 45
46#include "amd_iommu_proto.h"
47#include "amd_iommu_types.h"
6b474b82 48#include "irq_remapping.h"
b6c02715
JR		 49
50#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51
815b33fd 52#define LOOP_TIMEOUT 100000
136f78a1 53
aa3de9c0
OBC		 54/*
55 * This bitmap is used to advertise the page sizes our hardware support
56 * to the IOMMU core, which will then use this information to split
57 * physically contiguous memory regions it is mapping into page sizes
58 * that we support.
59 *
954e3dd8 60 * 512GB Pages are not supported due to a hardware bug
aa3de9c0 61 */
954e3dd8 62#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
aa3de9c0 63
b6c02715
JR		 64static DEFINE_RWLOCK(amd_iommu_devtable_lock);
65
bd60b735
JR		 66/* A list of preallocated protection domains */
67static LIST_HEAD(iommu_pd_list);
68static DEFINE_SPINLOCK(iommu_pd_list_lock);
69
8fa5f802
JR		 70/* List of all available dev_data structures */
71static LIST_HEAD(dev_data_list);
72static DEFINE_SPINLOCK(dev_data_list_lock);
73
6efed63b
JR		 74LIST_HEAD(ioapic_map);
75LIST_HEAD(hpet_map);
76
0feae533
JR		 77/*
78 * Domain for untranslated devices - only allocated
79 * if iommu=pt passed on kernel cmd line.
80 */
81static struct protection_domain *pt_domain;
82
b22f6434 83static const struct iommu_ops amd_iommu_ops;
26961efe 84
72e1dcc4 85static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
52815b75 86int amd_iommu_max_glx_val = -1;
72e1dcc4 87
ac1534a5
JR		 88static struct dma_map_ops amd_iommu_dma_ops;
89
50917e26
JR		 90/*
91 * This struct contains device specific data for the IOMMU
92 */
93struct iommu_dev_data {
94 struct list_head list; /* For domain->dev_list */
95 struct list_head dev_data_list; /* For global dev_data_list */
f251e187 96 struct list_head alias_list; /* Link alias-groups together */
50917e26
JR		 97 struct iommu_dev_data *alias_data;/* The alias dev_data */
98 struct protection_domain *domain; /* Domain the device is bound to */
50917e26
JR		 99 u16 devid; /* PCI Device ID */
100 bool iommu_v2; /* Device can make use of IOMMUv2 */
101 bool passthrough; /* Default for device is pt_domain */
102 struct {
103 bool enabled;
104 int qdep;
105 } ats; /* ATS state */
106 bool pri_tlp; /* PASID TLB required for
107 PPR completions */
108 u32 errata; /* Bitmap for errata to apply */
109};
110
431b2a20
JR		 111/*
112 * general struct to manage commands send to an IOMMU
113 */
d6449536 114struct iommu_cmd {
b6c02715
JR		 115 u32 data[4];
116};
117
05152a04
JR		 118struct kmem_cache *amd_iommu_irq_cache;
119
04bfdd84 120static void update_domain(struct protection_domain *domain);
5abcdba4 121static int __init alloc_passthrough_domain(void);
c1eee67b 122
15898bbc
JR		 123/****************************************************************************
124 *
125 * Helper functions
126 *
127 ****************************************************************************/
128
f62dda66 129static struct iommu_dev_data *alloc_dev_data(u16 devid)
8fa5f802
JR		 130{
131 struct iommu_dev_data *dev_data;
132 unsigned long flags;
133
134 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
135 if (!dev_data)
136 return NULL;
137
f251e187
JR		 138 INIT_LIST_HEAD(&dev_data->alias_list);
139
f62dda66 140 dev_data->devid = devid;
8fa5f802
JR		 141
142 spin_lock_irqsave(&dev_data_list_lock, flags);
143 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
144 spin_unlock_irqrestore(&dev_data_list_lock, flags);
145
146 return dev_data;
147}
148
149static void free_dev_data(struct iommu_dev_data *dev_data)
150{
151 unsigned long flags;
152
153 spin_lock_irqsave(&dev_data_list_lock, flags);
154 list_del(&dev_data->dev_data_list);
155 spin_unlock_irqrestore(&dev_data_list_lock, flags);
156
157 kfree(dev_data);
158}
159
3b03bb74
JR		 160static struct iommu_dev_data *search_dev_data(u16 devid)
161{
162 struct iommu_dev_data *dev_data;
163 unsigned long flags;
164
165 spin_lock_irqsave(&dev_data_list_lock, flags);
166 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
167 if (dev_data->devid == devid)
168 goto out_unlock;
169 }
170
171 dev_data = NULL;
172
173out_unlock:
174 spin_unlock_irqrestore(&dev_data_list_lock, flags);
175
176 return dev_data;
177}
178
179static struct iommu_dev_data *find_dev_data(u16 devid)
180{
181 struct iommu_dev_data *dev_data;
182
183 dev_data = search_dev_data(devid);
184
185 if (dev_data == NULL)
186 dev_data = alloc_dev_data(devid);
187
188 return dev_data;
189}
190
15898bbc
JR		 191static inline u16 get_device_id(struct device *dev)
192{
193 struct pci_dev *pdev = to_pci_dev(dev);
194
6f2729ba 195 return PCI_DEVID(pdev->bus->number, pdev->devfn);
15898bbc
JR		 196}
197
657cbb6b
JR		 198static struct iommu_dev_data *get_dev_data(struct device *dev)
199{
200 return dev->archdata.iommu;
201}
202
5abcdba4
JR		 203static bool pci_iommuv2_capable(struct pci_dev *pdev)
204{
205 static const int caps[] = {
206 PCI_EXT_CAP_ID_ATS,
46277b75
JR		 207 PCI_EXT_CAP_ID_PRI,
208 PCI_EXT_CAP_ID_PASID,
5abcdba4
JR		 209 };
210 int i, pos;
211
212 for (i = 0; i < 3; ++i) {
213 pos = pci_find_ext_capability(pdev, caps[i]);
214 if (pos == 0)
215 return false;
216 }
217
218 return true;
219}
220
6a113ddc
JR		 221static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
222{
223 struct iommu_dev_data *dev_data;
224
225 dev_data = get_dev_data(&pdev->dev);
226
227 return dev_data->errata & (1 << erratum) ? true : false;
228}
229
71c70984
JR		 230/*
231 * In this function the list of preallocated protection domains is traversed to
232 * find the domain for a specific device
233 */
234static struct dma_ops_domain *find_protection_domain(u16 devid)
235{
236 struct dma_ops_domain *entry, *ret = NULL;
237 unsigned long flags;
238 u16 alias = amd_iommu_alias_table[devid];
239
240 if (list_empty(&iommu_pd_list))
241 return NULL;
242
243 spin_lock_irqsave(&iommu_pd_list_lock, flags);
244
245 list_for_each_entry(entry, &iommu_pd_list, list) {
246 if (entry->target_dev == devid ||
247 entry->target_dev == alias) {
248 ret = entry;
249 break;
250 }
251 }
252
253 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
254
255 return ret;
256}
257
98fc5a69
JR		 258/*
259 * This function checks if the driver got a valid device from the caller to
260 * avoid dereferencing invalid pointers.
261 */
262static bool check_device(struct device *dev)
263{
264 u16 devid;
265
266 if (!dev || !dev->dma_mask)
267 return false;
268
b82a2272
YW		 269 /* No PCI device */
270 if (!dev_is_pci(dev))
98fc5a69
JR		 271 return false;
272
273 devid = get_device_id(dev);
274
275 /* Out of our scope? */
276 if (devid > amd_iommu_last_bdf)
277 return false;
278
279 if (amd_iommu_rlookup_table[devid] == NULL)
280 return false;
281
282 return true;
283}
284
2851db21
AW		 285static int init_iommu_group(struct device *dev)
286{
2851db21 287 struct iommu_group *group;
2851db21 288
65d5352f 289 group = iommu_group_get_for_dev(dev);
2851db21 290
65d5352f
AW		 291 if (IS_ERR(group))
292 return PTR_ERR(group);
2851db21 293
65d5352f
AW		 294 iommu_group_put(group);
295 return 0;
eb9c9527
AW		 296}
297
c1931090
AW		 298static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
299{
300 *(u16 *)data = alias;
301 return 0;
302}
303
304static u16 get_alias(struct device *dev)
305{
306 struct pci_dev *pdev = to_pci_dev(dev);
307 u16 devid, ivrs_alias, pci_alias;
308
309 devid = get_device_id(dev);
310 ivrs_alias = amd_iommu_alias_table[devid];
311 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
312
313 if (ivrs_alias == pci_alias)
314 return ivrs_alias;
315
316 /*
317 * DMA alias showdown
318 *
319 * The IVRS is fairly reliable in telling us about aliases, but it
320 * can't know about every screwy device. If we don't have an IVRS
321 * reported alias, use the PCI reported alias. In that case we may
322 * still need to initialize the rlookup and dev_table entries if the
323 * alias is to a non-existent device.
324 */
325 if (ivrs_alias == devid) {
326 if (!amd_iommu_rlookup_table[pci_alias]) {
327 amd_iommu_rlookup_table[pci_alias] =
328 amd_iommu_rlookup_table[devid];
329 memcpy(amd_iommu_dev_table[pci_alias].data,
330 amd_iommu_dev_table[devid].data,
331 sizeof(amd_iommu_dev_table[pci_alias].data));
332 }
333
334 return pci_alias;
335 }
336
337 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
338 "for device %s[%04x:%04x], kernel reported alias "
339 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
340 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
341 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
342 PCI_FUNC(pci_alias));
343
344 /*
345 * If we don't have a PCI DMA alias and the IVRS alias is on the same
346 * bus, then the IVRS table may know about a quirk that we don't.
347 */
348 if (pci_alias == devid &&
349 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
350 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
351 pdev->dma_alias_devfn = ivrs_alias & 0xff;
352 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
353 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
354 dev_name(dev));
355 }
356
357 return ivrs_alias;
358}
359
eb9c9527
AW		 360static int iommu_init_device(struct device *dev)
361{
362 struct pci_dev *pdev = to_pci_dev(dev);
363 struct iommu_dev_data *dev_data;
364 u16 alias;
365 int ret;
366
367 if (dev->archdata.iommu)
368 return 0;
369
370 dev_data = find_dev_data(get_device_id(dev));
371 if (!dev_data)
372 return -ENOMEM;
373
c1931090
AW		 374 alias = get_alias(dev);
375
eb9c9527
AW		 376 if (alias != dev_data->devid) {
377 struct iommu_dev_data *alias_data;
378
379 alias_data = find_dev_data(alias);
380 if (alias_data == NULL) {
381 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
382 dev_name(dev));
383 free_dev_data(dev_data);
384 return -ENOTSUPP;
385 }
386 dev_data->alias_data = alias_data;
f251e187
JR		 387
388 /* Add device to the alias_list */
389 list_add(&dev_data->alias_list, &alias_data->alias_list);
eb9c9527
AW		 390 }
391
392 ret = init_iommu_group(dev);
e644a013
RK		 393 if (ret) {
394 free_dev_data(dev_data);
9dcd6130 395 return ret;
e644a013 396 }
9dcd6130 397
5abcdba4
JR		 398 if (pci_iommuv2_capable(pdev)) {
399 struct amd_iommu *iommu;
400
401 iommu = amd_iommu_rlookup_table[dev_data->devid];
402 dev_data->iommu_v2 = iommu->is_iommu_v2;
403 }
404
657cbb6b
JR		 405 dev->archdata.iommu = dev_data;
406
066f2e98
AW		 407 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
408 dev);
409
657cbb6b
JR		 410 return 0;
411}
412
26018874
JR		 413static void iommu_ignore_device(struct device *dev)
414{
415 u16 devid, alias;
416
417 devid = get_device_id(dev);
418 alias = amd_iommu_alias_table[devid];
419
420 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
421 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
422
423 amd_iommu_rlookup_table[devid] = NULL;
424 amd_iommu_rlookup_table[alias] = NULL;
425}
426
657cbb6b
JR		 427static void iommu_uninit_device(struct device *dev)
428{
c1931090
AW		 429 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
430
431 if (!dev_data)
432 return;
433
066f2e98
AW		 434 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
435 dev);
436
9dcd6130
AW		 437 iommu_group_remove_device(dev);
438
c1931090
AW		 439 /* Unlink from alias, it may change if another device is re-plugged */
440 dev_data->alias_data = NULL;
441
8fa5f802 442 /*
c1931090
AW		 443 * We keep dev_data around for unplugged devices and reuse it when the
444 * device is re-plugged - not doing so would introduce a ton of races.
8fa5f802 445 */
657cbb6b 446}
b7cc9554
JR		 447
448void __init amd_iommu_uninit_devices(void)
449{
8fa5f802 450 struct iommu_dev_data *dev_data, *n;
b7cc9554
JR		 451 struct pci_dev *pdev = NULL;
452
453 for_each_pci_dev(pdev) {
454
455 if (!check_device(&pdev->dev))
456 continue;
457
458 iommu_uninit_device(&pdev->dev);
459 }
8fa5f802
JR		 460
461 /* Free all of our dev_data structures */
462 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
463 free_dev_data(dev_data);
b7cc9554
JR		 464}
465
466int __init amd_iommu_init_devices(void)
467{
468 struct pci_dev *pdev = NULL;
469 int ret = 0;
470
471 for_each_pci_dev(pdev) {
472
473 if (!check_device(&pdev->dev))
474 continue;
475
476 ret = iommu_init_device(&pdev->dev);
26018874
JR		 477 if (ret == -ENOTSUPP)
478 iommu_ignore_device(&pdev->dev);
479 else if (ret)
b7cc9554
JR		 480 goto out_free;
481 }
482
483 return 0;
484
485out_free:
486
487 amd_iommu_uninit_devices();
488
489 return ret;
490}
7f26508b
JR		 491#ifdef CONFIG_AMD_IOMMU_STATS
492
493/*
494 * Initialization code for statistics collection
495 */
496
da49f6df 497DECLARE_STATS_COUNTER(compl_wait);
0f2a86f2 498DECLARE_STATS_COUNTER(cnt_map_single);
146a6917 499DECLARE_STATS_COUNTER(cnt_unmap_single);
d03f067a 500DECLARE_STATS_COUNTER(cnt_map_sg);
55877a6b 501DECLARE_STATS_COUNTER(cnt_unmap_sg);
c8f0fb36 502DECLARE_STATS_COUNTER(cnt_alloc_coherent);
5d31ee7e 503DECLARE_STATS_COUNTER(cnt_free_coherent);
c1858976 504DECLARE_STATS_COUNTER(cross_page);
f57d98ae 505DECLARE_STATS_COUNTER(domain_flush_single);
18811f55 506DECLARE_STATS_COUNTER(domain_flush_all);
5774f7c5 507DECLARE_STATS_COUNTER(alloced_io_mem);
8ecaf8f1 508DECLARE_STATS_COUNTER(total_map_requests);
399be2f5
JR		 509DECLARE_STATS_COUNTER(complete_ppr);
510DECLARE_STATS_COUNTER(invalidate_iotlb);
511DECLARE_STATS_COUNTER(invalidate_iotlb_all);
512DECLARE_STATS_COUNTER(pri_requests);
513
7f26508b 514static struct dentry *stats_dir;
7f26508b
JR		 515static struct dentry *de_fflush;
516
517static void amd_iommu_stats_add(struct __iommu_counter *cnt)
518{
519 if (stats_dir == NULL)
520 return;
521
522 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
523 &cnt->value);
524}
525
526static void amd_iommu_stats_init(void)
527{
528 stats_dir = debugfs_create_dir("amd-iommu", NULL);
529 if (stats_dir == NULL)
530 return;
531
7f26508b 532 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
3775d481 533 &amd_iommu_unmap_flush);
da49f6df
JR		 534
535 amd_iommu_stats_add(&compl_wait);
0f2a86f2 536 amd_iommu_stats_add(&cnt_map_single);
146a6917 537 amd_iommu_stats_add(&cnt_unmap_single);
d03f067a 538 amd_iommu_stats_add(&cnt_map_sg);
55877a6b 539 amd_iommu_stats_add(&cnt_unmap_sg);
c8f0fb36 540 amd_iommu_stats_add(&cnt_alloc_coherent);
5d31ee7e 541 amd_iommu_stats_add(&cnt_free_coherent);
c1858976 542 amd_iommu_stats_add(&cross_page);
f57d98ae 543 amd_iommu_stats_add(&domain_flush_single);
18811f55 544 amd_iommu_stats_add(&domain_flush_all);
5774f7c5 545 amd_iommu_stats_add(&alloced_io_mem);
8ecaf8f1 546 amd_iommu_stats_add(&total_map_requests);
399be2f5
JR		 547 amd_iommu_stats_add(&complete_ppr);
548 amd_iommu_stats_add(&invalidate_iotlb);
549 amd_iommu_stats_add(&invalidate_iotlb_all);
550 amd_iommu_stats_add(&pri_requests);
7f26508b
JR		 551}
552
553#endif
554
a80dc3e0
JR		 555/****************************************************************************
556 *
557 * Interrupt handling functions
558 *
559 ****************************************************************************/
560
e3e59876
JR		 561static void dump_dte_entry(u16 devid)
562{
563 int i;
564
ee6c2868
JR		 565 for (i = 0; i < 4; ++i)
566 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
e3e59876
JR		 567 amd_iommu_dev_table[devid].data[i]);
568}
569
945b4ac4
JR		 570static void dump_command(unsigned long phys_addr)
571{
572 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
573 int i;
574
575 for (i = 0; i < 4; ++i)
576 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
577}
578
a345b23b 579static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
90008ee4 580{
3d06fca8
JR		 581 int type, devid, domid, flags;
582 volatile u32 *event = __evt;
583 int count = 0;
584 u64 address;
585
586retry:
587 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
588 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
589 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
590 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
591 address = (u64)(((u64)event[3]) << 32) | event[2];
592
593 if (type == 0) {
594 /* Did we hit the erratum? */
595 if (++count == LOOP_TIMEOUT) {
596 pr_err("AMD-Vi: No event written to event log\n");
597 return;
598 }
599 udelay(1);
600 goto retry;
601 }
90008ee4 602
4c6f40d4 603 printk(KERN_ERR "AMD-Vi: Event logged [");
90008ee4
JR		 604
605 switch (type) {
606 case EVENT_TYPE_ILL_DEV:
607 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
608 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 609 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4 610 address, flags);
e3e59876 611 dump_dte_entry(devid);
90008ee4
JR		 612 break;
613 case EVENT_TYPE_IO_FAULT:
614 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
615 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
c5081cd7 616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 617 domid, address, flags);
618 break;
619 case EVENT_TYPE_DEV_TAB_ERR:
620 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
621 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 622 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 623 address, flags);
624 break;
625 case EVENT_TYPE_PAGE_TAB_ERR:
626 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
627 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
c5081cd7 628 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 629 domid, address, flags);
630 break;
631 case EVENT_TYPE_ILL_CMD:
632 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
945b4ac4 633 dump_command(address);
90008ee4
JR		 634 break;
635 case EVENT_TYPE_CMD_HARD_ERR:
636 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
637 "flags=0x%04x]\n", address, flags);
638 break;
639 case EVENT_TYPE_IOTLB_INV_TO:
640 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
641 "address=0x%016llx]\n",
c5081cd7 642 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 643 address);
644 break;
645 case EVENT_TYPE_INV_DEV_REQ:
646 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
647 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 648 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 649 address, flags);
650 break;
651 default:
652 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
653 }
3d06fca8
JR		 654
655 memset(__evt, 0, 4 * sizeof(u32));
90008ee4
JR		 656}
657
658static void iommu_poll_events(struct amd_iommu *iommu)
659{
660 u32 head, tail;
90008ee4
JR		 661
662 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
663 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
664
665 while (head != tail) {
a345b23b 666 iommu_print_event(iommu, iommu->evt_buf + head);
90008ee4
JR		 667 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
668 }
669
670 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
90008ee4
JR		 671}
672
eee53537 673static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
72e1dcc4
JR		 674{
675 struct amd_iommu_fault fault;
72e1dcc4 676
399be2f5
JR		 677 INC_STATS_COUNTER(pri_requests);
678
72e1dcc4
JR		 679 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
680 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
681 return;
682 }
683
684 fault.address = raw[1];
685 fault.pasid = PPR_PASID(raw[0]);
686 fault.device_id = PPR_DEVID(raw[0]);
687 fault.tag = PPR_TAG(raw[0]);
688 fault.flags = PPR_FLAGS(raw[0]);
689
72e1dcc4
JR		 690 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
691}
692
693static void iommu_poll_ppr_log(struct amd_iommu *iommu)
694{
72e1dcc4
JR		 695 u32 head, tail;
696
697 if (iommu->ppr_log == NULL)
698 return;
699
72e1dcc4
JR		 700 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
701 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
702
703 while (head != tail) {
eee53537
JR		 704 volatile u64 *raw;
705 u64 entry[2];
706 int i;
707
708 raw = (u64 *)(iommu->ppr_log + head);
709
710 /*
711 * Hardware bug: Interrupt may arrive before the entry is
712 * written to memory. If this happens we need to wait for the
713 * entry to arrive.
714 */
715 for (i = 0; i < LOOP_TIMEOUT; ++i) {
716 if (PPR_REQ_TYPE(raw[0]) != 0)
717 break;
718 udelay(1);
719 }
72e1dcc4 720
eee53537
JR		 721 /* Avoid memcpy function-call overhead */
722 entry[0] = raw[0];
723 entry[1] = raw[1];
72e1dcc4 724
eee53537
JR		 725 /*
726 * To detect the hardware bug we need to clear the entry
727 * back to zero.
728 */
729 raw[0] = raw[1] = 0UL;
730
731 /* Update head pointer of hardware ring-buffer */
72e1dcc4
JR		 732 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
733 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
eee53537 734
eee53537
JR		 735 /* Handle PPR entry */
736 iommu_handle_ppr_entry(iommu, entry);
737
eee53537
JR		 738 /* Refresh ring-buffer information */
739 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
72e1dcc4
JR		 740 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
741 }
72e1dcc4
JR		 742}
743
72fe00f0 744irqreturn_t amd_iommu_int_thread(int irq, void *data)
a80dc3e0 745{
3f398bc7
SS		 746 struct amd_iommu *iommu = (struct amd_iommu *) data;
747 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 748
3f398bc7
SS		 749 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
750 /* Enable EVT and PPR interrupts again */
751 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
752 iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 753
3f398bc7
SS		 754 if (status & MMIO_STATUS_EVT_INT_MASK) {
755 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
756 iommu_poll_events(iommu);
757 }
90008ee4 758
3f398bc7
SS		 759 if (status & MMIO_STATUS_PPR_INT_MASK) {
760 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
761 iommu_poll_ppr_log(iommu);
762 }
90008ee4 763
3f398bc7
SS		 764 /*
765 * Hardware bug: ERBT1312
766 * When re-enabling interrupt (by writing 1
767 * to clear the bit), the hardware might also try to set
768 * the interrupt bit in the event status register.
769 * In this scenario, the bit will be set, and disable
770 * subsequent interrupts.
771 *
772 * Workaround: The IOMMU driver should read back the
773 * status register and check if the interrupt bits are cleared.
774 * If not, driver will need to go through the interrupt handler
775 * again and re-clear the bits
776 */
777 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
778 }
90008ee4 779 return IRQ_HANDLED;
a80dc3e0
JR		 780}
781
72fe00f0
JR		 782irqreturn_t amd_iommu_int_handler(int irq, void *data)
783{
784 return IRQ_WAKE_THREAD;
785}
786
431b2a20
JR		 787/****************************************************************************
788 *
789 * IOMMU command queuing functions
790 *
791 ****************************************************************************/
792
ac0ea6e9
JR		 793static int wait_on_sem(volatile u64 *sem)
794{
795 int i = 0;
796
797 while (*sem == 0 && i < LOOP_TIMEOUT) {
798 udelay(1);
799 i += 1;
800 }
801
802 if (i == LOOP_TIMEOUT) {
803 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
804 return -EIO;
805 }
806
807 return 0;
808}
809
810static void copy_cmd_to_buffer(struct amd_iommu *iommu,
811 struct iommu_cmd *cmd,
812 u32 tail)
a19ae1ec 813{
a19ae1ec
JR		 814 u8 *target;
815
8a7c5ef3 816 target = iommu->cmd_buf + tail;
ac0ea6e9
JR		 817 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
818
819 /* Copy command to buffer */
820 memcpy(target, cmd, sizeof(*cmd));
821
822 /* Tell the IOMMU about it */
a19ae1ec 823 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
ac0ea6e9 824}
a19ae1ec 825
815b33fd 826static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
ded46737 827{
815b33fd
JR		 828 WARN_ON(address & 0x7ULL);
829
ded46737 830 memset(cmd, 0, sizeof(*cmd));
815b33fd
JR		 831 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
832 cmd->data[1] = upper_32_bits(__pa(address));
833 cmd->data[2] = 1;
ded46737
JR		 834 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
835}
836
94fe79e2
JR		 837static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
838{
839 memset(cmd, 0, sizeof(*cmd));
840 cmd->data[0] = devid;
841 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
842}
843
11b6402c
JR		 844static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
845 size_t size, u16 domid, int pde)
846{
847 u64 pages;
848 int s;
849
850 pages = iommu_num_pages(address, size, PAGE_SIZE);
851 s = 0;
852
853 if (pages > 1) {
854 /*
855 * If we have to flush more than one page, flush all
856 * TLB entries for this domain
857 */
858 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
859 s = 1;
860 }
861
862 address &= PAGE_MASK;
863
864 memset(cmd, 0, sizeof(*cmd));
865 cmd->data[1] |= domid;
866 cmd->data[2] = lower_32_bits(address);
867 cmd->data[3] = upper_32_bits(address);
868 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
869 if (s) /* size bit - we flush more than one 4kb page */
870 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
df805abb 871 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
11b6402c
JR		 872 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
873}
874
cb41ed85
JR		 875static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
876 u64 address, size_t size)
877{
878 u64 pages;
879 int s;
880
881 pages = iommu_num_pages(address, size, PAGE_SIZE);
882 s = 0;
883
884 if (pages > 1) {
885 /*
886 * If we have to flush more than one page, flush all
887 * TLB entries for this domain
888 */
889 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
890 s = 1;
891 }
892
893 address &= PAGE_MASK;
894
895 memset(cmd, 0, sizeof(*cmd));
896 cmd->data[0] = devid;
897 cmd->data[0] |= (qdep & 0xff) << 24;
898 cmd->data[1] = devid;
899 cmd->data[2] = lower_32_bits(address);
900 cmd->data[3] = upper_32_bits(address);
901 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
902 if (s)
903 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
904}
905
22e266c7
JR		 906static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
907 u64 address, bool size)
908{
909 memset(cmd, 0, sizeof(*cmd));
910
911 address &= ~(0xfffULL);
912
a919a018 913 cmd->data[0] = pasid;
22e266c7
JR		 914 cmd->data[1] = domid;
915 cmd->data[2] = lower_32_bits(address);
916 cmd->data[3] = upper_32_bits(address);
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
918 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
919 if (size)
920 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
921 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
922}
923
924static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
925 int qdep, u64 address, bool size)
926{
927 memset(cmd, 0, sizeof(*cmd));
928
929 address &= ~(0xfffULL);
930
931 cmd->data[0] = devid;
e8d2d82d 932 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
22e266c7
JR		 933 cmd->data[0] |= (qdep & 0xff) << 24;
934 cmd->data[1] = devid;
e8d2d82d 935 cmd->data[1] |= (pasid & 0xff) << 16;
22e266c7
JR		 936 cmd->data[2] = lower_32_bits(address);
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
938 cmd->data[3] = upper_32_bits(address);
939 if (size)
940 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
941 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
942}
943
c99afa25
JR		 944static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
945 int status, int tag, bool gn)
946{
947 memset(cmd, 0, sizeof(*cmd));
948
949 cmd->data[0] = devid;
950 if (gn) {
a919a018 951 cmd->data[1] = pasid;
c99afa25
JR		 952 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
953 }
954 cmd->data[3] = tag & 0x1ff;
955 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
956
957 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
958}
959
58fc7f14
JR		 960static void build_inv_all(struct iommu_cmd *cmd)
961{
962 memset(cmd, 0, sizeof(*cmd));
963 CMD_SET_TYPE(cmd, CMD_INV_ALL);
a19ae1ec
JR		 964}
965
7ef2798d
JR		 966static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
967{
968 memset(cmd, 0, sizeof(*cmd));
969 cmd->data[0] = devid;
970 CMD_SET_TYPE(cmd, CMD_INV_IRT);
971}
972
431b2a20 973/*
431b2a20 974 * Writes the command to the IOMMUs command buffer and informs the
ac0ea6e9 975 * hardware about the new command.
431b2a20 976 */
f1ca1512
JR		 977static int iommu_queue_command_sync(struct amd_iommu *iommu,
978 struct iommu_cmd *cmd,
979 bool sync)
a19ae1ec 980{
ac0ea6e9 981 u32 left, tail, head, next_tail;
a19ae1ec 982 unsigned long flags;
a19ae1ec 983
549c90dc 984 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
ac0ea6e9
JR		 985
986again:
a19ae1ec 987 spin_lock_irqsave(&iommu->lock, flags);
a19ae1ec 988
ac0ea6e9
JR		 989 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
990 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
991 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
992 left = (head - next_tail) % iommu->cmd_buf_size;
a19ae1ec 993
ac0ea6e9
JR		 994 if (left <= 2) {
995 struct iommu_cmd sync_cmd;
996 volatile u64 sem = 0;
997 int ret;
8d201968 998
ac0ea6e9
JR		 999 build_completion_wait(&sync_cmd, (u64)&sem);
1000 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
da49f6df 1001
ac0ea6e9
JR		 1002 spin_unlock_irqrestore(&iommu->lock, flags);
1003
1004 if ((ret = wait_on_sem(&sem)) != 0)
1005 return ret;
1006
1007 goto again;
8d201968
JR		 1008 }
1009
ac0ea6e9
JR		 1010 copy_cmd_to_buffer(iommu, cmd, tail);
1011
1012 /* We need to sync now to make sure all commands are processed */
f1ca1512 1013 iommu->need_sync = sync;
ac0ea6e9 1014
a19ae1ec 1015 spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 1016
815b33fd 1017 return 0;
8d201968
JR		 1018}
1019
f1ca1512
JR		 1020static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1021{
1022 return iommu_queue_command_sync(iommu, cmd, true);
1023}
1024
8d201968
JR		 1025/*
1026 * This function queues a completion wait command into the command
1027 * buffer of an IOMMU
1028 */
a19ae1ec 1029static int iommu_completion_wait(struct amd_iommu *iommu)
8d201968
JR		 1030{
1031 struct iommu_cmd cmd;
815b33fd 1032 volatile u64 sem = 0;
ac0ea6e9 1033 int ret;
8d201968 1034
09ee17eb 1035 if (!iommu->need_sync)
815b33fd 1036 return 0;
09ee17eb 1037
815b33fd 1038 build_completion_wait(&cmd, (u64)&sem);
a19ae1ec 1039
f1ca1512 1040 ret = iommu_queue_command_sync(iommu, &cmd, false);
a19ae1ec 1041 if (ret)
815b33fd 1042 return ret;
8d201968 1043
ac0ea6e9 1044 return wait_on_sem(&sem);
8d201968
JR		 1045}
1046
d8c13085 1047static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
a19ae1ec 1048{
d8c13085 1049 struct iommu_cmd cmd;
a19ae1ec 1050
d8c13085 1051 build_inv_dte(&cmd, devid);
7e4f88da 1052
d8c13085
JR		 1053 return iommu_queue_command(iommu, &cmd);
1054}
09ee17eb 1055
7d0c5cc5
JR		 1056static void iommu_flush_dte_all(struct amd_iommu *iommu)
1057{
1058 u32 devid;
09ee17eb 1059
7d0c5cc5
JR		 1060 for (devid = 0; devid <= 0xffff; ++devid)
1061 iommu_flush_dte(iommu, devid);
a19ae1ec 1062
7d0c5cc5
JR		 1063 iommu_completion_wait(iommu);
1064}
84df8175 1065
7d0c5cc5
JR		 1066/*
1067 * This function uses heavy locking and may disable irqs for some time. But
1068 * this is no issue because it is only called during resume.
1069 */
1070static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1071{
1072 u32 dom_id;
a19ae1ec 1073
7d0c5cc5
JR		 1074 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1075 struct iommu_cmd cmd;
1076 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1077 dom_id, 1);
1078 iommu_queue_command(iommu, &cmd);
1079 }
8eed9833 1080
7d0c5cc5 1081 iommu_completion_wait(iommu);
a19ae1ec
JR		 1082}
1083
58fc7f14 1084static void iommu_flush_all(struct amd_iommu *iommu)
0518a3a4 1085{
58fc7f14 1086 struct iommu_cmd cmd;
0518a3a4 1087
58fc7f14 1088 build_inv_all(&cmd);
0518a3a4 1089
58fc7f14
JR		 1090 iommu_queue_command(iommu, &cmd);
1091 iommu_completion_wait(iommu);
1092}
1093
7ef2798d
JR		 1094static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1095{
1096 struct iommu_cmd cmd;
1097
1098 build_inv_irt(&cmd, devid);
1099
1100 iommu_queue_command(iommu, &cmd);
1101}
1102
1103static void iommu_flush_irt_all(struct amd_iommu *iommu)
1104{
1105 u32 devid;
1106
1107 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1108 iommu_flush_irt(iommu, devid);
1109
1110 iommu_completion_wait(iommu);
1111}
1112
7d0c5cc5
JR		 1113void iommu_flush_all_caches(struct amd_iommu *iommu)
1114{
58fc7f14
JR		 1115 if (iommu_feature(iommu, FEATURE_IA)) {
1116 iommu_flush_all(iommu);
1117 } else {
1118 iommu_flush_dte_all(iommu);
7ef2798d 1119 iommu_flush_irt_all(iommu);
58fc7f14 1120 iommu_flush_tlb_all(iommu);
0518a3a4
JR		 1121 }
1122}
1123
431b2a20 1124/*
cb41ed85 1125 * Command send function for flushing on-device TLB
431b2a20 1126 */
6c542047
JR		 1127static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1128 u64 address, size_t size)
3fa43655
JR		 1129{
1130 struct amd_iommu *iommu;
b00d3bcf 1131 struct iommu_cmd cmd;
cb41ed85 1132 int qdep;
3fa43655 1133
ea61cddb
JR		 1134 qdep = dev_data->ats.qdep;
1135 iommu = amd_iommu_rlookup_table[dev_data->devid];
3fa43655 1136
ea61cddb 1137 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
b00d3bcf
JR		 1138
1139 return iommu_queue_command(iommu, &cmd);
3fa43655
JR		 1140}
1141
431b2a20 1142/*
431b2a20 1143 * Command send function for invalidating a device table entry
431b2a20 1144 */
6c542047 1145static int device_flush_dte(struct iommu_dev_data *dev_data)
a19ae1ec 1146{
3fa43655 1147 struct amd_iommu *iommu;
ee2fa743 1148 int ret;
a19ae1ec 1149
6c542047 1150 iommu = amd_iommu_rlookup_table[dev_data->devid];
a19ae1ec 1151
f62dda66 1152 ret = iommu_flush_dte(iommu, dev_data->devid);
cb41ed85
JR		 1153 if (ret)
1154 return ret;
1155
ea61cddb 1156 if (dev_data->ats.enabled)
6c542047 1157 ret = device_flush_iotlb(dev_data, 0, ~0UL);
ee2fa743 1158
ee2fa743 1159 return ret;
a19ae1ec
JR		 1160}
1161
431b2a20
JR		 1162/*
1163 * TLB invalidation function which is called from the mapping functions.
1164 * It invalidates a single PTE if the range to flush is within a single
1165 * page. Otherwise it flushes the whole TLB of the IOMMU.
1166 */
17b124bf
JR		 1167static void __domain_flush_pages(struct protection_domain *domain,
1168 u64 address, size_t size, int pde)
a19ae1ec 1169{
cb41ed85 1170 struct iommu_dev_data *dev_data;
11b6402c
JR		 1171 struct iommu_cmd cmd;
1172 int ret = 0, i;
a19ae1ec 1173
11b6402c 1174 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
999ba417 1175
6de8ad9b
JR		 1176 for (i = 0; i < amd_iommus_present; ++i) {
1177 if (!domain->dev_iommu[i])
1178 continue;
1179
1180 /*
1181 * Devices of this domain are behind this IOMMU
1182 * We need a TLB flush
1183 */
11b6402c 1184 ret |= iommu_queue_command(amd_iommus[i], &cmd);
6de8ad9b
JR		 1185 }
1186
cb41ed85 1187 list_for_each_entry(dev_data, &domain->dev_list, list) {
cb41ed85 1188
ea61cddb 1189 if (!dev_data->ats.enabled)
cb41ed85
JR		 1190 continue;
1191
6c542047 1192 ret |= device_flush_iotlb(dev_data, address, size);
cb41ed85
JR		 1193 }
1194
11b6402c 1195 WARN_ON(ret);
6de8ad9b
JR		 1196}
1197
17b124bf
JR		 1198static void domain_flush_pages(struct protection_domain *domain,
1199 u64 address, size_t size)
6de8ad9b 1200{
17b124bf 1201 __domain_flush_pages(domain, address, size, 0);
a19ae1ec 1202}
b6c02715 1203
1c655773 1204/* Flush the whole IO/TLB for a given protection domain */
17b124bf 1205static void domain_flush_tlb(struct protection_domain *domain)
1c655773 1206{
17b124bf 1207 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1c655773
JR		 1208}
1209
42a49f96 1210/* Flush the whole IO/TLB for a given protection domain - including PDE */
17b124bf 1211static void domain_flush_tlb_pde(struct protection_domain *domain)
42a49f96 1212{
17b124bf 1213 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
42a49f96
CW		 1214}
1215
17b124bf 1216static void domain_flush_complete(struct protection_domain *domain)
b00d3bcf 1217{
17b124bf 1218 int i;
18811f55 1219
17b124bf
JR		 1220 for (i = 0; i < amd_iommus_present; ++i) {
1221 if (!domain->dev_iommu[i])
1222 continue;
bfd1be18 1223
17b124bf
JR		 1224 /*
1225 * Devices of this domain are behind this IOMMU
1226 * We need to wait for completion of all commands.
1227 */
1228 iommu_completion_wait(amd_iommus[i]);
bfd1be18 1229 }
e394d72a
JR		 1230}
1231
b00d3bcf 1232
09b42804 1233/*
b00d3bcf 1234 * This function flushes the DTEs for all devices in domain
09b42804 1235 */
17b124bf 1236static void domain_flush_devices(struct protection_domain *domain)
e394d72a 1237{
b00d3bcf 1238 struct iommu_dev_data *dev_data;
b26e81b8 1239
b00d3bcf 1240 list_for_each_entry(dev_data, &domain->dev_list, list)
6c542047 1241 device_flush_dte(dev_data);
a345b23b
JR		 1242}
1243
431b2a20
JR		 1244/****************************************************************************
1245 *
1246 * The functions below are used the create the page table mappings for
1247 * unity mapped regions.
1248 *
1249 ****************************************************************************/
1250
308973d3
JR		 1251/*
1252 * This function is used to add another level to an IO page table. Adding
1253 * another level increases the size of the address space by 9 bits to a size up
1254 * to 64 bits.
1255 */
1256static bool increase_address_space(struct protection_domain *domain,
1257 gfp_t gfp)
1258{
1259 u64 *pte;
1260
1261 if (domain->mode == PAGE_MODE_6_LEVEL)
1262 /* address space already 64 bit large */
1263 return false;
1264
1265 pte = (void *)get_zeroed_page(gfp);
1266 if (!pte)
1267 return false;
1268
1269 *pte = PM_LEVEL_PDE(domain->mode,
1270 virt_to_phys(domain->pt_root));
1271 domain->pt_root = pte;
1272 domain->mode += 1;
1273 domain->updated = true;
1274
1275 return true;
1276}
1277
1278static u64 *alloc_pte(struct protection_domain *domain,
1279 unsigned long address,
cbb9d729 1280 unsigned long page_size,
308973d3
JR		 1281 u64 **pte_page,
1282 gfp_t gfp)
1283{
cbb9d729 1284 int level, end_lvl;
308973d3 1285 u64 *pte, *page;
cbb9d729
JR		 1286
1287 BUG_ON(!is_power_of_2(page_size));
308973d3
JR		 1288
1289 while (address > PM_LEVEL_SIZE(domain->mode))
1290 increase_address_space(domain, gfp);
1291
cbb9d729
JR		 1292 level = domain->mode - 1;
1293 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1294 address = PAGE_SIZE_ALIGN(address, page_size);
1295 end_lvl = PAGE_SIZE_LEVEL(page_size);
308973d3
JR		 1296
1297 while (level > end_lvl) {
1298 if (!IOMMU_PTE_PRESENT(*pte)) {
1299 page = (u64 *)get_zeroed_page(gfp);
1300 if (!page)
1301 return NULL;
1302 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1303 }
1304
cbb9d729
JR		 1305 /* No level skipping support yet */
1306 if (PM_PTE_LEVEL(*pte) != level)
1307 return NULL;
1308
308973d3
JR		 1309 level -= 1;
1310
1311 pte = IOMMU_PTE_PAGE(*pte);
1312
1313 if (pte_page && level == end_lvl)
1314 *pte_page = pte;
1315
1316 pte = &pte[PM_LEVEL_INDEX(level, address)];
1317 }
1318
1319 return pte;
1320}
1321
1322/*
1323 * This function checks if there is a PTE for a given dma address. If
1324 * there is one, it returns the pointer to it.
1325 */
24cd7723 1326static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
308973d3
JR		 1327{
1328 int level;
1329 u64 *pte;
1330
24cd7723
JR		 1331 if (address > PM_LEVEL_SIZE(domain->mode))
1332 return NULL;
1333
1334 level = domain->mode - 1;
1335 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
308973d3 1336
24cd7723
JR		 1337 while (level > 0) {
1338
1339 /* Not Present */
308973d3
JR		 1340 if (!IOMMU_PTE_PRESENT(*pte))
1341 return NULL;
1342
24cd7723
JR		 1343 /* Large PTE */
1344 if (PM_PTE_LEVEL(*pte) == 0x07) {
1345 unsigned long pte_mask, __pte;
1346
1347 /*
1348 * If we have a series of large PTEs, make
1349 * sure to return a pointer to the first one.
1350 */
1351 pte_mask = PTE_PAGE_SIZE(*pte);
1352 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1353 __pte = ((unsigned long)pte) & pte_mask;
1354
1355 return (u64 *)__pte;
1356 }
1357
1358 /* No level skipping support yet */
1359 if (PM_PTE_LEVEL(*pte) != level)
1360 return NULL;
1361
308973d3
JR		 1362 level -= 1;
1363
24cd7723 1364 /* Walk to the next level */
308973d3
JR		 1365 pte = IOMMU_PTE_PAGE(*pte);
1366 pte = &pte[PM_LEVEL_INDEX(level, address)];
308973d3
JR		 1367 }
1368
1369 return pte;
1370}
1371
431b2a20
JR		 1372/*
1373 * Generic mapping functions. It maps a physical address into a DMA
1374 * address space. It allocates the page table pages if necessary.
1375 * In the future it can be extended to a generic mapping function
1376 * supporting all features of AMD IOMMU page tables like level skipping
1377 * and full 64 bit address spaces.
1378 */
38e817fe
JR		 1379static int iommu_map_page(struct protection_domain *dom,
1380 unsigned long bus_addr,
1381 unsigned long phys_addr,
abdc5eb3 1382 int prot,
cbb9d729 1383 unsigned long page_size)
bd0e5211 1384{
8bda3092 1385 u64 __pte, *pte;
cbb9d729 1386 int i, count;
abdc5eb3 1387
bad1cac2 1388 if (!(prot & IOMMU_PROT_MASK))
bd0e5211
JR		 1389 return -EINVAL;
1390
cbb9d729
JR		 1391 bus_addr = PAGE_ALIGN(bus_addr);
1392 phys_addr = PAGE_ALIGN(phys_addr);
1393 count = PAGE_SIZE_PTE_COUNT(page_size);
1394 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1395
1396 for (i = 0; i < count; ++i)
1397 if (IOMMU_PTE_PRESENT(pte[i]))
1398 return -EBUSY;
bd0e5211 1399
cbb9d729
JR		 1400 if (page_size > PAGE_SIZE) {
1401 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1402 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1403 } else
1404 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
bd0e5211 1405
bd0e5211
JR		 1406 if (prot & IOMMU_PROT_IR)
1407 __pte |= IOMMU_PTE_IR;
1408 if (prot & IOMMU_PROT_IW)
1409 __pte |= IOMMU_PTE_IW;
1410
cbb9d729
JR		 1411 for (i = 0; i < count; ++i)
1412 pte[i] = __pte;
bd0e5211 1413
04bfdd84
JR		 1414 update_domain(dom);
1415
bd0e5211
JR		 1416 return 0;
1417}
1418
24cd7723
JR		 1419static unsigned long iommu_unmap_page(struct protection_domain *dom,
1420 unsigned long bus_addr,
1421 unsigned long page_size)
eb74ff6c 1422{
24cd7723
JR		 1423 unsigned long long unmap_size, unmapped;
1424 u64 *pte;
1425
1426 BUG_ON(!is_power_of_2(page_size));
1427
1428 unmapped = 0;
eb74ff6c 1429
24cd7723
JR		 1430 while (unmapped < page_size) {
1431
1432 pte = fetch_pte(dom, bus_addr);
1433
1434 if (!pte) {
1435 /*
1436 * No PTE for this address
1437 * move forward in 4kb steps
1438 */
1439 unmap_size = PAGE_SIZE;
1440 } else if (PM_PTE_LEVEL(*pte) == 0) {
1441 /* 4kb PTE found for this address */
1442 unmap_size = PAGE_SIZE;
1443 *pte = 0ULL;
1444 } else {
1445 int count, i;
1446
1447 /* Large PTE found which maps this address */
1448 unmap_size = PTE_PAGE_SIZE(*pte);
60d0ca3c
AW		 1449
1450 /* Only unmap from the first pte in the page */
1451 if ((unmap_size - 1) & bus_addr)
1452 break;
24cd7723
JR		 1453 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1454 for (i = 0; i < count; i++)
1455 pte[i] = 0ULL;
1456 }
1457
1458 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1459 unmapped += unmap_size;
1460 }
1461
60d0ca3c 1462 BUG_ON(unmapped && !is_power_of_2(unmapped));
eb74ff6c 1463
24cd7723 1464 return unmapped;
eb74ff6c 1465}
eb74ff6c 1466
431b2a20
JR		 1467/*
1468 * This function checks if a specific unity mapping entry is needed for
1469 * this specific IOMMU.
1470 */
bd0e5211
JR		 1471static int iommu_for_unity_map(struct amd_iommu *iommu,
1472 struct unity_map_entry *entry)
1473{
1474 u16 bdf, i;
1475
1476 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1477 bdf = amd_iommu_alias_table[i];
1478 if (amd_iommu_rlookup_table[bdf] == iommu)
1479 return 1;
1480 }
1481
1482 return 0;
1483}
1484
431b2a20
JR		 1485/*
1486 * This function actually applies the mapping to the page table of the
1487 * dma_ops domain.
1488 */
bd0e5211
JR		 1489static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1490 struct unity_map_entry *e)
1491{
1492 u64 addr;
1493 int ret;
1494
1495 for (addr = e->address_start; addr < e->address_end;
1496 addr += PAGE_SIZE) {
abdc5eb3 1497 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
cbb9d729 1498 PAGE_SIZE);
bd0e5211
JR		 1499 if (ret)
1500 return ret;
1501 /*
1502 * if unity mapping is in aperture range mark the page
1503 * as allocated in the aperture
1504 */
1505 if (addr < dma_dom->aperture_size)
c3239567 1506 __set_bit(addr >> PAGE_SHIFT,
384de729 1507 dma_dom->aperture[0]->bitmap);
bd0e5211
JR		 1508 }
1509
1510 return 0;
1511}
1512
171e7b37
JR		 1513/*
1514 * Init the unity mappings for a specific IOMMU in the system
1515 *
1516 * Basically iterates over all unity mapping entries and applies them to
1517 * the default domain DMA of that IOMMU if necessary.
1518 */
1519static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1520{
1521 struct unity_map_entry *entry;
1522 int ret;
1523
1524 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1525 if (!iommu_for_unity_map(iommu, entry))
1526 continue;
1527 ret = dma_ops_unity_map(iommu->default_dom, entry);
1528 if (ret)
1529 return ret;
1530 }
1531
1532 return 0;
1533}
1534
431b2a20
JR		 1535/*
1536 * Inits the unity mappings required for a specific device
1537 */
bd0e5211
JR		 1538static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1539 u16 devid)
1540{
1541 struct unity_map_entry *e;
1542 int ret;
1543
1544 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1545 if (!(devid >= e->devid_start && devid <= e->devid_end))
1546 continue;
1547 ret = dma_ops_unity_map(dma_dom, e);
1548 if (ret)
1549 return ret;
1550 }
1551
1552 return 0;
1553}
1554
431b2a20
JR		 1555/****************************************************************************
1556 *
1557 * The next functions belong to the address allocator for the dma_ops
1558 * interface functions. They work like the allocators in the other IOMMU
1559 * drivers. Its basically a bitmap which marks the allocated pages in
1560 * the aperture. Maybe it could be enhanced in the future to a more
1561 * efficient allocator.
1562 *
1563 ****************************************************************************/
d3086444 1564
431b2a20 1565/*
384de729 1566 * The address allocator core functions.
431b2a20
JR		 1567 *
1568 * called with domain->lock held
1569 */
384de729 1570
171e7b37
JR		 1571/*
1572 * Used to reserve address ranges in the aperture (e.g. for exclusion
1573 * ranges.
1574 */
1575static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1576 unsigned long start_page,
1577 unsigned int pages)
1578{
1579 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1580
1581 if (start_page + pages > last_page)
1582 pages = last_page - start_page;
1583
1584 for (i = start_page; i < start_page + pages; ++i) {
1585 int index = i / APERTURE_RANGE_PAGES;
1586 int page = i % APERTURE_RANGE_PAGES;
1587 __set_bit(page, dom->aperture[index]->bitmap);
1588 }
1589}
1590
9cabe89b
JR		 1591/*
1592 * This function is used to add a new aperture range to an existing
1593 * aperture in case of dma_ops domain allocation or address allocation
1594 * failure.
1595 */
576175c2 1596static int alloc_new_range(struct dma_ops_domain *dma_dom,
9cabe89b
JR		 1597 bool populate, gfp_t gfp)
1598{
1599 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
576175c2 1600 struct amd_iommu *iommu;
17f5b569 1601 unsigned long i, old_size;
9cabe89b 1602
f5e9705c
JR		 1603#ifdef CONFIG_IOMMU_STRESS
1604 populate = false;
1605#endif
1606
9cabe89b
JR		 1607 if (index >= APERTURE_MAX_RANGES)
1608 return -ENOMEM;
1609
1610 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1611 if (!dma_dom->aperture[index])
1612 return -ENOMEM;
1613
1614 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1615 if (!dma_dom->aperture[index]->bitmap)
1616 goto out_free;
1617
1618 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1619
1620 if (populate) {
1621 unsigned long address = dma_dom->aperture_size;
1622 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1623 u64 *pte, *pte_page;
1624
1625 for (i = 0; i < num_ptes; ++i) {
cbb9d729 1626 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
9cabe89b
JR		 1627 &pte_page, gfp);
1628 if (!pte)
1629 goto out_free;
1630
1631 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1632
1633 address += APERTURE_RANGE_SIZE / 64;
1634 }
1635 }
1636
17f5b569 1637 old_size = dma_dom->aperture_size;
9cabe89b
JR		 1638 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1639
17f5b569
JR		 1640 /* Reserve address range used for MSI messages */
1641 if (old_size < MSI_ADDR_BASE_LO &&
1642 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1643 unsigned long spage;
1644 int pages;
1645
1646 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1647 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1648
1649 dma_ops_reserve_addresses(dma_dom, spage, pages);
1650 }
1651
b595076a 1652 /* Initialize the exclusion range if necessary */
576175c2
JR		 1653 for_each_iommu(iommu) {
1654 if (iommu->exclusion_start &&
1655 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1656 && iommu->exclusion_start < dma_dom->aperture_size) {
1657 unsigned long startpage;
1658 int pages = iommu_num_pages(iommu->exclusion_start,
1659 iommu->exclusion_length,
1660 PAGE_SIZE);
1661 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1662 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1663 }
00cd122a
JR		 1664 }
1665
1666 /*
1667 * Check for areas already mapped as present in the new aperture
1668 * range and mark those pages as reserved in the allocator. Such
1669 * mappings may already exist as a result of requested unity
1670 * mappings for devices.
1671 */
1672 for (i = dma_dom->aperture[index]->offset;
1673 i < dma_dom->aperture_size;
1674 i += PAGE_SIZE) {
24cd7723 1675 u64 *pte = fetch_pte(&dma_dom->domain, i);
00cd122a
JR		 1676 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1677 continue;
1678
fcd0861d 1679 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
00cd122a
JR		 1680 }
1681
04bfdd84
JR		 1682 update_domain(&dma_dom->domain);
1683
9cabe89b
JR		 1684 return 0;
1685
1686out_free:
04bfdd84
JR		 1687 update_domain(&dma_dom->domain);
1688
9cabe89b
JR		 1689 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1690
1691 kfree(dma_dom->aperture[index]);
1692 dma_dom->aperture[index] = NULL;
1693
1694 return -ENOMEM;
1695}
1696
384de729
JR		 1697static unsigned long dma_ops_area_alloc(struct device *dev,
1698 struct dma_ops_domain *dom,
1699 unsigned int pages,
1700 unsigned long align_mask,
1701 u64 dma_mask,
1702 unsigned long start)
1703{
803b8cb4 1704 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
384de729
JR		 1705 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1706 int i = start >> APERTURE_RANGE_SHIFT;
1707 unsigned long boundary_size;
1708 unsigned long address = -1;
1709 unsigned long limit;
1710
803b8cb4
JR		 1711 next_bit >>= PAGE_SHIFT;
1712
384de729
JR		 1713 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1714 PAGE_SIZE) >> PAGE_SHIFT;
1715
1716 for (;i < max_index; ++i) {
1717 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1718
1719 if (dom->aperture[i]->offset >= dma_mask)
1720 break;
1721
1722 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1723 dma_mask >> PAGE_SHIFT);
1724
1725 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1726 limit, next_bit, pages, 0,
1727 boundary_size, align_mask);
1728 if (address != -1) {
1729 address = dom->aperture[i]->offset +
1730 (address << PAGE_SHIFT);
803b8cb4 1731 dom->next_address = address + (pages << PAGE_SHIFT);
384de729
JR		 1732 break;
1733 }
1734
1735 next_bit = 0;
1736 }
1737
1738 return address;
1739}
1740
d3086444
JR		 1741static unsigned long dma_ops_alloc_addresses(struct device *dev,
1742 struct dma_ops_domain *dom,
6d4f343f 1743 unsigned int pages,
832a90c3
JR		 1744 unsigned long align_mask,
1745 u64 dma_mask)
d3086444 1746{
d3086444 1747 unsigned long address;
d3086444 1748
fe16f088
JR		 1749#ifdef CONFIG_IOMMU_STRESS
1750 dom->next_address = 0;
1751 dom->need_flush = true;
1752#endif
d3086444 1753
384de729 1754 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
803b8cb4 1755 dma_mask, dom->next_address);
d3086444 1756
1c655773 1757 if (address == -1) {
803b8cb4 1758 dom->next_address = 0;
384de729
JR		 1759 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1760 dma_mask, 0);
1c655773
JR		 1761 dom->need_flush = true;
1762 }
d3086444 1763
384de729 1764 if (unlikely(address == -1))
8fd524b3 1765 address = DMA_ERROR_CODE;
d3086444
JR		 1766
1767 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1768
1769 return address;
1770}
1771
431b2a20
JR		 1772/*
1773 * The address free function.
1774 *
1775 * called with domain->lock held
1776 */
d3086444
JR		 1777static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1778 unsigned long address,
1779 unsigned int pages)
1780{
384de729
JR		 1781 unsigned i = address >> APERTURE_RANGE_SHIFT;
1782 struct aperture_range *range = dom->aperture[i];
80be308d 1783
384de729
JR		 1784 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1785
47bccd6b
JR		 1786#ifdef CONFIG_IOMMU_STRESS
1787 if (i < 4)
1788 return;
1789#endif
80be308d 1790
803b8cb4 1791 if (address >= dom->next_address)
80be308d 1792 dom->need_flush = true;
384de729
JR		 1793
1794 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
803b8cb4 1795
a66022c4 1796 bitmap_clear(range->bitmap, address, pages);
384de729 1797
d3086444
JR		 1798}
1799
431b2a20
JR		 1800/****************************************************************************
1801 *
1802 * The next functions belong to the domain allocation. A domain is
1803 * allocated for every IOMMU as the default domain. If device isolation
1804 * is enabled, every device get its own domain. The most important thing
1805 * about domains is the page table mapping the DMA address space they
1806 * contain.
1807 *
1808 ****************************************************************************/
1809
aeb26f55
JR		 1810/*
1811 * This function adds a protection domain to the global protection domain list
1812 */
1813static void add_domain_to_list(struct protection_domain *domain)
1814{
1815 unsigned long flags;
1816
1817 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1818 list_add(&domain->list, &amd_iommu_pd_list);
1819 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1820}
1821
1822/*
1823 * This function removes a protection domain to the global
1824 * protection domain list
1825 */
1826static void del_domain_from_list(struct protection_domain *domain)
1827{
1828 unsigned long flags;
1829
1830 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1831 list_del(&domain->list);
1832 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1833}
1834
ec487d1a
JR		 1835static u16 domain_id_alloc(void)
1836{
1837 unsigned long flags;
1838 int id;
1839
1840 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1841 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1842 BUG_ON(id == 0);
1843 if (id > 0 && id < MAX_DOMAIN_ID)
1844 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1845 else
1846 id = 0;
1847 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1848
1849 return id;
1850}
1851
a2acfb75
JR		 1852static void domain_id_free(int id)
1853{
1854 unsigned long flags;
1855
1856 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1857 if (id > 0 && id < MAX_DOMAIN_ID)
1858 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1859 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1860}
a2acfb75 1861
5c34c403
JR		 1862#define DEFINE_FREE_PT_FN(LVL, FN) \
1863static void free_pt_##LVL (unsigned long __pt) \
1864{ \
1865 unsigned long p; \
1866 u64 *pt; \
1867 int i; \
1868 \
1869 pt = (u64 *)__pt; \
1870 \
1871 for (i = 0; i < 512; ++i) { \
1872 if (!IOMMU_PTE_PRESENT(pt[i])) \
1873 continue; \
1874 \
1875 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1876 FN(p); \
1877 } \
1878 free_page((unsigned long)pt); \
1879}
1880
1881DEFINE_FREE_PT_FN(l2, free_page)
1882DEFINE_FREE_PT_FN(l3, free_pt_l2)
1883DEFINE_FREE_PT_FN(l4, free_pt_l3)
1884DEFINE_FREE_PT_FN(l5, free_pt_l4)
1885DEFINE_FREE_PT_FN(l6, free_pt_l5)
1886
86db2e5d 1887static void free_pagetable(struct protection_domain *domain)
ec487d1a 1888{
5c34c403 1889 unsigned long root = (unsigned long)domain->pt_root;
ec487d1a 1890
5c34c403
JR		 1891 switch (domain->mode) {
1892 case PAGE_MODE_NONE:
1893 break;
1894 case PAGE_MODE_1_LEVEL:
1895 free_page(root);
1896 break;
1897 case PAGE_MODE_2_LEVEL:
1898 free_pt_l2(root);
1899 break;
1900 case PAGE_MODE_3_LEVEL:
1901 free_pt_l3(root);
1902 break;
1903 case PAGE_MODE_4_LEVEL:
1904 free_pt_l4(root);
1905 break;
1906 case PAGE_MODE_5_LEVEL:
1907 free_pt_l5(root);
1908 break;
1909 case PAGE_MODE_6_LEVEL:
1910 free_pt_l6(root);
1911 break;
1912 default:
1913 BUG();
ec487d1a 1914 }
ec487d1a
JR		 1915}
1916
b16137b1
JR		 1917static void free_gcr3_tbl_level1(u64 *tbl)
1918{
1919 u64 *ptr;
1920 int i;
1921
1922 for (i = 0; i < 512; ++i) {
1923 if (!(tbl[i] & GCR3_VALID))
1924 continue;
1925
1926 ptr = __va(tbl[i] & PAGE_MASK);
1927
1928 free_page((unsigned long)ptr);
1929 }
1930}
1931
1932static void free_gcr3_tbl_level2(u64 *tbl)
1933{
1934 u64 *ptr;
1935 int i;
1936
1937 for (i = 0; i < 512; ++i) {
1938 if (!(tbl[i] & GCR3_VALID))
1939 continue;
1940
1941 ptr = __va(tbl[i] & PAGE_MASK);
1942
1943 free_gcr3_tbl_level1(ptr);
1944 }
1945}
1946
52815b75
JR		 1947static void free_gcr3_table(struct protection_domain *domain)
1948{
b16137b1
JR		 1949 if (domain->glx == 2)
1950 free_gcr3_tbl_level2(domain->gcr3_tbl);
1951 else if (domain->glx == 1)
1952 free_gcr3_tbl_level1(domain->gcr3_tbl);
1953 else if (domain->glx != 0)
1954 BUG();
1955
52815b75
JR		 1956 free_page((unsigned long)domain->gcr3_tbl);
1957}
1958
431b2a20
JR		 1959/*
1960 * Free a domain, only used if something went wrong in the
1961 * allocation path and we need to free an already allocated page table
1962 */
ec487d1a
JR		 1963static void dma_ops_domain_free(struct dma_ops_domain *dom)
1964{
384de729
JR		 1965 int i;
1966
ec487d1a
JR		 1967 if (!dom)
1968 return;
1969
aeb26f55
JR		 1970 del_domain_from_list(&dom->domain);
1971
86db2e5d 1972 free_pagetable(&dom->domain);
ec487d1a 1973
384de729
JR		 1974 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1975 if (!dom->aperture[i])
1976 continue;
1977 free_page((unsigned long)dom->aperture[i]->bitmap);
1978 kfree(dom->aperture[i]);
1979 }
ec487d1a
JR		 1980
1981 kfree(dom);
1982}
1983
431b2a20
JR		 1984/*
1985 * Allocates a new protection domain usable for the dma_ops functions.
b595076a 1986 * It also initializes the page table and the address allocator data
431b2a20
JR		 1987 * structures required for the dma_ops interface
1988 */
87a64d52 1989static struct dma_ops_domain *dma_ops_domain_alloc(void)
ec487d1a
JR		 1990{
1991 struct dma_ops_domain *dma_dom;
ec487d1a
JR		 1992
1993 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1994 if (!dma_dom)
1995 return NULL;
1996
1997 spin_lock_init(&dma_dom->domain.lock);
1998
1999 dma_dom->domain.id = domain_id_alloc();
2000 if (dma_dom->domain.id == 0)
2001 goto free_dma_dom;
7c392cbe 2002 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
8f7a017c 2003 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
ec487d1a 2004 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
9fdb19d6 2005 dma_dom->domain.flags = PD_DMA_OPS_MASK;
ec487d1a
JR		 2006 dma_dom->domain.priv = dma_dom;
2007 if (!dma_dom->domain.pt_root)
2008 goto free_dma_dom;
ec487d1a 2009
1c655773 2010 dma_dom->need_flush = false;
bd60b735 2011 dma_dom->target_dev = 0xffff;
1c655773 2012
aeb26f55
JR		 2013 add_domain_to_list(&dma_dom->domain);
2014
576175c2 2015 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
ec487d1a 2016 goto free_dma_dom;
ec487d1a 2017
431b2a20 2018 /*
ec487d1a
JR		 2019 * mark the first page as allocated so we never return 0 as
2020 * a valid dma-address. So we can use 0 as error value
431b2a20 2021 */
384de729 2022 dma_dom->aperture[0]->bitmap[0] = 1;
803b8cb4 2023 dma_dom->next_address = 0;
ec487d1a 2024
ec487d1a
JR		 2025
2026 return dma_dom;
2027
2028free_dma_dom:
2029 dma_ops_domain_free(dma_dom);
2030
2031 return NULL;
2032}
2033
5b28df6f
JR		 2034/*
2035 * little helper function to check whether a given protection domain is a
2036 * dma_ops domain
2037 */
2038static bool dma_ops_domain(struct protection_domain *domain)
2039{
2040 return domain->flags & PD_DMA_OPS_MASK;
2041}
2042
fd7b5535 2043static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
b20ac0d4 2044{
132bd68f 2045 u64 pte_root = 0;
ee6c2868 2046 u64 flags = 0;
863c74eb 2047
132bd68f
JR		 2048 if (domain->mode != PAGE_MODE_NONE)
2049 pte_root = virt_to_phys(domain->pt_root);
2050
38ddf41b
JR		 2051 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2052 << DEV_ENTRY_MODE_SHIFT;
2053 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
b20ac0d4 2054
ee6c2868
JR		 2055 flags = amd_iommu_dev_table[devid].data[1];
2056
fd7b5535
JR		 2057 if (ats)
2058 flags |= DTE_FLAG_IOTLB;
2059
52815b75
JR		 2060 if (domain->flags & PD_IOMMUV2_MASK) {
2061 u64 gcr3 = __pa(domain->gcr3_tbl);
2062 u64 glx = domain->glx;
2063 u64 tmp;
2064
2065 pte_root |= DTE_FLAG_GV;
2066 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2067
2068 /* First mask out possible old values for GCR3 table */
2069 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2070 flags &= ~tmp;
2071
2072 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2073 flags &= ~tmp;
2074
2075 /* Encode GCR3 table into DTE */
2076 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2077 pte_root |= tmp;
2078
2079 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2080 flags |= tmp;
2081
2082 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2083 flags |= tmp;
2084 }
2085
ee6c2868
JR		 2086 flags &= ~(0xffffUL);
2087 flags |= domain->id;
2088
2089 amd_iommu_dev_table[devid].data[1] = flags;
2090 amd_iommu_dev_table[devid].data[0] = pte_root;
15898bbc
JR		 2091}
2092
2093static void clear_dte_entry(u16 devid)
2094{
15898bbc
JR		 2095 /* remove entry from the device table seen by the hardware */
2096 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2097 amd_iommu_dev_table[devid].data[1] = 0;
15898bbc
JR		 2098
2099 amd_iommu_apply_erratum_63(devid);
7f760ddd
JR		 2100}
2101
ec9e79ef
JR		 2102static void do_attach(struct iommu_dev_data *dev_data,
2103 struct protection_domain *domain)
7f760ddd 2104{
7f760ddd 2105 struct amd_iommu *iommu;
ec9e79ef 2106 bool ats;
fd7b5535 2107
ec9e79ef
JR		 2108 iommu = amd_iommu_rlookup_table[dev_data->devid];
2109 ats = dev_data->ats.enabled;
7f760ddd
JR		 2110
2111 /* Update data structures */
2112 dev_data->domain = domain;
2113 list_add(&dev_data->list, &domain->dev_list);
f62dda66 2114 set_dte_entry(dev_data->devid, domain, ats);
7f760ddd
JR		 2115
2116 /* Do reference counting */
2117 domain->dev_iommu[iommu->index] += 1;
2118 domain->dev_cnt += 1;
2119
2120 /* Flush the DTE entry */
6c542047 2121 device_flush_dte(dev_data);
7f760ddd
JR		 2122}
2123
ec9e79ef 2124static void do_detach(struct iommu_dev_data *dev_data)
7f760ddd 2125{
7f760ddd 2126 struct amd_iommu *iommu;
7f760ddd 2127
ec9e79ef 2128 iommu = amd_iommu_rlookup_table[dev_data->devid];
15898bbc
JR		 2129
2130 /* decrease reference counters */
7f760ddd
JR		 2131 dev_data->domain->dev_iommu[iommu->index] -= 1;
2132 dev_data->domain->dev_cnt -= 1;
2133
2134 /* Update data structures */
2135 dev_data->domain = NULL;
2136 list_del(&dev_data->list);
f62dda66 2137 clear_dte_entry(dev_data->devid);
15898bbc 2138
7f760ddd 2139 /* Flush the DTE entry */
6c542047 2140 device_flush_dte(dev_data);
2b681faf
JR		 2141}
2142
2143/*
2144 * If a device is not yet associated with a domain, this function does
2145 * assigns it visible for the hardware
2146 */
ec9e79ef 2147static int __attach_device(struct iommu_dev_data *dev_data,
15898bbc 2148 struct protection_domain *domain)
2b681faf 2149{
397111ab 2150 struct iommu_dev_data *head, *entry;
84fe6c19 2151 int ret;
657cbb6b 2152
2b681faf
JR		 2153 /* lock domain */
2154 spin_lock(&domain->lock);
2155
397111ab 2156 head = dev_data;
15898bbc 2157
397111ab
JR		 2158 if (head->alias_data != NULL)
2159 head = head->alias_data;
eba6ac60 2160
397111ab 2161 /* Now we have the root of the alias group, if any */
15898bbc 2162
397111ab
JR		 2163 ret = -EBUSY;
2164 if (head->domain != NULL)
2165 goto out_unlock;
24100055 2166
397111ab
JR		 2167 /* Attach alias group root */
2168 do_attach(head, domain);
15898bbc 2169
397111ab
JR		 2170 /* Attach other devices in the alias group */
2171 list_for_each_entry(entry, &head->alias_list, alias_list)
2172 do_attach(entry, domain);
24100055 2173
84fe6c19
JL		 2174 ret = 0;
2175
2176out_unlock:
2177
eba6ac60
JR		 2178 /* ready */
2179 spin_unlock(&domain->lock);
15898bbc 2180
84fe6c19 2181 return ret;
0feae533 2182}
b20ac0d4 2183
52815b75
JR		 2184
2185static void pdev_iommuv2_disable(struct pci_dev *pdev)
2186{
2187 pci_disable_ats(pdev);
2188 pci_disable_pri(pdev);
2189 pci_disable_pasid(pdev);
2190}
2191
6a113ddc
JR		 2192/* FIXME: Change generic reset-function to do the same */
2193static int pri_reset_while_enabled(struct pci_dev *pdev)
2194{
2195 u16 control;
2196 int pos;
2197
46277b75 2198 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
6a113ddc
JR		 2199 if (!pos)
2200 return -EINVAL;
2201
46277b75
JR		 2202 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2203 control |= PCI_PRI_CTRL_RESET;
2204 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
6a113ddc
JR		 2205
2206 return 0;
2207}
2208
52815b75
JR		 2209static int pdev_iommuv2_enable(struct pci_dev *pdev)
2210{
6a113ddc
JR		 2211 bool reset_enable;
2212 int reqs, ret;
2213
2214 /* FIXME: Hardcode number of outstanding requests for now */
2215 reqs = 32;
2216 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2217 reqs = 1;
2218 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
52815b75
JR		 2219
2220 /* Only allow access to user-accessible pages */
2221 ret = pci_enable_pasid(pdev, 0);
2222 if (ret)
2223 goto out_err;
2224
2225 /* First reset the PRI state of the device */
2226 ret = pci_reset_pri(pdev);
2227 if (ret)
2228 goto out_err;
2229
6a113ddc
JR		 2230 /* Enable PRI */
2231 ret = pci_enable_pri(pdev, reqs);
52815b75
JR		 2232 if (ret)
2233 goto out_err;
2234
6a113ddc
JR		 2235 if (reset_enable) {
2236 ret = pri_reset_while_enabled(pdev);
2237 if (ret)
2238 goto out_err;
2239 }
2240
52815b75
JR		 2241 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2242 if (ret)
2243 goto out_err;
2244
2245 return 0;
2246
2247out_err:
2248 pci_disable_pri(pdev);
2249 pci_disable_pasid(pdev);
2250
2251 return ret;
2252}
2253
c99afa25 2254/* FIXME: Move this to PCI code */
a3b93121 2255#define PCI_PRI_TLP_OFF (1 << 15)
c99afa25 2256
98f1ad25 2257static bool pci_pri_tlp_required(struct pci_dev *pdev)
c99afa25 2258{
a3b93121 2259 u16 status;
c99afa25
JR		 2260 int pos;
2261
46277b75 2262 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c99afa25
JR		 2263 if (!pos)
2264 return false;
2265
a3b93121 2266 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
c99afa25 2267
a3b93121 2268 return (status & PCI_PRI_TLP_OFF) ? true : false;
c99afa25
JR		 2269}
2270
407d733e 2271/*
df805abb 2272 * If a device is not yet associated with a domain, this function
407d733e
JR		 2273 * assigns it visible for the hardware
2274 */
15898bbc
JR		 2275static int attach_device(struct device *dev,
2276 struct protection_domain *domain)
0feae533 2277{
fd7b5535 2278 struct pci_dev *pdev = to_pci_dev(dev);
ea61cddb 2279 struct iommu_dev_data *dev_data;
eba6ac60 2280 unsigned long flags;
15898bbc 2281 int ret;
eba6ac60 2282
ea61cddb
JR		 2283 dev_data = get_dev_data(dev);
2284
52815b75
JR		 2285 if (domain->flags & PD_IOMMUV2_MASK) {
2286 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2287 return -EINVAL;
2288
2289 if (pdev_iommuv2_enable(pdev) != 0)
2290 return -EINVAL;
2291
2292 dev_data->ats.enabled = true;
2293 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
c99afa25 2294 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
52815b75
JR		 2295 } else if (amd_iommu_iotlb_sup &&
2296 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
ea61cddb
JR		 2297 dev_data->ats.enabled = true;
2298 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2299 }
fd7b5535 2300
eba6ac60 2301 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2302 ret = __attach_device(dev_data, domain);
b20ac0d4
JR		 2303 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2304
0feae533
JR		 2305 /*
2306 * We might boot into a crash-kernel here. The crashed kernel
2307 * left the caches in the IOMMU dirty. So we have to flush
2308 * here to evict all dirty stuff.
2309 */
17b124bf 2310 domain_flush_tlb_pde(domain);
15898bbc
JR		 2311
2312 return ret;
b20ac0d4
JR		 2313}
2314
355bf553
JR		 2315/*
2316 * Removes a device from a protection domain (unlocked)
2317 */
ec9e79ef 2318static void __detach_device(struct iommu_dev_data *dev_data)
355bf553 2319{
397111ab 2320 struct iommu_dev_data *head, *entry;
2ca76279 2321 struct protection_domain *domain;
7c392cbe 2322 unsigned long flags;
c4596114 2323
7f760ddd 2324 BUG_ON(!dev_data->domain);
355bf553 2325
2ca76279
JR		 2326 domain = dev_data->domain;
2327
2328 spin_lock_irqsave(&domain->lock, flags);
24100055 2329
397111ab
JR		 2330 head = dev_data;
2331 if (head->alias_data != NULL)
2332 head = head->alias_data;
71f77580 2333
397111ab
JR		 2334 list_for_each_entry(entry, &head->alias_list, alias_list)
2335 do_detach(entry);
24100055 2336
397111ab 2337 do_detach(head);
7f760ddd 2338
2ca76279 2339 spin_unlock_irqrestore(&domain->lock, flags);
21129f78
JR		 2340
2341 /*
2342 * If we run in passthrough mode the device must be assigned to the
d3ad9373
JR		 2343 * passthrough domain if it is detached from any other domain.
2344 * Make sure we can deassign from the pt_domain itself.
21129f78 2345 */
5abcdba4 2346 if (dev_data->passthrough &&
d3ad9373 2347 (dev_data->domain == NULL && domain != pt_domain))
ec9e79ef 2348 __attach_device(dev_data, pt_domain);
355bf553
JR		 2349}
2350
2351/*
2352 * Removes a device from a protection domain (with devtable_lock held)
2353 */
15898bbc 2354static void detach_device(struct device *dev)
355bf553 2355{
52815b75 2356 struct protection_domain *domain;
ea61cddb 2357 struct iommu_dev_data *dev_data;
355bf553
JR		 2358 unsigned long flags;
2359
ec9e79ef 2360 dev_data = get_dev_data(dev);
52815b75 2361 domain = dev_data->domain;
ec9e79ef 2362
355bf553
JR		 2363 /* lock device table */
2364 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2365 __detach_device(dev_data);
355bf553 2366 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
fd7b5535 2367
52815b75
JR		 2368 if (domain->flags & PD_IOMMUV2_MASK)
2369 pdev_iommuv2_disable(to_pci_dev(dev));
2370 else if (dev_data->ats.enabled)
ea61cddb 2371 pci_disable_ats(to_pci_dev(dev));
52815b75
JR		 2372
2373 dev_data->ats.enabled = false;
355bf553 2374}
e275a2a0 2375
15898bbc
JR		 2376/*
2377 * Find out the protection domain structure for a given PCI device. This
2378 * will give us the pointer to the page table root for example.
2379 */
2380static struct protection_domain *domain_for_device(struct device *dev)
2381{
71f77580 2382 struct iommu_dev_data *dev_data;
2b02b091 2383 struct protection_domain *dom = NULL;
15898bbc 2384 unsigned long flags;
15898bbc 2385
657cbb6b 2386 dev_data = get_dev_data(dev);
15898bbc 2387
2b02b091
JR		 2388 if (dev_data->domain)
2389 return dev_data->domain;
15898bbc 2390
71f77580
JR		 2391 if (dev_data->alias_data != NULL) {
2392 struct iommu_dev_data *alias_data = dev_data->alias_data;
2b02b091
JR		 2393
2394 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2395 if (alias_data->domain != NULL) {
2396 __attach_device(dev_data, alias_data->domain);
2397 dom = alias_data->domain;
2398 }
2399 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2400 }
15898bbc
JR		 2401
2402 return dom;
2403}
2404
e275a2a0
JR		 2405static int device_change_notifier(struct notifier_block *nb,
2406 unsigned long action, void *data)
2407{
e275a2a0 2408 struct dma_ops_domain *dma_domain;
5abcdba4
JR		 2409 struct protection_domain *domain;
2410 struct iommu_dev_data *dev_data;
2411 struct device *dev = data;
e275a2a0 2412 struct amd_iommu *iommu;
1ac4cbbc 2413 unsigned long flags;
5abcdba4 2414 u16 devid;
e275a2a0 2415
98fc5a69
JR		 2416 if (!check_device(dev))
2417 return 0;
e275a2a0 2418
5abcdba4
JR		 2419 devid = get_device_id(dev);
2420 iommu = amd_iommu_rlookup_table[devid];
2421 dev_data = get_dev_data(dev);
e275a2a0
JR		 2422
2423 switch (action) {
c1eee67b 2424 case BUS_NOTIFY_UNBOUND_DRIVER:
657cbb6b
JR		 2425
2426 domain = domain_for_device(dev);
2427
e275a2a0
JR		 2428 if (!domain)
2429 goto out;
5abcdba4 2430 if (dev_data->passthrough)
a1ca331c 2431 break;
15898bbc 2432 detach_device(dev);
1ac4cbbc
JR		 2433 break;
2434 case BUS_NOTIFY_ADD_DEVICE:
657cbb6b
JR		 2435
2436 iommu_init_device(dev);
2437
2c9195e9
JR		 2438 /*
2439 * dev_data is still NULL and
2440 * got initialized in iommu_init_device
2441 */
2442 dev_data = get_dev_data(dev);
2443
2444 if (iommu_pass_through || dev_data->iommu_v2) {
2445 dev_data->passthrough = true;
2446 attach_device(dev, pt_domain);
2447 break;
2448 }
2449
657cbb6b
JR		 2450 domain = domain_for_device(dev);
2451
1ac4cbbc
JR		 2452 /* allocate a protection domain if a device is added */
2453 dma_domain = find_protection_domain(devid);
c2a2876e
JR		 2454 if (!dma_domain) {
2455 dma_domain = dma_ops_domain_alloc();
2456 if (!dma_domain)
2457 goto out;
2458 dma_domain->target_dev = devid;
2459
2460 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2461 list_add_tail(&dma_domain->list, &iommu_pd_list);
2462 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2463 }
ac1534a5 2464
2c9195e9 2465 dev->archdata.dma_ops = &amd_iommu_dma_ops;
ac1534a5 2466
e275a2a0 2467 break;
657cbb6b
JR		 2468 case BUS_NOTIFY_DEL_DEVICE:
2469
2470 iommu_uninit_device(dev);
2471
e275a2a0
JR		 2472 default:
2473 goto out;
2474 }
2475
e275a2a0
JR		 2476 iommu_completion_wait(iommu);
2477
2478out:
2479 return 0;
2480}
2481
b25ae679 2482static struct notifier_block device_nb = {
e275a2a0
JR		 2483 .notifier_call = device_change_notifier,
2484};
355bf553 2485
8638c491
JR		 2486void amd_iommu_init_notifier(void)
2487{
2488 bus_register_notifier(&pci_bus_type, &device_nb);
2489}
2490
431b2a20
JR		 2491/*****************************************************************************
2492 *
2493 * The next functions belong to the dma_ops mapping/unmapping code.
2494 *
2495 *****************************************************************************/
2496
2497/*
2498 * In the dma_ops path we only have the struct device. This function
2499 * finds the corresponding IOMMU, the protection domain and the
2500 * requestor id for a given device.
2501 * If the device is not yet associated with a domain this is also done
2502 * in this function.
2503 */
94f6d190 2504static struct protection_domain *get_domain(struct device *dev)
b20ac0d4 2505{
94f6d190 2506 struct protection_domain *domain;
b20ac0d4 2507 struct dma_ops_domain *dma_dom;
94f6d190 2508 u16 devid = get_device_id(dev);
b20ac0d4 2509
f99c0f1c 2510 if (!check_device(dev))
94f6d190 2511 return ERR_PTR(-EINVAL);
b20ac0d4 2512
94f6d190
JR		 2513 domain = domain_for_device(dev);
2514 if (domain != NULL && !dma_ops_domain(domain))
2515 return ERR_PTR(-EBUSY);
f99c0f1c 2516
94f6d190
JR		 2517 if (domain != NULL)
2518 return domain;
b20ac0d4 2519
df805abb 2520 /* Device not bound yet - bind it */
94f6d190 2521 dma_dom = find_protection_domain(devid);
15898bbc 2522 if (!dma_dom)
94f6d190
JR		 2523 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2524 attach_device(dev, &dma_dom->domain);
15898bbc 2525 DUMP_printk("Using protection domain %d for device %s\n",
94f6d190 2526 dma_dom->domain.id, dev_name(dev));
f91ba190 2527
94f6d190 2528 return &dma_dom->domain;
b20ac0d4
JR		 2529}
2530
04bfdd84
JR		 2531static void update_device_table(struct protection_domain *domain)
2532{
492667da 2533 struct iommu_dev_data *dev_data;
04bfdd84 2534
ea61cddb
JR		 2535 list_for_each_entry(dev_data, &domain->dev_list, list)
2536 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
04bfdd84
JR		 2537}
2538
2539static void update_domain(struct protection_domain *domain)
2540{
2541 if (!domain->updated)
2542 return;
2543
2544 update_device_table(domain);
17b124bf
JR		 2545
2546 domain_flush_devices(domain);
2547 domain_flush_tlb_pde(domain);
04bfdd84
JR		 2548
2549 domain->updated = false;
2550}
2551
8bda3092
JR		 2552/*
2553 * This function fetches the PTE for a given address in the aperture
2554 */
2555static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2556 unsigned long address)
2557{
384de729 2558 struct aperture_range *aperture;
8bda3092
JR		 2559 u64 *pte, *pte_page;
2560
384de729
JR		 2561 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2562 if (!aperture)
2563 return NULL;
2564
2565 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
8bda3092 2566 if (!pte) {
cbb9d729 2567 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
abdc5eb3 2568 GFP_ATOMIC);
384de729
JR		 2569 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2570 } else
8c8c143c 2571 pte += PM_LEVEL_INDEX(0, address);
8bda3092 2572
04bfdd84 2573 update_domain(&dom->domain);
8bda3092
JR		 2574
2575 return pte;
2576}
2577
431b2a20
JR		 2578/*
2579 * This is the generic map function. It maps one 4kb page at paddr to
2580 * the given address in the DMA address space for the domain.
2581 */
680525e0 2582static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
cb76c322
JR		 2583 unsigned long address,
2584 phys_addr_t paddr,
2585 int direction)
2586{
2587 u64 *pte, __pte;
2588
2589 WARN_ON(address > dom->aperture_size);
2590
2591 paddr &= PAGE_MASK;
2592
8bda3092 2593 pte = dma_ops_get_pte(dom, address);
53812c11 2594 if (!pte)
8fd524b3 2595 return DMA_ERROR_CODE;
cb76c322
JR		 2596
2597 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2598
2599 if (direction == DMA_TO_DEVICE)
2600 __pte |= IOMMU_PTE_IR;
2601 else if (direction == DMA_FROM_DEVICE)
2602 __pte |= IOMMU_PTE_IW;
2603 else if (direction == DMA_BIDIRECTIONAL)
2604 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2605
2606 WARN_ON(*pte);
2607
2608 *pte = __pte;
2609
2610 return (dma_addr_t)address;
2611}
2612
431b2a20
JR		 2613/*
2614 * The generic unmapping function for on page in the DMA address space.
2615 */
680525e0 2616static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
cb76c322
JR		 2617 unsigned long address)
2618{
384de729 2619 struct aperture_range *aperture;
cb76c322
JR		 2620 u64 *pte;
2621
2622 if (address >= dom->aperture_size)
2623 return;
2624
384de729
JR		 2625 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2626 if (!aperture)
2627 return;
2628
2629 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2630 if (!pte)
2631 return;
cb76c322 2632
8c8c143c 2633 pte += PM_LEVEL_INDEX(0, address);
cb76c322
JR		 2634
2635 WARN_ON(!*pte);
2636
2637 *pte = 0ULL;
2638}
2639
431b2a20
JR		 2640/*
2641 * This function contains common code for mapping of a physically
24f81160
JR		 2642 * contiguous memory region into DMA address space. It is used by all
2643 * mapping functions provided with this IOMMU driver.
431b2a20
JR		 2644 * Must be called with the domain lock held.
2645 */
cb76c322 2646static dma_addr_t __map_single(struct device *dev,
cb76c322
JR		 2647 struct dma_ops_domain *dma_dom,
2648 phys_addr_t paddr,
2649 size_t size,
6d4f343f 2650 int dir,
832a90c3
JR		 2651 bool align,
2652 u64 dma_mask)
cb76c322
JR		 2653{
2654 dma_addr_t offset = paddr & ~PAGE_MASK;
53812c11 2655 dma_addr_t address, start, ret;
cb76c322 2656 unsigned int pages;
6d4f343f 2657 unsigned long align_mask = 0;
cb76c322
JR		 2658 int i;
2659
e3c449f5 2660 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
cb76c322
JR		 2661 paddr &= PAGE_MASK;
2662
8ecaf8f1
JR		 2663 INC_STATS_COUNTER(total_map_requests);
2664
c1858976
JR		 2665 if (pages > 1)
2666 INC_STATS_COUNTER(cross_page);
2667
6d4f343f
JR		 2668 if (align)
2669 align_mask = (1UL << get_order(size)) - 1;
2670
11b83888 2671retry:
832a90c3
JR		 2672 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2673 dma_mask);
8fd524b3 2674 if (unlikely(address == DMA_ERROR_CODE)) {
11b83888
JR		 2675 /*
2676 * setting next_address here will let the address
2677 * allocator only scan the new allocated range in the
2678 * first run. This is a small optimization.
2679 */
2680 dma_dom->next_address = dma_dom->aperture_size;
2681
576175c2 2682 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
11b83888
JR		 2683 goto out;
2684
2685 /*
af901ca1 2686 * aperture was successfully enlarged by 128 MB, try
11b83888
JR		 2687 * allocation again
2688 */
2689 goto retry;
2690 }
cb76c322
JR		 2691
2692 start = address;
2693 for (i = 0; i < pages; ++i) {
680525e0 2694 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
8fd524b3 2695 if (ret == DMA_ERROR_CODE)
53812c11
JR		 2696 goto out_unmap;
2697
cb76c322
JR		 2698 paddr += PAGE_SIZE;
2699 start += PAGE_SIZE;
2700 }
2701 address += offset;
2702
5774f7c5
JR		 2703 ADD_STATS_COUNTER(alloced_io_mem, size);
2704
afa9fdc2 2705 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
17b124bf 2706 domain_flush_tlb(&dma_dom->domain);
1c655773 2707 dma_dom->need_flush = false;
318afd41 2708 } else if (unlikely(amd_iommu_np_cache))
17b124bf 2709 domain_flush_pages(&dma_dom->domain, address, size);
270cab24 2710
cb76c322
JR		 2711out:
2712 return address;
53812c11
JR		 2713
2714out_unmap:
2715
2716 for (--i; i >= 0; --i) {
2717 start -= PAGE_SIZE;
680525e0 2718 dma_ops_domain_unmap(dma_dom, start);
53812c11
JR		 2719 }
2720
2721 dma_ops_free_addresses(dma_dom, address, pages);
2722
8fd524b3 2723 return DMA_ERROR_CODE;
cb76c322
JR		 2724}
2725
431b2a20
JR		 2726/*
2727 * Does the reverse of the __map_single function. Must be called with
2728 * the domain lock held too
2729 */
cd8c82e8 2730static void __unmap_single(struct dma_ops_domain *dma_dom,
cb76c322
JR		 2731 dma_addr_t dma_addr,
2732 size_t size,
2733 int dir)
2734{
04e0463e 2735 dma_addr_t flush_addr;
cb76c322
JR		 2736 dma_addr_t i, start;
2737 unsigned int pages;
2738
8fd524b3 2739 if ((dma_addr == DMA_ERROR_CODE) ||
b8d9905d 2740 (dma_addr + size > dma_dom->aperture_size))
cb76c322
JR		 2741 return;
2742
04e0463e 2743 flush_addr = dma_addr;
e3c449f5 2744 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
cb76c322
JR		 2745 dma_addr &= PAGE_MASK;
2746 start = dma_addr;
2747
2748 for (i = 0; i < pages; ++i) {
680525e0 2749 dma_ops_domain_unmap(dma_dom, start);
cb76c322
JR		 2750 start += PAGE_SIZE;
2751 }
2752
5774f7c5
JR		 2753 SUB_STATS_COUNTER(alloced_io_mem, size);
2754
cb76c322 2755 dma_ops_free_addresses(dma_dom, dma_addr, pages);
270cab24 2756
80be308d 2757 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
17b124bf 2758 domain_flush_pages(&dma_dom->domain, flush_addr, size);
80be308d
JR		 2759 dma_dom->need_flush = false;
2760 }
cb76c322
JR		 2761}
2762
431b2a20
JR		 2763/*
2764 * The exported map_single function for dma_ops.
2765 */
51491367
FT		 2766static dma_addr_t map_page(struct device *dev, struct page *page,
2767 unsigned long offset, size_t size,
2768 enum dma_data_direction dir,
2769 struct dma_attrs *attrs)
4da70b9e
JR		 2770{
2771 unsigned long flags;
4da70b9e 2772 struct protection_domain *domain;
4da70b9e 2773 dma_addr_t addr;
832a90c3 2774 u64 dma_mask;
51491367 2775 phys_addr_t paddr = page_to_phys(page) + offset;
4da70b9e 2776
0f2a86f2
JR		 2777 INC_STATS_COUNTER(cnt_map_single);
2778
94f6d190
JR		 2779 domain = get_domain(dev);
2780 if (PTR_ERR(domain) == -EINVAL)
4da70b9e 2781 return (dma_addr_t)paddr;
94f6d190
JR		 2782 else if (IS_ERR(domain))
2783 return DMA_ERROR_CODE;
4da70b9e 2784
f99c0f1c
JR		 2785 dma_mask = *dev->dma_mask;
2786
4da70b9e 2787 spin_lock_irqsave(&domain->lock, flags);
94f6d190 2788
cd8c82e8 2789 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
832a90c3 2790 dma_mask);
8fd524b3 2791 if (addr == DMA_ERROR_CODE)
4da70b9e
JR		 2792 goto out;
2793
17b124bf 2794 domain_flush_complete(domain);
4da70b9e
JR		 2795
2796out:
2797 spin_unlock_irqrestore(&domain->lock, flags);
2798
2799 return addr;
2800}
2801
431b2a20
JR		 2802/*
2803 * The exported unmap_single function for dma_ops.
2804 */
51491367
FT		 2805static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2806 enum dma_data_direction dir, struct dma_attrs *attrs)
4da70b9e
JR		 2807{
2808 unsigned long flags;
4da70b9e 2809 struct protection_domain *domain;
4da70b9e 2810
146a6917
JR		 2811 INC_STATS_COUNTER(cnt_unmap_single);
2812
94f6d190
JR		 2813 domain = get_domain(dev);
2814 if (IS_ERR(domain))
5b28df6f
JR		 2815 return;
2816
4da70b9e
JR		 2817 spin_lock_irqsave(&domain->lock, flags);
2818
cd8c82e8 2819 __unmap_single(domain->priv, dma_addr, size, dir);
4da70b9e 2820
17b124bf 2821 domain_flush_complete(domain);
4da70b9e
JR		 2822
2823 spin_unlock_irqrestore(&domain->lock, flags);
2824}
2825
431b2a20
JR		 2826/*
2827 * The exported map_sg function for dma_ops (handles scatter-gather
2828 * lists).
2829 */
65b050ad 2830static int map_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2831 int nelems, enum dma_data_direction dir,
2832 struct dma_attrs *attrs)
65b050ad
JR		 2833{
2834 unsigned long flags;
65b050ad 2835 struct protection_domain *domain;
65b050ad
JR		 2836 int i;
2837 struct scatterlist *s;
2838 phys_addr_t paddr;
2839 int mapped_elems = 0;
832a90c3 2840 u64 dma_mask;
65b050ad 2841
d03f067a
JR		 2842 INC_STATS_COUNTER(cnt_map_sg);
2843
94f6d190 2844 domain = get_domain(dev);
a0e191b2 2845 if (IS_ERR(domain))
94f6d190 2846 return 0;
dbcc112e 2847
832a90c3 2848 dma_mask = *dev->dma_mask;
65b050ad 2849
65b050ad
JR		 2850 spin_lock_irqsave(&domain->lock, flags);
2851
2852 for_each_sg(sglist, s, nelems, i) {
2853 paddr = sg_phys(s);
2854
cd8c82e8 2855 s->dma_address = __map_single(dev, domain->priv,
832a90c3
JR		 2856 paddr, s->length, dir, false,
2857 dma_mask);
65b050ad
JR		 2858
2859 if (s->dma_address) {
2860 s->dma_length = s->length;
2861 mapped_elems++;
2862 } else
2863 goto unmap;
65b050ad
JR		 2864 }
2865
17b124bf 2866 domain_flush_complete(domain);
65b050ad
JR		 2867
2868out:
2869 spin_unlock_irqrestore(&domain->lock, flags);
2870
2871 return mapped_elems;
2872unmap:
2873 for_each_sg(sglist, s, mapped_elems, i) {
2874 if (s->dma_address)
cd8c82e8 2875 __unmap_single(domain->priv, s->dma_address,
65b050ad
JR		 2876 s->dma_length, dir);
2877 s->dma_address = s->dma_length = 0;
2878 }
2879
2880 mapped_elems = 0;
2881
2882 goto out;
2883}
2884
431b2a20
JR		 2885/*
2886 * The exported map_sg function for dma_ops (handles scatter-gather
2887 * lists).
2888 */
65b050ad 2889static void unmap_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2890 int nelems, enum dma_data_direction dir,
2891 struct dma_attrs *attrs)
65b050ad
JR		 2892{
2893 unsigned long flags;
65b050ad
JR		 2894 struct protection_domain *domain;
2895 struct scatterlist *s;
65b050ad
JR		 2896 int i;
2897
55877a6b
JR		 2898 INC_STATS_COUNTER(cnt_unmap_sg);
2899
94f6d190
JR		 2900 domain = get_domain(dev);
2901 if (IS_ERR(domain))
5b28df6f
JR		 2902 return;
2903
65b050ad
JR		 2904 spin_lock_irqsave(&domain->lock, flags);
2905
2906 for_each_sg(sglist, s, nelems, i) {
cd8c82e8 2907 __unmap_single(domain->priv, s->dma_address,
65b050ad 2908 s->dma_length, dir);
65b050ad
JR		 2909 s->dma_address = s->dma_length = 0;
2910 }
2911
17b124bf 2912 domain_flush_complete(domain);
65b050ad
JR		 2913
2914 spin_unlock_irqrestore(&domain->lock, flags);
2915}
2916
431b2a20
JR		 2917/*
2918 * The exported alloc_coherent function for dma_ops.
2919 */
5d8b53cf 2920static void *alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 2921 dma_addr_t *dma_addr, gfp_t flag,
2922 struct dma_attrs *attrs)
5d8b53cf
JR		 2923{
2924 unsigned long flags;
2925 void *virt_addr;
5d8b53cf 2926 struct protection_domain *domain;
5d8b53cf 2927 phys_addr_t paddr;
832a90c3 2928 u64 dma_mask = dev->coherent_dma_mask;
5d8b53cf 2929
c8f0fb36
JR		 2930 INC_STATS_COUNTER(cnt_alloc_coherent);
2931
94f6d190
JR		 2932 domain = get_domain(dev);
2933 if (PTR_ERR(domain) == -EINVAL) {
f99c0f1c
JR		 2934 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2935 *dma_addr = __pa(virt_addr);
2936 return virt_addr;
94f6d190
JR		 2937 } else if (IS_ERR(domain))
2938 return NULL;
5d8b53cf 2939
f99c0f1c
JR		 2940 dma_mask = dev->coherent_dma_mask;
2941 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2942 flag |= __GFP_ZERO;
5d8b53cf
JR		 2943
2944 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2945 if (!virt_addr)
b25ae679 2946 return NULL;
5d8b53cf 2947
5d8b53cf
JR		 2948 paddr = virt_to_phys(virt_addr);
2949
832a90c3
JR		 2950 if (!dma_mask)
2951 dma_mask = *dev->dma_mask;
2952
5d8b53cf
JR		 2953 spin_lock_irqsave(&domain->lock, flags);
2954
cd8c82e8 2955 *dma_addr = __map_single(dev, domain->priv, paddr,
832a90c3 2956 size, DMA_BIDIRECTIONAL, true, dma_mask);
5d8b53cf 2957
8fd524b3 2958 if (*dma_addr == DMA_ERROR_CODE) {
367d04c4 2959 spin_unlock_irqrestore(&domain->lock, flags);
5b28df6f 2960 goto out_free;
367d04c4 2961 }
5d8b53cf 2962
17b124bf 2963 domain_flush_complete(domain);
5d8b53cf 2964
5d8b53cf
JR		 2965 spin_unlock_irqrestore(&domain->lock, flags);
2966
2967 return virt_addr;
5b28df6f
JR		 2968
2969out_free:
2970
2971 free_pages((unsigned long)virt_addr, get_order(size));
2972
2973 return NULL;
5d8b53cf
JR		 2974}
2975
431b2a20
JR		 2976/*
2977 * The exported free_coherent function for dma_ops.
431b2a20 2978 */
5d8b53cf 2979static void free_coherent(struct device *dev, size_t size,
baa676fc
AP		 2980 void *virt_addr, dma_addr_t dma_addr,
2981 struct dma_attrs *attrs)
5d8b53cf
JR		 2982{
2983 unsigned long flags;
5d8b53cf 2984 struct protection_domain *domain;
5d8b53cf 2985
5d31ee7e
JR		 2986 INC_STATS_COUNTER(cnt_free_coherent);
2987
94f6d190
JR		 2988 domain = get_domain(dev);
2989 if (IS_ERR(domain))
5b28df6f
JR		 2990 goto free_mem;
2991
5d8b53cf
JR		 2992 spin_lock_irqsave(&domain->lock, flags);
2993
cd8c82e8 2994 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
5d8b53cf 2995
17b124bf 2996 domain_flush_complete(domain);
5d8b53cf
JR		 2997
2998 spin_unlock_irqrestore(&domain->lock, flags);
2999
3000free_mem:
3001 free_pages((unsigned long)virt_addr, get_order(size));
3002}
3003
b39ba6ad
JR		 3004/*
3005 * This function is called by the DMA layer to find out if we can handle a
3006 * particular device. It is part of the dma_ops.
3007 */
3008static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3009{
420aef8a 3010 return check_device(dev);
b39ba6ad
JR		 3011}
3012
c432f3df 3013/*
431b2a20
JR		 3014 * The function for pre-allocating protection domains.
3015 *
c432f3df
JR		 3016 * If the driver core informs the DMA layer if a driver grabs a device
3017 * we don't need to preallocate the protection domains anymore.
3018 * For now we have to.
3019 */
943bc7e1 3020static void __init prealloc_protection_domains(void)
c432f3df 3021{
5abcdba4 3022 struct iommu_dev_data *dev_data;
c432f3df 3023 struct dma_ops_domain *dma_dom;
5abcdba4 3024 struct pci_dev *dev = NULL;
98fc5a69 3025 u16 devid;
c432f3df 3026
d18c69d3 3027 for_each_pci_dev(dev) {
98fc5a69
JR		 3028
3029 /* Do we handle this device? */
3030 if (!check_device(&dev->dev))
c432f3df 3031 continue;
98fc5a69 3032
5abcdba4
JR		 3033 dev_data = get_dev_data(&dev->dev);
3034 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3035 /* Make sure passthrough domain is allocated */
3036 alloc_passthrough_domain();
3037 dev_data->passthrough = true;
3038 attach_device(&dev->dev, pt_domain);
df805abb 3039 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
5abcdba4
JR		 3040 dev_name(&dev->dev));
3041 }
3042
98fc5a69 3043 /* Is there already any domain for it? */
15898bbc 3044 if (domain_for_device(&dev->dev))
c432f3df 3045 continue;
98fc5a69
JR		 3046
3047 devid = get_device_id(&dev->dev);
3048
87a64d52 3049 dma_dom = dma_ops_domain_alloc();
c432f3df
JR		 3050 if (!dma_dom)
3051 continue;
3052 init_unity_mappings_for_device(dma_dom, devid);
bd60b735
JR		 3053 dma_dom->target_dev = devid;
3054
15898bbc 3055 attach_device(&dev->dev, &dma_dom->domain);
be831297 3056
bd60b735 3057 list_add_tail(&dma_dom->list, &iommu_pd_list);
c432f3df
JR		 3058 }
3059}
3060
160c1d8e 3061static struct dma_map_ops amd_iommu_dma_ops = {
baa676fc
AP		 3062 .alloc = alloc_coherent,
3063 .free = free_coherent,
51491367
FT		 3064 .map_page = map_page,
3065 .unmap_page = unmap_page,
6631ee9d
JR		 3066 .map_sg = map_sg,
3067 .unmap_sg = unmap_sg,
b39ba6ad 3068 .dma_supported = amd_iommu_dma_supported,
6631ee9d
JR		 3069};
3070
27c2127a
JR		 3071static unsigned device_dma_ops_init(void)
3072{
5abcdba4 3073 struct iommu_dev_data *dev_data;
27c2127a
JR		 3074 struct pci_dev *pdev = NULL;
3075 unsigned unhandled = 0;
3076
3077 for_each_pci_dev(pdev) {
3078 if (!check_device(&pdev->dev)) {
af1be049
JR		 3079
3080 iommu_ignore_device(&pdev->dev);
3081
27c2127a
JR		 3082 unhandled += 1;
3083 continue;
3084 }
3085
5abcdba4
JR		 3086 dev_data = get_dev_data(&pdev->dev);
3087
3088 if (!dev_data->passthrough)
3089 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3090 else
3091 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
27c2127a
JR		 3092 }
3093
3094 return unhandled;
3095}
3096
431b2a20
JR		 3097/*
3098 * The function which clues the AMD IOMMU driver into dma_ops.
3099 */
f5325094
JR		 3100
3101void __init amd_iommu_init_api(void)
3102{
2cc21c42 3103 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
f5325094
JR		 3104}
3105
6631ee9d
JR		 3106int __init amd_iommu_init_dma_ops(void)
3107{
3108 struct amd_iommu *iommu;
27c2127a 3109 int ret, unhandled;
6631ee9d 3110
431b2a20
JR		 3111 /*
3112 * first allocate a default protection domain for every IOMMU we
3113 * found in the system. Devices not assigned to any other
3114 * protection domain will be assigned to the default one.
3115 */
3bd22172 3116 for_each_iommu(iommu) {
87a64d52 3117 iommu->default_dom = dma_ops_domain_alloc();
6631ee9d
JR		 3118 if (iommu->default_dom == NULL)
3119 return -ENOMEM;
e2dc14a2 3120 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
6631ee9d
JR		 3121 ret = iommu_init_unity_mappings(iommu);
3122 if (ret)
3123 goto free_domains;
3124 }
3125
431b2a20 3126 /*
8793abeb 3127 * Pre-allocate the protection domains for each device.
431b2a20 3128 */
8793abeb 3129 prealloc_protection_domains();
6631ee9d
JR		 3130
3131 iommu_detected = 1;
75f1cdf1 3132 swiotlb = 0;
6631ee9d 3133
431b2a20 3134 /* Make the driver finally visible to the drivers */
27c2127a
JR		 3135 unhandled = device_dma_ops_init();
3136 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3137 /* There are unhandled devices - initialize swiotlb for them */
3138 swiotlb = 1;
3139 }
6631ee9d 3140
7f26508b
JR		 3141 amd_iommu_stats_init();
3142
62410eeb
JR		 3143 if (amd_iommu_unmap_flush)
3144 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3145 else
3146 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3147
6631ee9d
JR		 3148 return 0;
3149
3150free_domains:
3151
3bd22172 3152 for_each_iommu(iommu) {
91457df7 3153 dma_ops_domain_free(iommu->default_dom);
6631ee9d
JR		 3154 }
3155
3156 return ret;
3157}
6d98cd80
JR		 3158
3159/*****************************************************************************
3160 *
3161 * The following functions belong to the exported interface of AMD IOMMU
3162 *
3163 * This interface allows access to lower level functions of the IOMMU
3164 * like protection domain handling and assignement of devices to domains
3165 * which is not possible with the dma_ops interface.
3166 *
3167 *****************************************************************************/
3168
6d98cd80
JR		 3169static void cleanup_domain(struct protection_domain *domain)
3170{
9b29d3c6 3171 struct iommu_dev_data *entry;
6d98cd80 3172 unsigned long flags;
6d98cd80
JR		 3173
3174 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3175
9b29d3c6
JR		 3176 while (!list_empty(&domain->dev_list)) {
3177 entry = list_first_entry(&domain->dev_list,
3178 struct iommu_dev_data, list);
3179 __detach_device(entry);
492667da 3180 }
6d98cd80
JR		 3181
3182 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3183}
3184
2650815f
JR		 3185static void protection_domain_free(struct protection_domain *domain)
3186{
3187 if (!domain)
3188 return;
3189
aeb26f55
JR		 3190 del_domain_from_list(domain);
3191
2650815f
JR		 3192 if (domain->id)
3193 domain_id_free(domain->id);
3194
3195 kfree(domain);
3196}
3197
3198static struct protection_domain *protection_domain_alloc(void)
c156e347
JR		 3199{
3200 struct protection_domain *domain;
3201
3202 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3203 if (!domain)
2650815f 3204 return NULL;
c156e347
JR		 3205
3206 spin_lock_init(&domain->lock);
5d214fe6 3207 mutex_init(&domain->api_lock);
c156e347
JR		 3208 domain->id = domain_id_alloc();
3209 if (!domain->id)
2650815f 3210 goto out_err;
7c392cbe 3211 INIT_LIST_HEAD(&domain->dev_list);
2650815f 3212
aeb26f55
JR		 3213 add_domain_to_list(domain);
3214
2650815f
JR		 3215 return domain;
3216
3217out_err:
3218 kfree(domain);
3219
3220 return NULL;
3221}
3222
5abcdba4
JR		 3223static int __init alloc_passthrough_domain(void)
3224{
3225 if (pt_domain != NULL)
3226 return 0;
3227
3228 /* allocate passthrough domain */
3229 pt_domain = protection_domain_alloc();
3230 if (!pt_domain)
3231 return -ENOMEM;
3232
3233 pt_domain->mode = PAGE_MODE_NONE;
3234
3235 return 0;
3236}
2650815f
JR		 3237static int amd_iommu_domain_init(struct iommu_domain *dom)
3238{
3239 struct protection_domain *domain;
3240
3241 domain = protection_domain_alloc();
3242 if (!domain)
c156e347 3243 goto out_free;
2650815f
JR		 3244
3245 domain->mode = PAGE_MODE_3_LEVEL;
c156e347
JR		 3246 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3247 if (!domain->pt_root)
3248 goto out_free;
3249
f3572db8
JR		 3250 domain->iommu_domain = dom;
3251
c156e347
JR		 3252 dom->priv = domain;
3253
0ff64f80
JR		 3254 dom->geometry.aperture_start = 0;
3255 dom->geometry.aperture_end = ~0ULL;
3256 dom->geometry.force_aperture = true;
3257
c156e347
JR		 3258 return 0;
3259
3260out_free:
2650815f 3261 protection_domain_free(domain);
c156e347
JR		 3262
3263 return -ENOMEM;
3264}
3265
98383fc3
JR		 3266static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3267{
3268 struct protection_domain *domain = dom->priv;
3269
3270 if (!domain)
3271 return;
3272
3273 if (domain->dev_cnt > 0)
3274 cleanup_domain(domain);
3275
3276 BUG_ON(domain->dev_cnt != 0);
3277
132bd68f
JR		 3278 if (domain->mode != PAGE_MODE_NONE)
3279 free_pagetable(domain);
98383fc3 3280
52815b75
JR		 3281 if (domain->flags & PD_IOMMUV2_MASK)
3282 free_gcr3_table(domain);
3283
8b408fe4 3284 protection_domain_free(domain);
98383fc3
JR		 3285
3286 dom->priv = NULL;
3287}
3288
684f2888
JR		 3289static void amd_iommu_detach_device(struct iommu_domain *dom,
3290 struct device *dev)
3291{
657cbb6b 3292 struct iommu_dev_data *dev_data = dev->archdata.iommu;
684f2888 3293 struct amd_iommu *iommu;
684f2888
JR		 3294 u16 devid;
3295
98fc5a69 3296 if (!check_device(dev))
684f2888
JR		 3297 return;
3298
98fc5a69 3299 devid = get_device_id(dev);
684f2888 3300
657cbb6b 3301 if (dev_data->domain != NULL)
15898bbc 3302 detach_device(dev);
684f2888
JR		 3303
3304 iommu = amd_iommu_rlookup_table[devid];
3305 if (!iommu)
3306 return;
3307
684f2888
JR		 3308 iommu_completion_wait(iommu);
3309}
3310
01106066
JR		 3311static int amd_iommu_attach_device(struct iommu_domain *dom,
3312 struct device *dev)
3313{
3314 struct protection_domain *domain = dom->priv;
657cbb6b 3315 struct iommu_dev_data *dev_data;
01106066 3316 struct amd_iommu *iommu;
15898bbc 3317 int ret;
01106066 3318
98fc5a69 3319 if (!check_device(dev))
01106066
JR		 3320 return -EINVAL;
3321
657cbb6b
JR		 3322 dev_data = dev->archdata.iommu;
3323
f62dda66 3324 iommu = amd_iommu_rlookup_table[dev_data->devid];
01106066
JR		 3325 if (!iommu)
3326 return -EINVAL;
3327
657cbb6b 3328 if (dev_data->domain)
15898bbc 3329 detach_device(dev);
01106066 3330
15898bbc 3331 ret = attach_device(dev, domain);
01106066
JR		 3332
3333 iommu_completion_wait(iommu);
3334
15898bbc 3335 return ret;
01106066
JR		 3336}
3337
468e2366 3338static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
5009065d 3339 phys_addr_t paddr, size_t page_size, int iommu_prot)
c6229ca6
JR		 3340{
3341 struct protection_domain *domain = dom->priv;
c6229ca6
JR		 3342 int prot = 0;
3343 int ret;
3344
132bd68f
JR		 3345 if (domain->mode == PAGE_MODE_NONE)
3346 return -EINVAL;
3347
c6229ca6
JR		 3348 if (iommu_prot & IOMMU_READ)
3349 prot |= IOMMU_PROT_IR;
3350 if (iommu_prot & IOMMU_WRITE)
3351 prot |= IOMMU_PROT_IW;
3352
5d214fe6 3353 mutex_lock(&domain->api_lock);
795e74f7 3354 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
5d214fe6
JR		 3355 mutex_unlock(&domain->api_lock);
3356
795e74f7 3357 return ret;
c6229ca6
JR		 3358}
3359
5009065d
OBC		 3360static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3361 size_t page_size)
eb74ff6c 3362{
eb74ff6c 3363 struct protection_domain *domain = dom->priv;
5009065d 3364 size_t unmap_size;
eb74ff6c 3365
132bd68f
JR		 3366 if (domain->mode == PAGE_MODE_NONE)
3367 return -EINVAL;
3368
5d214fe6 3369 mutex_lock(&domain->api_lock);
468e2366 3370 unmap_size = iommu_unmap_page(domain, iova, page_size);
795e74f7 3371 mutex_unlock(&domain->api_lock);
eb74ff6c 3372
17b124bf 3373 domain_flush_tlb_pde(domain);
5d214fe6 3374
5009065d 3375 return unmap_size;
eb74ff6c
JR		 3376}
3377
645c4c8d 3378static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
bb5547ac 3379 dma_addr_t iova)
645c4c8d
JR		 3380{
3381 struct protection_domain *domain = dom->priv;
f03152bb 3382 unsigned long offset_mask;
645c4c8d 3383 phys_addr_t paddr;
f03152bb 3384 u64 *pte, __pte;
645c4c8d 3385
132bd68f
JR		 3386 if (domain->mode == PAGE_MODE_NONE)
3387 return iova;
3388
24cd7723 3389 pte = fetch_pte(domain, iova);
645c4c8d 3390
a6d41a40 3391 if (!pte || !IOMMU_PTE_PRESENT(*pte))
645c4c8d
JR		 3392 return 0;
3393
f03152bb
JR		 3394 if (PM_PTE_LEVEL(*pte) == 0)
3395 offset_mask = PAGE_SIZE - 1;
3396 else
3397 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3398
3399 __pte = *pte & PM_ADDR_MASK;
3400 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
645c4c8d
JR		 3401
3402 return paddr;
3403}
3404
dbb9fd86
SY		 3405static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3406 unsigned long cap)
3407{
80a506b8
JR		 3408 switch (cap) {
3409 case IOMMU_CAP_CACHE_COHERENCY:
3410 return 1;
bdddadcb
JR		 3411 case IOMMU_CAP_INTR_REMAP:
3412 return irq_remapping_enabled;
80a506b8
JR		 3413 }
3414
dbb9fd86
SY		 3415 return 0;
3416}
3417
b22f6434 3418static const struct iommu_ops amd_iommu_ops = {
26961efe
JR		 3419 .domain_init = amd_iommu_domain_init,
3420 .domain_destroy = amd_iommu_domain_destroy,
3421 .attach_dev = amd_iommu_attach_device,
3422 .detach_dev = amd_iommu_detach_device,
468e2366
JR		 3423 .map = amd_iommu_map,
3424 .unmap = amd_iommu_unmap,
26961efe 3425 .iova_to_phys = amd_iommu_iova_to_phys,
dbb9fd86 3426 .domain_has_cap = amd_iommu_domain_has_cap,
aa3de9c0 3427 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
26961efe
JR		 3428};
3429
0feae533
JR		 3430/*****************************************************************************
3431 *
3432 * The next functions do a basic initialization of IOMMU for pass through
3433 * mode
3434 *
3435 * In passthrough mode the IOMMU is initialized and enabled but not used for
3436 * DMA-API translation.
3437 *
3438 *****************************************************************************/
3439
3440int __init amd_iommu_init_passthrough(void)
3441{
5abcdba4 3442 struct iommu_dev_data *dev_data;
0feae533 3443 struct pci_dev *dev = NULL;
5abcdba4 3444 int ret;
0feae533 3445
5abcdba4
JR		 3446 ret = alloc_passthrough_domain();
3447 if (ret)
3448 return ret;
0feae533 3449
6c54aabd 3450 for_each_pci_dev(dev) {
98fc5a69 3451 if (!check_device(&dev->dev))
0feae533
JR		 3452 continue;
3453
5abcdba4
JR		 3454 dev_data = get_dev_data(&dev->dev);
3455 dev_data->passthrough = true;
3456
15898bbc 3457 attach_device(&dev->dev, pt_domain);
0feae533
JR		 3458 }
3459
2655d7a2
JR		 3460 amd_iommu_stats_init();
3461
0feae533
JR		 3462 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3463
3464 return 0;
3465}
72e1dcc4
JR		 3466
3467/* IOMMUv2 specific functions */
3468int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3469{
3470 return atomic_notifier_chain_register(&ppr_notifier, nb);
3471}
3472EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3473
3474int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3475{
3476 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3477}
3478EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
132bd68f
JR		 3479
3480void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3481{
3482 struct protection_domain *domain = dom->priv;
3483 unsigned long flags;
3484
3485 spin_lock_irqsave(&domain->lock, flags);
3486
3487 /* Update data structure */
3488 domain->mode = PAGE_MODE_NONE;
3489 domain->updated = true;
3490
3491 /* Make changes visible to IOMMUs */
3492 update_domain(domain);
3493
3494 /* Page-table is not visible to IOMMU anymore, so free it */
3495 free_pagetable(domain);
3496
3497 spin_unlock_irqrestore(&domain->lock, flags);
3498}
3499EXPORT_SYMBOL(amd_iommu_domain_direct_map);
52815b75
JR		 3500
3501int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3502{
3503 struct protection_domain *domain = dom->priv;
3504 unsigned long flags;
3505 int levels, ret;
3506
3507 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3508 return -EINVAL;
3509
3510 /* Number of GCR3 table levels required */
3511 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3512 levels += 1;
3513
3514 if (levels > amd_iommu_max_glx_val)
3515 return -EINVAL;
3516
3517 spin_lock_irqsave(&domain->lock, flags);
3518
3519 /*
3520 * Save us all sanity checks whether devices already in the
3521 * domain support IOMMUv2. Just force that the domain has no
3522 * devices attached when it is switched into IOMMUv2 mode.
3523 */
3524 ret = -EBUSY;
3525 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3526 goto out;
3527
3528 ret = -ENOMEM;
3529 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3530 if (domain->gcr3_tbl == NULL)
3531 goto out;
3532
3533 domain->glx = levels;
3534 domain->flags |= PD_IOMMUV2_MASK;
3535 domain->updated = true;
3536
3537 update_domain(domain);
3538
3539 ret = 0;
3540
3541out:
3542 spin_unlock_irqrestore(&domain->lock, flags);
3543
3544 return ret;
3545}
3546EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
22e266c7
JR		 3547
3548static int __flush_pasid(struct protection_domain *domain, int pasid,
3549 u64 address, bool size)
3550{
3551 struct iommu_dev_data *dev_data;
3552 struct iommu_cmd cmd;
3553 int i, ret;
3554
3555 if (!(domain->flags & PD_IOMMUV2_MASK))
3556 return -EINVAL;
3557
3558 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3559
3560 /*
3561 * IOMMU TLB needs to be flushed before Device TLB to
3562 * prevent device TLB refill from IOMMU TLB
3563 */
3564 for (i = 0; i < amd_iommus_present; ++i) {
3565 if (domain->dev_iommu[i] == 0)
3566 continue;
3567
3568 ret = iommu_queue_command(amd_iommus[i], &cmd);
3569 if (ret != 0)
3570 goto out;
3571 }
3572
3573 /* Wait until IOMMU TLB flushes are complete */
3574 domain_flush_complete(domain);
3575
3576 /* Now flush device TLBs */
3577 list_for_each_entry(dev_data, &domain->dev_list, list) {
3578 struct amd_iommu *iommu;
3579 int qdep;
3580
3581 BUG_ON(!dev_data->ats.enabled);
3582
3583 qdep = dev_data->ats.qdep;
3584 iommu = amd_iommu_rlookup_table[dev_data->devid];
3585
3586 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3587 qdep, address, size);
3588
3589 ret = iommu_queue_command(iommu, &cmd);
3590 if (ret != 0)
3591 goto out;
3592 }
3593
3594 /* Wait until all device TLBs are flushed */
3595 domain_flush_complete(domain);
3596
3597 ret = 0;
3598
3599out:
3600
3601 return ret;
3602}
3603
3604static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3605 u64 address)
3606{
399be2f5
JR		 3607 INC_STATS_COUNTER(invalidate_iotlb);
3608
22e266c7
JR		 3609 return __flush_pasid(domain, pasid, address, false);
3610}
3611
3612int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3613 u64 address)
3614{
3615 struct protection_domain *domain = dom->priv;
3616 unsigned long flags;
3617 int ret;
3618
3619 spin_lock_irqsave(&domain->lock, flags);
3620 ret = __amd_iommu_flush_page(domain, pasid, address);
3621 spin_unlock_irqrestore(&domain->lock, flags);
3622
3623 return ret;
3624}
3625EXPORT_SYMBOL(amd_iommu_flush_page);
3626
3627static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3628{
399be2f5
JR		 3629 INC_STATS_COUNTER(invalidate_iotlb_all);
3630
22e266c7
JR		 3631 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3632 true);
3633}
3634
3635int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3636{
3637 struct protection_domain *domain = dom->priv;
3638 unsigned long flags;
3639 int ret;
3640
3641 spin_lock_irqsave(&domain->lock, flags);
3642 ret = __amd_iommu_flush_tlb(domain, pasid);
3643 spin_unlock_irqrestore(&domain->lock, flags);
3644
3645 return ret;
3646}
3647EXPORT_SYMBOL(amd_iommu_flush_tlb);
3648
b16137b1
JR		 3649static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3650{
3651 int index;
3652 u64 *pte;
3653
3654 while (true) {
3655
3656 index = (pasid >> (9 * level)) & 0x1ff;
3657 pte = &root[index];
3658
3659 if (level == 0)
3660 break;
3661
3662 if (!(*pte & GCR3_VALID)) {
3663 if (!alloc)
3664 return NULL;
3665
3666 root = (void *)get_zeroed_page(GFP_ATOMIC);
3667 if (root == NULL)
3668 return NULL;
3669
3670 *pte = __pa(root) | GCR3_VALID;
3671 }
3672
3673 root = __va(*pte & PAGE_MASK);
3674
3675 level -= 1;
3676 }
3677
3678 return pte;
3679}
3680
3681static int __set_gcr3(struct protection_domain *domain, int pasid,
3682 unsigned long cr3)
3683{
3684 u64 *pte;
3685
3686 if (domain->mode != PAGE_MODE_NONE)
3687 return -EINVAL;
3688
3689 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3690 if (pte == NULL)
3691 return -ENOMEM;
3692
3693 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3694
3695 return __amd_iommu_flush_tlb(domain, pasid);
3696}
3697
3698static int __clear_gcr3(struct protection_domain *domain, int pasid)
3699{
3700 u64 *pte;
3701
3702 if (domain->mode != PAGE_MODE_NONE)
3703 return -EINVAL;
3704
3705 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3706 if (pte == NULL)
3707 return 0;
3708
3709 *pte = 0;
3710
3711 return __amd_iommu_flush_tlb(domain, pasid);
3712}
3713
3714int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3715 unsigned long cr3)
3716{
3717 struct protection_domain *domain = dom->priv;
3718 unsigned long flags;
3719 int ret;
3720
3721 spin_lock_irqsave(&domain->lock, flags);
3722 ret = __set_gcr3(domain, pasid, cr3);
3723 spin_unlock_irqrestore(&domain->lock, flags);
3724
3725 return ret;
3726}
3727EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3728
3729int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3730{
3731 struct protection_domain *domain = dom->priv;
3732 unsigned long flags;
3733 int ret;
3734
3735 spin_lock_irqsave(&domain->lock, flags);
3736 ret = __clear_gcr3(domain, pasid);
3737 spin_unlock_irqrestore(&domain->lock, flags);
3738
3739 return ret;
3740}
3741EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
c99afa25
JR		 3742
3743int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3744 int status, int tag)
3745{
3746 struct iommu_dev_data *dev_data;
3747 struct amd_iommu *iommu;
3748 struct iommu_cmd cmd;
3749
399be2f5
JR		 3750 INC_STATS_COUNTER(complete_ppr);
3751
c99afa25
JR		 3752 dev_data = get_dev_data(&pdev->dev);
3753 iommu = amd_iommu_rlookup_table[dev_data->devid];
3754
3755 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3756 tag, dev_data->pri_tlp);
3757
3758 return iommu_queue_command(iommu, &cmd);
3759}
3760EXPORT_SYMBOL(amd_iommu_complete_ppr);
f3572db8
JR		 3761
3762struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3763{
3764 struct protection_domain *domain;
3765
3766 domain = get_domain(&pdev->dev);
3767 if (IS_ERR(domain))
3768 return NULL;
3769
3770 /* Only return IOMMUv2 domains */
3771 if (!(domain->flags & PD_IOMMUV2_MASK))
3772 return NULL;
3773
3774 return domain->iommu_domain;
3775}
3776EXPORT_SYMBOL(amd_iommu_get_v2_domain);
6a113ddc
JR		 3777
3778void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3779{
3780 struct iommu_dev_data *dev_data;
3781
3782 if (!amd_iommu_v2_supported())
3783 return;
3784
3785 dev_data = get_dev_data(&pdev->dev);
3786 dev_data->errata |= (1 << erratum);
3787}
3788EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
52efdb89
JR		 3789
3790int amd_iommu_device_info(struct pci_dev *pdev,
3791 struct amd_iommu_device_info *info)
3792{
3793 int max_pasids;
3794 int pos;
3795
3796 if (pdev == NULL || info == NULL)
3797 return -EINVAL;
3798
3799 if (!amd_iommu_v2_supported())
3800 return -EINVAL;
3801
3802 memset(info, 0, sizeof(*info));
3803
3804 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3805 if (pos)
3806 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3807
3808 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3809 if (pos)
3810 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3811
3812 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3813 if (pos) {
3814 int features;
3815
3816 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3817 max_pasids = min(max_pasids, (1 << 20));
3818
3819 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3820 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3821
3822 features = pci_pasid_features(pdev);
3823 if (features & PCI_PASID_CAP_EXEC)
3824 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3825 if (features & PCI_PASID_CAP_PRIV)
3826 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3827 }
3828
3829 return 0;
3830}
3831EXPORT_SYMBOL(amd_iommu_device_info);
2b324506
JR		 3832
3833#ifdef CONFIG_IRQ_REMAP
3834
3835/*****************************************************************************
3836 *
3837 * Interrupt Remapping Implementation
3838 *
3839 *****************************************************************************/
3840
3841union irte {
3842 u32 val;
3843 struct {
3844 u32 valid : 1,
3845 no_fault : 1,
3846 int_type : 3,
3847 rq_eoi : 1,
3848 dm : 1,
3849 rsvd_1 : 1,
3850 destination : 8,
3851 vector : 8,
3852 rsvd_2 : 8;
3853 } fields;
3854};
3855
3856#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3857#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3858#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3859#define DTE_IRQ_REMAP_ENABLE 1ULL
3860
3861static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3862{
3863 u64 dte;
3864
3865 dte = amd_iommu_dev_table[devid].data[2];
3866 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3867 dte |= virt_to_phys(table->table);
3868 dte |= DTE_IRQ_REMAP_INTCTL;
3869 dte |= DTE_IRQ_TABLE_LEN;
3870 dte |= DTE_IRQ_REMAP_ENABLE;
3871
3872 amd_iommu_dev_table[devid].data[2] = dte;
3873}
3874
3875#define IRTE_ALLOCATED (~1U)
3876
3877static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3878{
3879 struct irq_remap_table *table = NULL;
3880 struct amd_iommu *iommu;
3881 unsigned long flags;
3882 u16 alias;
3883
3884 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3885
3886 iommu = amd_iommu_rlookup_table[devid];
3887 if (!iommu)
3888 goto out_unlock;
3889
3890 table = irq_lookup_table[devid];
3891 if (table)
3892 goto out;
3893
3894 alias = amd_iommu_alias_table[devid];
3895 table = irq_lookup_table[alias];
3896 if (table) {
3897 irq_lookup_table[devid] = table;
3898 set_dte_irq_entry(devid, table);
3899 iommu_flush_dte(iommu, devid);
3900 goto out;
3901 }
3902
3903 /* Nothing there yet, allocate new irq remapping table */
3904 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3905 if (!table)
3906 goto out;
3907
197887f0
JR		 3908 /* Initialize table spin-lock */
3909 spin_lock_init(&table->lock);
3910
2b324506
JR		 3911 if (ioapic)
3912 /* Keep the first 32 indexes free for IOAPIC interrupts */
3913 table->min_index = 32;
3914
3915 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3916 if (!table->table) {
3917 kfree(table);
821f0f68 3918 table = NULL;
2b324506
JR		 3919 goto out;
3920 }
3921
3922 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3923
3924 if (ioapic) {
3925 int i;
3926
3927 for (i = 0; i < 32; ++i)
3928 table->table[i] = IRTE_ALLOCATED;
3929 }
3930
3931 irq_lookup_table[devid] = table;
3932 set_dte_irq_entry(devid, table);
3933 iommu_flush_dte(iommu, devid);
3934 if (devid != alias) {
3935 irq_lookup_table[alias] = table;
e028a9e6 3936 set_dte_irq_entry(alias, table);
2b324506
JR		 3937 iommu_flush_dte(iommu, alias);
3938 }
3939
3940out:
3941 iommu_completion_wait(iommu);
3942
3943out_unlock:
3944 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3945
3946 return table;
3947}
3948
3949static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3950{
3951 struct irq_remap_table *table;
3952 unsigned long flags;
3953 int index, c;
3954
3955 table = get_irq_table(devid, false);
3956 if (!table)
3957 return -ENODEV;
3958
3959 spin_lock_irqsave(&table->lock, flags);
3960
3961 /* Scan table for free entries */
3962 for (c = 0, index = table->min_index;
3963 index < MAX_IRQS_PER_TABLE;
3964 ++index) {
3965 if (table->table[index] == 0)
3966 c += 1;
3967 else
3968 c = 0;
3969
3970 if (c == count) {
0dfedd61 3971 struct irq_2_irte *irte_info;
2b324506
JR		 3972
3973 for (; c != 0; --c)
3974 table->table[index - c + 1] = IRTE_ALLOCATED;
3975
3976 index -= count - 1;
3977
9b1b0e42 3978 cfg->remapped = 1;
0dfedd61
JR		 3979 irte_info = &cfg->irq_2_irte;
3980 irte_info->devid = devid;
3981 irte_info->index = index;
2b324506
JR		 3982
3983 goto out;
3984 }
3985 }
3986
3987 index = -ENOSPC;
3988
3989out:
3990 spin_unlock_irqrestore(&table->lock, flags);
3991
3992 return index;
3993}
3994
3995static int get_irte(u16 devid, int index, union irte *irte)
3996{
3997 struct irq_remap_table *table;
3998 unsigned long flags;
3999
4000 table = get_irq_table(devid, false);
4001 if (!table)
4002 return -ENOMEM;
4003
4004 spin_lock_irqsave(&table->lock, flags);
4005 irte->val = table->table[index];
4006 spin_unlock_irqrestore(&table->lock, flags);
4007
4008 return 0;
4009}
4010
4011static int modify_irte(u16 devid, int index, union irte irte)
4012{
4013 struct irq_remap_table *table;
4014 struct amd_iommu *iommu;
4015 unsigned long flags;
4016
4017 iommu = amd_iommu_rlookup_table[devid];
4018 if (iommu == NULL)
4019 return -EINVAL;
4020
4021 table = get_irq_table(devid, false);
4022 if (!table)
4023 return -ENOMEM;
4024
4025 spin_lock_irqsave(&table->lock, flags);
4026 table->table[index] = irte.val;
4027 spin_unlock_irqrestore(&table->lock, flags);
4028
4029 iommu_flush_irt(iommu, devid);
4030 iommu_completion_wait(iommu);
4031
4032 return 0;
4033}
4034
4035static void free_irte(u16 devid, int index)
4036{
4037 struct irq_remap_table *table;
4038 struct amd_iommu *iommu;
4039 unsigned long flags;
4040
4041 iommu = amd_iommu_rlookup_table[devid];
4042 if (iommu == NULL)
4043 return;
4044
4045 table = get_irq_table(devid, false);
4046 if (!table)
4047 return;
4048
4049 spin_lock_irqsave(&table->lock, flags);
4050 table->table[index] = 0;
4051 spin_unlock_irqrestore(&table->lock, flags);
4052
4053 iommu_flush_irt(iommu, devid);
4054 iommu_completion_wait(iommu);
4055}
4056
5527de74
JR		 4057static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4058 unsigned int destination, int vector,
4059 struct io_apic_irq_attr *attr)
4060{
4061 struct irq_remap_table *table;
0dfedd61 4062 struct irq_2_irte *irte_info;
5527de74
JR		 4063 struct irq_cfg *cfg;
4064 union irte irte;
4065 int ioapic_id;
4066 int index;
4067 int devid;
4068 int ret;
4069
4070 cfg = irq_get_chip_data(irq);
4071 if (!cfg)
4072 return -EINVAL;
4073
0dfedd61 4074 irte_info = &cfg->irq_2_irte;
5527de74
JR		 4075 ioapic_id = mpc_ioapic_id(attr->ioapic);
4076 devid = get_ioapic_devid(ioapic_id);
4077
4078 if (devid < 0)
4079 return devid;
4080
4081 table = get_irq_table(devid, true);
4082 if (table == NULL)
4083 return -ENOMEM;
4084
4085 index = attr->ioapic_pin;
4086
4087 /* Setup IRQ remapping info */
9b1b0e42 4088 cfg->remapped = 1;
0dfedd61
JR		 4089 irte_info->devid = devid;
4090 irte_info->index = index;
5527de74
JR		 4091
4092 /* Setup IRTE for IOMMU */
4093 irte.val = 0;
4094 irte.fields.vector = vector;
4095 irte.fields.int_type = apic->irq_delivery_mode;
4096 irte.fields.destination = destination;
4097 irte.fields.dm = apic->irq_dest_mode;
4098 irte.fields.valid = 1;
4099
4100 ret = modify_irte(devid, index, irte);
4101 if (ret)
4102 return ret;
4103
4104 /* Setup IOAPIC entry */
4105 memset(entry, 0, sizeof(*entry));
4106
4107 entry->vector = index;
4108 entry->mask = 0;
4109 entry->trigger = attr->trigger;
4110 entry->polarity = attr->polarity;
4111
4112 /*
4113 * Mask level triggered irqs.
5527de74
JR		 4114 */
4115 if (attr->trigger)
4116 entry->mask = 1;
4117
4118 return 0;
4119}
4120
4121static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4122 bool force)
4123{
0dfedd61 4124 struct irq_2_irte *irte_info;
5527de74
JR		 4125 unsigned int dest, irq;
4126 struct irq_cfg *cfg;
4127 union irte irte;
4128 int err;
4129
4130 if (!config_enabled(CONFIG_SMP))
4131 return -1;
4132
4133 cfg = data->chip_data;
4134 irq = data->irq;
0dfedd61 4135 irte_info = &cfg->irq_2_irte;
5527de74
JR		 4136
4137 if (!cpumask_intersects(mask, cpu_online_mask))
4138 return -EINVAL;
4139
0dfedd61 4140 if (get_irte(irte_info->devid, irte_info->index, &irte))
5527de74
JR		 4141 return -EBUSY;
4142
4143 if (assign_irq_vector(irq, cfg, mask))
4144 return -EBUSY;
4145
4146 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4147 if (err) {
4148 if (assign_irq_vector(irq, cfg, data->affinity))
4149 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4150 return err;
4151 }
4152
4153 irte.fields.vector = cfg->vector;
4154 irte.fields.destination = dest;
4155
0dfedd61 4156 modify_irte(irte_info->devid, irte_info->index, irte);
5527de74
JR		 4157
4158 if (cfg->move_in_progress)
4159 send_cleanup_vector(cfg);
4160
4161 cpumask_copy(data->affinity, mask);
4162
4163 return 0;
4164}
4165
4166static int free_irq(int irq)
4167{
0dfedd61 4168 struct irq_2_irte *irte_info;
5527de74
JR		 4169 struct irq_cfg *cfg;
4170
4171 cfg = irq_get_chip_data(irq);
4172 if (!cfg)
4173 return -EINVAL;
4174
0dfedd61 4175 irte_info = &cfg->irq_2_irte;
5527de74 4176
0dfedd61 4177 free_irte(irte_info->devid, irte_info->index);
5527de74
JR		 4178
4179 return 0;
4180}
4181
0b4d48cb
JR		 4182static void compose_msi_msg(struct pci_dev *pdev,
4183 unsigned int irq, unsigned int dest,
4184 struct msi_msg *msg, u8 hpet_id)
4185{
0dfedd61 4186 struct irq_2_irte *irte_info;
0b4d48cb
JR		 4187 struct irq_cfg *cfg;
4188 union irte irte;
4189
4190 cfg = irq_get_chip_data(irq);
4191 if (!cfg)
4192 return;
4193
0dfedd61 4194 irte_info = &cfg->irq_2_irte;
0b4d48cb
JR		 4195
4196 irte.val = 0;
4197 irte.fields.vector = cfg->vector;
4198 irte.fields.int_type = apic->irq_delivery_mode;
4199 irte.fields.destination = dest;
4200 irte.fields.dm = apic->irq_dest_mode;
4201 irte.fields.valid = 1;
4202
0dfedd61 4203 modify_irte(irte_info->devid, irte_info->index, irte);
0b4d48cb
JR		 4204
4205 msg->address_hi = MSI_ADDR_BASE_HI;
4206 msg->address_lo = MSI_ADDR_BASE_LO;
0dfedd61 4207 msg->data = irte_info->index;
0b4d48cb
JR		 4208}
4209
4210static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4211{
4212 struct irq_cfg *cfg;
4213 int index;
4214 u16 devid;
4215
4216 if (!pdev)
4217 return -EINVAL;
4218
4219 cfg = irq_get_chip_data(irq);
4220 if (!cfg)
4221 return -EINVAL;
4222
4223 devid = get_device_id(&pdev->dev);
4224 index = alloc_irq_index(cfg, devid, nvec);
4225
4226 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4227}
4228
4229static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4230 int index, int offset)
4231{
0dfedd61 4232 struct irq_2_irte *irte_info;
0b4d48cb
JR		 4233 struct irq_cfg *cfg;
4234 u16 devid;
4235
4236 if (!pdev)
4237 return -EINVAL;
4238
4239 cfg = irq_get_chip_data(irq);
4240 if (!cfg)
4241 return -EINVAL;
4242
4243 if (index >= MAX_IRQS_PER_TABLE)
4244 return 0;
4245
4246 devid = get_device_id(&pdev->dev);
0dfedd61 4247 irte_info = &cfg->irq_2_irte;
0b4d48cb 4248
9b1b0e42 4249 cfg->remapped = 1;
0dfedd61
JR		 4250 irte_info->devid = devid;
4251 irte_info->index = index + offset;
0b4d48cb
JR		 4252
4253 return 0;
4254}
4255
d976195c
JR		 4256static int setup_hpet_msi(unsigned int irq, unsigned int id)
4257{
0dfedd61 4258 struct irq_2_irte *irte_info;
d976195c
JR		 4259 struct irq_cfg *cfg;
4260 int index, devid;
4261
4262 cfg = irq_get_chip_data(irq);
4263 if (!cfg)
4264 return -EINVAL;
4265
0dfedd61 4266 irte_info = &cfg->irq_2_irte;
d976195c
JR		 4267 devid = get_hpet_devid(id);
4268 if (devid < 0)
4269 return devid;
4270
4271 index = alloc_irq_index(cfg, devid, 1);
4272 if (index < 0)
4273 return index;
4274
9b1b0e42 4275 cfg->remapped = 1;
0dfedd61
JR		 4276 irte_info->devid = devid;
4277 irte_info->index = index;
d976195c
JR		 4278
4279 return 0;
4280}
4281
6b474b82
JR		 4282struct irq_remap_ops amd_iommu_irq_ops = {
4283 .supported = amd_iommu_supported,
4284 .prepare = amd_iommu_prepare,
4285 .enable = amd_iommu_enable,
4286 .disable = amd_iommu_disable,
4287 .reenable = amd_iommu_reenable,
4288 .enable_faulting = amd_iommu_enable_faulting,
4289 .setup_ioapic_entry = setup_ioapic_entry,
4290 .set_affinity = set_affinity,
4291 .free_irq = free_irq,
4292 .compose_msi_msg = compose_msi_msg,
4293 .msi_alloc_irq = msi_alloc_irq,
4294 .msi_setup_irq = msi_setup_irq,
4295 .setup_hpet_msi = setup_hpet_msi,
4296};
2b324506 4297#endif
Linux kernel - Deliverables
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