Commit | Line | Data |
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f6e2e6b6 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f3c6ea1b | 24 | #include <linux/syscore_ops.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
403f81d8 | 27 | #include <linux/amd-iommu.h> |
400a28a0 | 28 | #include <linux/export.h> |
02f3b3f5 JR |
29 | #include <linux/acpi.h> |
30 | #include <acpi/acpi.h> | |
f6e2e6b6 | 31 | #include <asm/pci-direct.h> |
46a7fa27 | 32 | #include <asm/iommu.h> |
1d9b16d1 | 33 | #include <asm/gart.h> |
ea1b0d39 | 34 | #include <asm/x86_init.h> |
22e6daf4 | 35 | #include <asm/iommu_table.h> |
eb1eb7ae | 36 | #include <asm/io_apic.h> |
403f81d8 JR |
37 | |
38 | #include "amd_iommu_proto.h" | |
39 | #include "amd_iommu_types.h" | |
05152a04 | 40 | #include "irq_remapping.h" |
403f81d8 | 41 | |
f6e2e6b6 JR |
42 | /* |
43 | * definitions for the ACPI scanning code | |
44 | */ | |
f6e2e6b6 | 45 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
46 | |
47 | #define ACPI_IVHD_TYPE 0x10 | |
48 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
49 | #define ACPI_IVMD_TYPE 0x21 | |
50 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
51 | ||
52 | #define IVHD_DEV_ALL 0x01 | |
53 | #define IVHD_DEV_SELECT 0x02 | |
54 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
55 | #define IVHD_DEV_RANGE_END 0x04 | |
56 | #define IVHD_DEV_ALIAS 0x42 | |
57 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
58 | #define IVHD_DEV_EXT_SELECT 0x46 | |
59 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
6efed63b JR |
60 | #define IVHD_DEV_SPECIAL 0x48 |
61 | ||
62 | #define IVHD_SPECIAL_IOAPIC 1 | |
63 | #define IVHD_SPECIAL_HPET 2 | |
f6e2e6b6 | 64 | |
6da7342f JR |
65 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
66 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
67 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
68 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
69 | |
70 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
71 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
72 | ||
73 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
74 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
75 | #define ACPI_DEVFLAG_NMI 0x04 | |
76 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
77 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
78 | #define ACPI_DEVFLAG_LINT0 0x40 | |
79 | #define ACPI_DEVFLAG_LINT1 0x80 | |
80 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
81 | ||
b65233a9 JR |
82 | /* |
83 | * ACPI table definitions | |
84 | * | |
85 | * These data structures are laid over the table to parse the important values | |
86 | * out of it. | |
87 | */ | |
88 | ||
89 | /* | |
90 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
91 | * or more ivhd_entrys. | |
92 | */ | |
f6e2e6b6 JR |
93 | struct ivhd_header { |
94 | u8 type; | |
95 | u8 flags; | |
96 | u16 length; | |
97 | u16 devid; | |
98 | u16 cap_ptr; | |
99 | u64 mmio_phys; | |
100 | u16 pci_seg; | |
101 | u16 info; | |
102 | u32 reserved; | |
103 | } __attribute__((packed)); | |
104 | ||
b65233a9 JR |
105 | /* |
106 | * A device entry describing which devices a specific IOMMU translates and | |
107 | * which requestor ids they use. | |
108 | */ | |
f6e2e6b6 JR |
109 | struct ivhd_entry { |
110 | u8 type; | |
111 | u16 devid; | |
112 | u8 flags; | |
113 | u32 ext; | |
114 | } __attribute__((packed)); | |
115 | ||
b65233a9 JR |
116 | /* |
117 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
118 | * ranges for devices and regions that should be unity mapped. | |
119 | */ | |
f6e2e6b6 JR |
120 | struct ivmd_header { |
121 | u8 type; | |
122 | u8 flags; | |
123 | u16 length; | |
124 | u16 devid; | |
125 | u16 aux; | |
126 | u64 resv; | |
127 | u64 range_start; | |
128 | u64 range_length; | |
129 | } __attribute__((packed)); | |
130 | ||
fefda117 | 131 | bool amd_iommu_dump; |
05152a04 | 132 | bool amd_iommu_irq_remap __read_mostly; |
fefda117 | 133 | |
02f3b3f5 | 134 | static bool amd_iommu_detected; |
a5235725 | 135 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 136 | |
b65233a9 JR |
137 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
138 | to handle */ | |
2e22847f | 139 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 140 | we find in ACPI */ |
3775d481 | 141 | u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 142 | |
2e22847f | 143 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 144 | system */ |
928abd25 | 145 | |
bb52777e JR |
146 | /* Array to assign indices to IOMMUs*/ |
147 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
148 | int amd_iommus_present; | |
149 | ||
318afd41 JR |
150 | /* IOMMUs have a non-present cache? */ |
151 | bool amd_iommu_np_cache __read_mostly; | |
60f723b4 | 152 | bool amd_iommu_iotlb_sup __read_mostly = true; |
318afd41 | 153 | |
62f71abb JR |
154 | u32 amd_iommu_max_pasids __read_mostly = ~0; |
155 | ||
400a28a0 JR |
156 | bool amd_iommu_v2_present __read_mostly; |
157 | ||
5abcdba4 JR |
158 | bool amd_iommu_force_isolation __read_mostly; |
159 | ||
aeb26f55 JR |
160 | /* |
161 | * List of protection domains - used during resume | |
162 | */ | |
163 | LIST_HEAD(amd_iommu_pd_list); | |
164 | spinlock_t amd_iommu_pd_lock; | |
165 | ||
b65233a9 JR |
166 | /* |
167 | * Pointer to the device table which is shared by all AMD IOMMUs | |
168 | * it is indexed by the PCI device id or the HT unit id and contains | |
169 | * information about the domain the device belongs to as well as the | |
170 | * page table root pointer. | |
171 | */ | |
928abd25 | 172 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
173 | |
174 | /* | |
175 | * The alias table is a driver specific data structure which contains the | |
176 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
177 | * More than one device can share the same requestor id. | |
178 | */ | |
928abd25 | 179 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
180 | |
181 | /* | |
182 | * The rlookup table is used to find the IOMMU which is responsible | |
183 | * for a specific device. It is also indexed by the PCI device id. | |
184 | */ | |
928abd25 | 185 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 186 | |
0ea2c422 JR |
187 | /* |
188 | * This table is used to find the irq remapping table for a given device id | |
189 | * quickly. | |
190 | */ | |
191 | struct irq_remap_table **irq_lookup_table; | |
192 | ||
b65233a9 JR |
193 | /* |
194 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
195 | * to know which ones are already in use. | |
196 | */ | |
928abd25 JR |
197 | unsigned long *amd_iommu_pd_alloc_bitmap; |
198 | ||
b65233a9 JR |
199 | static u32 dev_table_size; /* size of the device table */ |
200 | static u32 alias_table_size; /* size of the alias table */ | |
201 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 202 | |
2c0ae172 JR |
203 | enum iommu_init_state { |
204 | IOMMU_START_STATE, | |
205 | IOMMU_IVRS_DETECTED, | |
206 | IOMMU_ACPI_FINISHED, | |
207 | IOMMU_ENABLED, | |
208 | IOMMU_PCI_INIT, | |
209 | IOMMU_INTERRUPTS_EN, | |
210 | IOMMU_DMA_OPS, | |
211 | IOMMU_INITIALIZED, | |
212 | IOMMU_NOT_FOUND, | |
213 | IOMMU_INIT_ERROR, | |
214 | }; | |
215 | ||
216 | static enum iommu_init_state init_state = IOMMU_START_STATE; | |
217 | ||
ae295142 | 218 | static int amd_iommu_enable_interrupts(void); |
2c0ae172 | 219 | static int __init iommu_go_to_state(enum iommu_init_state state); |
3d9761e7 | 220 | |
208ec8c9 JR |
221 | static inline void update_last_devid(u16 devid) |
222 | { | |
223 | if (devid > amd_iommu_last_bdf) | |
224 | amd_iommu_last_bdf = devid; | |
225 | } | |
226 | ||
c571484e JR |
227 | static inline unsigned long tbl_size(int entry_size) |
228 | { | |
229 | unsigned shift = PAGE_SHIFT + | |
421f909c | 230 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
231 | |
232 | return 1UL << shift; | |
233 | } | |
234 | ||
5bcd757f MG |
235 | /* Access to l1 and l2 indexed register spaces */ |
236 | ||
237 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | |
238 | { | |
239 | u32 val; | |
240 | ||
241 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
242 | pci_read_config_dword(iommu->dev, 0xfc, &val); | |
243 | return val; | |
244 | } | |
245 | ||
246 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | |
247 | { | |
248 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | |
249 | pci_write_config_dword(iommu->dev, 0xfc, val); | |
250 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
251 | } | |
252 | ||
253 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | |
254 | { | |
255 | u32 val; | |
256 | ||
257 | pci_write_config_dword(iommu->dev, 0xf0, address); | |
258 | pci_read_config_dword(iommu->dev, 0xf4, &val); | |
259 | return val; | |
260 | } | |
261 | ||
262 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | |
263 | { | |
264 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | |
265 | pci_write_config_dword(iommu->dev, 0xf4, val); | |
266 | } | |
267 | ||
b65233a9 JR |
268 | /**************************************************************************** |
269 | * | |
270 | * AMD IOMMU MMIO register space handling functions | |
271 | * | |
272 | * These functions are used to program the IOMMU device registers in | |
273 | * MMIO space required for that driver. | |
274 | * | |
275 | ****************************************************************************/ | |
3e8064ba | 276 | |
b65233a9 JR |
277 | /* |
278 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
279 | * exclusion range are passed through untranslated | |
280 | */ | |
05f92db9 | 281 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
282 | { |
283 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
284 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
285 | u64 entry; | |
286 | ||
287 | if (!iommu->exclusion_start) | |
288 | return; | |
289 | ||
290 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
291 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
292 | &entry, sizeof(entry)); | |
293 | ||
294 | entry = limit; | |
295 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
296 | &entry, sizeof(entry)); | |
297 | } | |
298 | ||
b65233a9 | 299 | /* Programs the physical address of the device table into the IOMMU hardware */ |
6b7f000e | 300 | static void iommu_set_device_table(struct amd_iommu *iommu) |
b2026aa2 | 301 | { |
f609891f | 302 | u64 entry; |
b2026aa2 JR |
303 | |
304 | BUG_ON(iommu->mmio_base == NULL); | |
305 | ||
306 | entry = virt_to_phys(amd_iommu_dev_table); | |
307 | entry |= (dev_table_size >> 12) - 1; | |
308 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
309 | &entry, sizeof(entry)); | |
310 | } | |
311 | ||
b65233a9 | 312 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 313 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
314 | { |
315 | u32 ctrl; | |
316 | ||
317 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
318 | ctrl |= (1 << bit); | |
319 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
320 | } | |
321 | ||
ca020711 | 322 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
323 | { |
324 | u32 ctrl; | |
325 | ||
199d0d50 | 326 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
327 | ctrl &= ~(1 << bit); |
328 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
329 | } | |
330 | ||
1456e9d2 JR |
331 | static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) |
332 | { | |
333 | u32 ctrl; | |
334 | ||
335 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
336 | ctrl &= ~CTRL_INV_TO_MASK; | |
337 | ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; | |
338 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
339 | } | |
340 | ||
b65233a9 | 341 | /* Function to enable the hardware */ |
05f92db9 | 342 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 343 | { |
b2026aa2 | 344 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); |
b2026aa2 JR |
345 | } |
346 | ||
92ac4320 | 347 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 348 | { |
a8c485bb CW |
349 | /* Disable command buffer */ |
350 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
351 | ||
352 | /* Disable event logging and event interrupts */ | |
353 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
354 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
355 | ||
356 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 357 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
358 | } |
359 | ||
b65233a9 JR |
360 | /* |
361 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
362 | * the system has one. | |
363 | */ | |
98f1ad25 | 364 | static u8 __iomem * __init iommu_map_mmio_space(u64 address) |
6c56747b | 365 | { |
e82752d8 JR |
366 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { |
367 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | |
368 | address); | |
369 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | |
6c56747b | 370 | return NULL; |
e82752d8 | 371 | } |
6c56747b | 372 | |
98f1ad25 | 373 | return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH); |
6c56747b JR |
374 | } |
375 | ||
376 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
377 | { | |
378 | if (iommu->mmio_base) | |
379 | iounmap(iommu->mmio_base); | |
380 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
381 | } | |
382 | ||
b65233a9 JR |
383 | /**************************************************************************** |
384 | * | |
385 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
386 | * parsing. In this pass we try to find out the highest device id this | |
387 | * code has to handle. Upon this information the size of the shared data | |
388 | * structures is determined later. | |
389 | * | |
390 | ****************************************************************************/ | |
391 | ||
b514e555 JR |
392 | /* |
393 | * This function calculates the length of a given IVHD entry | |
394 | */ | |
395 | static inline int ivhd_entry_length(u8 *ivhd) | |
396 | { | |
397 | return 0x04 << (*ivhd >> 6); | |
398 | } | |
399 | ||
b65233a9 JR |
400 | /* |
401 | * This function reads the last device id the IOMMU has to handle from the PCI | |
402 | * capability header for this IOMMU | |
403 | */ | |
3e8064ba JR |
404 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
405 | { | |
406 | u32 cap; | |
407 | ||
408 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 409 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
b65233a9 JR |
414 | /* |
415 | * After reading the highest device id from the IOMMU PCI capability header | |
416 | * this function looks if there is a higher device id defined in the ACPI table | |
417 | */ | |
3e8064ba JR |
418 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
419 | { | |
420 | u8 *p = (void *)h, *end = (void *)h; | |
421 | struct ivhd_entry *dev; | |
422 | ||
423 | p += sizeof(*h); | |
424 | end += h->length; | |
425 | ||
426 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
427 | PCI_SLOT(h->devid), | |
428 | PCI_FUNC(h->devid), | |
429 | h->cap_ptr); | |
430 | ||
431 | while (p < end) { | |
432 | dev = (struct ivhd_entry *)p; | |
433 | switch (dev->type) { | |
434 | case IVHD_DEV_SELECT: | |
435 | case IVHD_DEV_RANGE_END: | |
436 | case IVHD_DEV_ALIAS: | |
437 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 438 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 439 | update_last_devid(dev->devid); |
3e8064ba JR |
440 | break; |
441 | default: | |
442 | break; | |
443 | } | |
b514e555 | 444 | p += ivhd_entry_length(p); |
3e8064ba JR |
445 | } |
446 | ||
447 | WARN_ON(p != end); | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
b65233a9 JR |
452 | /* |
453 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
454 | * id which we need to handle. This is the first of three functions which parse | |
455 | * the ACPI table. So we check the checksum here. | |
456 | */ | |
3e8064ba JR |
457 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
458 | { | |
459 | int i; | |
460 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
461 | struct ivhd_header *h; | |
462 | ||
463 | /* | |
464 | * Validate checksum here so we don't need to do it when | |
465 | * we actually parse the table | |
466 | */ | |
467 | for (i = 0; i < table->length; ++i) | |
468 | checksum += p[i]; | |
02f3b3f5 | 469 | if (checksum != 0) |
3e8064ba | 470 | /* ACPI table corrupt */ |
02f3b3f5 | 471 | return -ENODEV; |
3e8064ba JR |
472 | |
473 | p += IVRS_HEADER_LENGTH; | |
474 | ||
475 | end += table->length; | |
476 | while (p < end) { | |
477 | h = (struct ivhd_header *)p; | |
478 | switch (h->type) { | |
479 | case ACPI_IVHD_TYPE: | |
480 | find_last_devid_from_ivhd(h); | |
481 | break; | |
482 | default: | |
483 | break; | |
484 | } | |
485 | p += h->length; | |
486 | } | |
487 | WARN_ON(p != end); | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
b65233a9 JR |
492 | /**************************************************************************** |
493 | * | |
494 | * The following functions belong the the code path which parses the ACPI table | |
495 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
496 | * data structures, initialize the device/alias/rlookup table and also | |
497 | * basically initialize the hardware. | |
498 | * | |
499 | ****************************************************************************/ | |
500 | ||
501 | /* | |
502 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
503 | * write commands to that buffer later and the IOMMU will execute them | |
504 | * asynchronously | |
505 | */ | |
b36ca91e JR |
506 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
507 | { | |
d0312b21 | 508 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 509 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
510 | |
511 | if (cmd_buf == NULL) | |
512 | return NULL; | |
513 | ||
549c90dc | 514 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 515 | |
58492e12 JR |
516 | return cmd_buf; |
517 | } | |
518 | ||
93f1cc67 JR |
519 | /* |
520 | * This function resets the command buffer if the IOMMU stopped fetching | |
521 | * commands from it. | |
522 | */ | |
523 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
524 | { | |
525 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
526 | ||
527 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
528 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
529 | ||
530 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
531 | } | |
532 | ||
58492e12 JR |
533 | /* |
534 | * This function writes the command buffer address to the hardware and | |
535 | * enables it. | |
536 | */ | |
537 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
538 | { | |
539 | u64 entry; | |
540 | ||
541 | BUG_ON(iommu->cmd_buf == NULL); | |
542 | ||
543 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 544 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 545 | |
b36ca91e | 546 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 547 | &entry, sizeof(entry)); |
b36ca91e | 548 | |
93f1cc67 | 549 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 550 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
551 | } |
552 | ||
553 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
554 | { | |
23c1713f | 555 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 556 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
557 | } |
558 | ||
335503e5 JR |
559 | /* allocates the memory where the IOMMU will log its events to */ |
560 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
561 | { | |
335503e5 JR |
562 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
563 | get_order(EVT_BUFFER_SIZE)); | |
564 | ||
565 | if (iommu->evt_buf == NULL) | |
566 | return NULL; | |
567 | ||
1bc6f838 JR |
568 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
569 | ||
58492e12 JR |
570 | return iommu->evt_buf; |
571 | } | |
572 | ||
573 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
574 | { | |
575 | u64 entry; | |
576 | ||
577 | BUG_ON(iommu->evt_buf == NULL); | |
578 | ||
335503e5 | 579 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 580 | |
335503e5 JR |
581 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
582 | &entry, sizeof(entry)); | |
583 | ||
09067207 JR |
584 | /* set head and tail to zero manually */ |
585 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
586 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
587 | ||
58492e12 | 588 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
589 | } |
590 | ||
591 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
592 | { | |
593 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
594 | } | |
595 | ||
1a29ac01 JR |
596 | /* allocates the memory where the IOMMU will log its events to */ |
597 | static u8 * __init alloc_ppr_log(struct amd_iommu *iommu) | |
598 | { | |
599 | iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
600 | get_order(PPR_LOG_SIZE)); | |
601 | ||
602 | if (iommu->ppr_log == NULL) | |
603 | return NULL; | |
604 | ||
605 | return iommu->ppr_log; | |
606 | } | |
607 | ||
608 | static void iommu_enable_ppr_log(struct amd_iommu *iommu) | |
609 | { | |
610 | u64 entry; | |
611 | ||
612 | if (iommu->ppr_log == NULL) | |
613 | return; | |
614 | ||
615 | entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; | |
616 | ||
617 | memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, | |
618 | &entry, sizeof(entry)); | |
619 | ||
620 | /* set head and tail to zero manually */ | |
621 | writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
622 | writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
623 | ||
624 | iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); | |
625 | iommu_feature_enable(iommu, CONTROL_PPR_EN); | |
626 | } | |
627 | ||
628 | static void __init free_ppr_log(struct amd_iommu *iommu) | |
629 | { | |
630 | if (iommu->ppr_log == NULL) | |
631 | return; | |
632 | ||
633 | free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); | |
634 | } | |
635 | ||
cbc33a90 JR |
636 | static void iommu_enable_gt(struct amd_iommu *iommu) |
637 | { | |
638 | if (!iommu_feature(iommu, FEATURE_GT)) | |
639 | return; | |
640 | ||
641 | iommu_feature_enable(iommu, CONTROL_GT_EN); | |
642 | } | |
643 | ||
b65233a9 | 644 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
645 | static void set_dev_entry_bit(u16 devid, u8 bit) |
646 | { | |
ee6c2868 JR |
647 | int i = (bit >> 6) & 0x03; |
648 | int _bit = bit & 0x3f; | |
3566b778 | 649 | |
ee6c2868 | 650 | amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); |
3566b778 JR |
651 | } |
652 | ||
c5cca146 JR |
653 | static int get_dev_entry_bit(u16 devid, u8 bit) |
654 | { | |
ee6c2868 JR |
655 | int i = (bit >> 6) & 0x03; |
656 | int _bit = bit & 0x3f; | |
c5cca146 | 657 | |
ee6c2868 | 658 | return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; |
c5cca146 JR |
659 | } |
660 | ||
661 | ||
662 | void amd_iommu_apply_erratum_63(u16 devid) | |
663 | { | |
664 | int sysmgt; | |
665 | ||
666 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
667 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
668 | ||
669 | if (sysmgt == 0x01) | |
670 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
671 | } | |
672 | ||
5ff4789d JR |
673 | /* Writes the specific IOMMU for a device into the rlookup table */ |
674 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
675 | { | |
676 | amd_iommu_rlookup_table[devid] = iommu; | |
677 | } | |
678 | ||
b65233a9 JR |
679 | /* |
680 | * This function takes the device specific flags read from the ACPI | |
681 | * table and sets up the device table entry with that information | |
682 | */ | |
5ff4789d JR |
683 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
684 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
685 | { |
686 | if (flags & ACPI_DEVFLAG_INITPASS) | |
687 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
688 | if (flags & ACPI_DEVFLAG_EXTINT) | |
689 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
690 | if (flags & ACPI_DEVFLAG_NMI) | |
691 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
692 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
693 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
694 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
695 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
696 | if (flags & ACPI_DEVFLAG_LINT0) | |
697 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
698 | if (flags & ACPI_DEVFLAG_LINT1) | |
699 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 700 | |
c5cca146 JR |
701 | amd_iommu_apply_erratum_63(devid); |
702 | ||
5ff4789d | 703 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
704 | } |
705 | ||
6efed63b JR |
706 | static int add_special_device(u8 type, u8 id, u16 devid) |
707 | { | |
708 | struct devid_map *entry; | |
709 | struct list_head *list; | |
710 | ||
711 | if (type != IVHD_SPECIAL_IOAPIC && type != IVHD_SPECIAL_HPET) | |
712 | return -EINVAL; | |
713 | ||
714 | entry = kzalloc(sizeof(*entry), GFP_KERNEL); | |
715 | if (!entry) | |
716 | return -ENOMEM; | |
717 | ||
718 | entry->id = id; | |
719 | entry->devid = devid; | |
720 | ||
721 | if (type == IVHD_SPECIAL_IOAPIC) | |
722 | list = &ioapic_map; | |
723 | else | |
724 | list = &hpet_map; | |
725 | ||
726 | list_add_tail(&entry->list, list); | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
b65233a9 JR |
731 | /* |
732 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
733 | * it | |
734 | */ | |
3566b778 JR |
735 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
736 | { | |
737 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
738 | ||
739 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
740 | return; | |
741 | ||
742 | if (iommu) { | |
b65233a9 JR |
743 | /* |
744 | * We only can configure exclusion ranges per IOMMU, not | |
745 | * per device. But we can enable the exclusion range per | |
746 | * device. This is done here | |
747 | */ | |
3566b778 JR |
748 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
749 | iommu->exclusion_start = m->range_start; | |
750 | iommu->exclusion_length = m->range_length; | |
751 | } | |
752 | } | |
753 | ||
b65233a9 JR |
754 | /* |
755 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
756 | * initializes the hardware and our data structures with it. | |
757 | */ | |
6efed63b | 758 | static int __init init_iommu_from_acpi(struct amd_iommu *iommu, |
5d0c8e49 JR |
759 | struct ivhd_header *h) |
760 | { | |
761 | u8 *p = (u8 *)h; | |
762 | u8 *end = p, flags = 0; | |
0de66d5b JR |
763 | u16 devid = 0, devid_start = 0, devid_to = 0; |
764 | u32 dev_i, ext_flags = 0; | |
58a3bee5 | 765 | bool alias = false; |
5d0c8e49 JR |
766 | struct ivhd_entry *e; |
767 | ||
768 | /* | |
e9bf5197 | 769 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 770 | */ |
e9bf5197 | 771 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
772 | |
773 | /* | |
774 | * Done. Now parse the device entries | |
775 | */ | |
776 | p += sizeof(struct ivhd_header); | |
777 | end += h->length; | |
778 | ||
42a698f4 | 779 | |
5d0c8e49 JR |
780 | while (p < end) { |
781 | e = (struct ivhd_entry *)p; | |
782 | switch (e->type) { | |
783 | case IVHD_DEV_ALL: | |
42a698f4 JR |
784 | |
785 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
786 | " last device %02x:%02x.%x flags: %02x\n", | |
787 | PCI_BUS(iommu->first_device), | |
788 | PCI_SLOT(iommu->first_device), | |
789 | PCI_FUNC(iommu->first_device), | |
790 | PCI_BUS(iommu->last_device), | |
791 | PCI_SLOT(iommu->last_device), | |
792 | PCI_FUNC(iommu->last_device), | |
793 | e->flags); | |
794 | ||
5d0c8e49 JR |
795 | for (dev_i = iommu->first_device; |
796 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
797 | set_dev_entry_from_acpi(iommu, dev_i, |
798 | e->flags, 0); | |
5d0c8e49 JR |
799 | break; |
800 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
801 | |
802 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
803 | "flags: %02x\n", | |
804 | PCI_BUS(e->devid), | |
805 | PCI_SLOT(e->devid), | |
806 | PCI_FUNC(e->devid), | |
807 | e->flags); | |
808 | ||
5d0c8e49 | 809 | devid = e->devid; |
5ff4789d | 810 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
811 | break; |
812 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
813 | |
814 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
815 | "devid: %02x:%02x.%x flags: %02x\n", | |
816 | PCI_BUS(e->devid), | |
817 | PCI_SLOT(e->devid), | |
818 | PCI_FUNC(e->devid), | |
819 | e->flags); | |
820 | ||
5d0c8e49 JR |
821 | devid_start = e->devid; |
822 | flags = e->flags; | |
823 | ext_flags = 0; | |
58a3bee5 | 824 | alias = false; |
5d0c8e49 JR |
825 | break; |
826 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
827 | |
828 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
829 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
830 | PCI_BUS(e->devid), | |
831 | PCI_SLOT(e->devid), | |
832 | PCI_FUNC(e->devid), | |
833 | e->flags, | |
834 | PCI_BUS(e->ext >> 8), | |
835 | PCI_SLOT(e->ext >> 8), | |
836 | PCI_FUNC(e->ext >> 8)); | |
837 | ||
5d0c8e49 JR |
838 | devid = e->devid; |
839 | devid_to = e->ext >> 8; | |
7a6a3a08 | 840 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 841 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
842 | amd_iommu_alias_table[devid] = devid_to; |
843 | break; | |
844 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
845 | |
846 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
847 | "devid: %02x:%02x.%x flags: %02x " | |
848 | "devid_to: %02x:%02x.%x\n", | |
849 | PCI_BUS(e->devid), | |
850 | PCI_SLOT(e->devid), | |
851 | PCI_FUNC(e->devid), | |
852 | e->flags, | |
853 | PCI_BUS(e->ext >> 8), | |
854 | PCI_SLOT(e->ext >> 8), | |
855 | PCI_FUNC(e->ext >> 8)); | |
856 | ||
5d0c8e49 JR |
857 | devid_start = e->devid; |
858 | flags = e->flags; | |
859 | devid_to = e->ext >> 8; | |
860 | ext_flags = 0; | |
58a3bee5 | 861 | alias = true; |
5d0c8e49 JR |
862 | break; |
863 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
864 | |
865 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
866 | "flags: %02x ext: %08x\n", | |
867 | PCI_BUS(e->devid), | |
868 | PCI_SLOT(e->devid), | |
869 | PCI_FUNC(e->devid), | |
870 | e->flags, e->ext); | |
871 | ||
5d0c8e49 | 872 | devid = e->devid; |
5ff4789d JR |
873 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
874 | e->ext); | |
5d0c8e49 JR |
875 | break; |
876 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
877 | |
878 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
879 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
880 | PCI_BUS(e->devid), | |
881 | PCI_SLOT(e->devid), | |
882 | PCI_FUNC(e->devid), | |
883 | e->flags, e->ext); | |
884 | ||
5d0c8e49 JR |
885 | devid_start = e->devid; |
886 | flags = e->flags; | |
887 | ext_flags = e->ext; | |
58a3bee5 | 888 | alias = false; |
5d0c8e49 JR |
889 | break; |
890 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
891 | |
892 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
893 | PCI_BUS(e->devid), | |
894 | PCI_SLOT(e->devid), | |
895 | PCI_FUNC(e->devid)); | |
896 | ||
5d0c8e49 JR |
897 | devid = e->devid; |
898 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 899 | if (alias) { |
5d0c8e49 | 900 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
901 | set_dev_entry_from_acpi(iommu, |
902 | devid_to, flags, ext_flags); | |
903 | } | |
904 | set_dev_entry_from_acpi(iommu, dev_i, | |
905 | flags, ext_flags); | |
5d0c8e49 JR |
906 | } |
907 | break; | |
6efed63b JR |
908 | case IVHD_DEV_SPECIAL: { |
909 | u8 handle, type; | |
910 | const char *var; | |
911 | u16 devid; | |
912 | int ret; | |
913 | ||
914 | handle = e->ext & 0xff; | |
915 | devid = (e->ext >> 8) & 0xffff; | |
916 | type = (e->ext >> 24) & 0xff; | |
917 | ||
918 | if (type == IVHD_SPECIAL_IOAPIC) | |
919 | var = "IOAPIC"; | |
920 | else if (type == IVHD_SPECIAL_HPET) | |
921 | var = "HPET"; | |
922 | else | |
923 | var = "UNKNOWN"; | |
924 | ||
925 | DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", | |
926 | var, (int)handle, | |
927 | PCI_BUS(devid), | |
928 | PCI_SLOT(devid), | |
929 | PCI_FUNC(devid)); | |
930 | ||
931 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); | |
932 | ret = add_special_device(type, handle, devid); | |
933 | if (ret) | |
934 | return ret; | |
935 | break; | |
936 | } | |
5d0c8e49 JR |
937 | default: |
938 | break; | |
939 | } | |
940 | ||
b514e555 | 941 | p += ivhd_entry_length(p); |
5d0c8e49 | 942 | } |
6efed63b JR |
943 | |
944 | return 0; | |
5d0c8e49 JR |
945 | } |
946 | ||
b65233a9 | 947 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
948 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
949 | { | |
0de66d5b | 950 | u32 i; |
5d0c8e49 JR |
951 | |
952 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
953 | set_iommu_for_device(iommu, i); | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
e47d402d JR |
958 | static void __init free_iommu_one(struct amd_iommu *iommu) |
959 | { | |
960 | free_command_buffer(iommu); | |
335503e5 | 961 | free_event_buffer(iommu); |
1a29ac01 | 962 | free_ppr_log(iommu); |
e47d402d JR |
963 | iommu_unmap_mmio_space(iommu); |
964 | } | |
965 | ||
966 | static void __init free_iommu_all(void) | |
967 | { | |
968 | struct amd_iommu *iommu, *next; | |
969 | ||
3bd22172 | 970 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
971 | list_del(&iommu->list); |
972 | free_iommu_one(iommu); | |
973 | kfree(iommu); | |
974 | } | |
975 | } | |
976 | ||
b65233a9 JR |
977 | /* |
978 | * This function clues the initialization function for one IOMMU | |
979 | * together and also allocates the command buffer and programs the | |
980 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
981 | */ | |
e47d402d JR |
982 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
983 | { | |
6efed63b JR |
984 | int ret; |
985 | ||
e47d402d | 986 | spin_lock_init(&iommu->lock); |
bb52777e JR |
987 | |
988 | /* Add IOMMU to internal data structures */ | |
e47d402d | 989 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
990 | iommu->index = amd_iommus_present++; |
991 | ||
992 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
993 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
994 | return -ENOSYS; | |
995 | } | |
996 | ||
997 | /* Index is fine - add IOMMU to the array */ | |
998 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
999 | |
1000 | /* | |
1001 | * Copy data from ACPI table entry to the iommu struct | |
1002 | */ | |
23c742db | 1003 | iommu->devid = h->devid; |
e47d402d | 1004 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 1005 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
1006 | iommu->mmio_phys = h->mmio_phys; |
1007 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
1008 | if (!iommu->mmio_base) | |
1009 | return -ENOMEM; | |
1010 | ||
e47d402d JR |
1011 | iommu->cmd_buf = alloc_command_buffer(iommu); |
1012 | if (!iommu->cmd_buf) | |
1013 | return -ENOMEM; | |
1014 | ||
335503e5 JR |
1015 | iommu->evt_buf = alloc_event_buffer(iommu); |
1016 | if (!iommu->evt_buf) | |
1017 | return -ENOMEM; | |
1018 | ||
a80dc3e0 JR |
1019 | iommu->int_enabled = false; |
1020 | ||
6efed63b JR |
1021 | ret = init_iommu_from_acpi(iommu, h); |
1022 | if (ret) | |
1023 | return ret; | |
e47d402d JR |
1024 | init_iommu_devices(iommu); |
1025 | ||
23c742db | 1026 | return 0; |
e47d402d JR |
1027 | } |
1028 | ||
b65233a9 JR |
1029 | /* |
1030 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
1031 | * IOMMU structure and initializes it with init_iommu_one() | |
1032 | */ | |
e47d402d JR |
1033 | static int __init init_iommu_all(struct acpi_table_header *table) |
1034 | { | |
1035 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1036 | struct ivhd_header *h; | |
1037 | struct amd_iommu *iommu; | |
1038 | int ret; | |
1039 | ||
e47d402d JR |
1040 | end += table->length; |
1041 | p += IVRS_HEADER_LENGTH; | |
1042 | ||
1043 | while (p < end) { | |
1044 | h = (struct ivhd_header *)p; | |
1045 | switch (*p) { | |
1046 | case ACPI_IVHD_TYPE: | |
9c72041f | 1047 | |
ae908c22 | 1048 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
1049 | "seg: %d flags: %01x info %04x\n", |
1050 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
1051 | PCI_FUNC(h->devid), h->cap_ptr, | |
1052 | h->pci_seg, h->flags, h->info); | |
1053 | DUMP_printk(" mmio-addr: %016llx\n", | |
1054 | h->mmio_phys); | |
1055 | ||
e47d402d | 1056 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
02f3b3f5 JR |
1057 | if (iommu == NULL) |
1058 | return -ENOMEM; | |
3551a708 | 1059 | |
e47d402d | 1060 | ret = init_iommu_one(iommu, h); |
02f3b3f5 JR |
1061 | if (ret) |
1062 | return ret; | |
e47d402d JR |
1063 | break; |
1064 | default: | |
1065 | break; | |
1066 | } | |
1067 | p += h->length; | |
1068 | ||
1069 | } | |
1070 | WARN_ON(p != end); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
23c742db JR |
1075 | static int iommu_init_pci(struct amd_iommu *iommu) |
1076 | { | |
1077 | int cap_ptr = iommu->cap_ptr; | |
1078 | u32 range, misc, low, high; | |
1079 | ||
1080 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(iommu->devid), | |
1081 | iommu->devid & 0xff); | |
1082 | if (!iommu->dev) | |
1083 | return -ENODEV; | |
1084 | ||
1085 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, | |
1086 | &iommu->cap); | |
1087 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
1088 | &range); | |
1089 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, | |
1090 | &misc); | |
1091 | ||
1092 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), | |
1093 | MMIO_GET_FD(range)); | |
1094 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
1095 | MMIO_GET_LD(range)); | |
1096 | ||
1097 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) | |
1098 | amd_iommu_iotlb_sup = false; | |
1099 | ||
1100 | /* read extended feature bits */ | |
1101 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | |
1102 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | |
1103 | ||
1104 | iommu->features = ((u64)high << 32) | low; | |
1105 | ||
1106 | if (iommu_feature(iommu, FEATURE_GT)) { | |
1107 | int glxval; | |
1108 | u32 pasids; | |
1109 | u64 shift; | |
1110 | ||
1111 | shift = iommu->features & FEATURE_PASID_MASK; | |
1112 | shift >>= FEATURE_PASID_SHIFT; | |
1113 | pasids = (1 << shift); | |
1114 | ||
1115 | amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids); | |
1116 | ||
1117 | glxval = iommu->features & FEATURE_GLXVAL_MASK; | |
1118 | glxval >>= FEATURE_GLXVAL_SHIFT; | |
1119 | ||
1120 | if (amd_iommu_max_glx_val == -1) | |
1121 | amd_iommu_max_glx_val = glxval; | |
1122 | else | |
1123 | amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); | |
1124 | } | |
1125 | ||
1126 | if (iommu_feature(iommu, FEATURE_GT) && | |
1127 | iommu_feature(iommu, FEATURE_PPR)) { | |
1128 | iommu->is_iommu_v2 = true; | |
1129 | amd_iommu_v2_present = true; | |
1130 | } | |
1131 | ||
1132 | if (iommu_feature(iommu, FEATURE_PPR)) { | |
1133 | iommu->ppr_log = alloc_ppr_log(iommu); | |
1134 | if (!iommu->ppr_log) | |
1135 | return -ENOMEM; | |
1136 | } | |
1137 | ||
1138 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) | |
1139 | amd_iommu_np_cache = true; | |
1140 | ||
1141 | if (is_rd890_iommu(iommu->dev)) { | |
1142 | int i, j; | |
1143 | ||
1144 | iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number, | |
1145 | PCI_DEVFN(0, 0)); | |
1146 | ||
1147 | /* | |
1148 | * Some rd890 systems may not be fully reconfigured by the | |
1149 | * BIOS, so it's necessary for us to store this information so | |
1150 | * it can be reprogrammed on resume | |
1151 | */ | |
1152 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1153 | &iommu->stored_addr_lo); | |
1154 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1155 | &iommu->stored_addr_hi); | |
1156 | ||
1157 | /* Low bit locks writes to configuration space */ | |
1158 | iommu->stored_addr_lo &= ~1; | |
1159 | ||
1160 | for (i = 0; i < 6; i++) | |
1161 | for (j = 0; j < 0x12; j++) | |
1162 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | |
1163 | ||
1164 | for (i = 0; i < 0x83; i++) | |
1165 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | |
1166 | } | |
1167 | ||
1168 | return pci_enable_device(iommu->dev); | |
1169 | } | |
1170 | ||
4d121c32 JR |
1171 | static void print_iommu_info(void) |
1172 | { | |
1173 | static const char * const feat_str[] = { | |
1174 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | |
1175 | "IA", "GA", "HE", "PC" | |
1176 | }; | |
1177 | struct amd_iommu *iommu; | |
1178 | ||
1179 | for_each_iommu(iommu) { | |
1180 | int i; | |
1181 | ||
1182 | pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n", | |
1183 | dev_name(&iommu->dev->dev), iommu->cap_ptr); | |
1184 | ||
1185 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { | |
1186 | pr_info("AMD-Vi: Extended features: "); | |
2bd5ed00 | 1187 | for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { |
4d121c32 JR |
1188 | if (iommu_feature(iommu, (1ULL << i))) |
1189 | pr_cont(" %s", feat_str[i]); | |
1190 | } | |
1191 | } | |
1192 | pr_cont("\n"); | |
1193 | } | |
1194 | } | |
1195 | ||
2c0ae172 | 1196 | static int __init amd_iommu_init_pci(void) |
23c742db JR |
1197 | { |
1198 | struct amd_iommu *iommu; | |
1199 | int ret = 0; | |
1200 | ||
1201 | for_each_iommu(iommu) { | |
1202 | ret = iommu_init_pci(iommu); | |
1203 | if (ret) | |
1204 | break; | |
1205 | } | |
1206 | ||
23c742db JR |
1207 | ret = amd_iommu_init_devices(); |
1208 | ||
4d121c32 JR |
1209 | print_iommu_info(); |
1210 | ||
23c742db JR |
1211 | return ret; |
1212 | } | |
1213 | ||
a80dc3e0 JR |
1214 | /**************************************************************************** |
1215 | * | |
1216 | * The following functions initialize the MSI interrupts for all IOMMUs | |
1217 | * in the system. Its a bit challenging because there could be multiple | |
1218 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
1219 | * pci_dev. | |
1220 | * | |
1221 | ****************************************************************************/ | |
1222 | ||
9f800de3 | 1223 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1224 | { |
1225 | int r; | |
a80dc3e0 | 1226 | |
9ddd592a JR |
1227 | r = pci_enable_msi(iommu->dev); |
1228 | if (r) | |
1229 | return r; | |
a80dc3e0 | 1230 | |
72fe00f0 JR |
1231 | r = request_threaded_irq(iommu->dev->irq, |
1232 | amd_iommu_int_handler, | |
1233 | amd_iommu_int_thread, | |
1234 | 0, "AMD-Vi", | |
1235 | iommu->dev); | |
a80dc3e0 JR |
1236 | |
1237 | if (r) { | |
1238 | pci_disable_msi(iommu->dev); | |
9ddd592a | 1239 | return r; |
a80dc3e0 JR |
1240 | } |
1241 | ||
fab6afa3 | 1242 | iommu->int_enabled = true; |
1a29ac01 | 1243 | |
a80dc3e0 JR |
1244 | return 0; |
1245 | } | |
1246 | ||
05f92db9 | 1247 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 | 1248 | { |
9ddd592a JR |
1249 | int ret; |
1250 | ||
a80dc3e0 | 1251 | if (iommu->int_enabled) |
9ddd592a | 1252 | goto enable_faults; |
a80dc3e0 | 1253 | |
d91cecdd | 1254 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
9ddd592a JR |
1255 | ret = iommu_setup_msi(iommu); |
1256 | else | |
1257 | ret = -ENODEV; | |
1258 | ||
1259 | if (ret) | |
1260 | return ret; | |
a80dc3e0 | 1261 | |
9ddd592a JR |
1262 | enable_faults: |
1263 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
a80dc3e0 | 1264 | |
9ddd592a JR |
1265 | if (iommu->ppr_log != NULL) |
1266 | iommu_feature_enable(iommu, CONTROL_PPFINT_EN); | |
1267 | ||
1268 | return 0; | |
a80dc3e0 JR |
1269 | } |
1270 | ||
b65233a9 JR |
1271 | /**************************************************************************** |
1272 | * | |
1273 | * The next functions belong to the third pass of parsing the ACPI | |
1274 | * table. In this last pass the memory mapping requirements are | |
1275 | * gathered (like exclusion and unity mapping reanges). | |
1276 | * | |
1277 | ****************************************************************************/ | |
1278 | ||
be2a022c JR |
1279 | static void __init free_unity_maps(void) |
1280 | { | |
1281 | struct unity_map_entry *entry, *next; | |
1282 | ||
1283 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1284 | list_del(&entry->list); | |
1285 | kfree(entry); | |
1286 | } | |
1287 | } | |
1288 | ||
b65233a9 | 1289 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1290 | static int __init init_exclusion_range(struct ivmd_header *m) |
1291 | { | |
1292 | int i; | |
1293 | ||
1294 | switch (m->type) { | |
1295 | case ACPI_IVMD_TYPE: | |
1296 | set_device_exclusion_range(m->devid, m); | |
1297 | break; | |
1298 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1299 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1300 | set_device_exclusion_range(i, m); |
1301 | break; | |
1302 | case ACPI_IVMD_TYPE_RANGE: | |
1303 | for (i = m->devid; i <= m->aux; ++i) | |
1304 | set_device_exclusion_range(i, m); | |
1305 | break; | |
1306 | default: | |
1307 | break; | |
1308 | } | |
1309 | ||
1310 | return 0; | |
1311 | } | |
1312 | ||
b65233a9 | 1313 | /* called for unity map ACPI definition */ |
be2a022c JR |
1314 | static int __init init_unity_map_range(struct ivmd_header *m) |
1315 | { | |
98f1ad25 | 1316 | struct unity_map_entry *e = NULL; |
02acc43a | 1317 | char *s; |
be2a022c JR |
1318 | |
1319 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1320 | if (e == NULL) | |
1321 | return -ENOMEM; | |
1322 | ||
1323 | switch (m->type) { | |
1324 | default: | |
0bc252f4 JR |
1325 | kfree(e); |
1326 | return 0; | |
be2a022c | 1327 | case ACPI_IVMD_TYPE: |
02acc43a | 1328 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1329 | e->devid_start = e->devid_end = m->devid; |
1330 | break; | |
1331 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1332 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1333 | e->devid_start = 0; |
1334 | e->devid_end = amd_iommu_last_bdf; | |
1335 | break; | |
1336 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1337 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1338 | e->devid_start = m->devid; |
1339 | e->devid_end = m->aux; | |
1340 | break; | |
1341 | } | |
1342 | e->address_start = PAGE_ALIGN(m->range_start); | |
1343 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1344 | e->prot = m->flags >> 1; | |
1345 | ||
02acc43a JR |
1346 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1347 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1348 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1349 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1350 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1351 | e->address_start, e->address_end, m->flags); | |
1352 | ||
be2a022c JR |
1353 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
b65233a9 | 1358 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1359 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1360 | { | |
1361 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1362 | struct ivmd_header *m; | |
1363 | ||
be2a022c JR |
1364 | end += table->length; |
1365 | p += IVRS_HEADER_LENGTH; | |
1366 | ||
1367 | while (p < end) { | |
1368 | m = (struct ivmd_header *)p; | |
1369 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1370 | init_exclusion_range(m); | |
1371 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1372 | init_unity_map_range(m); | |
1373 | ||
1374 | p += m->length; | |
1375 | } | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
9f5f5fb3 JR |
1380 | /* |
1381 | * Init the device table to not allow DMA access for devices and | |
1382 | * suppress all page faults | |
1383 | */ | |
33f28c59 | 1384 | static void init_device_table_dma(void) |
9f5f5fb3 | 1385 | { |
0de66d5b | 1386 | u32 devid; |
9f5f5fb3 JR |
1387 | |
1388 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1389 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1390 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1391 | } |
1392 | } | |
1393 | ||
33f28c59 JR |
1394 | static void init_device_table(void) |
1395 | { | |
1396 | u32 devid; | |
1397 | ||
1398 | if (!amd_iommu_irq_remap) | |
1399 | return; | |
1400 | ||
1401 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1402 | set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); | |
1403 | } | |
1404 | ||
e9bf5197 JR |
1405 | static void iommu_init_flags(struct amd_iommu *iommu) |
1406 | { | |
1407 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1408 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1409 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1410 | ||
1411 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1412 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1413 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1414 | ||
1415 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1416 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1417 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1418 | ||
1419 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1420 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1421 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1422 | ||
1423 | /* | |
1424 | * make IOMMU memory accesses cache coherent | |
1425 | */ | |
1426 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1456e9d2 JR |
1427 | |
1428 | /* Set IOTLB invalidation timeout to 1s */ | |
1429 | iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); | |
e9bf5197 JR |
1430 | } |
1431 | ||
5bcd757f | 1432 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) |
4c894f47 | 1433 | { |
5bcd757f MG |
1434 | int i, j; |
1435 | u32 ioc_feature_control; | |
c1bf94ec | 1436 | struct pci_dev *pdev = iommu->root_pdev; |
5bcd757f MG |
1437 | |
1438 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | |
c1bf94ec | 1439 | if (!is_rd890_iommu(iommu->dev) || !pdev) |
5bcd757f MG |
1440 | return; |
1441 | ||
1442 | /* | |
1443 | * First, we need to ensure that the iommu is enabled. This is | |
1444 | * controlled by a register in the northbridge | |
1445 | */ | |
5bcd757f MG |
1446 | |
1447 | /* Select Northbridge indirect register 0x75 and enable writing */ | |
1448 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | |
1449 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | |
1450 | ||
1451 | /* Enable the iommu */ | |
1452 | if (!(ioc_feature_control & 0x1)) | |
1453 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | |
1454 | ||
5bcd757f MG |
1455 | /* Restore the iommu BAR */ |
1456 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1457 | iommu->stored_addr_lo); | |
1458 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1459 | iommu->stored_addr_hi); | |
1460 | ||
1461 | /* Restore the l1 indirect regs for each of the 6 l1s */ | |
1462 | for (i = 0; i < 6; i++) | |
1463 | for (j = 0; j < 0x12; j++) | |
1464 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | |
1465 | ||
1466 | /* Restore the l2 indirect regs */ | |
1467 | for (i = 0; i < 0x83; i++) | |
1468 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | |
1469 | ||
1470 | /* Lock PCI setup registers */ | |
1471 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1472 | iommu->stored_addr_lo | 1); | |
4c894f47 JR |
1473 | } |
1474 | ||
b65233a9 JR |
1475 | /* |
1476 | * This function finally enables all IOMMUs found in the system after | |
1477 | * they have been initialized | |
1478 | */ | |
11ee5ac4 | 1479 | static void early_enable_iommus(void) |
8736197b JR |
1480 | { |
1481 | struct amd_iommu *iommu; | |
1482 | ||
3bd22172 | 1483 | for_each_iommu(iommu) { |
a8c485bb | 1484 | iommu_disable(iommu); |
e9bf5197 | 1485 | iommu_init_flags(iommu); |
58492e12 JR |
1486 | iommu_set_device_table(iommu); |
1487 | iommu_enable_command_buffer(iommu); | |
1488 | iommu_enable_event_buffer(iommu); | |
8736197b JR |
1489 | iommu_set_exclusion_range(iommu); |
1490 | iommu_enable(iommu); | |
7d0c5cc5 | 1491 | iommu_flush_all_caches(iommu); |
8736197b JR |
1492 | } |
1493 | } | |
1494 | ||
11ee5ac4 JR |
1495 | static void enable_iommus_v2(void) |
1496 | { | |
1497 | struct amd_iommu *iommu; | |
1498 | ||
1499 | for_each_iommu(iommu) { | |
1500 | iommu_enable_ppr_log(iommu); | |
1501 | iommu_enable_gt(iommu); | |
1502 | } | |
1503 | } | |
1504 | ||
1505 | static void enable_iommus(void) | |
1506 | { | |
1507 | early_enable_iommus(); | |
1508 | ||
1509 | enable_iommus_v2(); | |
1510 | } | |
1511 | ||
92ac4320 JR |
1512 | static void disable_iommus(void) |
1513 | { | |
1514 | struct amd_iommu *iommu; | |
1515 | ||
1516 | for_each_iommu(iommu) | |
1517 | iommu_disable(iommu); | |
1518 | } | |
1519 | ||
7441e9cb JR |
1520 | /* |
1521 | * Suspend/Resume support | |
1522 | * disable suspend until real resume implemented | |
1523 | */ | |
1524 | ||
f3c6ea1b | 1525 | static void amd_iommu_resume(void) |
7441e9cb | 1526 | { |
5bcd757f MG |
1527 | struct amd_iommu *iommu; |
1528 | ||
1529 | for_each_iommu(iommu) | |
1530 | iommu_apply_resume_quirks(iommu); | |
1531 | ||
736501ee JR |
1532 | /* re-load the hardware */ |
1533 | enable_iommus(); | |
3d9761e7 JR |
1534 | |
1535 | amd_iommu_enable_interrupts(); | |
7441e9cb JR |
1536 | } |
1537 | ||
f3c6ea1b | 1538 | static int amd_iommu_suspend(void) |
7441e9cb | 1539 | { |
736501ee JR |
1540 | /* disable IOMMUs to go out of the way for BIOS */ |
1541 | disable_iommus(); | |
1542 | ||
1543 | return 0; | |
7441e9cb JR |
1544 | } |
1545 | ||
f3c6ea1b | 1546 | static struct syscore_ops amd_iommu_syscore_ops = { |
7441e9cb JR |
1547 | .suspend = amd_iommu_suspend, |
1548 | .resume = amd_iommu_resume, | |
1549 | }; | |
1550 | ||
8704a1ba JR |
1551 | static void __init free_on_init_error(void) |
1552 | { | |
0ea2c422 JR |
1553 | free_pages((unsigned long)irq_lookup_table, |
1554 | get_order(rlookup_table_size)); | |
1555 | ||
05152a04 JR |
1556 | if (amd_iommu_irq_cache) { |
1557 | kmem_cache_destroy(amd_iommu_irq_cache); | |
1558 | amd_iommu_irq_cache = NULL; | |
0ea2c422 | 1559 | |
05152a04 JR |
1560 | } |
1561 | ||
8704a1ba JR |
1562 | amd_iommu_uninit_devices(); |
1563 | ||
1564 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, | |
1565 | get_order(MAX_DOMAIN_ID/8)); | |
1566 | ||
1567 | free_pages((unsigned long)amd_iommu_rlookup_table, | |
1568 | get_order(rlookup_table_size)); | |
1569 | ||
1570 | free_pages((unsigned long)amd_iommu_alias_table, | |
1571 | get_order(alias_table_size)); | |
1572 | ||
1573 | free_pages((unsigned long)amd_iommu_dev_table, | |
1574 | get_order(dev_table_size)); | |
1575 | ||
1576 | free_iommu_all(); | |
1577 | ||
1578 | free_unity_maps(); | |
1579 | ||
1580 | #ifdef CONFIG_GART_IOMMU | |
1581 | /* | |
1582 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1583 | * if possible. | |
1584 | */ | |
1585 | gart_iommu_init(); | |
1586 | ||
1587 | #endif | |
1588 | } | |
1589 | ||
eb1eb7ae JR |
1590 | static bool __init check_ioapic_information(void) |
1591 | { | |
1592 | int idx; | |
1593 | ||
1594 | for (idx = 0; idx < nr_ioapics; idx++) { | |
1595 | int id = mpc_ioapic_id(idx); | |
1596 | ||
1597 | if (get_ioapic_devid(id) < 0) { | |
1598 | pr_err(FW_BUG "AMD-Vi: IO-APIC[%d] not in IVRS table\n", id); | |
1599 | pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug\n"); | |
1600 | return false; | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | return true; | |
1605 | } | |
1606 | ||
b65233a9 | 1607 | /* |
8704a1ba JR |
1608 | * This is the hardware init function for AMD IOMMU in the system. |
1609 | * This function is called either from amd_iommu_init or from the interrupt | |
1610 | * remapping setup code. | |
b65233a9 JR |
1611 | * |
1612 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1613 | * three times: | |
1614 | * | |
1615 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1616 | * Upon this information the size of the data structures is | |
1617 | * determined that needs to be allocated. | |
1618 | * | |
1619 | * 2 pass) Initialize the data structures just allocated with the | |
1620 | * information in the ACPI table about available AMD IOMMUs | |
1621 | * in the system. It also maps the PCI devices in the | |
1622 | * system to specific IOMMUs | |
1623 | * | |
1624 | * 3 pass) After the basic data structures are allocated and | |
1625 | * initialized we update them with information about memory | |
1626 | * remapping requirements parsed out of the ACPI table in | |
1627 | * this last pass. | |
1628 | * | |
8704a1ba JR |
1629 | * After everything is set up the IOMMUs are enabled and the necessary |
1630 | * hotplug and suspend notifiers are registered. | |
b65233a9 | 1631 | */ |
643511b3 | 1632 | static int __init early_amd_iommu_init(void) |
fe74c9cf | 1633 | { |
02f3b3f5 JR |
1634 | struct acpi_table_header *ivrs_base; |
1635 | acpi_size ivrs_size; | |
1636 | acpi_status status; | |
fe74c9cf JR |
1637 | int i, ret = 0; |
1638 | ||
643511b3 | 1639 | if (!amd_iommu_detected) |
8704a1ba JR |
1640 | return -ENODEV; |
1641 | ||
02f3b3f5 JR |
1642 | status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size); |
1643 | if (status == AE_NOT_FOUND) | |
1644 | return -ENODEV; | |
1645 | else if (ACPI_FAILURE(status)) { | |
1646 | const char *err = acpi_format_exception(status); | |
1647 | pr_err("AMD-Vi: IVRS table error: %s\n", err); | |
1648 | return -EINVAL; | |
1649 | } | |
1650 | ||
fe74c9cf JR |
1651 | /* |
1652 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1653 | * we need to handle. Upon this information the shared data | |
1654 | * structures for the IOMMUs in the system will be allocated | |
1655 | */ | |
2c0ae172 JR |
1656 | ret = find_last_devid_acpi(ivrs_base); |
1657 | if (ret) | |
3551a708 JR |
1658 | goto out; |
1659 | ||
c571484e JR |
1660 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1661 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1662 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf | 1663 | |
fe74c9cf | 1664 | /* Device table - directly used by all IOMMUs */ |
8704a1ba | 1665 | ret = -ENOMEM; |
5dc8bff0 | 1666 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1667 | get_order(dev_table_size)); |
1668 | if (amd_iommu_dev_table == NULL) | |
1669 | goto out; | |
1670 | ||
1671 | /* | |
1672 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1673 | * IOMMU see for that device | |
1674 | */ | |
1675 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1676 | get_order(alias_table_size)); | |
1677 | if (amd_iommu_alias_table == NULL) | |
2c0ae172 | 1678 | goto out; |
fe74c9cf JR |
1679 | |
1680 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1681 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1682 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1683 | get_order(rlookup_table_size)); |
1684 | if (amd_iommu_rlookup_table == NULL) | |
2c0ae172 | 1685 | goto out; |
fe74c9cf | 1686 | |
5dc8bff0 JR |
1687 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1688 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1689 | get_order(MAX_DOMAIN_ID/8)); |
1690 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
2c0ae172 | 1691 | goto out; |
fe74c9cf JR |
1692 | |
1693 | /* | |
5dc8bff0 | 1694 | * let all alias entries point to itself |
fe74c9cf | 1695 | */ |
3a61ec38 | 1696 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1697 | amd_iommu_alias_table[i] = i; |
1698 | ||
fe74c9cf JR |
1699 | /* |
1700 | * never allocate domain 0 because its used as the non-allocated and | |
1701 | * error value placeholder | |
1702 | */ | |
1703 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1704 | ||
aeb26f55 JR |
1705 | spin_lock_init(&amd_iommu_pd_lock); |
1706 | ||
fe74c9cf JR |
1707 | /* |
1708 | * now the data structures are allocated and basically initialized | |
1709 | * start the real acpi table scan | |
1710 | */ | |
02f3b3f5 JR |
1711 | ret = init_iommu_all(ivrs_base); |
1712 | if (ret) | |
2c0ae172 | 1713 | goto out; |
fe74c9cf | 1714 | |
eb1eb7ae JR |
1715 | if (amd_iommu_irq_remap) |
1716 | amd_iommu_irq_remap = check_ioapic_information(); | |
1717 | ||
05152a04 JR |
1718 | if (amd_iommu_irq_remap) { |
1719 | /* | |
1720 | * Interrupt remapping enabled, create kmem_cache for the | |
1721 | * remapping tables. | |
1722 | */ | |
1723 | amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", | |
1724 | MAX_IRQS_PER_TABLE * sizeof(u32), | |
1725 | IRQ_TABLE_ALIGNMENT, | |
1726 | 0, NULL); | |
1727 | if (!amd_iommu_irq_cache) | |
1728 | goto out; | |
0ea2c422 JR |
1729 | |
1730 | irq_lookup_table = (void *)__get_free_pages( | |
1731 | GFP_KERNEL | __GFP_ZERO, | |
1732 | get_order(rlookup_table_size)); | |
1733 | if (!irq_lookup_table) | |
1734 | goto out; | |
05152a04 JR |
1735 | } |
1736 | ||
02f3b3f5 JR |
1737 | ret = init_memory_definitions(ivrs_base); |
1738 | if (ret) | |
2c0ae172 | 1739 | goto out; |
3551a708 | 1740 | |
eb1eb7ae JR |
1741 | /* init the device table */ |
1742 | init_device_table(); | |
1743 | ||
8704a1ba | 1744 | out: |
02f3b3f5 JR |
1745 | /* Don't leak any ACPI memory */ |
1746 | early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size); | |
1747 | ivrs_base = NULL; | |
1748 | ||
643511b3 JR |
1749 | return ret; |
1750 | } | |
1751 | ||
ae295142 | 1752 | static int amd_iommu_enable_interrupts(void) |
3d9761e7 JR |
1753 | { |
1754 | struct amd_iommu *iommu; | |
1755 | int ret = 0; | |
1756 | ||
1757 | for_each_iommu(iommu) { | |
1758 | ret = iommu_init_msi(iommu); | |
1759 | if (ret) | |
1760 | goto out; | |
1761 | } | |
1762 | ||
1763 | out: | |
1764 | return ret; | |
1765 | } | |
1766 | ||
02f3b3f5 JR |
1767 | static bool detect_ivrs(void) |
1768 | { | |
1769 | struct acpi_table_header *ivrs_base; | |
1770 | acpi_size ivrs_size; | |
1771 | acpi_status status; | |
1772 | ||
1773 | status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size); | |
1774 | if (status == AE_NOT_FOUND) | |
1775 | return false; | |
1776 | else if (ACPI_FAILURE(status)) { | |
1777 | const char *err = acpi_format_exception(status); | |
1778 | pr_err("AMD-Vi: IVRS table error: %s\n", err); | |
1779 | return false; | |
1780 | } | |
1781 | ||
1782 | early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size); | |
1783 | ||
1adb7d31 JR |
1784 | /* Make sure ACS will be enabled during PCI probe */ |
1785 | pci_request_acs(); | |
1786 | ||
05152a04 JR |
1787 | if (!disable_irq_remap) |
1788 | amd_iommu_irq_remap = true; | |
1789 | ||
02f3b3f5 JR |
1790 | return true; |
1791 | } | |
1792 | ||
b9b1ce70 JR |
1793 | static int amd_iommu_init_dma(void) |
1794 | { | |
33f28c59 | 1795 | struct amd_iommu *iommu; |
b9b1ce70 JR |
1796 | int ret; |
1797 | ||
33f28c59 JR |
1798 | init_device_table_dma(); |
1799 | ||
1800 | for_each_iommu(iommu) | |
1801 | iommu_flush_all_caches(iommu); | |
1802 | ||
b9b1ce70 JR |
1803 | if (iommu_pass_through) |
1804 | ret = amd_iommu_init_passthrough(); | |
1805 | else | |
1806 | ret = amd_iommu_init_dma_ops(); | |
1807 | ||
1808 | if (ret) | |
1809 | return ret; | |
1810 | ||
1811 | amd_iommu_init_api(); | |
1812 | ||
1813 | amd_iommu_init_notifier(); | |
1814 | ||
1815 | return 0; | |
1816 | } | |
1817 | ||
2c0ae172 | 1818 | /**************************************************************************** |
8704a1ba | 1819 | * |
2c0ae172 JR |
1820 | * AMD IOMMU Initialization State Machine |
1821 | * | |
1822 | ****************************************************************************/ | |
1823 | ||
1824 | static int __init state_next(void) | |
8704a1ba JR |
1825 | { |
1826 | int ret = 0; | |
1827 | ||
2c0ae172 JR |
1828 | switch (init_state) { |
1829 | case IOMMU_START_STATE: | |
1830 | if (!detect_ivrs()) { | |
1831 | init_state = IOMMU_NOT_FOUND; | |
1832 | ret = -ENODEV; | |
1833 | } else { | |
1834 | init_state = IOMMU_IVRS_DETECTED; | |
1835 | } | |
1836 | break; | |
1837 | case IOMMU_IVRS_DETECTED: | |
1838 | ret = early_amd_iommu_init(); | |
1839 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; | |
1840 | break; | |
1841 | case IOMMU_ACPI_FINISHED: | |
1842 | early_enable_iommus(); | |
1843 | register_syscore_ops(&amd_iommu_syscore_ops); | |
1844 | x86_platform.iommu_shutdown = disable_iommus; | |
1845 | init_state = IOMMU_ENABLED; | |
1846 | break; | |
1847 | case IOMMU_ENABLED: | |
1848 | ret = amd_iommu_init_pci(); | |
1849 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; | |
1850 | enable_iommus_v2(); | |
1851 | break; | |
1852 | case IOMMU_PCI_INIT: | |
1853 | ret = amd_iommu_enable_interrupts(); | |
1854 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; | |
1855 | break; | |
1856 | case IOMMU_INTERRUPTS_EN: | |
1857 | ret = amd_iommu_init_dma(); | |
1858 | init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS; | |
1859 | break; | |
1860 | case IOMMU_DMA_OPS: | |
1861 | init_state = IOMMU_INITIALIZED; | |
1862 | break; | |
1863 | case IOMMU_INITIALIZED: | |
1864 | /* Nothing to do */ | |
1865 | break; | |
1866 | case IOMMU_NOT_FOUND: | |
1867 | case IOMMU_INIT_ERROR: | |
1868 | /* Error states => do nothing */ | |
1869 | ret = -EINVAL; | |
1870 | break; | |
1871 | default: | |
1872 | /* Unknown state */ | |
1873 | BUG(); | |
1874 | } | |
3d9761e7 | 1875 | |
2c0ae172 JR |
1876 | return ret; |
1877 | } | |
7441e9cb | 1878 | |
2c0ae172 JR |
1879 | static int __init iommu_go_to_state(enum iommu_init_state state) |
1880 | { | |
1881 | int ret = 0; | |
f5325094 | 1882 | |
2c0ae172 JR |
1883 | while (init_state != state) { |
1884 | ret = state_next(); | |
1885 | if (init_state == IOMMU_NOT_FOUND || | |
1886 | init_state == IOMMU_INIT_ERROR) | |
1887 | break; | |
1888 | } | |
f2f12b6f | 1889 | |
fe74c9cf | 1890 | return ret; |
2c0ae172 | 1891 | } |
fe74c9cf | 1892 | |
d7f07769 | 1893 | |
d7f07769 | 1894 | |
2c0ae172 JR |
1895 | /* |
1896 | * This is the core init function for AMD IOMMU hardware in the system. | |
1897 | * This function is called from the generic x86 DMA layer initialization | |
1898 | * code. | |
1899 | */ | |
1900 | static int __init amd_iommu_init(void) | |
1901 | { | |
1902 | int ret; | |
1903 | ||
1904 | ret = iommu_go_to_state(IOMMU_INITIALIZED); | |
1905 | if (ret) { | |
1906 | disable_iommus(); | |
1907 | free_on_init_error(); | |
1908 | } | |
1909 | ||
1910 | return ret; | |
fe74c9cf JR |
1911 | } |
1912 | ||
b65233a9 JR |
1913 | /**************************************************************************** |
1914 | * | |
1915 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1916 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1917 | * IOMMUs | |
1918 | * | |
1919 | ****************************************************************************/ | |
480125ba | 1920 | int __init amd_iommu_detect(void) |
ae7877de | 1921 | { |
2c0ae172 | 1922 | int ret; |
02f3b3f5 | 1923 | |
75f1cdf1 | 1924 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
480125ba | 1925 | return -ENODEV; |
ae7877de | 1926 | |
a5235725 | 1927 | if (amd_iommu_disabled) |
480125ba | 1928 | return -ENODEV; |
a5235725 | 1929 | |
2c0ae172 JR |
1930 | ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); |
1931 | if (ret) | |
1932 | return ret; | |
11bd04f6 | 1933 | |
02f3b3f5 JR |
1934 | amd_iommu_detected = true; |
1935 | iommu_detected = 1; | |
1936 | x86_init.iommu.iommu_init = amd_iommu_init; | |
1937 | ||
02f3b3f5 | 1938 | return 0; |
ae7877de JR |
1939 | } |
1940 | ||
b65233a9 JR |
1941 | /**************************************************************************** |
1942 | * | |
1943 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1944 | * options. | |
1945 | * | |
1946 | ****************************************************************************/ | |
1947 | ||
fefda117 JR |
1948 | static int __init parse_amd_iommu_dump(char *str) |
1949 | { | |
1950 | amd_iommu_dump = true; | |
1951 | ||
1952 | return 1; | |
1953 | } | |
1954 | ||
918ad6c5 JR |
1955 | static int __init parse_amd_iommu_options(char *str) |
1956 | { | |
1957 | for (; *str; ++str) { | |
695b5676 | 1958 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1959 | amd_iommu_unmap_flush = true; |
a5235725 JR |
1960 | if (strncmp(str, "off", 3) == 0) |
1961 | amd_iommu_disabled = true; | |
5abcdba4 JR |
1962 | if (strncmp(str, "force_isolation", 15) == 0) |
1963 | amd_iommu_force_isolation = true; | |
918ad6c5 JR |
1964 | } |
1965 | ||
1966 | return 1; | |
1967 | } | |
1968 | ||
fefda117 | 1969 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1970 | __setup("amd_iommu=", parse_amd_iommu_options); |
22e6daf4 KRW |
1971 | |
1972 | IOMMU_INIT_FINISH(amd_iommu_detect, | |
1973 | gart_iommu_hole_init, | |
98f1ad25 JR |
1974 | NULL, |
1975 | NULL); | |
400a28a0 JR |
1976 | |
1977 | bool amd_iommu_v2_supported(void) | |
1978 | { | |
1979 | return amd_iommu_v2_present; | |
1980 | } | |
1981 | EXPORT_SYMBOL(amd_iommu_v2_supported); |