Commit | Line | Data |
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e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
d73a6d72 | 48 | unsigned mmu_notifier_count; /* Counting nested mmu_notifier |
e79df31c | 49 | calls */ |
ed96f228 JR |
50 | struct task_struct *task; /* Task bound to this PASID */ |
51 | struct mm_struct *mm; /* mm_struct for the faults */ | |
ff6d0cce | 52 | struct mmu_notifier mn; /* mmu_notifier handle */ |
ed96f228 JR |
53 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
54 | struct device_state *device_state; /* Link to our device_state */ | |
55 | int pasid; /* PASID index */ | |
d73a6d72 JR |
56 | spinlock_t lock; /* Protect pri_queues and |
57 | mmu_notifer_count */ | |
028eeacc | 58 | wait_queue_head_t wq; /* To wait for count == 0 */ |
ed96f228 JR |
59 | }; |
60 | ||
61 | struct device_state { | |
741669c7 JR |
62 | struct list_head list; |
63 | u16 devid; | |
ed96f228 JR |
64 | atomic_t count; |
65 | struct pci_dev *pdev; | |
66 | struct pasid_state **states; | |
67 | struct iommu_domain *domain; | |
68 | int pasid_levels; | |
69 | int max_pasids; | |
175d6146 | 70 | amd_iommu_invalid_ppr_cb inv_ppr_cb; |
bc21662f | 71 | amd_iommu_invalidate_ctx inv_ctx_cb; |
ed96f228 | 72 | spinlock_t lock; |
028eeacc JR |
73 | wait_queue_head_t wq; |
74 | }; | |
75 | ||
76 | struct fault { | |
77 | struct work_struct work; | |
78 | struct device_state *dev_state; | |
79 | struct pasid_state *state; | |
80 | struct mm_struct *mm; | |
81 | u64 address; | |
82 | u16 devid; | |
83 | u16 pasid; | |
84 | u16 tag; | |
85 | u16 finish; | |
86 | u16 flags; | |
ed96f228 JR |
87 | }; |
88 | ||
741669c7 | 89 | static LIST_HEAD(state_list); |
ed96f228 JR |
90 | static spinlock_t state_lock; |
91 | ||
028eeacc JR |
92 | static struct workqueue_struct *iommu_wq; |
93 | ||
8736b2c3 JR |
94 | /* |
95 | * Empty page table - Used between | |
96 | * mmu_notifier_invalidate_range_start and | |
97 | * mmu_notifier_invalidate_range_end | |
98 | */ | |
99 | static u64 *empty_page_table; | |
100 | ||
2d5503b6 JR |
101 | static void free_pasid_states(struct device_state *dev_state); |
102 | static void unbind_pasid(struct device_state *dev_state, int pasid); | |
ed96f228 JR |
103 | |
104 | static u16 device_id(struct pci_dev *pdev) | |
105 | { | |
106 | u16 devid; | |
107 | ||
108 | devid = pdev->bus->number; | |
109 | devid = (devid << 8) | pdev->devfn; | |
110 | ||
111 | return devid; | |
112 | } | |
113 | ||
b87d2d7c JR |
114 | static struct device_state *__get_device_state(u16 devid) |
115 | { | |
741669c7 JR |
116 | struct device_state *dev_state; |
117 | ||
118 | list_for_each_entry(dev_state, &state_list, list) { | |
119 | if (dev_state->devid == devid) | |
120 | return dev_state; | |
121 | } | |
122 | ||
123 | return NULL; | |
b87d2d7c JR |
124 | } |
125 | ||
ed96f228 JR |
126 | static struct device_state *get_device_state(u16 devid) |
127 | { | |
128 | struct device_state *dev_state; | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&state_lock, flags); | |
b87d2d7c | 132 | dev_state = __get_device_state(devid); |
ed96f228 JR |
133 | if (dev_state != NULL) |
134 | atomic_inc(&dev_state->count); | |
135 | spin_unlock_irqrestore(&state_lock, flags); | |
136 | ||
137 | return dev_state; | |
138 | } | |
139 | ||
140 | static void free_device_state(struct device_state *dev_state) | |
141 | { | |
2d5503b6 JR |
142 | /* |
143 | * First detach device from domain - No more PRI requests will arrive | |
144 | * from that device after it is unbound from the IOMMUv2 domain. | |
145 | */ | |
ed96f228 | 146 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
147 | |
148 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 149 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
150 | |
151 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
152 | kfree(dev_state); |
153 | } | |
154 | ||
155 | static void put_device_state(struct device_state *dev_state) | |
156 | { | |
157 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 158 | wake_up(&dev_state->wq); |
ed96f228 JR |
159 | } |
160 | ||
028eeacc JR |
161 | static void put_device_state_wait(struct device_state *dev_state) |
162 | { | |
163 | DEFINE_WAIT(wait); | |
164 | ||
165 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
166 | if (!atomic_dec_and_test(&dev_state->count)) | |
167 | schedule(); | |
168 | finish_wait(&dev_state->wq, &wait); | |
169 | ||
170 | free_device_state(dev_state); | |
171 | } | |
8736b2c3 | 172 | |
2d5503b6 JR |
173 | /* Must be called under dev_state->lock */ |
174 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
175 | int pasid, bool alloc) | |
176 | { | |
177 | struct pasid_state **root, **ptr; | |
178 | int level, index; | |
179 | ||
180 | level = dev_state->pasid_levels; | |
181 | root = dev_state->states; | |
182 | ||
183 | while (true) { | |
184 | ||
185 | index = (pasid >> (9 * level)) & 0x1ff; | |
186 | ptr = &root[index]; | |
187 | ||
188 | if (level == 0) | |
189 | break; | |
190 | ||
191 | if (*ptr == NULL) { | |
192 | if (!alloc) | |
193 | return NULL; | |
194 | ||
195 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
196 | if (*ptr == NULL) | |
197 | return NULL; | |
198 | } | |
199 | ||
200 | root = (struct pasid_state **)*ptr; | |
201 | level -= 1; | |
202 | } | |
203 | ||
204 | return ptr; | |
205 | } | |
206 | ||
207 | static int set_pasid_state(struct device_state *dev_state, | |
208 | struct pasid_state *pasid_state, | |
209 | int pasid) | |
210 | { | |
211 | struct pasid_state **ptr; | |
212 | unsigned long flags; | |
213 | int ret; | |
214 | ||
215 | spin_lock_irqsave(&dev_state->lock, flags); | |
216 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
217 | ||
218 | ret = -ENOMEM; | |
219 | if (ptr == NULL) | |
220 | goto out_unlock; | |
221 | ||
222 | ret = -ENOMEM; | |
223 | if (*ptr != NULL) | |
224 | goto out_unlock; | |
225 | ||
226 | *ptr = pasid_state; | |
227 | ||
228 | ret = 0; | |
229 | ||
230 | out_unlock: | |
231 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
236 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
237 | { | |
238 | struct pasid_state **ptr; | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&dev_state->lock, flags); | |
242 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
243 | ||
244 | if (ptr == NULL) | |
245 | goto out_unlock; | |
246 | ||
247 | *ptr = NULL; | |
248 | ||
249 | out_unlock: | |
250 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
251 | } | |
252 | ||
253 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
254 | int pasid) | |
255 | { | |
256 | struct pasid_state **ptr, *ret = NULL; | |
257 | unsigned long flags; | |
258 | ||
259 | spin_lock_irqsave(&dev_state->lock, flags); | |
260 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
261 | ||
262 | if (ptr == NULL) | |
263 | goto out_unlock; | |
264 | ||
265 | ret = *ptr; | |
266 | if (ret) | |
267 | atomic_inc(&ret->count); | |
268 | ||
269 | out_unlock: | |
270 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
275 | static void free_pasid_state(struct pasid_state *pasid_state) | |
276 | { | |
277 | kfree(pasid_state); | |
278 | } | |
279 | ||
280 | static void put_pasid_state(struct pasid_state *pasid_state) | |
281 | { | |
282 | if (atomic_dec_and_test(&pasid_state->count)) { | |
283 | put_device_state(pasid_state->device_state); | |
028eeacc | 284 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
285 | } |
286 | } | |
287 | ||
028eeacc JR |
288 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
289 | { | |
290 | DEFINE_WAIT(wait); | |
291 | ||
292 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
293 | ||
294 | if (atomic_dec_and_test(&pasid_state->count)) | |
295 | put_device_state(pasid_state->device_state); | |
296 | else | |
297 | schedule(); | |
298 | ||
299 | finish_wait(&pasid_state->wq, &wait); | |
300 | mmput(pasid_state->mm); | |
301 | free_pasid_state(pasid_state); | |
302 | } | |
303 | ||
8736b2c3 JR |
304 | static void __unbind_pasid(struct pasid_state *pasid_state) |
305 | { | |
306 | struct iommu_domain *domain; | |
307 | ||
308 | domain = pasid_state->device_state->domain; | |
309 | ||
310 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); | |
311 | clear_pasid_state(pasid_state->device_state, pasid_state->pasid); | |
312 | ||
313 | /* Make sure no more pending faults are in the queue */ | |
314 | flush_workqueue(iommu_wq); | |
8736b2c3 JR |
315 | } |
316 | ||
2d5503b6 JR |
317 | static void unbind_pasid(struct device_state *dev_state, int pasid) |
318 | { | |
319 | struct pasid_state *pasid_state; | |
320 | ||
321 | pasid_state = get_pasid_state(dev_state, pasid); | |
322 | if (pasid_state == NULL) | |
323 | return; | |
324 | ||
8736b2c3 | 325 | __unbind_pasid(pasid_state); |
c5db16ad | 326 | put_pasid_state(pasid_state); /* Reference taken in this function */ |
2d5503b6 JR |
327 | } |
328 | ||
329 | static void free_pasid_states_level1(struct pasid_state **tbl) | |
330 | { | |
331 | int i; | |
332 | ||
333 | for (i = 0; i < 512; ++i) { | |
334 | if (tbl[i] == NULL) | |
335 | continue; | |
336 | ||
337 | free_page((unsigned long)tbl[i]); | |
338 | } | |
339 | } | |
340 | ||
341 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
342 | { | |
343 | struct pasid_state **ptr; | |
344 | int i; | |
345 | ||
346 | for (i = 0; i < 512; ++i) { | |
347 | if (tbl[i] == NULL) | |
348 | continue; | |
349 | ||
350 | ptr = (struct pasid_state **)tbl[i]; | |
351 | free_pasid_states_level1(ptr); | |
352 | } | |
353 | } | |
354 | ||
355 | static void free_pasid_states(struct device_state *dev_state) | |
356 | { | |
357 | struct pasid_state *pasid_state; | |
358 | int i; | |
359 | ||
360 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
361 | pasid_state = get_pasid_state(dev_state, i); | |
362 | if (pasid_state == NULL) | |
363 | continue; | |
364 | ||
2d5503b6 | 365 | put_pasid_state(pasid_state); |
a40d4c67 JR |
366 | |
367 | /* | |
368 | * This will call the mn_release function and | |
369 | * unbind the PASID | |
370 | */ | |
371 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
c5db16ad JR |
372 | |
373 | put_pasid_state_wait(pasid_state); /* Reference taken in | |
374 | amd_iommu_pasid_bind */ | |
2d5503b6 JR |
375 | } |
376 | ||
377 | if (dev_state->pasid_levels == 2) | |
378 | free_pasid_states_level2(dev_state->states); | |
379 | else if (dev_state->pasid_levels == 1) | |
380 | free_pasid_states_level1(dev_state->states); | |
381 | else if (dev_state->pasid_levels != 0) | |
382 | BUG(); | |
383 | ||
384 | free_page((unsigned long)dev_state->states); | |
385 | } | |
386 | ||
8736b2c3 JR |
387 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
388 | { | |
389 | return container_of(mn, struct pasid_state, mn); | |
390 | } | |
391 | ||
392 | static void __mn_flush_page(struct mmu_notifier *mn, | |
393 | unsigned long address) | |
394 | { | |
395 | struct pasid_state *pasid_state; | |
396 | struct device_state *dev_state; | |
397 | ||
398 | pasid_state = mn_to_state(mn); | |
399 | dev_state = pasid_state->device_state; | |
400 | ||
401 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
402 | } | |
403 | ||
404 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
405 | struct mm_struct *mm, | |
406 | unsigned long address) | |
407 | { | |
408 | __mn_flush_page(mn, address); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | static void mn_change_pte(struct mmu_notifier *mn, | |
414 | struct mm_struct *mm, | |
415 | unsigned long address, | |
416 | pte_t pte) | |
417 | { | |
418 | __mn_flush_page(mn, address); | |
419 | } | |
420 | ||
421 | static void mn_invalidate_page(struct mmu_notifier *mn, | |
422 | struct mm_struct *mm, | |
423 | unsigned long address) | |
424 | { | |
425 | __mn_flush_page(mn, address); | |
426 | } | |
427 | ||
428 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
429 | struct mm_struct *mm, | |
430 | unsigned long start, unsigned long end) | |
431 | { | |
432 | struct pasid_state *pasid_state; | |
433 | struct device_state *dev_state; | |
d73a6d72 | 434 | unsigned long flags; |
8736b2c3 JR |
435 | |
436 | pasid_state = mn_to_state(mn); | |
437 | dev_state = pasid_state->device_state; | |
438 | ||
d73a6d72 JR |
439 | spin_lock_irqsave(&pasid_state->lock, flags); |
440 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
441 | amd_iommu_domain_set_gcr3(dev_state->domain, |
442 | pasid_state->pasid, | |
443 | __pa(empty_page_table)); | |
444 | } | |
d73a6d72 JR |
445 | pasid_state->mmu_notifier_count += 1; |
446 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
8736b2c3 JR |
447 | } |
448 | ||
449 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
450 | struct mm_struct *mm, | |
451 | unsigned long start, unsigned long end) | |
452 | { | |
453 | struct pasid_state *pasid_state; | |
454 | struct device_state *dev_state; | |
d73a6d72 | 455 | unsigned long flags; |
8736b2c3 JR |
456 | |
457 | pasid_state = mn_to_state(mn); | |
458 | dev_state = pasid_state->device_state; | |
459 | ||
d73a6d72 JR |
460 | spin_lock_irqsave(&pasid_state->lock, flags); |
461 | pasid_state->mmu_notifier_count -= 1; | |
462 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
463 | amd_iommu_domain_set_gcr3(dev_state->domain, |
464 | pasid_state->pasid, | |
465 | __pa(pasid_state->mm->pgd)); | |
466 | } | |
d73a6d72 | 467 | spin_unlock_irqrestore(&pasid_state->lock, flags); |
8736b2c3 JR |
468 | } |
469 | ||
a40d4c67 JR |
470 | static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm) |
471 | { | |
472 | struct pasid_state *pasid_state; | |
473 | struct device_state *dev_state; | |
474 | ||
475 | might_sleep(); | |
476 | ||
477 | pasid_state = mn_to_state(mn); | |
478 | dev_state = pasid_state->device_state; | |
479 | ||
480 | if (pasid_state->device_state->inv_ctx_cb) | |
481 | dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid); | |
482 | ||
483 | unbind_pasid(dev_state, pasid_state->pasid); | |
484 | } | |
485 | ||
8736b2c3 | 486 | static struct mmu_notifier_ops iommu_mn = { |
a40d4c67 | 487 | .release = mn_release, |
8736b2c3 JR |
488 | .clear_flush_young = mn_clear_flush_young, |
489 | .change_pte = mn_change_pte, | |
490 | .invalidate_page = mn_invalidate_page, | |
491 | .invalidate_range_start = mn_invalidate_range_start, | |
492 | .invalidate_range_end = mn_invalidate_range_end, | |
493 | }; | |
494 | ||
028eeacc JR |
495 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
496 | u16 tag, int status) | |
497 | { | |
498 | unsigned long flags; | |
499 | ||
500 | spin_lock_irqsave(&pasid_state->lock, flags); | |
501 | pasid_state->pri[tag].status = status; | |
502 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
503 | } | |
504 | ||
505 | static void finish_pri_tag(struct device_state *dev_state, | |
506 | struct pasid_state *pasid_state, | |
507 | u16 tag) | |
508 | { | |
509 | unsigned long flags; | |
510 | ||
511 | spin_lock_irqsave(&pasid_state->lock, flags); | |
512 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
513 | pasid_state->pri[tag].finish) { | |
514 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
515 | pasid_state->pri[tag].status, tag); | |
516 | pasid_state->pri[tag].finish = false; | |
517 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
518 | } | |
519 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
520 | } | |
521 | ||
522 | static void do_fault(struct work_struct *work) | |
523 | { | |
524 | struct fault *fault = container_of(work, struct fault, work); | |
525 | int npages, write; | |
526 | struct page *page; | |
527 | ||
528 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
529 | ||
4378d992 | 530 | down_read(&fault->state->mm->mmap_sem); |
028eeacc JR |
531 | npages = get_user_pages(fault->state->task, fault->state->mm, |
532 | fault->address, 1, write, 0, &page, NULL); | |
4378d992 | 533 | up_read(&fault->state->mm->mmap_sem); |
028eeacc | 534 | |
175d6146 | 535 | if (npages == 1) { |
028eeacc | 536 | put_page(page); |
175d6146 JR |
537 | } else if (fault->dev_state->inv_ppr_cb) { |
538 | int status; | |
539 | ||
540 | status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev, | |
541 | fault->pasid, | |
542 | fault->address, | |
543 | fault->flags); | |
544 | switch (status) { | |
545 | case AMD_IOMMU_INV_PRI_RSP_SUCCESS: | |
546 | set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS); | |
547 | break; | |
548 | case AMD_IOMMU_INV_PRI_RSP_INVALID: | |
549 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
550 | break; | |
551 | case AMD_IOMMU_INV_PRI_RSP_FAIL: | |
552 | set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE); | |
553 | break; | |
554 | default: | |
555 | BUG(); | |
556 | } | |
557 | } else { | |
028eeacc | 558 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); |
175d6146 | 559 | } |
028eeacc JR |
560 | |
561 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); | |
562 | ||
563 | put_pasid_state(fault->state); | |
564 | ||
565 | kfree(fault); | |
566 | } | |
567 | ||
568 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
569 | { | |
570 | struct amd_iommu_fault *iommu_fault; | |
571 | struct pasid_state *pasid_state; | |
572 | struct device_state *dev_state; | |
573 | unsigned long flags; | |
574 | struct fault *fault; | |
575 | bool finish; | |
576 | u16 tag; | |
577 | int ret; | |
578 | ||
579 | iommu_fault = data; | |
580 | tag = iommu_fault->tag & 0x1ff; | |
581 | finish = (iommu_fault->tag >> 9) & 1; | |
582 | ||
583 | ret = NOTIFY_DONE; | |
584 | dev_state = get_device_state(iommu_fault->device_id); | |
585 | if (dev_state == NULL) | |
586 | goto out; | |
587 | ||
588 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
589 | if (pasid_state == NULL) { | |
590 | /* We know the device but not the PASID -> send INVALID */ | |
591 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
592 | PPR_INVALID, tag); | |
593 | goto out_drop_state; | |
594 | } | |
595 | ||
596 | spin_lock_irqsave(&pasid_state->lock, flags); | |
597 | atomic_inc(&pasid_state->pri[tag].inflight); | |
598 | if (finish) | |
599 | pasid_state->pri[tag].finish = true; | |
600 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
601 | ||
602 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
603 | if (fault == NULL) { | |
604 | /* We are OOM - send success and let the device re-fault */ | |
605 | finish_pri_tag(dev_state, pasid_state, tag); | |
606 | goto out_drop_state; | |
607 | } | |
608 | ||
609 | fault->dev_state = dev_state; | |
610 | fault->address = iommu_fault->address; | |
611 | fault->state = pasid_state; | |
612 | fault->tag = tag; | |
613 | fault->finish = finish; | |
b00675b8 | 614 | fault->pasid = iommu_fault->pasid; |
028eeacc JR |
615 | fault->flags = iommu_fault->flags; |
616 | INIT_WORK(&fault->work, do_fault); | |
617 | ||
618 | queue_work(iommu_wq, &fault->work); | |
619 | ||
620 | ret = NOTIFY_OK; | |
621 | ||
622 | out_drop_state: | |
623 | put_device_state(dev_state); | |
624 | ||
625 | out: | |
626 | return ret; | |
627 | } | |
628 | ||
629 | static struct notifier_block ppr_nb = { | |
630 | .notifier_call = ppr_notifier, | |
631 | }; | |
632 | ||
2d5503b6 JR |
633 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
634 | struct task_struct *task) | |
635 | { | |
636 | struct pasid_state *pasid_state; | |
637 | struct device_state *dev_state; | |
638 | u16 devid; | |
639 | int ret; | |
640 | ||
641 | might_sleep(); | |
642 | ||
643 | if (!amd_iommu_v2_supported()) | |
644 | return -ENODEV; | |
645 | ||
646 | devid = device_id(pdev); | |
647 | dev_state = get_device_state(devid); | |
648 | ||
649 | if (dev_state == NULL) | |
650 | return -EINVAL; | |
651 | ||
652 | ret = -EINVAL; | |
653 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
654 | goto out; | |
655 | ||
656 | ret = -ENOMEM; | |
657 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
658 | if (pasid_state == NULL) | |
659 | goto out; | |
660 | ||
661 | atomic_set(&pasid_state->count, 1); | |
028eeacc | 662 | init_waitqueue_head(&pasid_state->wq); |
2c13d47a JR |
663 | spin_lock_init(&pasid_state->lock); |
664 | ||
2d5503b6 JR |
665 | pasid_state->task = task; |
666 | pasid_state->mm = get_task_mm(task); | |
667 | pasid_state->device_state = dev_state; | |
668 | pasid_state->pasid = pasid; | |
8736b2c3 | 669 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
670 | |
671 | if (pasid_state->mm == NULL) | |
672 | goto out_free; | |
673 | ||
8736b2c3 JR |
674 | mmu_notifier_register(&pasid_state->mn, pasid_state->mm); |
675 | ||
2d5503b6 JR |
676 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
677 | if (ret) | |
8736b2c3 | 678 | goto out_unregister; |
2d5503b6 JR |
679 | |
680 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
681 | __pa(pasid_state->mm->pgd)); | |
682 | if (ret) | |
683 | goto out_clear_state; | |
684 | ||
2d5503b6 JR |
685 | return 0; |
686 | ||
687 | out_clear_state: | |
688 | clear_pasid_state(dev_state, pasid); | |
689 | ||
8736b2c3 JR |
690 | out_unregister: |
691 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
692 | ||
2d5503b6 | 693 | out_free: |
c5db16ad | 694 | mmput(pasid_state->mm); |
028eeacc | 695 | free_pasid_state(pasid_state); |
2d5503b6 JR |
696 | |
697 | out: | |
698 | put_device_state(dev_state); | |
699 | ||
700 | return ret; | |
701 | } | |
702 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
703 | ||
704 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
705 | { | |
a40d4c67 | 706 | struct pasid_state *pasid_state; |
2d5503b6 JR |
707 | struct device_state *dev_state; |
708 | u16 devid; | |
709 | ||
710 | might_sleep(); | |
711 | ||
712 | if (!amd_iommu_v2_supported()) | |
713 | return; | |
714 | ||
715 | devid = device_id(pdev); | |
716 | dev_state = get_device_state(devid); | |
717 | if (dev_state == NULL) | |
718 | return; | |
719 | ||
720 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
721 | goto out; | |
722 | ||
a40d4c67 JR |
723 | pasid_state = get_pasid_state(dev_state, pasid); |
724 | if (pasid_state == NULL) | |
725 | goto out; | |
726 | /* | |
727 | * Drop reference taken here. We are safe because we still hold | |
728 | * the reference taken in the amd_iommu_bind_pasid function. | |
729 | */ | |
730 | put_pasid_state(pasid_state); | |
731 | ||
732 | /* This will call the mn_release function and unbind the PASID */ | |
733 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
2d5503b6 | 734 | |
c5db16ad JR |
735 | put_pasid_state_wait(pasid_state); /* Reference taken in |
736 | amd_iommu_pasid_bind */ | |
2d5503b6 JR |
737 | out: |
738 | put_device_state(dev_state); | |
739 | } | |
740 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
741 | ||
ed96f228 JR |
742 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
743 | { | |
744 | struct device_state *dev_state; | |
745 | unsigned long flags; | |
746 | int ret, tmp; | |
747 | u16 devid; | |
748 | ||
749 | might_sleep(); | |
750 | ||
751 | if (!amd_iommu_v2_supported()) | |
752 | return -ENODEV; | |
753 | ||
754 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
755 | return -EINVAL; | |
756 | ||
757 | devid = device_id(pdev); | |
758 | ||
759 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
760 | if (dev_state == NULL) | |
761 | return -ENOMEM; | |
762 | ||
763 | spin_lock_init(&dev_state->lock); | |
028eeacc | 764 | init_waitqueue_head(&dev_state->wq); |
741669c7 JR |
765 | dev_state->pdev = pdev; |
766 | dev_state->devid = devid; | |
ed96f228 JR |
767 | |
768 | tmp = pasids; | |
769 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
770 | dev_state->pasid_levels += 1; | |
771 | ||
772 | atomic_set(&dev_state->count, 1); | |
773 | dev_state->max_pasids = pasids; | |
774 | ||
775 | ret = -ENOMEM; | |
776 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
777 | if (dev_state->states == NULL) | |
778 | goto out_free_dev_state; | |
779 | ||
780 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
781 | if (dev_state->domain == NULL) | |
782 | goto out_free_states; | |
783 | ||
784 | amd_iommu_domain_direct_map(dev_state->domain); | |
785 | ||
786 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
787 | if (ret) | |
788 | goto out_free_domain; | |
789 | ||
790 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
791 | if (ret != 0) | |
792 | goto out_free_domain; | |
793 | ||
794 | spin_lock_irqsave(&state_lock, flags); | |
795 | ||
741669c7 | 796 | if (__get_device_state(devid) != NULL) { |
ed96f228 JR |
797 | spin_unlock_irqrestore(&state_lock, flags); |
798 | ret = -EBUSY; | |
799 | goto out_free_domain; | |
800 | } | |
801 | ||
741669c7 | 802 | list_add_tail(&dev_state->list, &state_list); |
ed96f228 JR |
803 | |
804 | spin_unlock_irqrestore(&state_lock, flags); | |
805 | ||
806 | return 0; | |
807 | ||
808 | out_free_domain: | |
809 | iommu_domain_free(dev_state->domain); | |
810 | ||
811 | out_free_states: | |
812 | free_page((unsigned long)dev_state->states); | |
813 | ||
814 | out_free_dev_state: | |
815 | kfree(dev_state); | |
816 | ||
817 | return ret; | |
818 | } | |
819 | EXPORT_SYMBOL(amd_iommu_init_device); | |
820 | ||
821 | void amd_iommu_free_device(struct pci_dev *pdev) | |
822 | { | |
823 | struct device_state *dev_state; | |
824 | unsigned long flags; | |
825 | u16 devid; | |
826 | ||
827 | if (!amd_iommu_v2_supported()) | |
828 | return; | |
829 | ||
830 | devid = device_id(pdev); | |
831 | ||
832 | spin_lock_irqsave(&state_lock, flags); | |
833 | ||
b87d2d7c | 834 | dev_state = __get_device_state(devid); |
ed96f228 JR |
835 | if (dev_state == NULL) { |
836 | spin_unlock_irqrestore(&state_lock, flags); | |
837 | return; | |
838 | } | |
839 | ||
741669c7 | 840 | list_del(&dev_state->list); |
ed96f228 JR |
841 | |
842 | spin_unlock_irqrestore(&state_lock, flags); | |
843 | ||
2d5503b6 JR |
844 | /* Get rid of any remaining pasid states */ |
845 | free_pasid_states(dev_state); | |
846 | ||
028eeacc | 847 | put_device_state_wait(dev_state); |
ed96f228 JR |
848 | } |
849 | EXPORT_SYMBOL(amd_iommu_free_device); | |
850 | ||
175d6146 JR |
851 | int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
852 | amd_iommu_invalid_ppr_cb cb) | |
853 | { | |
854 | struct device_state *dev_state; | |
855 | unsigned long flags; | |
856 | u16 devid; | |
857 | int ret; | |
858 | ||
859 | if (!amd_iommu_v2_supported()) | |
860 | return -ENODEV; | |
861 | ||
862 | devid = device_id(pdev); | |
863 | ||
864 | spin_lock_irqsave(&state_lock, flags); | |
865 | ||
866 | ret = -EINVAL; | |
b87d2d7c | 867 | dev_state = __get_device_state(devid); |
175d6146 JR |
868 | if (dev_state == NULL) |
869 | goto out_unlock; | |
870 | ||
871 | dev_state->inv_ppr_cb = cb; | |
872 | ||
873 | ret = 0; | |
874 | ||
875 | out_unlock: | |
876 | spin_unlock_irqrestore(&state_lock, flags); | |
877 | ||
878 | return ret; | |
879 | } | |
880 | EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb); | |
881 | ||
bc21662f JR |
882 | int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev, |
883 | amd_iommu_invalidate_ctx cb) | |
884 | { | |
885 | struct device_state *dev_state; | |
886 | unsigned long flags; | |
887 | u16 devid; | |
888 | int ret; | |
889 | ||
890 | if (!amd_iommu_v2_supported()) | |
891 | return -ENODEV; | |
892 | ||
893 | devid = device_id(pdev); | |
894 | ||
895 | spin_lock_irqsave(&state_lock, flags); | |
896 | ||
897 | ret = -EINVAL; | |
b87d2d7c | 898 | dev_state = __get_device_state(devid); |
bc21662f JR |
899 | if (dev_state == NULL) |
900 | goto out_unlock; | |
901 | ||
902 | dev_state->inv_ctx_cb = cb; | |
903 | ||
904 | ret = 0; | |
905 | ||
906 | out_unlock: | |
907 | spin_unlock_irqrestore(&state_lock, flags); | |
908 | ||
909 | return ret; | |
910 | } | |
911 | EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb); | |
912 | ||
e3c495c7 JR |
913 | static int __init amd_iommu_v2_init(void) |
914 | { | |
028eeacc | 915 | int ret; |
ed96f228 | 916 | |
474d567d JR |
917 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n"); |
918 | ||
919 | if (!amd_iommu_v2_supported()) { | |
07db0409 | 920 | pr_info("AMD IOMMUv2 functionality not available on this system\n"); |
474d567d JR |
921 | /* |
922 | * Load anyway to provide the symbols to other modules | |
923 | * which may use AMD IOMMUv2 optionally. | |
924 | */ | |
925 | return 0; | |
926 | } | |
e3c495c7 | 927 | |
ed96f228 JR |
928 | spin_lock_init(&state_lock); |
929 | ||
028eeacc JR |
930 | ret = -ENOMEM; |
931 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 932 | if (iommu_wq == NULL) |
741669c7 | 933 | goto out; |
8736b2c3 JR |
934 | |
935 | ret = -ENOMEM; | |
936 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
937 | if (empty_page_table == NULL) | |
938 | goto out_destroy_wq; | |
028eeacc JR |
939 | |
940 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
941 | ||
e3c495c7 | 942 | return 0; |
028eeacc | 943 | |
8736b2c3 JR |
944 | out_destroy_wq: |
945 | destroy_workqueue(iommu_wq); | |
946 | ||
741669c7 | 947 | out: |
028eeacc | 948 | return ret; |
e3c495c7 JR |
949 | } |
950 | ||
951 | static void __exit amd_iommu_v2_exit(void) | |
952 | { | |
ed96f228 | 953 | struct device_state *dev_state; |
ed96f228 JR |
954 | int i; |
955 | ||
474d567d JR |
956 | if (!amd_iommu_v2_supported()) |
957 | return; | |
958 | ||
028eeacc JR |
959 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
960 | ||
961 | flush_workqueue(iommu_wq); | |
962 | ||
963 | /* | |
964 | * The loop below might call flush_workqueue(), so call | |
965 | * destroy_workqueue() after it | |
966 | */ | |
ed96f228 JR |
967 | for (i = 0; i < MAX_DEVICES; ++i) { |
968 | dev_state = get_device_state(i); | |
969 | ||
970 | if (dev_state == NULL) | |
971 | continue; | |
972 | ||
973 | WARN_ON_ONCE(1); | |
974 | ||
ed96f228 | 975 | put_device_state(dev_state); |
028eeacc | 976 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
977 | } |
978 | ||
028eeacc JR |
979 | destroy_workqueue(iommu_wq); |
980 | ||
8736b2c3 | 981 | free_page((unsigned long)empty_page_table); |
e3c495c7 JR |
982 | } |
983 | ||
984 | module_init(amd_iommu_v2_init); | |
985 | module_exit(amd_iommu_v2_exit); |