Commit | Line | Data |
---|---|---|
e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
d73a6d72 | 48 | unsigned mmu_notifier_count; /* Counting nested mmu_notifier |
e79df31c | 49 | calls */ |
ed96f228 JR |
50 | struct task_struct *task; /* Task bound to this PASID */ |
51 | struct mm_struct *mm; /* mm_struct for the faults */ | |
ff6d0cce | 52 | struct mmu_notifier mn; /* mmu_notifier handle */ |
ed96f228 JR |
53 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
54 | struct device_state *device_state; /* Link to our device_state */ | |
55 | int pasid; /* PASID index */ | |
d73a6d72 JR |
56 | spinlock_t lock; /* Protect pri_queues and |
57 | mmu_notifer_count */ | |
028eeacc | 58 | wait_queue_head_t wq; /* To wait for count == 0 */ |
ed96f228 JR |
59 | }; |
60 | ||
61 | struct device_state { | |
741669c7 JR |
62 | struct list_head list; |
63 | u16 devid; | |
ed96f228 JR |
64 | atomic_t count; |
65 | struct pci_dev *pdev; | |
66 | struct pasid_state **states; | |
67 | struct iommu_domain *domain; | |
68 | int pasid_levels; | |
69 | int max_pasids; | |
175d6146 | 70 | amd_iommu_invalid_ppr_cb inv_ppr_cb; |
bc21662f | 71 | amd_iommu_invalidate_ctx inv_ctx_cb; |
ed96f228 | 72 | spinlock_t lock; |
028eeacc JR |
73 | wait_queue_head_t wq; |
74 | }; | |
75 | ||
76 | struct fault { | |
77 | struct work_struct work; | |
78 | struct device_state *dev_state; | |
79 | struct pasid_state *state; | |
80 | struct mm_struct *mm; | |
81 | u64 address; | |
82 | u16 devid; | |
83 | u16 pasid; | |
84 | u16 tag; | |
85 | u16 finish; | |
86 | u16 flags; | |
ed96f228 JR |
87 | }; |
88 | ||
741669c7 | 89 | static LIST_HEAD(state_list); |
ed96f228 JR |
90 | static spinlock_t state_lock; |
91 | ||
028eeacc JR |
92 | static struct workqueue_struct *iommu_wq; |
93 | ||
8736b2c3 JR |
94 | /* |
95 | * Empty page table - Used between | |
96 | * mmu_notifier_invalidate_range_start and | |
97 | * mmu_notifier_invalidate_range_end | |
98 | */ | |
99 | static u64 *empty_page_table; | |
100 | ||
2d5503b6 | 101 | static void free_pasid_states(struct device_state *dev_state); |
ed96f228 JR |
102 | |
103 | static u16 device_id(struct pci_dev *pdev) | |
104 | { | |
105 | u16 devid; | |
106 | ||
107 | devid = pdev->bus->number; | |
108 | devid = (devid << 8) | pdev->devfn; | |
109 | ||
110 | return devid; | |
111 | } | |
112 | ||
b87d2d7c JR |
113 | static struct device_state *__get_device_state(u16 devid) |
114 | { | |
741669c7 JR |
115 | struct device_state *dev_state; |
116 | ||
117 | list_for_each_entry(dev_state, &state_list, list) { | |
118 | if (dev_state->devid == devid) | |
119 | return dev_state; | |
120 | } | |
121 | ||
122 | return NULL; | |
b87d2d7c JR |
123 | } |
124 | ||
ed96f228 JR |
125 | static struct device_state *get_device_state(u16 devid) |
126 | { | |
127 | struct device_state *dev_state; | |
128 | unsigned long flags; | |
129 | ||
130 | spin_lock_irqsave(&state_lock, flags); | |
b87d2d7c | 131 | dev_state = __get_device_state(devid); |
ed96f228 JR |
132 | if (dev_state != NULL) |
133 | atomic_inc(&dev_state->count); | |
134 | spin_unlock_irqrestore(&state_lock, flags); | |
135 | ||
136 | return dev_state; | |
137 | } | |
138 | ||
139 | static void free_device_state(struct device_state *dev_state) | |
140 | { | |
2d5503b6 JR |
141 | /* |
142 | * First detach device from domain - No more PRI requests will arrive | |
143 | * from that device after it is unbound from the IOMMUv2 domain. | |
144 | */ | |
ed96f228 | 145 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
146 | |
147 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 148 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
149 | |
150 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
151 | kfree(dev_state); |
152 | } | |
153 | ||
154 | static void put_device_state(struct device_state *dev_state) | |
155 | { | |
156 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 157 | wake_up(&dev_state->wq); |
ed96f228 JR |
158 | } |
159 | ||
028eeacc JR |
160 | static void put_device_state_wait(struct device_state *dev_state) |
161 | { | |
162 | DEFINE_WAIT(wait); | |
163 | ||
164 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
165 | if (!atomic_dec_and_test(&dev_state->count)) | |
166 | schedule(); | |
167 | finish_wait(&dev_state->wq, &wait); | |
168 | ||
169 | free_device_state(dev_state); | |
170 | } | |
8736b2c3 | 171 | |
2d5503b6 JR |
172 | /* Must be called under dev_state->lock */ |
173 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
174 | int pasid, bool alloc) | |
175 | { | |
176 | struct pasid_state **root, **ptr; | |
177 | int level, index; | |
178 | ||
179 | level = dev_state->pasid_levels; | |
180 | root = dev_state->states; | |
181 | ||
182 | while (true) { | |
183 | ||
184 | index = (pasid >> (9 * level)) & 0x1ff; | |
185 | ptr = &root[index]; | |
186 | ||
187 | if (level == 0) | |
188 | break; | |
189 | ||
190 | if (*ptr == NULL) { | |
191 | if (!alloc) | |
192 | return NULL; | |
193 | ||
194 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
195 | if (*ptr == NULL) | |
196 | return NULL; | |
197 | } | |
198 | ||
199 | root = (struct pasid_state **)*ptr; | |
200 | level -= 1; | |
201 | } | |
202 | ||
203 | return ptr; | |
204 | } | |
205 | ||
206 | static int set_pasid_state(struct device_state *dev_state, | |
207 | struct pasid_state *pasid_state, | |
208 | int pasid) | |
209 | { | |
210 | struct pasid_state **ptr; | |
211 | unsigned long flags; | |
212 | int ret; | |
213 | ||
214 | spin_lock_irqsave(&dev_state->lock, flags); | |
215 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
216 | ||
217 | ret = -ENOMEM; | |
218 | if (ptr == NULL) | |
219 | goto out_unlock; | |
220 | ||
221 | ret = -ENOMEM; | |
222 | if (*ptr != NULL) | |
223 | goto out_unlock; | |
224 | ||
225 | *ptr = pasid_state; | |
226 | ||
227 | ret = 0; | |
228 | ||
229 | out_unlock: | |
230 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
231 | ||
232 | return ret; | |
233 | } | |
234 | ||
235 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
236 | { | |
237 | struct pasid_state **ptr; | |
238 | unsigned long flags; | |
239 | ||
240 | spin_lock_irqsave(&dev_state->lock, flags); | |
241 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
242 | ||
243 | if (ptr == NULL) | |
244 | goto out_unlock; | |
245 | ||
246 | *ptr = NULL; | |
247 | ||
248 | out_unlock: | |
249 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
250 | } | |
251 | ||
252 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
253 | int pasid) | |
254 | { | |
255 | struct pasid_state **ptr, *ret = NULL; | |
256 | unsigned long flags; | |
257 | ||
258 | spin_lock_irqsave(&dev_state->lock, flags); | |
259 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
260 | ||
261 | if (ptr == NULL) | |
262 | goto out_unlock; | |
263 | ||
264 | ret = *ptr; | |
265 | if (ret) | |
266 | atomic_inc(&ret->count); | |
267 | ||
268 | out_unlock: | |
269 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
270 | ||
271 | return ret; | |
272 | } | |
273 | ||
274 | static void free_pasid_state(struct pasid_state *pasid_state) | |
275 | { | |
276 | kfree(pasid_state); | |
277 | } | |
278 | ||
279 | static void put_pasid_state(struct pasid_state *pasid_state) | |
280 | { | |
281 | if (atomic_dec_and_test(&pasid_state->count)) { | |
282 | put_device_state(pasid_state->device_state); | |
028eeacc | 283 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
284 | } |
285 | } | |
286 | ||
028eeacc JR |
287 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
288 | { | |
289 | DEFINE_WAIT(wait); | |
290 | ||
291 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
292 | ||
293 | if (atomic_dec_and_test(&pasid_state->count)) | |
294 | put_device_state(pasid_state->device_state); | |
295 | else | |
296 | schedule(); | |
297 | ||
298 | finish_wait(&pasid_state->wq, &wait); | |
299 | mmput(pasid_state->mm); | |
300 | free_pasid_state(pasid_state); | |
301 | } | |
302 | ||
61feb438 | 303 | static void unbind_pasid(struct pasid_state *pasid_state) |
8736b2c3 JR |
304 | { |
305 | struct iommu_domain *domain; | |
306 | ||
307 | domain = pasid_state->device_state->domain; | |
308 | ||
309 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); | |
310 | clear_pasid_state(pasid_state->device_state, pasid_state->pasid); | |
311 | ||
312 | /* Make sure no more pending faults are in the queue */ | |
313 | flush_workqueue(iommu_wq); | |
8736b2c3 JR |
314 | } |
315 | ||
2d5503b6 JR |
316 | static void free_pasid_states_level1(struct pasid_state **tbl) |
317 | { | |
318 | int i; | |
319 | ||
320 | for (i = 0; i < 512; ++i) { | |
321 | if (tbl[i] == NULL) | |
322 | continue; | |
323 | ||
324 | free_page((unsigned long)tbl[i]); | |
325 | } | |
326 | } | |
327 | ||
328 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
329 | { | |
330 | struct pasid_state **ptr; | |
331 | int i; | |
332 | ||
333 | for (i = 0; i < 512; ++i) { | |
334 | if (tbl[i] == NULL) | |
335 | continue; | |
336 | ||
337 | ptr = (struct pasid_state **)tbl[i]; | |
338 | free_pasid_states_level1(ptr); | |
339 | } | |
340 | } | |
341 | ||
342 | static void free_pasid_states(struct device_state *dev_state) | |
343 | { | |
344 | struct pasid_state *pasid_state; | |
345 | int i; | |
346 | ||
347 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
348 | pasid_state = get_pasid_state(dev_state, i); | |
349 | if (pasid_state == NULL) | |
350 | continue; | |
351 | ||
2d5503b6 | 352 | put_pasid_state(pasid_state); |
a40d4c67 JR |
353 | |
354 | /* | |
355 | * This will call the mn_release function and | |
356 | * unbind the PASID | |
357 | */ | |
358 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
c5db16ad JR |
359 | |
360 | put_pasid_state_wait(pasid_state); /* Reference taken in | |
361 | amd_iommu_pasid_bind */ | |
2d5503b6 JR |
362 | } |
363 | ||
364 | if (dev_state->pasid_levels == 2) | |
365 | free_pasid_states_level2(dev_state->states); | |
366 | else if (dev_state->pasid_levels == 1) | |
367 | free_pasid_states_level1(dev_state->states); | |
368 | else if (dev_state->pasid_levels != 0) | |
369 | BUG(); | |
370 | ||
371 | free_page((unsigned long)dev_state->states); | |
372 | } | |
373 | ||
8736b2c3 JR |
374 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
375 | { | |
376 | return container_of(mn, struct pasid_state, mn); | |
377 | } | |
378 | ||
379 | static void __mn_flush_page(struct mmu_notifier *mn, | |
380 | unsigned long address) | |
381 | { | |
382 | struct pasid_state *pasid_state; | |
383 | struct device_state *dev_state; | |
384 | ||
385 | pasid_state = mn_to_state(mn); | |
386 | dev_state = pasid_state->device_state; | |
387 | ||
388 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
389 | } | |
390 | ||
391 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
392 | struct mm_struct *mm, | |
393 | unsigned long address) | |
394 | { | |
395 | __mn_flush_page(mn, address); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | static void mn_change_pte(struct mmu_notifier *mn, | |
401 | struct mm_struct *mm, | |
402 | unsigned long address, | |
403 | pte_t pte) | |
404 | { | |
405 | __mn_flush_page(mn, address); | |
406 | } | |
407 | ||
408 | static void mn_invalidate_page(struct mmu_notifier *mn, | |
409 | struct mm_struct *mm, | |
410 | unsigned long address) | |
411 | { | |
412 | __mn_flush_page(mn, address); | |
413 | } | |
414 | ||
415 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
416 | struct mm_struct *mm, | |
417 | unsigned long start, unsigned long end) | |
418 | { | |
419 | struct pasid_state *pasid_state; | |
420 | struct device_state *dev_state; | |
d73a6d72 | 421 | unsigned long flags; |
8736b2c3 JR |
422 | |
423 | pasid_state = mn_to_state(mn); | |
424 | dev_state = pasid_state->device_state; | |
425 | ||
d73a6d72 JR |
426 | spin_lock_irqsave(&pasid_state->lock, flags); |
427 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
428 | amd_iommu_domain_set_gcr3(dev_state->domain, |
429 | pasid_state->pasid, | |
430 | __pa(empty_page_table)); | |
431 | } | |
d73a6d72 JR |
432 | pasid_state->mmu_notifier_count += 1; |
433 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
8736b2c3 JR |
434 | } |
435 | ||
436 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
437 | struct mm_struct *mm, | |
438 | unsigned long start, unsigned long end) | |
439 | { | |
440 | struct pasid_state *pasid_state; | |
441 | struct device_state *dev_state; | |
d73a6d72 | 442 | unsigned long flags; |
8736b2c3 JR |
443 | |
444 | pasid_state = mn_to_state(mn); | |
445 | dev_state = pasid_state->device_state; | |
446 | ||
d73a6d72 JR |
447 | spin_lock_irqsave(&pasid_state->lock, flags); |
448 | pasid_state->mmu_notifier_count -= 1; | |
449 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
450 | amd_iommu_domain_set_gcr3(dev_state->domain, |
451 | pasid_state->pasid, | |
452 | __pa(pasid_state->mm->pgd)); | |
453 | } | |
d73a6d72 | 454 | spin_unlock_irqrestore(&pasid_state->lock, flags); |
8736b2c3 JR |
455 | } |
456 | ||
a40d4c67 JR |
457 | static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm) |
458 | { | |
459 | struct pasid_state *pasid_state; | |
460 | struct device_state *dev_state; | |
461 | ||
462 | might_sleep(); | |
463 | ||
464 | pasid_state = mn_to_state(mn); | |
465 | dev_state = pasid_state->device_state; | |
466 | ||
467 | if (pasid_state->device_state->inv_ctx_cb) | |
468 | dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid); | |
469 | ||
61feb438 | 470 | unbind_pasid(pasid_state); |
a40d4c67 JR |
471 | } |
472 | ||
8736b2c3 | 473 | static struct mmu_notifier_ops iommu_mn = { |
a40d4c67 | 474 | .release = mn_release, |
8736b2c3 JR |
475 | .clear_flush_young = mn_clear_flush_young, |
476 | .change_pte = mn_change_pte, | |
477 | .invalidate_page = mn_invalidate_page, | |
478 | .invalidate_range_start = mn_invalidate_range_start, | |
479 | .invalidate_range_end = mn_invalidate_range_end, | |
480 | }; | |
481 | ||
028eeacc JR |
482 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
483 | u16 tag, int status) | |
484 | { | |
485 | unsigned long flags; | |
486 | ||
487 | spin_lock_irqsave(&pasid_state->lock, flags); | |
488 | pasid_state->pri[tag].status = status; | |
489 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
490 | } | |
491 | ||
492 | static void finish_pri_tag(struct device_state *dev_state, | |
493 | struct pasid_state *pasid_state, | |
494 | u16 tag) | |
495 | { | |
496 | unsigned long flags; | |
497 | ||
498 | spin_lock_irqsave(&pasid_state->lock, flags); | |
499 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
500 | pasid_state->pri[tag].finish) { | |
501 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
502 | pasid_state->pri[tag].status, tag); | |
503 | pasid_state->pri[tag].finish = false; | |
504 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
505 | } | |
506 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
507 | } | |
508 | ||
509 | static void do_fault(struct work_struct *work) | |
510 | { | |
511 | struct fault *fault = container_of(work, struct fault, work); | |
512 | int npages, write; | |
513 | struct page *page; | |
514 | ||
515 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
516 | ||
4378d992 | 517 | down_read(&fault->state->mm->mmap_sem); |
028eeacc JR |
518 | npages = get_user_pages(fault->state->task, fault->state->mm, |
519 | fault->address, 1, write, 0, &page, NULL); | |
4378d992 | 520 | up_read(&fault->state->mm->mmap_sem); |
028eeacc | 521 | |
175d6146 | 522 | if (npages == 1) { |
028eeacc | 523 | put_page(page); |
175d6146 JR |
524 | } else if (fault->dev_state->inv_ppr_cb) { |
525 | int status; | |
526 | ||
527 | status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev, | |
528 | fault->pasid, | |
529 | fault->address, | |
530 | fault->flags); | |
531 | switch (status) { | |
532 | case AMD_IOMMU_INV_PRI_RSP_SUCCESS: | |
533 | set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS); | |
534 | break; | |
535 | case AMD_IOMMU_INV_PRI_RSP_INVALID: | |
536 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
537 | break; | |
538 | case AMD_IOMMU_INV_PRI_RSP_FAIL: | |
539 | set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE); | |
540 | break; | |
541 | default: | |
542 | BUG(); | |
543 | } | |
544 | } else { | |
028eeacc | 545 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); |
175d6146 | 546 | } |
028eeacc JR |
547 | |
548 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); | |
549 | ||
550 | put_pasid_state(fault->state); | |
551 | ||
552 | kfree(fault); | |
553 | } | |
554 | ||
555 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
556 | { | |
557 | struct amd_iommu_fault *iommu_fault; | |
558 | struct pasid_state *pasid_state; | |
559 | struct device_state *dev_state; | |
560 | unsigned long flags; | |
561 | struct fault *fault; | |
562 | bool finish; | |
563 | u16 tag; | |
564 | int ret; | |
565 | ||
566 | iommu_fault = data; | |
567 | tag = iommu_fault->tag & 0x1ff; | |
568 | finish = (iommu_fault->tag >> 9) & 1; | |
569 | ||
570 | ret = NOTIFY_DONE; | |
571 | dev_state = get_device_state(iommu_fault->device_id); | |
572 | if (dev_state == NULL) | |
573 | goto out; | |
574 | ||
575 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
576 | if (pasid_state == NULL) { | |
577 | /* We know the device but not the PASID -> send INVALID */ | |
578 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
579 | PPR_INVALID, tag); | |
580 | goto out_drop_state; | |
581 | } | |
582 | ||
583 | spin_lock_irqsave(&pasid_state->lock, flags); | |
584 | atomic_inc(&pasid_state->pri[tag].inflight); | |
585 | if (finish) | |
586 | pasid_state->pri[tag].finish = true; | |
587 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
588 | ||
589 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
590 | if (fault == NULL) { | |
591 | /* We are OOM - send success and let the device re-fault */ | |
592 | finish_pri_tag(dev_state, pasid_state, tag); | |
593 | goto out_drop_state; | |
594 | } | |
595 | ||
596 | fault->dev_state = dev_state; | |
597 | fault->address = iommu_fault->address; | |
598 | fault->state = pasid_state; | |
599 | fault->tag = tag; | |
600 | fault->finish = finish; | |
b00675b8 | 601 | fault->pasid = iommu_fault->pasid; |
028eeacc JR |
602 | fault->flags = iommu_fault->flags; |
603 | INIT_WORK(&fault->work, do_fault); | |
604 | ||
605 | queue_work(iommu_wq, &fault->work); | |
606 | ||
607 | ret = NOTIFY_OK; | |
608 | ||
609 | out_drop_state: | |
dc88db7e JR |
610 | |
611 | if (ret != NOTIFY_OK && pasid_state) | |
612 | put_pasid_state(pasid_state); | |
613 | ||
028eeacc JR |
614 | put_device_state(dev_state); |
615 | ||
616 | out: | |
617 | return ret; | |
618 | } | |
619 | ||
620 | static struct notifier_block ppr_nb = { | |
621 | .notifier_call = ppr_notifier, | |
622 | }; | |
623 | ||
2d5503b6 JR |
624 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
625 | struct task_struct *task) | |
626 | { | |
627 | struct pasid_state *pasid_state; | |
628 | struct device_state *dev_state; | |
629 | u16 devid; | |
630 | int ret; | |
631 | ||
632 | might_sleep(); | |
633 | ||
634 | if (!amd_iommu_v2_supported()) | |
635 | return -ENODEV; | |
636 | ||
637 | devid = device_id(pdev); | |
638 | dev_state = get_device_state(devid); | |
639 | ||
640 | if (dev_state == NULL) | |
641 | return -EINVAL; | |
642 | ||
643 | ret = -EINVAL; | |
644 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
645 | goto out; | |
646 | ||
647 | ret = -ENOMEM; | |
648 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
649 | if (pasid_state == NULL) | |
650 | goto out; | |
651 | ||
652 | atomic_set(&pasid_state->count, 1); | |
028eeacc | 653 | init_waitqueue_head(&pasid_state->wq); |
2c13d47a JR |
654 | spin_lock_init(&pasid_state->lock); |
655 | ||
2d5503b6 JR |
656 | pasid_state->task = task; |
657 | pasid_state->mm = get_task_mm(task); | |
658 | pasid_state->device_state = dev_state; | |
659 | pasid_state->pasid = pasid; | |
8736b2c3 | 660 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
661 | |
662 | if (pasid_state->mm == NULL) | |
663 | goto out_free; | |
664 | ||
8736b2c3 JR |
665 | mmu_notifier_register(&pasid_state->mn, pasid_state->mm); |
666 | ||
2d5503b6 JR |
667 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
668 | if (ret) | |
8736b2c3 | 669 | goto out_unregister; |
2d5503b6 JR |
670 | |
671 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
672 | __pa(pasid_state->mm->pgd)); | |
673 | if (ret) | |
674 | goto out_clear_state; | |
675 | ||
2d5503b6 JR |
676 | return 0; |
677 | ||
678 | out_clear_state: | |
679 | clear_pasid_state(dev_state, pasid); | |
680 | ||
8736b2c3 JR |
681 | out_unregister: |
682 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
683 | ||
2d5503b6 | 684 | out_free: |
c5db16ad | 685 | mmput(pasid_state->mm); |
028eeacc | 686 | free_pasid_state(pasid_state); |
2d5503b6 JR |
687 | |
688 | out: | |
689 | put_device_state(dev_state); | |
690 | ||
691 | return ret; | |
692 | } | |
693 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
694 | ||
695 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
696 | { | |
a40d4c67 | 697 | struct pasid_state *pasid_state; |
2d5503b6 JR |
698 | struct device_state *dev_state; |
699 | u16 devid; | |
700 | ||
701 | might_sleep(); | |
702 | ||
703 | if (!amd_iommu_v2_supported()) | |
704 | return; | |
705 | ||
706 | devid = device_id(pdev); | |
707 | dev_state = get_device_state(devid); | |
708 | if (dev_state == NULL) | |
709 | return; | |
710 | ||
711 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
712 | goto out; | |
713 | ||
a40d4c67 JR |
714 | pasid_state = get_pasid_state(dev_state, pasid); |
715 | if (pasid_state == NULL) | |
716 | goto out; | |
717 | /* | |
718 | * Drop reference taken here. We are safe because we still hold | |
719 | * the reference taken in the amd_iommu_bind_pasid function. | |
720 | */ | |
721 | put_pasid_state(pasid_state); | |
722 | ||
723 | /* This will call the mn_release function and unbind the PASID */ | |
724 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
2d5503b6 | 725 | |
c5db16ad JR |
726 | put_pasid_state_wait(pasid_state); /* Reference taken in |
727 | amd_iommu_pasid_bind */ | |
2d5503b6 JR |
728 | out: |
729 | put_device_state(dev_state); | |
730 | } | |
731 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
732 | ||
ed96f228 JR |
733 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
734 | { | |
735 | struct device_state *dev_state; | |
736 | unsigned long flags; | |
737 | int ret, tmp; | |
738 | u16 devid; | |
739 | ||
740 | might_sleep(); | |
741 | ||
742 | if (!amd_iommu_v2_supported()) | |
743 | return -ENODEV; | |
744 | ||
745 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
746 | return -EINVAL; | |
747 | ||
748 | devid = device_id(pdev); | |
749 | ||
750 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
751 | if (dev_state == NULL) | |
752 | return -ENOMEM; | |
753 | ||
754 | spin_lock_init(&dev_state->lock); | |
028eeacc | 755 | init_waitqueue_head(&dev_state->wq); |
741669c7 JR |
756 | dev_state->pdev = pdev; |
757 | dev_state->devid = devid; | |
ed96f228 JR |
758 | |
759 | tmp = pasids; | |
760 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
761 | dev_state->pasid_levels += 1; | |
762 | ||
763 | atomic_set(&dev_state->count, 1); | |
764 | dev_state->max_pasids = pasids; | |
765 | ||
766 | ret = -ENOMEM; | |
767 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
768 | if (dev_state->states == NULL) | |
769 | goto out_free_dev_state; | |
770 | ||
771 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
772 | if (dev_state->domain == NULL) | |
773 | goto out_free_states; | |
774 | ||
775 | amd_iommu_domain_direct_map(dev_state->domain); | |
776 | ||
777 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
778 | if (ret) | |
779 | goto out_free_domain; | |
780 | ||
781 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
782 | if (ret != 0) | |
783 | goto out_free_domain; | |
784 | ||
785 | spin_lock_irqsave(&state_lock, flags); | |
786 | ||
741669c7 | 787 | if (__get_device_state(devid) != NULL) { |
ed96f228 JR |
788 | spin_unlock_irqrestore(&state_lock, flags); |
789 | ret = -EBUSY; | |
790 | goto out_free_domain; | |
791 | } | |
792 | ||
741669c7 | 793 | list_add_tail(&dev_state->list, &state_list); |
ed96f228 JR |
794 | |
795 | spin_unlock_irqrestore(&state_lock, flags); | |
796 | ||
797 | return 0; | |
798 | ||
799 | out_free_domain: | |
800 | iommu_domain_free(dev_state->domain); | |
801 | ||
802 | out_free_states: | |
803 | free_page((unsigned long)dev_state->states); | |
804 | ||
805 | out_free_dev_state: | |
806 | kfree(dev_state); | |
807 | ||
808 | return ret; | |
809 | } | |
810 | EXPORT_SYMBOL(amd_iommu_init_device); | |
811 | ||
812 | void amd_iommu_free_device(struct pci_dev *pdev) | |
813 | { | |
814 | struct device_state *dev_state; | |
815 | unsigned long flags; | |
816 | u16 devid; | |
817 | ||
818 | if (!amd_iommu_v2_supported()) | |
819 | return; | |
820 | ||
821 | devid = device_id(pdev); | |
822 | ||
823 | spin_lock_irqsave(&state_lock, flags); | |
824 | ||
b87d2d7c | 825 | dev_state = __get_device_state(devid); |
ed96f228 JR |
826 | if (dev_state == NULL) { |
827 | spin_unlock_irqrestore(&state_lock, flags); | |
828 | return; | |
829 | } | |
830 | ||
741669c7 | 831 | list_del(&dev_state->list); |
ed96f228 JR |
832 | |
833 | spin_unlock_irqrestore(&state_lock, flags); | |
834 | ||
2d5503b6 JR |
835 | /* Get rid of any remaining pasid states */ |
836 | free_pasid_states(dev_state); | |
837 | ||
028eeacc | 838 | put_device_state_wait(dev_state); |
ed96f228 JR |
839 | } |
840 | EXPORT_SYMBOL(amd_iommu_free_device); | |
841 | ||
175d6146 JR |
842 | int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
843 | amd_iommu_invalid_ppr_cb cb) | |
844 | { | |
845 | struct device_state *dev_state; | |
846 | unsigned long flags; | |
847 | u16 devid; | |
848 | int ret; | |
849 | ||
850 | if (!amd_iommu_v2_supported()) | |
851 | return -ENODEV; | |
852 | ||
853 | devid = device_id(pdev); | |
854 | ||
855 | spin_lock_irqsave(&state_lock, flags); | |
856 | ||
857 | ret = -EINVAL; | |
b87d2d7c | 858 | dev_state = __get_device_state(devid); |
175d6146 JR |
859 | if (dev_state == NULL) |
860 | goto out_unlock; | |
861 | ||
862 | dev_state->inv_ppr_cb = cb; | |
863 | ||
864 | ret = 0; | |
865 | ||
866 | out_unlock: | |
867 | spin_unlock_irqrestore(&state_lock, flags); | |
868 | ||
869 | return ret; | |
870 | } | |
871 | EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb); | |
872 | ||
bc21662f JR |
873 | int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev, |
874 | amd_iommu_invalidate_ctx cb) | |
875 | { | |
876 | struct device_state *dev_state; | |
877 | unsigned long flags; | |
878 | u16 devid; | |
879 | int ret; | |
880 | ||
881 | if (!amd_iommu_v2_supported()) | |
882 | return -ENODEV; | |
883 | ||
884 | devid = device_id(pdev); | |
885 | ||
886 | spin_lock_irqsave(&state_lock, flags); | |
887 | ||
888 | ret = -EINVAL; | |
b87d2d7c | 889 | dev_state = __get_device_state(devid); |
bc21662f JR |
890 | if (dev_state == NULL) |
891 | goto out_unlock; | |
892 | ||
893 | dev_state->inv_ctx_cb = cb; | |
894 | ||
895 | ret = 0; | |
896 | ||
897 | out_unlock: | |
898 | spin_unlock_irqrestore(&state_lock, flags); | |
899 | ||
900 | return ret; | |
901 | } | |
902 | EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb); | |
903 | ||
e3c495c7 JR |
904 | static int __init amd_iommu_v2_init(void) |
905 | { | |
028eeacc | 906 | int ret; |
ed96f228 | 907 | |
474d567d JR |
908 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n"); |
909 | ||
910 | if (!amd_iommu_v2_supported()) { | |
07db0409 | 911 | pr_info("AMD IOMMUv2 functionality not available on this system\n"); |
474d567d JR |
912 | /* |
913 | * Load anyway to provide the symbols to other modules | |
914 | * which may use AMD IOMMUv2 optionally. | |
915 | */ | |
916 | return 0; | |
917 | } | |
e3c495c7 | 918 | |
ed96f228 JR |
919 | spin_lock_init(&state_lock); |
920 | ||
028eeacc JR |
921 | ret = -ENOMEM; |
922 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 923 | if (iommu_wq == NULL) |
741669c7 | 924 | goto out; |
8736b2c3 JR |
925 | |
926 | ret = -ENOMEM; | |
927 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
928 | if (empty_page_table == NULL) | |
929 | goto out_destroy_wq; | |
028eeacc JR |
930 | |
931 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
932 | ||
e3c495c7 | 933 | return 0; |
028eeacc | 934 | |
8736b2c3 JR |
935 | out_destroy_wq: |
936 | destroy_workqueue(iommu_wq); | |
937 | ||
741669c7 | 938 | out: |
028eeacc | 939 | return ret; |
e3c495c7 JR |
940 | } |
941 | ||
942 | static void __exit amd_iommu_v2_exit(void) | |
943 | { | |
ed96f228 | 944 | struct device_state *dev_state; |
ed96f228 JR |
945 | int i; |
946 | ||
474d567d JR |
947 | if (!amd_iommu_v2_supported()) |
948 | return; | |
949 | ||
028eeacc JR |
950 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
951 | ||
952 | flush_workqueue(iommu_wq); | |
953 | ||
954 | /* | |
955 | * The loop below might call flush_workqueue(), so call | |
956 | * destroy_workqueue() after it | |
957 | */ | |
ed96f228 JR |
958 | for (i = 0; i < MAX_DEVICES; ++i) { |
959 | dev_state = get_device_state(i); | |
960 | ||
961 | if (dev_state == NULL) | |
962 | continue; | |
963 | ||
964 | WARN_ON_ONCE(1); | |
965 | ||
ed96f228 | 966 | put_device_state(dev_state); |
028eeacc | 967 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
968 | } |
969 | ||
028eeacc JR |
970 | destroy_workqueue(iommu_wq); |
971 | ||
8736b2c3 | 972 | free_page((unsigned long)empty_page_table); |
e3c495c7 JR |
973 | } |
974 | ||
975 | module_init(amd_iommu_v2_init); | |
976 | module_exit(amd_iommu_v2_exit); |