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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
2a96536e KC |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
312900c6 | 17 | #include <linux/io.h> |
2a96536e | 18 | #include <linux/iommu.h> |
312900c6 | 19 | #include <linux/interrupt.h> |
2a96536e | 20 | #include <linux/list.h> |
312900c6 MS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/slab.h> | |
2a96536e KC |
24 | |
25 | #include <asm/cacheflush.h> | |
26 | #include <asm/pgtable.h> | |
27 | ||
d09d78fc CK |
28 | typedef u32 sysmmu_iova_t; |
29 | typedef u32 sysmmu_pte_t; | |
30 | ||
f171abab | 31 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
32 | #define SECT_ORDER 20 |
33 | #define LPAGE_ORDER 16 | |
34 | #define SPAGE_ORDER 12 | |
35 | ||
36 | #define SECT_SIZE (1 << SECT_ORDER) | |
37 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
38 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
39 | ||
40 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
41 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
42 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
43 | ||
66a7ed84 CK |
44 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
45 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
46 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
47 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
48 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
49 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
50 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
51 | ||
52 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
53 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
54 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
55 | ||
d09d78fc CK |
56 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
57 | { | |
58 | return iova & (size - 1); | |
59 | } | |
60 | ||
2a96536e | 61 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 62 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 63 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 64 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 65 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 66 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
67 | |
68 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 69 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 70 | |
d09d78fc CK |
71 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
72 | { | |
73 | return iova >> SECT_ORDER; | |
74 | } | |
75 | ||
76 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
77 | { | |
78 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
79 | } | |
80 | ||
81 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) | |
2a96536e KC |
82 | |
83 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
84 | ||
85 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
86 | ||
87 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
88 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
89 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
90 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
91 | ||
92 | #define CTRL_ENABLE 0x5 | |
93 | #define CTRL_BLOCK 0x7 | |
94 | #define CTRL_DISABLE 0x0 | |
95 | ||
eeb5184b CK |
96 | #define CFG_LRU 0x1 |
97 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
98 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
99 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
100 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
101 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
102 | ||
2a96536e KC |
103 | #define REG_MMU_CTRL 0x000 |
104 | #define REG_MMU_CFG 0x004 | |
105 | #define REG_MMU_STATUS 0x008 | |
106 | #define REG_MMU_FLUSH 0x00C | |
107 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
108 | #define REG_PT_BASE_ADDR 0x014 | |
109 | #define REG_INT_STATUS 0x018 | |
110 | #define REG_INT_CLEAR 0x01C | |
111 | ||
112 | #define REG_PAGE_FAULT_ADDR 0x024 | |
113 | #define REG_AW_FAULT_ADDR 0x028 | |
114 | #define REG_AR_FAULT_ADDR 0x02C | |
115 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
116 | ||
117 | #define REG_MMU_VERSION 0x034 | |
118 | ||
eeb5184b CK |
119 | #define MMU_MAJ_VER(val) ((val) >> 7) |
120 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
121 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
122 | ||
123 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
124 | ||
2a96536e KC |
125 | #define REG_PB0_SADDR 0x04C |
126 | #define REG_PB0_EADDR 0x050 | |
127 | #define REG_PB1_SADDR 0x054 | |
128 | #define REG_PB1_EADDR 0x058 | |
129 | ||
6b21a5db CK |
130 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
131 | ||
734c3c73 | 132 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
133 | static sysmmu_pte_t *zero_lv2_table; |
134 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 135 | |
d09d78fc | 136 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
137 | { |
138 | return pgtable + lv1ent_offset(iova); | |
139 | } | |
140 | ||
d09d78fc | 141 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 142 | { |
d09d78fc | 143 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 144 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
145 | } |
146 | ||
147 | enum exynos_sysmmu_inttype { | |
148 | SYSMMU_PAGEFAULT, | |
149 | SYSMMU_AR_MULTIHIT, | |
150 | SYSMMU_AW_MULTIHIT, | |
151 | SYSMMU_BUSERROR, | |
152 | SYSMMU_AR_SECURITY, | |
153 | SYSMMU_AR_ACCESS, | |
154 | SYSMMU_AW_SECURITY, | |
155 | SYSMMU_AW_PROTECTION, /* 7 */ | |
156 | SYSMMU_FAULT_UNKNOWN, | |
157 | SYSMMU_FAULTS_NUM | |
158 | }; | |
159 | ||
2a96536e KC |
160 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
161 | REG_PAGE_FAULT_ADDR, | |
162 | REG_AR_FAULT_ADDR, | |
163 | REG_AW_FAULT_ADDR, | |
164 | REG_DEFAULT_SLAVE_ADDR, | |
165 | REG_AR_FAULT_ADDR, | |
166 | REG_AR_FAULT_ADDR, | |
167 | REG_AW_FAULT_ADDR, | |
168 | REG_AW_FAULT_ADDR | |
169 | }; | |
170 | ||
171 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
172 | "PAGE FAULT", | |
173 | "AR MULTI-HIT FAULT", | |
174 | "AW MULTI-HIT FAULT", | |
175 | "BUS ERROR", | |
176 | "AR SECURITY PROTECTION FAULT", | |
177 | "AR ACCESS PROTECTION FAULT", | |
178 | "AW SECURITY PROTECTION FAULT", | |
179 | "AW ACCESS PROTECTION FAULT", | |
180 | "UNKNOWN FAULT" | |
181 | }; | |
182 | ||
2860af3c MS |
183 | /* |
184 | * This structure is attached to dev.archdata.iommu of the master device | |
185 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
186 | * which are bound to given master device. It is usually referenced by 'owner' | |
187 | * pointer. | |
188 | */ | |
6b21a5db | 189 | struct exynos_iommu_owner { |
2860af3c | 190 | struct device *sysmmu; /* sysmmu controller for given master */ |
6b21a5db CK |
191 | }; |
192 | ||
2860af3c MS |
193 | /* |
194 | * This structure exynos specific generalization of struct iommu_domain. | |
195 | * It contains list of SYSMMU controllers from all master devices, which has | |
196 | * been attached to this domain and page tables of IO address space defined by | |
197 | * it. It is usually referenced by 'domain' pointer. | |
198 | */ | |
2a96536e | 199 | struct exynos_iommu_domain { |
2860af3c MS |
200 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
201 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
202 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
203 | spinlock_t lock; /* lock for modyfying list of clients */ | |
204 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 205 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
206 | }; |
207 | ||
2860af3c MS |
208 | /* |
209 | * This structure hold all data of a single SYSMMU controller, this includes | |
210 | * hw resources like registers and clocks, pointers and list nodes to connect | |
211 | * it to all other structures, internal state and parameters read from device | |
212 | * tree. It is usually referenced by 'data' pointer. | |
213 | */ | |
2a96536e | 214 | struct sysmmu_drvdata { |
2860af3c MS |
215 | struct device *sysmmu; /* SYSMMU controller device */ |
216 | struct device *master; /* master device (owner) */ | |
217 | void __iomem *sfrbase; /* our registers */ | |
218 | struct clk *clk; /* SYSMMU's clock */ | |
219 | struct clk *clk_master; /* master's device clock */ | |
220 | int activations; /* number of calls to sysmmu_enable */ | |
221 | spinlock_t lock; /* lock for modyfying state */ | |
222 | struct exynos_iommu_domain *domain; /* domain we belong to */ | |
223 | struct list_head domain_node; /* node for domain clients list */ | |
224 | phys_addr_t pgtable; /* assigned page table structure */ | |
225 | unsigned int version; /* our version */ | |
2a96536e KC |
226 | }; |
227 | ||
e1fd1eaa JR |
228 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
229 | { | |
230 | return container_of(dom, struct exynos_iommu_domain, domain); | |
231 | } | |
232 | ||
2a96536e KC |
233 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) |
234 | { | |
235 | /* return true if the System MMU was not active previously | |
236 | and it needs to be initialized */ | |
237 | return ++data->activations == 1; | |
238 | } | |
239 | ||
240 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
241 | { | |
242 | /* return true if the System MMU is needed to be disabled */ | |
243 | BUG_ON(data->activations < 1); | |
244 | return --data->activations == 0; | |
245 | } | |
246 | ||
247 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
248 | { | |
249 | return data->activations > 0; | |
250 | } | |
251 | ||
252 | static void sysmmu_unblock(void __iomem *sfrbase) | |
253 | { | |
254 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
255 | } | |
256 | ||
257 | static bool sysmmu_block(void __iomem *sfrbase) | |
258 | { | |
259 | int i = 120; | |
260 | ||
261 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
262 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
263 | --i; | |
264 | ||
265 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
266 | sysmmu_unblock(sfrbase); | |
267 | return false; | |
268 | } | |
269 | ||
270 | return true; | |
271 | } | |
272 | ||
273 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
274 | { | |
275 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
276 | } | |
277 | ||
278 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 279 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 280 | { |
3ad6b7f3 | 281 | unsigned int i; |
365409db | 282 | |
3ad6b7f3 CK |
283 | for (i = 0; i < num_inv; i++) { |
284 | __raw_writel((iova & SPAGE_MASK) | 1, | |
285 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
286 | iova += SPAGE_SIZE; | |
287 | } | |
2a96536e KC |
288 | } |
289 | ||
290 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 291 | phys_addr_t pgd) |
2a96536e | 292 | { |
2a96536e KC |
293 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); |
294 | ||
295 | __sysmmu_tlb_invalidate(sfrbase); | |
296 | } | |
297 | ||
1fab7fa7 CK |
298 | static void show_fault_information(const char *name, |
299 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 300 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 301 | { |
d09d78fc | 302 | sysmmu_pte_t *ent; |
2a96536e KC |
303 | |
304 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
305 | itype = SYSMMU_FAULT_UNKNOWN; | |
306 | ||
d09d78fc | 307 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 308 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 309 | |
7222e8db | 310 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 311 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
312 | |
313 | if (lv1ent_page(ent)) { | |
314 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 315 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 316 | } |
2a96536e KC |
317 | } |
318 | ||
319 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
320 | { | |
f171abab | 321 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 322 | struct sysmmu_drvdata *data = dev_id; |
2a96536e | 323 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 324 | sysmmu_iova_t addr = -1; |
7222e8db | 325 | int ret = -ENOSYS; |
2a96536e | 326 | |
2a96536e KC |
327 | WARN_ON(!is_sysmmu_active(data)); |
328 | ||
9d4e7a24 CK |
329 | spin_lock(&data->lock); |
330 | ||
70605870 CK |
331 | if (!IS_ERR(data->clk_master)) |
332 | clk_enable(data->clk_master); | |
9d4e7a24 | 333 | |
7222e8db CK |
334 | itype = (enum exynos_sysmmu_inttype) |
335 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
336 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 337 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
338 | else |
339 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 340 | |
1fab7fa7 CK |
341 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
342 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
343 | __func__, dev_name(data->sysmmu)); | |
344 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
345 | __func__); | |
346 | BUG(); | |
347 | } else { | |
d09d78fc | 348 | unsigned int base = |
1fab7fa7 CK |
349 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
350 | show_fault_information(dev_name(data->sysmmu), | |
351 | itype, base, addr); | |
352 | if (data->domain) | |
a9133b99 | 353 | ret = report_iommu_fault(&data->domain->domain, |
6b21a5db | 354 | data->master, addr, itype); |
2a96536e KC |
355 | } |
356 | ||
1fab7fa7 CK |
357 | /* fault is not recovered by fault handler */ |
358 | BUG_ON(ret != 0); | |
2a96536e | 359 | |
1fab7fa7 CK |
360 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
361 | ||
362 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 363 | |
70605870 CK |
364 | if (!IS_ERR(data->clk_master)) |
365 | clk_disable(data->clk_master); | |
366 | ||
9d4e7a24 | 367 | spin_unlock(&data->lock); |
2a96536e KC |
368 | |
369 | return IRQ_HANDLED; | |
370 | } | |
371 | ||
6b21a5db | 372 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 373 | { |
70605870 CK |
374 | if (!IS_ERR(data->clk_master)) |
375 | clk_enable(data->clk_master); | |
376 | ||
7222e8db | 377 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 378 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 379 | |
46c16d1e | 380 | clk_disable(data->clk); |
70605870 CK |
381 | if (!IS_ERR(data->clk_master)) |
382 | clk_disable(data->clk_master); | |
2a96536e KC |
383 | } |
384 | ||
6b21a5db | 385 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 386 | { |
6b21a5db | 387 | bool disabled; |
2a96536e KC |
388 | unsigned long flags; |
389 | ||
9d4e7a24 | 390 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 391 | |
6b21a5db CK |
392 | disabled = set_sysmmu_inactive(data); |
393 | ||
394 | if (disabled) { | |
395 | data->pgtable = 0; | |
396 | data->domain = NULL; | |
397 | ||
398 | __sysmmu_disable_nocount(data); | |
2a96536e | 399 | |
6b21a5db CK |
400 | dev_dbg(data->sysmmu, "Disabled\n"); |
401 | } else { | |
402 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
403 | data->activations); | |
2a96536e KC |
404 | } |
405 | ||
6b21a5db CK |
406 | spin_unlock_irqrestore(&data->lock, flags); |
407 | ||
408 | return disabled; | |
409 | } | |
2a96536e | 410 | |
6b21a5db CK |
411 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
412 | { | |
eeb5184b CK |
413 | unsigned int cfg = CFG_LRU | CFG_QOS(15); |
414 | unsigned int ver; | |
415 | ||
512bd0c6 | 416 | ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); |
eeb5184b CK |
417 | if (MMU_MAJ_VER(ver) == 3) { |
418 | if (MMU_MIN_VER(ver) >= 2) { | |
419 | cfg |= CFG_FLPDCACHE; | |
420 | if (MMU_MIN_VER(ver) == 3) { | |
421 | cfg |= CFG_ACGEN; | |
422 | cfg &= ~CFG_LRU; | |
423 | } else { | |
424 | cfg |= CFG_SYSSEL; | |
425 | } | |
426 | } | |
427 | } | |
6b21a5db CK |
428 | |
429 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
512bd0c6 | 430 | data->version = ver; |
6b21a5db CK |
431 | } |
432 | ||
433 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
434 | { | |
70605870 CK |
435 | if (!IS_ERR(data->clk_master)) |
436 | clk_enable(data->clk_master); | |
437 | clk_enable(data->clk); | |
438 | ||
6b21a5db CK |
439 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
440 | ||
441 | __sysmmu_init_config(data); | |
442 | ||
443 | __sysmmu_set_ptbase(data->sfrbase, data->pgtable); | |
2a96536e | 444 | |
7222e8db CK |
445 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
446 | ||
70605870 CK |
447 | if (!IS_ERR(data->clk_master)) |
448 | clk_disable(data->clk_master); | |
6b21a5db | 449 | } |
70605870 | 450 | |
bfa00489 | 451 | static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable, |
a9133b99 | 452 | struct exynos_iommu_domain *domain) |
6b21a5db CK |
453 | { |
454 | int ret = 0; | |
455 | unsigned long flags; | |
456 | ||
457 | spin_lock_irqsave(&data->lock, flags); | |
458 | if (set_sysmmu_active(data)) { | |
459 | data->pgtable = pgtable; | |
a9133b99 | 460 | data->domain = domain; |
6b21a5db CK |
461 | |
462 | __sysmmu_enable_nocount(data); | |
463 | ||
464 | dev_dbg(data->sysmmu, "Enabled\n"); | |
465 | } else { | |
466 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
467 | ||
468 | dev_dbg(data->sysmmu, "already enabled\n"); | |
469 | } | |
470 | ||
471 | if (WARN_ON(ret < 0)) | |
472 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 473 | |
9d4e7a24 | 474 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
475 | |
476 | return ret; | |
477 | } | |
478 | ||
66a7ed84 CK |
479 | static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
480 | sysmmu_iova_t iova) | |
481 | { | |
512bd0c6 | 482 | if (data->version == MAKE_MMU_VER(3, 3)) |
66a7ed84 CK |
483 | __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY); |
484 | } | |
485 | ||
469acebe | 486 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
487 | sysmmu_iova_t iova) |
488 | { | |
489 | unsigned long flags; | |
66a7ed84 CK |
490 | |
491 | if (!IS_ERR(data->clk_master)) | |
492 | clk_enable(data->clk_master); | |
493 | ||
494 | spin_lock_irqsave(&data->lock, flags); | |
495 | if (is_sysmmu_active(data)) | |
496 | __sysmmu_tlb_invalidate_flpdcache(data, iova); | |
497 | spin_unlock_irqrestore(&data->lock, flags); | |
498 | ||
499 | if (!IS_ERR(data->clk_master)) | |
500 | clk_disable(data->clk_master); | |
501 | } | |
502 | ||
469acebe MS |
503 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
504 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
505 | { |
506 | unsigned long flags; | |
2a96536e | 507 | |
6b21a5db | 508 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 509 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 510 | unsigned int num_inv = 1; |
70605870 CK |
511 | |
512 | if (!IS_ERR(data->clk_master)) | |
513 | clk_enable(data->clk_master); | |
514 | ||
3ad6b7f3 CK |
515 | /* |
516 | * L2TLB invalidation required | |
517 | * 4KB page: 1 invalidation | |
f171abab SK |
518 | * 64KB page: 16 invalidations |
519 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
520 | * because it is set-associative TLB |
521 | * with 8-way and 64 sets. | |
522 | * 1MB page can be cached in one of all sets. | |
523 | * 64KB page can be one of 16 consecutive sets. | |
524 | */ | |
512bd0c6 | 525 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
526 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
527 | ||
7222e8db CK |
528 | if (sysmmu_block(data->sfrbase)) { |
529 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 530 | data->sfrbase, iova, num_inv); |
7222e8db | 531 | sysmmu_unblock(data->sfrbase); |
2a96536e | 532 | } |
70605870 CK |
533 | if (!IS_ERR(data->clk_master)) |
534 | clk_disable(data->clk_master); | |
2a96536e | 535 | } else { |
469acebe MS |
536 | dev_dbg(data->master, |
537 | "disabled. Skipping TLB invalidation @ %#x\n", iova); | |
2a96536e | 538 | } |
9d4e7a24 | 539 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
540 | } |
541 | ||
6b21a5db | 542 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 543 | { |
46c16d1e | 544 | int irq, ret; |
7222e8db | 545 | struct device *dev = &pdev->dev; |
2a96536e | 546 | struct sysmmu_drvdata *data; |
7222e8db | 547 | struct resource *res; |
2a96536e | 548 | |
46c16d1e CK |
549 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
550 | if (!data) | |
551 | return -ENOMEM; | |
2a96536e | 552 | |
7222e8db | 553 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
554 | data->sfrbase = devm_ioremap_resource(dev, res); |
555 | if (IS_ERR(data->sfrbase)) | |
556 | return PTR_ERR(data->sfrbase); | |
2a96536e | 557 | |
46c16d1e CK |
558 | irq = platform_get_irq(pdev, 0); |
559 | if (irq <= 0) { | |
0bf4e54d | 560 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 561 | return irq; |
2a96536e KC |
562 | } |
563 | ||
46c16d1e | 564 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
565 | dev_name(dev), data); |
566 | if (ret) { | |
46c16d1e CK |
567 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
568 | return ret; | |
2a96536e KC |
569 | } |
570 | ||
46c16d1e CK |
571 | data->clk = devm_clk_get(dev, "sysmmu"); |
572 | if (IS_ERR(data->clk)) { | |
573 | dev_err(dev, "Failed to get clock!\n"); | |
574 | return PTR_ERR(data->clk); | |
575 | } else { | |
576 | ret = clk_prepare(data->clk); | |
577 | if (ret) { | |
578 | dev_err(dev, "Failed to prepare clk\n"); | |
579 | return ret; | |
580 | } | |
2a96536e KC |
581 | } |
582 | ||
70605870 CK |
583 | data->clk_master = devm_clk_get(dev, "master"); |
584 | if (!IS_ERR(data->clk_master)) { | |
585 | ret = clk_prepare(data->clk_master); | |
586 | if (ret) { | |
587 | clk_unprepare(data->clk); | |
588 | dev_err(dev, "Failed to prepare master's clk\n"); | |
589 | return ret; | |
590 | } | |
591 | } | |
592 | ||
2a96536e | 593 | data->sysmmu = dev; |
9d4e7a24 | 594 | spin_lock_init(&data->lock); |
2a96536e | 595 | |
7222e8db CK |
596 | platform_set_drvdata(pdev, data); |
597 | ||
f4723ec1 | 598 | pm_runtime_enable(dev); |
2a96536e | 599 | |
2a96536e | 600 | return 0; |
2a96536e KC |
601 | } |
602 | ||
6b21a5db CK |
603 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
604 | { .compatible = "samsung,exynos-sysmmu", }, | |
605 | { }, | |
606 | }; | |
607 | ||
608 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
609 | .probe = exynos_sysmmu_probe, | |
610 | .driver = { | |
2a96536e | 611 | .name = "exynos-sysmmu", |
6b21a5db | 612 | .of_match_table = sysmmu_of_match, |
2a96536e KC |
613 | } |
614 | }; | |
615 | ||
616 | static inline void pgtable_flush(void *vastart, void *vaend) | |
617 | { | |
618 | dmac_flush_range(vastart, vaend); | |
619 | outer_flush_range(virt_to_phys(vastart), | |
620 | virt_to_phys(vaend)); | |
621 | } | |
622 | ||
e1fd1eaa | 623 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 624 | { |
bfa00489 | 625 | struct exynos_iommu_domain *domain; |
66a7ed84 | 626 | int i; |
2a96536e | 627 | |
e1fd1eaa JR |
628 | if (type != IOMMU_DOMAIN_UNMANAGED) |
629 | return NULL; | |
630 | ||
bfa00489 MS |
631 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
632 | if (!domain) | |
e1fd1eaa | 633 | return NULL; |
2a96536e | 634 | |
bfa00489 MS |
635 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
636 | if (!domain->pgtable) | |
2a96536e KC |
637 | goto err_pgtable; |
638 | ||
bfa00489 MS |
639 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
640 | if (!domain->lv2entcnt) | |
2a96536e KC |
641 | goto err_counter; |
642 | ||
f171abab | 643 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 644 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
bfa00489 MS |
645 | domain->pgtable[i + 0] = ZERO_LV2LINK; |
646 | domain->pgtable[i + 1] = ZERO_LV2LINK; | |
647 | domain->pgtable[i + 2] = ZERO_LV2LINK; | |
648 | domain->pgtable[i + 3] = ZERO_LV2LINK; | |
649 | domain->pgtable[i + 4] = ZERO_LV2LINK; | |
650 | domain->pgtable[i + 5] = ZERO_LV2LINK; | |
651 | domain->pgtable[i + 6] = ZERO_LV2LINK; | |
652 | domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
653 | } |
654 | ||
bfa00489 | 655 | pgtable_flush(domain->pgtable, domain->pgtable + NUM_LV1ENTRIES); |
2a96536e | 656 | |
bfa00489 MS |
657 | spin_lock_init(&domain->lock); |
658 | spin_lock_init(&domain->pgtablelock); | |
659 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 660 | |
bfa00489 MS |
661 | domain->domain.geometry.aperture_start = 0; |
662 | domain->domain.geometry.aperture_end = ~0UL; | |
663 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 664 | |
bfa00489 | 665 | return &domain->domain; |
2a96536e KC |
666 | |
667 | err_counter: | |
bfa00489 | 668 | free_pages((unsigned long)domain->pgtable, 2); |
2a96536e | 669 | err_pgtable: |
bfa00489 | 670 | kfree(domain); |
e1fd1eaa | 671 | return NULL; |
2a96536e KC |
672 | } |
673 | ||
bfa00489 | 674 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 675 | { |
bfa00489 | 676 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 677 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
678 | unsigned long flags; |
679 | int i; | |
680 | ||
bfa00489 | 681 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 682 | |
bfa00489 | 683 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 684 | |
bfa00489 | 685 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
686 | if (__sysmmu_disable(data)) |
687 | data->master = NULL; | |
688 | list_del_init(&data->domain_node); | |
2a96536e KC |
689 | } |
690 | ||
bfa00489 | 691 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e KC |
692 | |
693 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
bfa00489 | 694 | if (lv1ent_page(domain->pgtable + i)) |
734c3c73 | 695 | kmem_cache_free(lv2table_kmem_cache, |
bfa00489 | 696 | phys_to_virt(lv2table_base(domain->pgtable + i))); |
2a96536e | 697 | |
bfa00489 MS |
698 | free_pages((unsigned long)domain->pgtable, 2); |
699 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
700 | kfree(domain); | |
2a96536e KC |
701 | } |
702 | ||
bfa00489 | 703 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
704 | struct device *dev) |
705 | { | |
6b21a5db | 706 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 707 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 708 | struct sysmmu_drvdata *data; |
bfa00489 | 709 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 710 | unsigned long flags; |
469acebe | 711 | int ret = -ENODEV; |
2a96536e | 712 | |
469acebe MS |
713 | if (!has_sysmmu(dev)) |
714 | return -ENODEV; | |
2a96536e | 715 | |
469acebe MS |
716 | data = dev_get_drvdata(owner->sysmmu); |
717 | if (data) { | |
a9133b99 | 718 | ret = __sysmmu_enable(data, pagetable, domain); |
469acebe MS |
719 | if (ret >= 0) { |
720 | data->master = dev; | |
721 | ||
bfa00489 MS |
722 | spin_lock_irqsave(&domain->lock, flags); |
723 | list_add_tail(&data->domain_node, &domain->clients); | |
724 | spin_unlock_irqrestore(&domain->lock, flags); | |
469acebe MS |
725 | } |
726 | } | |
2a96536e KC |
727 | |
728 | if (ret < 0) { | |
7222e8db CK |
729 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
730 | __func__, &pagetable); | |
7222e8db | 731 | return ret; |
2a96536e KC |
732 | } |
733 | ||
7222e8db CK |
734 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
735 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
736 | ||
2a96536e KC |
737 | return ret; |
738 | } | |
739 | ||
bfa00489 | 740 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
741 | struct device *dev) |
742 | { | |
bfa00489 MS |
743 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
744 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
469acebe | 745 | struct sysmmu_drvdata *data; |
2a96536e | 746 | unsigned long flags; |
469acebe | 747 | bool found = false; |
2a96536e | 748 | |
469acebe MS |
749 | if (!has_sysmmu(dev)) |
750 | return; | |
2a96536e | 751 | |
bfa00489 MS |
752 | spin_lock_irqsave(&domain->lock, flags); |
753 | list_for_each_entry(data, &domain->clients, domain_node) { | |
469acebe MS |
754 | if (data->master == dev) { |
755 | if (__sysmmu_disable(data)) { | |
756 | data->master = NULL; | |
757 | list_del_init(&data->domain_node); | |
758 | } | |
759 | found = true; | |
2a96536e KC |
760 | break; |
761 | } | |
762 | } | |
bfa00489 | 763 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 764 | |
469acebe | 765 | if (found) |
7222e8db CK |
766 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
767 | __func__, &pagetable); | |
6b21a5db CK |
768 | else |
769 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
770 | } |
771 | ||
bfa00489 | 772 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 773 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 774 | { |
61128f08 | 775 | if (lv1ent_section(sent)) { |
d09d78fc | 776 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
777 | return ERR_PTR(-EADDRINUSE); |
778 | } | |
779 | ||
2a96536e | 780 | if (lv1ent_fault(sent)) { |
d09d78fc | 781 | sysmmu_pte_t *pent; |
66a7ed84 | 782 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 783 | |
734c3c73 | 784 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 785 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 786 | if (!pent) |
61128f08 | 787 | return ERR_PTR(-ENOMEM); |
2a96536e | 788 | |
7222e8db | 789 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
dc3814f4 | 790 | kmemleak_ignore(pent); |
2a96536e KC |
791 | *pgcounter = NUM_LV2ENTRIES; |
792 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
793 | pgtable_flush(sent, sent + 1); | |
66a7ed84 CK |
794 | |
795 | /* | |
f171abab SK |
796 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
797 | * FLPD cache may cache the address of zero_l2_table. This | |
798 | * function replaces the zero_l2_table with new L2 page table | |
799 | * to write valid mappings. | |
66a7ed84 | 800 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
801 | * cache may still cache zero_l2_table for the valid area |
802 | * instead of new L2 page table that has the mapping | |
803 | * information of the valid area. | |
66a7ed84 CK |
804 | * Thus any replacement of zero_l2_table with other valid L2 |
805 | * page table must involve FLPD cache invalidation for System | |
806 | * MMU v3.3. | |
807 | * FLPD cache invalidation is performed with TLB invalidation | |
808 | * by VPN without blocking. It is safe to invalidate TLB without | |
809 | * blocking because the target address of TLB invalidation is | |
810 | * not currently mapped. | |
811 | */ | |
812 | if (need_flush_flpd_cache) { | |
469acebe | 813 | struct sysmmu_drvdata *data; |
365409db | 814 | |
bfa00489 MS |
815 | spin_lock(&domain->lock); |
816 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 817 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 818 | spin_unlock(&domain->lock); |
66a7ed84 | 819 | } |
2a96536e KC |
820 | } |
821 | ||
822 | return page_entry(sent, iova); | |
823 | } | |
824 | ||
bfa00489 | 825 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 826 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 827 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 828 | { |
61128f08 | 829 | if (lv1ent_section(sent)) { |
d09d78fc | 830 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 831 | iova); |
2a96536e | 832 | return -EADDRINUSE; |
61128f08 | 833 | } |
2a96536e KC |
834 | |
835 | if (lv1ent_page(sent)) { | |
61128f08 | 836 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 837 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 838 | iova); |
2a96536e | 839 | return -EADDRINUSE; |
61128f08 | 840 | } |
2a96536e | 841 | |
734c3c73 | 842 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
843 | *pgcnt = 0; |
844 | } | |
845 | ||
846 | *sent = mk_lv1ent_sect(paddr); | |
847 | ||
848 | pgtable_flush(sent, sent + 1); | |
849 | ||
bfa00489 | 850 | spin_lock(&domain->lock); |
66a7ed84 | 851 | if (lv1ent_page_zero(sent)) { |
469acebe | 852 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
853 | /* |
854 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
855 | * entry by speculative prefetch of SLPD which has no mapping. | |
856 | */ | |
bfa00489 | 857 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 858 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 859 | } |
bfa00489 | 860 | spin_unlock(&domain->lock); |
66a7ed84 | 861 | |
2a96536e KC |
862 | return 0; |
863 | } | |
864 | ||
d09d78fc | 865 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
866 | short *pgcnt) |
867 | { | |
868 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 869 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
870 | return -EADDRINUSE; |
871 | ||
872 | *pent = mk_lv2ent_spage(paddr); | |
873 | pgtable_flush(pent, pent + 1); | |
874 | *pgcnt -= 1; | |
875 | } else { /* size == LPAGE_SIZE */ | |
876 | int i; | |
365409db | 877 | |
2a96536e | 878 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 879 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
880 | if (i > 0) |
881 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
882 | return -EADDRINUSE; |
883 | } | |
884 | ||
885 | *pent = mk_lv2ent_lpage(paddr); | |
886 | } | |
887 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
888 | *pgcnt -= SPAGES_PER_LPAGE; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
66a7ed84 CK |
894 | /* |
895 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
896 | * | |
f171abab | 897 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 898 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
899 | * However, the logic has a bug that while caching faulty page table entries, |
900 | * System MMU reports page fault if the cached fault entry is hit even though | |
901 | * the fault entry is updated to a valid entry after the entry is cached. | |
902 | * To prevent caching faulty page table entries which may be updated to valid | |
903 | * entries later, the virtual memory manager should care about the workaround | |
904 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
905 | * |
906 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 907 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 908 | * |
f171abab | 909 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
910 | * the following sizes for System MMU v3.1 and v3.2. |
911 | * System MMU v3.1: 128KiB | |
912 | * System MMU v3.2: 256KiB | |
913 | * | |
914 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
915 | * more workarounds. |
916 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
917 | * than or equal to 128KiB. | |
66a7ed84 CK |
918 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
919 | */ | |
bfa00489 MS |
920 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
921 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
922 | int prot) | |
2a96536e | 923 | { |
bfa00489 | 924 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
925 | sysmmu_pte_t *entry; |
926 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
927 | unsigned long flags; |
928 | int ret = -ENOMEM; | |
929 | ||
bfa00489 | 930 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 931 | |
bfa00489 | 932 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 933 | |
bfa00489 | 934 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
935 | |
936 | if (size == SECT_SIZE) { | |
bfa00489 MS |
937 | ret = lv1set_section(domain, entry, iova, paddr, |
938 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 939 | } else { |
d09d78fc | 940 | sysmmu_pte_t *pent; |
2a96536e | 941 | |
bfa00489 MS |
942 | pent = alloc_lv2entry(domain, entry, iova, |
943 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 944 | |
61128f08 CK |
945 | if (IS_ERR(pent)) |
946 | ret = PTR_ERR(pent); | |
2a96536e KC |
947 | else |
948 | ret = lv2set_page(pent, paddr, size, | |
bfa00489 | 949 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
950 | } |
951 | ||
61128f08 | 952 | if (ret) |
0bf4e54d CK |
953 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
954 | __func__, ret, size, iova); | |
2a96536e | 955 | |
bfa00489 | 956 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
957 | |
958 | return ret; | |
959 | } | |
960 | ||
bfa00489 MS |
961 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
962 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 963 | { |
469acebe | 964 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
965 | unsigned long flags; |
966 | ||
bfa00489 | 967 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 968 | |
bfa00489 | 969 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 970 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 971 | |
bfa00489 | 972 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
973 | } |
974 | ||
bfa00489 MS |
975 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
976 | unsigned long l_iova, size_t size) | |
2a96536e | 977 | { |
bfa00489 | 978 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
979 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
980 | sysmmu_pte_t *ent; | |
61128f08 | 981 | size_t err_pgsize; |
d09d78fc | 982 | unsigned long flags; |
2a96536e | 983 | |
bfa00489 | 984 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 985 | |
bfa00489 | 986 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 987 | |
bfa00489 | 988 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
989 | |
990 | if (lv1ent_section(ent)) { | |
0bf4e54d | 991 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
992 | err_pgsize = SECT_SIZE; |
993 | goto err; | |
994 | } | |
2a96536e | 995 | |
f171abab SK |
996 | /* workaround for h/w bug in System MMU v3.3 */ |
997 | *ent = ZERO_LV2LINK; | |
2a96536e KC |
998 | pgtable_flush(ent, ent + 1); |
999 | size = SECT_SIZE; | |
1000 | goto done; | |
1001 | } | |
1002 | ||
1003 | if (unlikely(lv1ent_fault(ent))) { | |
1004 | if (size > SECT_SIZE) | |
1005 | size = SECT_SIZE; | |
1006 | goto done; | |
1007 | } | |
1008 | ||
1009 | /* lv1ent_page(sent) == true here */ | |
1010 | ||
1011 | ent = page_entry(ent, iova); | |
1012 | ||
1013 | if (unlikely(lv2ent_fault(ent))) { | |
1014 | size = SPAGE_SIZE; | |
1015 | goto done; | |
1016 | } | |
1017 | ||
1018 | if (lv2ent_small(ent)) { | |
1019 | *ent = 0; | |
1020 | size = SPAGE_SIZE; | |
6cb47ed7 | 1021 | pgtable_flush(ent, ent + 1); |
bfa00489 | 1022 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1023 | goto done; |
1024 | } | |
1025 | ||
1026 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1027 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1028 | err_pgsize = LPAGE_SIZE; |
1029 | goto err; | |
1030 | } | |
2a96536e KC |
1031 | |
1032 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 1033 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
1034 | |
1035 | size = LPAGE_SIZE; | |
bfa00489 | 1036 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1037 | done: |
bfa00489 | 1038 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1039 | |
bfa00489 | 1040 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1041 | |
2a96536e | 1042 | return size; |
61128f08 | 1043 | err: |
bfa00489 | 1044 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1045 | |
0bf4e54d CK |
1046 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1047 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1048 | |
1049 | return 0; | |
2a96536e KC |
1050 | } |
1051 | ||
bfa00489 | 1052 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1053 | dma_addr_t iova) |
2a96536e | 1054 | { |
bfa00489 | 1055 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1056 | sysmmu_pte_t *entry; |
2a96536e KC |
1057 | unsigned long flags; |
1058 | phys_addr_t phys = 0; | |
1059 | ||
bfa00489 | 1060 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1061 | |
bfa00489 | 1062 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1063 | |
1064 | if (lv1ent_section(entry)) { | |
1065 | phys = section_phys(entry) + section_offs(iova); | |
1066 | } else if (lv1ent_page(entry)) { | |
1067 | entry = page_entry(entry, iova); | |
1068 | ||
1069 | if (lv2ent_large(entry)) | |
1070 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1071 | else if (lv2ent_small(entry)) | |
1072 | phys = spage_phys(entry) + spage_offs(iova); | |
1073 | } | |
1074 | ||
bfa00489 | 1075 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1076 | |
1077 | return phys; | |
1078 | } | |
1079 | ||
bf4a1c92 AM |
1080 | static int exynos_iommu_add_device(struct device *dev) |
1081 | { | |
1082 | struct iommu_group *group; | |
1083 | int ret; | |
1084 | ||
1085 | group = iommu_group_get(dev); | |
1086 | ||
1087 | if (!group) { | |
1088 | group = iommu_group_alloc(); | |
1089 | if (IS_ERR(group)) { | |
1090 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1091 | return PTR_ERR(group); | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | ret = iommu_group_add_device(group, dev); | |
1096 | iommu_group_put(group); | |
1097 | ||
1098 | return ret; | |
1099 | } | |
1100 | ||
1101 | static void exynos_iommu_remove_device(struct device *dev) | |
1102 | { | |
1103 | iommu_group_remove_device(dev); | |
1104 | } | |
1105 | ||
b22f6434 | 1106 | static const struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1107 | .domain_alloc = exynos_iommu_domain_alloc, |
1108 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1109 | .attach_dev = exynos_iommu_attach_device, |
1110 | .detach_dev = exynos_iommu_detach_device, | |
1111 | .map = exynos_iommu_map, | |
1112 | .unmap = exynos_iommu_unmap, | |
315786eb | 1113 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 BH |
1114 | .iova_to_phys = exynos_iommu_iova_to_phys, |
1115 | .add_device = exynos_iommu_add_device, | |
1116 | .remove_device = exynos_iommu_remove_device, | |
2a96536e KC |
1117 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
1118 | }; | |
1119 | ||
1120 | static int __init exynos_iommu_init(void) | |
1121 | { | |
a7b67cd5 | 1122 | struct device_node *np; |
2a96536e KC |
1123 | int ret; |
1124 | ||
a7b67cd5 TR |
1125 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1126 | if (!np) | |
1127 | return 0; | |
1128 | ||
1129 | of_node_put(np); | |
1130 | ||
734c3c73 CK |
1131 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1132 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1133 | if (!lv2table_kmem_cache) { | |
1134 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1135 | return -ENOMEM; | |
1136 | } | |
1137 | ||
2a96536e | 1138 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1139 | if (ret) { |
1140 | pr_err("%s: Failed to register driver\n", __func__); | |
1141 | goto err_reg_driver; | |
1142 | } | |
2a96536e | 1143 | |
66a7ed84 CK |
1144 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1145 | if (zero_lv2_table == NULL) { | |
1146 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1147 | __func__); | |
1148 | ret = -ENOMEM; | |
1149 | goto err_zero_lv2; | |
1150 | } | |
1151 | ||
734c3c73 CK |
1152 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1153 | if (ret) { | |
1154 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1155 | __func__); | |
1156 | goto err_set_iommu; | |
1157 | } | |
2a96536e | 1158 | |
734c3c73 CK |
1159 | return 0; |
1160 | err_set_iommu: | |
66a7ed84 CK |
1161 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1162 | err_zero_lv2: | |
734c3c73 CK |
1163 | platform_driver_unregister(&exynos_sysmmu_driver); |
1164 | err_reg_driver: | |
1165 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1166 | return ret; |
1167 | } | |
1168 | subsys_initcall(exynos_iommu_init); |