Commit | Line | Data |
---|---|---|
2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/memblock.h> | |
27 | #include <linux/export.h> | |
28 | ||
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/pgtable.h> | |
31 | ||
2a96536e KC |
32 | /* We does not consider super section mapping (16MB) */ |
33 | #define SECT_ORDER 20 | |
34 | #define LPAGE_ORDER 16 | |
35 | #define SPAGE_ORDER 12 | |
36 | ||
37 | #define SECT_SIZE (1 << SECT_ORDER) | |
38 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
39 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
40 | ||
41 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
42 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
43 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
44 | ||
45 | #define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
46 | #define lv1ent_page(sent) ((*(sent) & 3) == 1) | |
47 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) | |
48 | ||
49 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
50 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
51 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
52 | ||
53 | #define section_phys(sent) (*(sent) & SECT_MASK) | |
54 | #define section_offs(iova) ((iova) & 0xFFFFF) | |
55 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) | |
56 | #define lpage_offs(iova) ((iova) & 0xFFFF) | |
57 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) | |
58 | #define spage_offs(iova) ((iova) & 0xFFF) | |
59 | ||
60 | #define lv1ent_offset(iova) ((iova) >> SECT_ORDER) | |
61 | #define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER) | |
62 | ||
63 | #define NUM_LV1ENTRIES 4096 | |
64 | #define NUM_LV2ENTRIES 256 | |
65 | ||
66 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long)) | |
67 | ||
68 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
69 | ||
70 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
71 | ||
72 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
73 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
74 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
75 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
76 | ||
77 | #define CTRL_ENABLE 0x5 | |
78 | #define CTRL_BLOCK 0x7 | |
79 | #define CTRL_DISABLE 0x0 | |
80 | ||
81 | #define REG_MMU_CTRL 0x000 | |
82 | #define REG_MMU_CFG 0x004 | |
83 | #define REG_MMU_STATUS 0x008 | |
84 | #define REG_MMU_FLUSH 0x00C | |
85 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
86 | #define REG_PT_BASE_ADDR 0x014 | |
87 | #define REG_INT_STATUS 0x018 | |
88 | #define REG_INT_CLEAR 0x01C | |
89 | ||
90 | #define REG_PAGE_FAULT_ADDR 0x024 | |
91 | #define REG_AW_FAULT_ADDR 0x028 | |
92 | #define REG_AR_FAULT_ADDR 0x02C | |
93 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
94 | ||
95 | #define REG_MMU_VERSION 0x034 | |
96 | ||
97 | #define REG_PB0_SADDR 0x04C | |
98 | #define REG_PB0_EADDR 0x050 | |
99 | #define REG_PB1_SADDR 0x054 | |
100 | #define REG_PB1_EADDR 0x058 | |
101 | ||
734c3c73 CK |
102 | static struct kmem_cache *lv2table_kmem_cache; |
103 | ||
2a96536e KC |
104 | static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova) |
105 | { | |
106 | return pgtable + lv1ent_offset(iova); | |
107 | } | |
108 | ||
109 | static unsigned long *page_entry(unsigned long *sent, unsigned long iova) | |
110 | { | |
7222e8db CK |
111 | return (unsigned long *)phys_to_virt( |
112 | lv2table_base(sent)) + lv2ent_offset(iova); | |
2a96536e KC |
113 | } |
114 | ||
115 | enum exynos_sysmmu_inttype { | |
116 | SYSMMU_PAGEFAULT, | |
117 | SYSMMU_AR_MULTIHIT, | |
118 | SYSMMU_AW_MULTIHIT, | |
119 | SYSMMU_BUSERROR, | |
120 | SYSMMU_AR_SECURITY, | |
121 | SYSMMU_AR_ACCESS, | |
122 | SYSMMU_AW_SECURITY, | |
123 | SYSMMU_AW_PROTECTION, /* 7 */ | |
124 | SYSMMU_FAULT_UNKNOWN, | |
125 | SYSMMU_FAULTS_NUM | |
126 | }; | |
127 | ||
128 | /* | |
129 | * @itype: type of fault. | |
130 | * @pgtable_base: the physical address of page table base. This is 0 if @itype | |
131 | * is SYSMMU_BUSERROR. | |
132 | * @fault_addr: the device (virtual) address that the System MMU tried to | |
133 | * translated. This is 0 if @itype is SYSMMU_BUSERROR. | |
134 | */ | |
135 | typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype, | |
7222e8db | 136 | phys_addr_t pgtable_base, unsigned long fault_addr); |
2a96536e KC |
137 | |
138 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { | |
139 | REG_PAGE_FAULT_ADDR, | |
140 | REG_AR_FAULT_ADDR, | |
141 | REG_AW_FAULT_ADDR, | |
142 | REG_DEFAULT_SLAVE_ADDR, | |
143 | REG_AR_FAULT_ADDR, | |
144 | REG_AR_FAULT_ADDR, | |
145 | REG_AW_FAULT_ADDR, | |
146 | REG_AW_FAULT_ADDR | |
147 | }; | |
148 | ||
149 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
150 | "PAGE FAULT", | |
151 | "AR MULTI-HIT FAULT", | |
152 | "AW MULTI-HIT FAULT", | |
153 | "BUS ERROR", | |
154 | "AR SECURITY PROTECTION FAULT", | |
155 | "AR ACCESS PROTECTION FAULT", | |
156 | "AW SECURITY PROTECTION FAULT", | |
157 | "AW ACCESS PROTECTION FAULT", | |
158 | "UNKNOWN FAULT" | |
159 | }; | |
160 | ||
161 | struct exynos_iommu_domain { | |
162 | struct list_head clients; /* list of sysmmu_drvdata.node */ | |
163 | unsigned long *pgtable; /* lv1 page table, 16KB */ | |
164 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
165 | spinlock_t lock; /* lock for this structure */ | |
166 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
167 | }; | |
168 | ||
169 | struct sysmmu_drvdata { | |
170 | struct list_head node; /* entry of exynos_iommu_domain.clients */ | |
171 | struct device *sysmmu; /* System MMU's device descriptor */ | |
172 | struct device *dev; /* Owner of system MMU */ | |
7222e8db CK |
173 | void __iomem *sfrbase; |
174 | struct clk *clk; | |
2a96536e KC |
175 | int activations; |
176 | rwlock_t lock; | |
177 | struct iommu_domain *domain; | |
178 | sysmmu_fault_handler_t fault_handler; | |
7222e8db | 179 | phys_addr_t pgtable; |
2a96536e KC |
180 | }; |
181 | ||
182 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) | |
183 | { | |
184 | /* return true if the System MMU was not active previously | |
185 | and it needs to be initialized */ | |
186 | return ++data->activations == 1; | |
187 | } | |
188 | ||
189 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
190 | { | |
191 | /* return true if the System MMU is needed to be disabled */ | |
192 | BUG_ON(data->activations < 1); | |
193 | return --data->activations == 0; | |
194 | } | |
195 | ||
196 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
197 | { | |
198 | return data->activations > 0; | |
199 | } | |
200 | ||
201 | static void sysmmu_unblock(void __iomem *sfrbase) | |
202 | { | |
203 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
204 | } | |
205 | ||
206 | static bool sysmmu_block(void __iomem *sfrbase) | |
207 | { | |
208 | int i = 120; | |
209 | ||
210 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
211 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
212 | --i; | |
213 | ||
214 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
215 | sysmmu_unblock(sfrbase); | |
216 | return false; | |
217 | } | |
218 | ||
219 | return true; | |
220 | } | |
221 | ||
222 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
223 | { | |
224 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
225 | } | |
226 | ||
227 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
3ad6b7f3 | 228 | unsigned long iova, unsigned int num_inv) |
2a96536e | 229 | { |
3ad6b7f3 CK |
230 | unsigned int i; |
231 | for (i = 0; i < num_inv; i++) { | |
232 | __raw_writel((iova & SPAGE_MASK) | 1, | |
233 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
234 | iova += SPAGE_SIZE; | |
235 | } | |
2a96536e KC |
236 | } |
237 | ||
238 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
239 | unsigned long pgd) | |
240 | { | |
241 | __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */ | |
242 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); | |
243 | ||
244 | __sysmmu_tlb_invalidate(sfrbase); | |
245 | } | |
246 | ||
2a96536e KC |
247 | static void __set_fault_handler(struct sysmmu_drvdata *data, |
248 | sysmmu_fault_handler_t handler) | |
249 | { | |
250 | unsigned long flags; | |
251 | ||
252 | write_lock_irqsave(&data->lock, flags); | |
253 | data->fault_handler = handler; | |
254 | write_unlock_irqrestore(&data->lock, flags); | |
255 | } | |
256 | ||
257 | void exynos_sysmmu_set_fault_handler(struct device *dev, | |
258 | sysmmu_fault_handler_t handler) | |
259 | { | |
260 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
261 | ||
262 | __set_fault_handler(data, handler); | |
263 | } | |
264 | ||
265 | static int default_fault_handler(enum exynos_sysmmu_inttype itype, | |
7222e8db | 266 | phys_addr_t pgtable_base, unsigned long fault_addr) |
2a96536e KC |
267 | { |
268 | unsigned long *ent; | |
269 | ||
270 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
271 | itype = SYSMMU_FAULT_UNKNOWN; | |
272 | ||
7222e8db CK |
273 | pr_err("%s occurred at 0x%lx(Page table base: %pa)\n", |
274 | sysmmu_fault_name[itype], fault_addr, &pgtable_base); | |
2a96536e | 275 | |
7222e8db | 276 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
2a96536e KC |
277 | pr_err("\tLv1 entry: 0x%lx\n", *ent); |
278 | ||
279 | if (lv1ent_page(ent)) { | |
280 | ent = page_entry(ent, fault_addr); | |
281 | pr_err("\t Lv2 entry: 0x%lx\n", *ent); | |
282 | } | |
283 | ||
284 | pr_err("Generating Kernel OOPS... because it is unrecoverable.\n"); | |
285 | ||
286 | BUG(); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
292 | { | |
293 | /* SYSMMU is in blocked when interrupt occurred. */ | |
294 | struct sysmmu_drvdata *data = dev_id; | |
2a96536e KC |
295 | enum exynos_sysmmu_inttype itype; |
296 | unsigned long addr = -1; | |
7222e8db | 297 | int ret = -ENOSYS; |
2a96536e KC |
298 | |
299 | read_lock(&data->lock); | |
300 | ||
301 | WARN_ON(!is_sysmmu_active(data)); | |
302 | ||
7222e8db CK |
303 | itype = (enum exynos_sysmmu_inttype) |
304 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
305 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 306 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
307 | else |
308 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e KC |
309 | |
310 | if (data->domain) | |
7222e8db | 311 | ret = report_iommu_fault(data->domain, data->dev, addr, itype); |
2a96536e KC |
312 | |
313 | if ((ret == -ENOSYS) && data->fault_handler) { | |
314 | unsigned long base = data->pgtable; | |
315 | if (itype != SYSMMU_FAULT_UNKNOWN) | |
7222e8db | 316 | base = __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
2a96536e KC |
317 | ret = data->fault_handler(itype, base, addr); |
318 | } | |
319 | ||
320 | if (!ret && (itype != SYSMMU_FAULT_UNKNOWN)) | |
7222e8db | 321 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
2a96536e | 322 | else |
e5cf63c3 CK |
323 | dev_dbg(data->sysmmu, "%s is not handled.\n", |
324 | sysmmu_fault_name[itype]); | |
2a96536e KC |
325 | |
326 | if (itype != SYSMMU_FAULT_UNKNOWN) | |
7222e8db | 327 | sysmmu_unblock(data->sfrbase); |
2a96536e KC |
328 | |
329 | read_unlock(&data->lock); | |
330 | ||
331 | return IRQ_HANDLED; | |
332 | } | |
333 | ||
334 | static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data) | |
335 | { | |
336 | unsigned long flags; | |
337 | bool disabled = false; | |
2a96536e KC |
338 | |
339 | write_lock_irqsave(&data->lock, flags); | |
340 | ||
341 | if (!set_sysmmu_inactive(data)) | |
342 | goto finish; | |
343 | ||
7222e8db | 344 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e | 345 | |
46c16d1e | 346 | clk_disable(data->clk); |
2a96536e KC |
347 | |
348 | disabled = true; | |
349 | data->pgtable = 0; | |
350 | data->domain = NULL; | |
351 | finish: | |
352 | write_unlock_irqrestore(&data->lock, flags); | |
353 | ||
354 | if (disabled) | |
e5cf63c3 | 355 | dev_dbg(data->sysmmu, "Disabled\n"); |
2a96536e | 356 | else |
e5cf63c3 CK |
357 | dev_dbg(data->sysmmu, "%d times left to be disabled\n", |
358 | data->activations); | |
2a96536e KC |
359 | |
360 | return disabled; | |
361 | } | |
362 | ||
363 | /* __exynos_sysmmu_enable: Enables System MMU | |
364 | * | |
365 | * returns -error if an error occurred and System MMU is not enabled, | |
366 | * 0 if the System MMU has been just enabled and 1 if System MMU was already | |
367 | * enabled before. | |
368 | */ | |
369 | static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data, | |
370 | unsigned long pgtable, struct iommu_domain *domain) | |
371 | { | |
7222e8db | 372 | int ret = 0; |
2a96536e KC |
373 | unsigned long flags; |
374 | ||
375 | write_lock_irqsave(&data->lock, flags); | |
376 | ||
377 | if (!set_sysmmu_active(data)) { | |
378 | if (WARN_ON(pgtable != data->pgtable)) { | |
379 | ret = -EBUSY; | |
380 | set_sysmmu_inactive(data); | |
381 | } else { | |
382 | ret = 1; | |
383 | } | |
384 | ||
e5cf63c3 | 385 | dev_dbg(data->sysmmu, "Already enabled\n"); |
2a96536e KC |
386 | goto finish; |
387 | } | |
388 | ||
46c16d1e | 389 | clk_enable(data->clk); |
2a96536e KC |
390 | |
391 | data->pgtable = pgtable; | |
392 | ||
7222e8db | 393 | __sysmmu_set_ptbase(data->sfrbase, pgtable); |
2a96536e | 394 | |
7222e8db CK |
395 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
396 | ||
2a96536e KC |
397 | data->domain = domain; |
398 | ||
e5cf63c3 | 399 | dev_dbg(data->sysmmu, "Enabled\n"); |
2a96536e KC |
400 | finish: |
401 | write_unlock_irqrestore(&data->lock, flags); | |
402 | ||
403 | return ret; | |
404 | } | |
405 | ||
406 | int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable) | |
407 | { | |
408 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
409 | int ret; | |
410 | ||
411 | BUG_ON(!memblock_is_memory(pgtable)); | |
412 | ||
413 | ret = pm_runtime_get_sync(data->sysmmu); | |
414 | if (ret < 0) { | |
e5cf63c3 | 415 | dev_dbg(data->sysmmu, "Failed to enable\n"); |
2a96536e KC |
416 | return ret; |
417 | } | |
418 | ||
419 | ret = __exynos_sysmmu_enable(data, pgtable, NULL); | |
420 | if (WARN_ON(ret < 0)) { | |
421 | pm_runtime_put(data->sysmmu); | |
e5cf63c3 CK |
422 | dev_err(data->sysmmu, "Already enabled with page table %#x\n", |
423 | data->pgtable); | |
2a96536e KC |
424 | } else { |
425 | data->dev = dev; | |
426 | } | |
427 | ||
428 | return ret; | |
429 | } | |
430 | ||
77e38350 | 431 | static bool exynos_sysmmu_disable(struct device *dev) |
2a96536e KC |
432 | { |
433 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
434 | bool disabled; | |
435 | ||
436 | disabled = __exynos_sysmmu_disable(data); | |
437 | pm_runtime_put(data->sysmmu); | |
438 | ||
439 | return disabled; | |
440 | } | |
441 | ||
3ad6b7f3 CK |
442 | static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova, |
443 | size_t size) | |
2a96536e KC |
444 | { |
445 | unsigned long flags; | |
446 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
447 | ||
448 | read_lock_irqsave(&data->lock, flags); | |
449 | ||
450 | if (is_sysmmu_active(data)) { | |
3ad6b7f3 CK |
451 | unsigned int maj; |
452 | unsigned int num_inv = 1; | |
453 | maj = __raw_readl(data->sfrbase + REG_MMU_VERSION); | |
454 | /* | |
455 | * L2TLB invalidation required | |
456 | * 4KB page: 1 invalidation | |
457 | * 64KB page: 16 invalidation | |
458 | * 1MB page: 64 invalidation | |
459 | * because it is set-associative TLB | |
460 | * with 8-way and 64 sets. | |
461 | * 1MB page can be cached in one of all sets. | |
462 | * 64KB page can be one of 16 consecutive sets. | |
463 | */ | |
464 | if ((maj >> 28) == 2) /* major version number */ | |
465 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); | |
466 | ||
7222e8db CK |
467 | if (sysmmu_block(data->sfrbase)) { |
468 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 469 | data->sfrbase, iova, num_inv); |
7222e8db | 470 | sysmmu_unblock(data->sfrbase); |
2a96536e KC |
471 | } |
472 | } else { | |
e5cf63c3 | 473 | dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n"); |
2a96536e KC |
474 | } |
475 | ||
476 | read_unlock_irqrestore(&data->lock, flags); | |
477 | } | |
478 | ||
479 | void exynos_sysmmu_tlb_invalidate(struct device *dev) | |
480 | { | |
481 | unsigned long flags; | |
482 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
483 | ||
484 | read_lock_irqsave(&data->lock, flags); | |
485 | ||
486 | if (is_sysmmu_active(data)) { | |
7222e8db CK |
487 | if (sysmmu_block(data->sfrbase)) { |
488 | __sysmmu_tlb_invalidate(data->sfrbase); | |
489 | sysmmu_unblock(data->sfrbase); | |
2a96536e KC |
490 | } |
491 | } else { | |
e5cf63c3 | 492 | dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n"); |
2a96536e KC |
493 | } |
494 | ||
495 | read_unlock_irqrestore(&data->lock, flags); | |
496 | } | |
497 | ||
498 | static int exynos_sysmmu_probe(struct platform_device *pdev) | |
499 | { | |
46c16d1e | 500 | int irq, ret; |
7222e8db | 501 | struct device *dev = &pdev->dev; |
2a96536e | 502 | struct sysmmu_drvdata *data; |
7222e8db | 503 | struct resource *res; |
2a96536e | 504 | |
46c16d1e CK |
505 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
506 | if (!data) | |
507 | return -ENOMEM; | |
2a96536e | 508 | |
7222e8db | 509 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
510 | data->sfrbase = devm_ioremap_resource(dev, res); |
511 | if (IS_ERR(data->sfrbase)) | |
512 | return PTR_ERR(data->sfrbase); | |
2a96536e | 513 | |
46c16d1e CK |
514 | irq = platform_get_irq(pdev, 0); |
515 | if (irq <= 0) { | |
7222e8db | 516 | dev_dbg(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 517 | return irq; |
2a96536e KC |
518 | } |
519 | ||
46c16d1e | 520 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
521 | dev_name(dev), data); |
522 | if (ret) { | |
46c16d1e CK |
523 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
524 | return ret; | |
2a96536e KC |
525 | } |
526 | ||
46c16d1e CK |
527 | data->clk = devm_clk_get(dev, "sysmmu"); |
528 | if (IS_ERR(data->clk)) { | |
529 | dev_err(dev, "Failed to get clock!\n"); | |
530 | return PTR_ERR(data->clk); | |
531 | } else { | |
532 | ret = clk_prepare(data->clk); | |
533 | if (ret) { | |
534 | dev_err(dev, "Failed to prepare clk\n"); | |
535 | return ret; | |
536 | } | |
2a96536e KC |
537 | } |
538 | ||
539 | data->sysmmu = dev; | |
540 | rwlock_init(&data->lock); | |
541 | INIT_LIST_HEAD(&data->node); | |
542 | ||
543 | __set_fault_handler(data, &default_fault_handler); | |
544 | ||
7222e8db CK |
545 | platform_set_drvdata(pdev, data); |
546 | ||
f4723ec1 | 547 | pm_runtime_enable(dev); |
2a96536e | 548 | |
2a96536e | 549 | return 0; |
2a96536e KC |
550 | } |
551 | ||
552 | static struct platform_driver exynos_sysmmu_driver = { | |
553 | .probe = exynos_sysmmu_probe, | |
554 | .driver = { | |
555 | .owner = THIS_MODULE, | |
556 | .name = "exynos-sysmmu", | |
557 | } | |
558 | }; | |
559 | ||
560 | static inline void pgtable_flush(void *vastart, void *vaend) | |
561 | { | |
562 | dmac_flush_range(vastart, vaend); | |
563 | outer_flush_range(virt_to_phys(vastart), | |
564 | virt_to_phys(vaend)); | |
565 | } | |
566 | ||
567 | static int exynos_iommu_domain_init(struct iommu_domain *domain) | |
568 | { | |
569 | struct exynos_iommu_domain *priv; | |
570 | ||
571 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
572 | if (!priv) | |
573 | return -ENOMEM; | |
574 | ||
575 | priv->pgtable = (unsigned long *)__get_free_pages( | |
576 | GFP_KERNEL | __GFP_ZERO, 2); | |
577 | if (!priv->pgtable) | |
578 | goto err_pgtable; | |
579 | ||
580 | priv->lv2entcnt = (short *)__get_free_pages( | |
581 | GFP_KERNEL | __GFP_ZERO, 1); | |
582 | if (!priv->lv2entcnt) | |
583 | goto err_counter; | |
584 | ||
585 | pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES); | |
586 | ||
587 | spin_lock_init(&priv->lock); | |
588 | spin_lock_init(&priv->pgtablelock); | |
589 | INIT_LIST_HEAD(&priv->clients); | |
590 | ||
eb51637b SK |
591 | domain->geometry.aperture_start = 0; |
592 | domain->geometry.aperture_end = ~0UL; | |
593 | domain->geometry.force_aperture = true; | |
3177bb76 | 594 | |
2a96536e KC |
595 | domain->priv = priv; |
596 | return 0; | |
597 | ||
598 | err_counter: | |
599 | free_pages((unsigned long)priv->pgtable, 2); | |
600 | err_pgtable: | |
601 | kfree(priv); | |
602 | return -ENOMEM; | |
603 | } | |
604 | ||
605 | static void exynos_iommu_domain_destroy(struct iommu_domain *domain) | |
606 | { | |
607 | struct exynos_iommu_domain *priv = domain->priv; | |
608 | struct sysmmu_drvdata *data; | |
609 | unsigned long flags; | |
610 | int i; | |
611 | ||
612 | WARN_ON(!list_empty(&priv->clients)); | |
613 | ||
614 | spin_lock_irqsave(&priv->lock, flags); | |
615 | ||
616 | list_for_each_entry(data, &priv->clients, node) { | |
617 | while (!exynos_sysmmu_disable(data->dev)) | |
618 | ; /* until System MMU is actually disabled */ | |
619 | } | |
620 | ||
621 | spin_unlock_irqrestore(&priv->lock, flags); | |
622 | ||
623 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
624 | if (lv1ent_page(priv->pgtable + i)) | |
734c3c73 CK |
625 | kmem_cache_free(lv2table_kmem_cache, |
626 | phys_to_virt(lv2table_base(priv->pgtable + i))); | |
2a96536e KC |
627 | |
628 | free_pages((unsigned long)priv->pgtable, 2); | |
629 | free_pages((unsigned long)priv->lv2entcnt, 1); | |
630 | kfree(domain->priv); | |
631 | domain->priv = NULL; | |
632 | } | |
633 | ||
634 | static int exynos_iommu_attach_device(struct iommu_domain *domain, | |
635 | struct device *dev) | |
636 | { | |
637 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
638 | struct exynos_iommu_domain *priv = domain->priv; | |
7222e8db | 639 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
640 | unsigned long flags; |
641 | int ret; | |
642 | ||
643 | ret = pm_runtime_get_sync(data->sysmmu); | |
644 | if (ret < 0) | |
645 | return ret; | |
646 | ||
647 | ret = 0; | |
648 | ||
649 | spin_lock_irqsave(&priv->lock, flags); | |
650 | ||
7222e8db | 651 | ret = __exynos_sysmmu_enable(data, pagetable, domain); |
2a96536e KC |
652 | |
653 | if (ret == 0) { | |
654 | /* 'data->node' must not be appeared in priv->clients */ | |
655 | BUG_ON(!list_empty(&data->node)); | |
656 | data->dev = dev; | |
657 | list_add_tail(&data->node, &priv->clients); | |
658 | } | |
659 | ||
660 | spin_unlock_irqrestore(&priv->lock, flags); | |
661 | ||
662 | if (ret < 0) { | |
7222e8db CK |
663 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
664 | __func__, &pagetable); | |
2a96536e | 665 | pm_runtime_put(data->sysmmu); |
7222e8db | 666 | return ret; |
2a96536e KC |
667 | } |
668 | ||
7222e8db CK |
669 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
670 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
671 | ||
2a96536e KC |
672 | return ret; |
673 | } | |
674 | ||
675 | static void exynos_iommu_detach_device(struct iommu_domain *domain, | |
676 | struct device *dev) | |
677 | { | |
678 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
679 | struct exynos_iommu_domain *priv = domain->priv; | |
680 | struct list_head *pos; | |
7222e8db | 681 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
682 | unsigned long flags; |
683 | bool found = false; | |
684 | ||
685 | spin_lock_irqsave(&priv->lock, flags); | |
686 | ||
687 | list_for_each(pos, &priv->clients) { | |
688 | if (list_entry(pos, struct sysmmu_drvdata, node) == data) { | |
689 | found = true; | |
690 | break; | |
691 | } | |
692 | } | |
693 | ||
694 | if (!found) | |
695 | goto finish; | |
696 | ||
697 | if (__exynos_sysmmu_disable(data)) { | |
7222e8db CK |
698 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
699 | __func__, &pagetable); | |
f8ffcc92 | 700 | list_del_init(&data->node); |
2a96536e KC |
701 | |
702 | } else { | |
7222e8db CK |
703 | dev_dbg(dev, "%s: Detaching IOMMU with pgtable %pa delayed", |
704 | __func__, &pagetable); | |
2a96536e KC |
705 | } |
706 | ||
707 | finish: | |
708 | spin_unlock_irqrestore(&priv->lock, flags); | |
709 | ||
710 | if (found) | |
711 | pm_runtime_put(data->sysmmu); | |
712 | } | |
713 | ||
714 | static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova, | |
715 | short *pgcounter) | |
716 | { | |
61128f08 CK |
717 | if (lv1ent_section(sent)) { |
718 | WARN(1, "Trying mapping on %#08lx mapped with 1MiB page", iova); | |
719 | return ERR_PTR(-EADDRINUSE); | |
720 | } | |
721 | ||
2a96536e KC |
722 | if (lv1ent_fault(sent)) { |
723 | unsigned long *pent; | |
724 | ||
734c3c73 | 725 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
2a96536e KC |
726 | BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1)); |
727 | if (!pent) | |
61128f08 | 728 | return ERR_PTR(-ENOMEM); |
2a96536e | 729 | |
7222e8db | 730 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
2a96536e KC |
731 | *pgcounter = NUM_LV2ENTRIES; |
732 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
733 | pgtable_flush(sent, sent + 1); | |
734 | } | |
735 | ||
736 | return page_entry(sent, iova); | |
737 | } | |
738 | ||
61128f08 CK |
739 | static int lv1set_section(unsigned long *sent, unsigned long iova, |
740 | phys_addr_t paddr, short *pgcnt) | |
2a96536e | 741 | { |
61128f08 CK |
742 | if (lv1ent_section(sent)) { |
743 | WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped", | |
744 | iova); | |
2a96536e | 745 | return -EADDRINUSE; |
61128f08 | 746 | } |
2a96536e KC |
747 | |
748 | if (lv1ent_page(sent)) { | |
61128f08 CK |
749 | if (*pgcnt != NUM_LV2ENTRIES) { |
750 | WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped", | |
751 | iova); | |
2a96536e | 752 | return -EADDRINUSE; |
61128f08 | 753 | } |
2a96536e | 754 | |
734c3c73 | 755 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
756 | *pgcnt = 0; |
757 | } | |
758 | ||
759 | *sent = mk_lv1ent_sect(paddr); | |
760 | ||
761 | pgtable_flush(sent, sent + 1); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size, | |
767 | short *pgcnt) | |
768 | { | |
769 | if (size == SPAGE_SIZE) { | |
61128f08 CK |
770 | if (!lv2ent_fault(pent)) { |
771 | WARN(1, "Trying mapping on 4KiB where mapping exists"); | |
2a96536e | 772 | return -EADDRINUSE; |
61128f08 | 773 | } |
2a96536e KC |
774 | |
775 | *pent = mk_lv2ent_spage(paddr); | |
776 | pgtable_flush(pent, pent + 1); | |
777 | *pgcnt -= 1; | |
778 | } else { /* size == LPAGE_SIZE */ | |
779 | int i; | |
780 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { | |
781 | if (!lv2ent_fault(pent)) { | |
61128f08 CK |
782 | WARN(1, |
783 | "Trying mapping on 64KiB where mapping exists"); | |
784 | if (i > 0) | |
785 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
786 | return -EADDRINUSE; |
787 | } | |
788 | ||
789 | *pent = mk_lv2ent_lpage(paddr); | |
790 | } | |
791 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
792 | *pgcnt -= SPAGES_PER_LPAGE; | |
793 | } | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
799 | phys_addr_t paddr, size_t size, int prot) | |
800 | { | |
801 | struct exynos_iommu_domain *priv = domain->priv; | |
802 | unsigned long *entry; | |
803 | unsigned long flags; | |
804 | int ret = -ENOMEM; | |
805 | ||
806 | BUG_ON(priv->pgtable == NULL); | |
807 | ||
808 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
809 | ||
810 | entry = section_entry(priv->pgtable, iova); | |
811 | ||
812 | if (size == SECT_SIZE) { | |
61128f08 | 813 | ret = lv1set_section(entry, iova, paddr, |
2a96536e KC |
814 | &priv->lv2entcnt[lv1ent_offset(iova)]); |
815 | } else { | |
816 | unsigned long *pent; | |
817 | ||
818 | pent = alloc_lv2entry(entry, iova, | |
819 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
820 | ||
61128f08 CK |
821 | if (IS_ERR(pent)) |
822 | ret = PTR_ERR(pent); | |
2a96536e KC |
823 | else |
824 | ret = lv2set_page(pent, paddr, size, | |
825 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
826 | } | |
827 | ||
61128f08 | 828 | if (ret) |
2a96536e KC |
829 | pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n", |
830 | __func__, iova, size); | |
2a96536e KC |
831 | |
832 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
833 | ||
834 | return ret; | |
835 | } | |
836 | ||
837 | static size_t exynos_iommu_unmap(struct iommu_domain *domain, | |
838 | unsigned long iova, size_t size) | |
839 | { | |
840 | struct exynos_iommu_domain *priv = domain->priv; | |
841 | struct sysmmu_drvdata *data; | |
842 | unsigned long flags; | |
843 | unsigned long *ent; | |
61128f08 | 844 | size_t err_pgsize; |
2a96536e KC |
845 | |
846 | BUG_ON(priv->pgtable == NULL); | |
847 | ||
848 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
849 | ||
850 | ent = section_entry(priv->pgtable, iova); | |
851 | ||
852 | if (lv1ent_section(ent)) { | |
61128f08 CK |
853 | if (size < SECT_SIZE) { |
854 | err_pgsize = SECT_SIZE; | |
855 | goto err; | |
856 | } | |
2a96536e KC |
857 | |
858 | *ent = 0; | |
859 | pgtable_flush(ent, ent + 1); | |
860 | size = SECT_SIZE; | |
861 | goto done; | |
862 | } | |
863 | ||
864 | if (unlikely(lv1ent_fault(ent))) { | |
865 | if (size > SECT_SIZE) | |
866 | size = SECT_SIZE; | |
867 | goto done; | |
868 | } | |
869 | ||
870 | /* lv1ent_page(sent) == true here */ | |
871 | ||
872 | ent = page_entry(ent, iova); | |
873 | ||
874 | if (unlikely(lv2ent_fault(ent))) { | |
875 | size = SPAGE_SIZE; | |
876 | goto done; | |
877 | } | |
878 | ||
879 | if (lv2ent_small(ent)) { | |
880 | *ent = 0; | |
881 | size = SPAGE_SIZE; | |
6cb47ed7 | 882 | pgtable_flush(ent, ent + 1); |
2a96536e KC |
883 | priv->lv2entcnt[lv1ent_offset(iova)] += 1; |
884 | goto done; | |
885 | } | |
886 | ||
887 | /* lv1ent_large(ent) == true here */ | |
61128f08 CK |
888 | if (size < LPAGE_SIZE) { |
889 | err_pgsize = LPAGE_SIZE; | |
890 | goto err; | |
891 | } | |
2a96536e KC |
892 | |
893 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 894 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
895 | |
896 | size = LPAGE_SIZE; | |
897 | priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; | |
898 | done: | |
899 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
900 | ||
901 | spin_lock_irqsave(&priv->lock, flags); | |
902 | list_for_each_entry(data, &priv->clients, node) | |
3ad6b7f3 | 903 | sysmmu_tlb_invalidate_entry(data->dev, iova, size); |
2a96536e KC |
904 | spin_unlock_irqrestore(&priv->lock, flags); |
905 | ||
2a96536e | 906 | return size; |
61128f08 CK |
907 | err: |
908 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
909 | ||
910 | WARN(1, | |
911 | "%s: Failed due to size(%#x) @ %#08lx is smaller than page size %#x\n", | |
912 | __func__, size, iova, err_pgsize); | |
913 | ||
914 | return 0; | |
2a96536e KC |
915 | } |
916 | ||
917 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 918 | dma_addr_t iova) |
2a96536e KC |
919 | { |
920 | struct exynos_iommu_domain *priv = domain->priv; | |
921 | unsigned long *entry; | |
922 | unsigned long flags; | |
923 | phys_addr_t phys = 0; | |
924 | ||
925 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
926 | ||
927 | entry = section_entry(priv->pgtable, iova); | |
928 | ||
929 | if (lv1ent_section(entry)) { | |
930 | phys = section_phys(entry) + section_offs(iova); | |
931 | } else if (lv1ent_page(entry)) { | |
932 | entry = page_entry(entry, iova); | |
933 | ||
934 | if (lv2ent_large(entry)) | |
935 | phys = lpage_phys(entry) + lpage_offs(iova); | |
936 | else if (lv2ent_small(entry)) | |
937 | phys = spage_phys(entry) + spage_offs(iova); | |
938 | } | |
939 | ||
940 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
941 | ||
942 | return phys; | |
943 | } | |
944 | ||
945 | static struct iommu_ops exynos_iommu_ops = { | |
946 | .domain_init = &exynos_iommu_domain_init, | |
947 | .domain_destroy = &exynos_iommu_domain_destroy, | |
948 | .attach_dev = &exynos_iommu_attach_device, | |
949 | .detach_dev = &exynos_iommu_detach_device, | |
950 | .map = &exynos_iommu_map, | |
951 | .unmap = &exynos_iommu_unmap, | |
952 | .iova_to_phys = &exynos_iommu_iova_to_phys, | |
953 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, | |
954 | }; | |
955 | ||
956 | static int __init exynos_iommu_init(void) | |
957 | { | |
958 | int ret; | |
959 | ||
734c3c73 CK |
960 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
961 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
962 | if (!lv2table_kmem_cache) { | |
963 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
964 | return -ENOMEM; | |
965 | } | |
966 | ||
2a96536e | 967 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
968 | if (ret) { |
969 | pr_err("%s: Failed to register driver\n", __func__); | |
970 | goto err_reg_driver; | |
971 | } | |
2a96536e | 972 | |
734c3c73 CK |
973 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
974 | if (ret) { | |
975 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
976 | __func__); | |
977 | goto err_set_iommu; | |
978 | } | |
2a96536e | 979 | |
734c3c73 CK |
980 | return 0; |
981 | err_set_iommu: | |
982 | platform_driver_unregister(&exynos_sysmmu_driver); | |
983 | err_reg_driver: | |
984 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
985 | return ret; |
986 | } | |
987 | subsys_initcall(exynos_iommu_init); |