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iommu/vt-d: Allocate space for ACPI devices
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 18 */
19
20#include <linux/init.h>
21#include <linux/bitmap.h>
5e0d2a6f 22#include <linux/debugfs.h>
54485c30 23#include <linux/export.h>
ba395927
KA		 24#include <linux/slab.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
ba395927
KA		 27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/dmar.h>
30#include <linux/dma-mapping.h>
31#include <linux/mempool.h>
75f05569 32#include <linux/memory.h>
5e0d2a6f 33#include <linux/timer.h>
38717946 34#include <linux/iova.h>
5d450806 35#include <linux/iommu.h>
38717946 36#include <linux/intel-iommu.h>
134fac3f 37#include <linux/syscore_ops.h>
69575d38 38#include <linux/tboot.h>
adb2fe02 39#include <linux/dmi.h>
5cdede24 40#include <linux/pci-ats.h>
0ee332c1 41#include <linux/memblock.h>
8a8f422d 42#include <asm/irq_remapping.h>
ba395927 43#include <asm/cacheflush.h>
46a7fa27 44#include <asm/iommu.h>
ba395927 45
078e1ee2 46#include "irq_remapping.h"
61e015ac 47#include "pci.h"
078e1ee2 48
5b6985ce
FY		 49#define ROOT_SIZE VTD_PAGE_SIZE
50#define CONTEXT_SIZE VTD_PAGE_SIZE
51
ba395927
KA		 52#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
53#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 54#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 55
56#define IOAPIC_RANGE_START (0xfee00000)
57#define IOAPIC_RANGE_END (0xfeefffff)
58#define IOVA_START_ADDR (0x1000)
59
60#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
61
4ed0d3e6 62#define MAX_AGAW_WIDTH 64
5c645b35 63#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 64
2ebe3151
DW		 65#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
67
68/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 73
f27be03b 74#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 75#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 76#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 77
df08cdc7
AM		 78/* page table handling */
79#define LEVEL_STRIDE (9)
80#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
81
6d1c56a9
OBC		 82/*
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
86 * that we support.
87 *
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
91 *
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
94 *
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
97 */
98#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
99
df08cdc7
AM		 100static inline int agaw_to_level(int agaw)
101{
102 return agaw + 2;
103}
104
105static inline int agaw_to_width(int agaw)
106{
5c645b35 107 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 108}
109
110static inline int width_to_agaw(int width)
111{
5c645b35 112 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 113}
114
115static inline unsigned int level_to_offset_bits(int level)
116{
117 return (level - 1) * LEVEL_STRIDE;
118}
119
120static inline int pfn_level_offset(unsigned long pfn, int level)
121{
122 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
123}
124
125static inline unsigned long level_mask(int level)
126{
127 return -1UL << level_to_offset_bits(level);
128}
129
130static inline unsigned long level_size(int level)
131{
132 return 1UL << level_to_offset_bits(level);
133}
134
135static inline unsigned long align_to_level(unsigned long pfn, int level)
136{
137 return (pfn + level_size(level) - 1) & level_mask(level);
138}
fd18de50 139
6dd9a7c7
YS		 140static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
141{
5c645b35 142 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 143}
144
dd4e8319
DW		 145/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
148{
149 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
150}
151
152static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
153{
154 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
155}
156static inline unsigned long page_to_dma_pfn(struct page *pg)
157{
158 return mm_to_dma_pfn(page_to_pfn(pg));
159}
160static inline unsigned long virt_to_dma_pfn(void *p)
161{
162 return page_to_dma_pfn(virt_to_page(p));
163}
164
d9630fe9
WH		 165/* global iommu list, set NULL for ignored DMAR units */
166static struct intel_iommu **g_iommus;
167
e0fc7e0b 168static void __init check_tylersburg_isoch(void);
9af88143
DW		 169static int rwbf_quirk;
170
b779260b
JC		 171/*
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
174 */
175static int force_on = 0;
176
46b08e1a
MM		 177/*
178 * 0: Present
179 * 1-11: Reserved
180 * 12-63: Context Ptr (12 - (haw-1))
181 * 64-127: Reserved
182 */
183struct root_entry {
184 u64 val;
185 u64 rsvd1;
186};
187#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188static inline bool root_present(struct root_entry *root)
189{
190 return (root->val & 1);
191}
192static inline void set_root_present(struct root_entry *root)
193{
194 root->val |= 1;
195}
196static inline void set_root_value(struct root_entry *root, unsigned long value)
197{
198 root->val |= value & VTD_PAGE_MASK;
199}
200
201static inline struct context_entry *
202get_context_addr_from_root(struct root_entry *root)
203{
204 return (struct context_entry *)
205 (root_present(root)?phys_to_virt(
206 root->val & VTD_PAGE_MASK) :
207 NULL);
208}
209
7a8fc25e
MM		 210/*
211 * low 64 bits:
212 * 0: present
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
216 * high 64 bits:
217 * 0-2: address width
218 * 3-6: aval
219 * 8-23: domain id
220 */
221struct context_entry {
222 u64 lo;
223 u64 hi;
224};
c07e7d21
MM		 225
226static inline bool context_present(struct context_entry *context)
227{
228 return (context->lo & 1);
229}
230static inline void context_set_present(struct context_entry *context)
231{
232 context->lo |= 1;
233}
234
235static inline void context_set_fault_enable(struct context_entry *context)
236{
237 context->lo &= (((u64)-1) << 2) | 1;
238}
239
c07e7d21
MM		 240static inline void context_set_translation_type(struct context_entry *context,
241 unsigned long value)
242{
243 context->lo &= (((u64)-1) << 4) | 3;
244 context->lo |= (value & 3) << 2;
245}
246
247static inline void context_set_address_root(struct context_entry *context,
248 unsigned long value)
249{
250 context->lo |= value & VTD_PAGE_MASK;
251}
252
253static inline void context_set_address_width(struct context_entry *context,
254 unsigned long value)
255{
256 context->hi |= value & 7;
257}
258
259static inline void context_set_domain_id(struct context_entry *context,
260 unsigned long value)
261{
262 context->hi |= (value & ((1 << 16) - 1)) << 8;
263}
264
265static inline void context_clear_entry(struct context_entry *context)
266{
267 context->lo = 0;
268 context->hi = 0;
269}
7a8fc25e 270
622ba12a
MM		 271/*
272 * 0: readable
273 * 1: writable
274 * 2-6: reserved
275 * 7: super page
9cf06697
SY		 276 * 8-10: available
277 * 11: snoop behavior
622ba12a
MM		 278 * 12-63: Host physcial address
279 */
280struct dma_pte {
281 u64 val;
282};
622ba12a 283
19c239ce
MM		 284static inline void dma_clear_pte(struct dma_pte *pte)
285{
286 pte->val = 0;
287}
288
19c239ce
MM		 289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
19c239ce
MM		 299static inline bool dma_pte_present(struct dma_pte *pte)
300{
301 return (pte->val & 3) != 0;
302}
622ba12a 303
4399c8bf
AK		 304static inline bool dma_pte_superpage(struct dma_pte *pte)
305{
306 return (pte->val & (1 << 7));
307}
308
75e6bf96
DW		 309static inline int first_pte_in_page(struct dma_pte *pte)
310{
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312}
313
2c2e2c38
FY		 314/*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
19943b0e
DW		 320static struct dmar_domain *si_domain;
321static int hw_pass_through = 1;
2c2e2c38 322
3b5410e7 323/* devices under the same p2p bridge are owned in one domain */
cdc7b837 324#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 325
1ce28feb
WH		 326/* domain represents a virtual machine, more than one devices
327 * across iommus may be owned in one domain, e.g. kvm guest.
328 */
329#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
330
2c2e2c38
FY		 331/* si_domain contains mulitple devices */
332#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
333
1b198bb0
MT		 334/* define the limit of IOMMUs supported in each domain */
335#ifdef CONFIG_X86
336# define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
337#else
338# define IOMMU_UNITS_SUPPORTED 64
339#endif
340
99126f7c
MM		 341struct dmar_domain {
342 int id; /* domain id */
4c923d47 343 int nid; /* node id */
1b198bb0
MT		 344 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
345 /* bitmap of iommus this domain uses*/
99126f7c
MM		 346
347 struct list_head devices; /* all devices' list */
348 struct iova_domain iovad; /* iova's that belong to this domain */
349
350 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 351 int gaw; /* max guest address width */
352
353 /* adjusted guest address width, 0 is level 2 30-bit */
354 int agaw;
355
3b5410e7 356 int flags; /* flags to find out type of domain */
8e604097
WH		 357
358 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 359 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 360 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 361 int iommu_superpage;/* Level of superpages supported:
362 0 == 4KiB (no superpages), 1 == 2MiB,
363 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 364 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 365 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 366};
367
a647dacb
MM		 368/* PCI domain-device relationship */
369struct device_domain_info {
370 struct list_head link; /* link to domain siblings */
371 struct list_head global; /* link to global list */
276dbf99
DW		 372 int segment; /* PCI domain */
373 u8 bus; /* PCI bus number */
a647dacb 374 u8 devfn; /* PCI devfn number */
45e829ea 375 struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 376 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 377 struct dmar_domain *domain; /* pointer to domain */
378};
379
b94e4117
JL		 380struct dmar_rmrr_unit {
381 struct list_head list; /* list of rmrr units */
382 struct acpi_dmar_header *hdr; /* ACPI header */
383 u64 base_address; /* reserved base address*/
384 u64 end_address; /* reserved end address */
0e242612 385 struct pci_dev __rcu **devices; /* target devices */
b94e4117
JL		 386 int devices_cnt; /* target device count */
387};
388
389struct dmar_atsr_unit {
390 struct list_head list; /* list of ATSR units */
391 struct acpi_dmar_header *hdr; /* ACPI header */
0e242612 392 struct pci_dev __rcu **devices; /* target devices */
b94e4117
JL		 393 int devices_cnt; /* target device count */
394 u8 include_all:1; /* include all ports */
395};
396
397static LIST_HEAD(dmar_atsr_units);
398static LIST_HEAD(dmar_rmrr_units);
399
400#define for_each_rmrr_units(rmrr) \
401 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
402
5e0d2a6f 403static void flush_unmaps_timeout(unsigned long data);
404
b707cb02 405static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 406
80b20dd8 407#define HIGH_WATER_MARK 250
408struct deferred_flush_tables {
409 int next;
410 struct iova *iova[HIGH_WATER_MARK];
411 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 412 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 413};
414
415static struct deferred_flush_tables *deferred_flush;
416
5e0d2a6f 417/* bitmap for indexing intel_iommus */
5e0d2a6f 418static int g_num_of_iommus;
419
420static DEFINE_SPINLOCK(async_umap_flush_lock);
421static LIST_HEAD(unmaps_to_do);
422
423static int timer_on;
424static long list_size;
5e0d2a6f 425
92d03cc8 426static void domain_exit(struct dmar_domain *domain);
ba395927 427static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117
JL		 428static void domain_remove_one_dev_info(struct dmar_domain *domain,
429 struct pci_dev *pdev);
92d03cc8
JL		 430static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
431 struct pci_dev *pdev);
ba395927 432
d3f13810 433#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 434int dmar_disabled = 0;
435#else
436int dmar_disabled = 1;
d3f13810 437#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 438
8bc1f85c
ED		 439int intel_iommu_enabled = 0;
440EXPORT_SYMBOL_GPL(intel_iommu_enabled);
441
2d9e667e 442static int dmar_map_gfx = 1;
7d3b03ce 443static int dmar_forcedac;
5e0d2a6f 444static int intel_iommu_strict;
6dd9a7c7 445static int intel_iommu_superpage = 1;
ba395927 446
c0771df8
DW		 447int intel_iommu_gfx_mapped;
448EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
449
ba395927
KA		 450#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
451static DEFINE_SPINLOCK(device_domain_lock);
452static LIST_HEAD(device_domain_list);
453
a8bcbb0d
JR		 454static struct iommu_ops intel_iommu_ops;
455
ba395927
KA		 456static int __init intel_iommu_setup(char *str)
457{
458 if (!str)
459 return -EINVAL;
460 while (*str) {
0cd5c3c8
KM		 461 if (!strncmp(str, "on", 2)) {
462 dmar_disabled = 0;
463 printk(KERN_INFO "Intel-IOMMU: enabled\n");
464 } else if (!strncmp(str, "off", 3)) {
ba395927 465 dmar_disabled = 1;
0cd5c3c8 466 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 467 } else if (!strncmp(str, "igfx_off", 8)) {
468 dmar_map_gfx = 0;
469 printk(KERN_INFO
470 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 471 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 472 printk(KERN_INFO
7d3b03ce
KA		 473 "Intel-IOMMU: Forcing DAC for PCI devices\n");
474 dmar_forcedac = 1;
5e0d2a6f 475 } else if (!strncmp(str, "strict", 6)) {
476 printk(KERN_INFO
477 "Intel-IOMMU: disable batched IOTLB flush\n");
478 intel_iommu_strict = 1;
6dd9a7c7
YS		 479 } else if (!strncmp(str, "sp_off", 6)) {
480 printk(KERN_INFO
481 "Intel-IOMMU: disable supported super page\n");
482 intel_iommu_superpage = 0;
ba395927
KA		 483 }
484
485 str += strcspn(str, ",");
486 while (*str == ',')
487 str++;
488 }
489 return 0;
490}
491__setup("intel_iommu=", intel_iommu_setup);
492
493static struct kmem_cache *iommu_domain_cache;
494static struct kmem_cache *iommu_devinfo_cache;
495static struct kmem_cache *iommu_iova_cache;
496
4c923d47 497static inline void *alloc_pgtable_page(int node)
eb3fa7cb 498{
4c923d47
SS		 499 struct page *page;
500 void *vaddr = NULL;
eb3fa7cb 501
4c923d47
SS		 502 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
503 if (page)
504 vaddr = page_address(page);
eb3fa7cb 505 return vaddr;
ba395927
KA		 506}
507
508static inline void free_pgtable_page(void *vaddr)
509{
510 free_page((unsigned long)vaddr);
511}
512
513static inline void *alloc_domain_mem(void)
514{
354bb65e 515 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 516}
517
38717946 518static void free_domain_mem(void *vaddr)
ba395927
KA		 519{
520 kmem_cache_free(iommu_domain_cache, vaddr);
521}
522
523static inline void * alloc_devinfo_mem(void)
524{
354bb65e 525 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 526}
527
528static inline void free_devinfo_mem(void *vaddr)
529{
530 kmem_cache_free(iommu_devinfo_cache, vaddr);
531}
532
533struct iova *alloc_iova_mem(void)
534{
354bb65e 535 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 536}
537
538void free_iova_mem(struct iova *iova)
539{
540 kmem_cache_free(iommu_iova_cache, iova);
541}
542
1b573683 543
4ed0d3e6 544static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 545{
546 unsigned long sagaw;
547 int agaw = -1;
548
549 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 550 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 551 agaw >= 0; agaw--) {
552 if (test_bit(agaw, &sagaw))
553 break;
554 }
555
556 return agaw;
557}
558
4ed0d3e6
FY		 559/*
560 * Calculate max SAGAW for each iommu.
561 */
562int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
563{
564 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
565}
566
567/*
568 * calculate agaw for each iommu.
569 * "SAGAW" may be different across iommus, use a default agaw, and
570 * get a supported less agaw for iommus that don't support the default agaw.
571 */
572int iommu_calculate_agaw(struct intel_iommu *iommu)
573{
574 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
575}
576
2c2e2c38 577/* This functionin only returns single iommu in a domain */
8c11e798
WH		 578static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
579{
580 int iommu_id;
581
2c2e2c38 582 /* si_domain and vm domain should not get here. */
1ce28feb 583 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 584 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 585
1b198bb0 586 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 587 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
588 return NULL;
589
590 return g_iommus[iommu_id];
591}
592
8e604097
WH		 593static void domain_update_iommu_coherency(struct dmar_domain *domain)
594{
d0501960
DW		 595 struct dmar_drhd_unit *drhd;
596 struct intel_iommu *iommu;
597 int i, found = 0;
2e12bc29 598
d0501960 599 domain->iommu_coherency = 1;
8e604097 600
1b198bb0 601 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
d0501960 602 found = 1;
8e604097
WH		 603 if (!ecap_coherent(g_iommus[i]->ecap)) {
604 domain->iommu_coherency = 0;
605 break;
606 }
8e604097 607 }
d0501960
DW		 608 if (found)
609 return;
610
611 /* No hardware attached; use lowest common denominator */
612 rcu_read_lock();
613 for_each_active_iommu(iommu, drhd) {
614 if (!ecap_coherent(iommu->ecap)) {
615 domain->iommu_coherency = 0;
616 break;
617 }
618 }
619 rcu_read_unlock();
8e604097
WH		 620}
621
58c610bd
SY		 622static void domain_update_iommu_snooping(struct dmar_domain *domain)
623{
624 int i;
625
626 domain->iommu_snooping = 1;
627
1b198bb0 628 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 629 if (!ecap_sc_support(g_iommus[i]->ecap)) {
630 domain->iommu_snooping = 0;
631 break;
632 }
58c610bd
SY		 633 }
634}
635
6dd9a7c7
YS		 636static void domain_update_iommu_superpage(struct dmar_domain *domain)
637{
8140a95d
AK		 638 struct dmar_drhd_unit *drhd;
639 struct intel_iommu *iommu = NULL;
640 int mask = 0xf;
6dd9a7c7
YS		 641
642 if (!intel_iommu_superpage) {
643 domain->iommu_superpage = 0;
644 return;
645 }
646
8140a95d 647 /* set iommu_superpage to the smallest common denominator */
0e242612 648 rcu_read_lock();
8140a95d
AK		 649 for_each_active_iommu(iommu, drhd) {
650 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 651 if (!mask) {
652 break;
653 }
654 }
0e242612
JL		 655 rcu_read_unlock();
656
6dd9a7c7
YS		 657 domain->iommu_superpage = fls(mask);
658}
659
58c610bd
SY		 660/* Some capabilities may be different across iommus */
661static void domain_update_iommu_cap(struct dmar_domain *domain)
662{
663 domain_update_iommu_coherency(domain);
664 domain_update_iommu_snooping(domain);
6dd9a7c7 665 domain_update_iommu_superpage(domain);
58c610bd
SY		 666}
667
276dbf99 668static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 669{
670 struct dmar_drhd_unit *drhd = NULL;
b683b230
JL		 671 struct intel_iommu *iommu;
672 struct pci_dev *dev;
c7151a8d
WH		 673 int i;
674
0e242612 675 rcu_read_lock();
b683b230 676 for_each_active_iommu(iommu, drhd) {
276dbf99
DW		 677 if (segment != drhd->segment)
678 continue;
c7151a8d 679
b683b230
JL		 680 for_each_active_dev_scope(drhd->devices,
681 drhd->devices_cnt, i, dev) {
682 if (dev->bus->number == bus && dev->devfn == devfn)
683 goto out;
684 if (dev->subordinate &&
685 dev->subordinate->number <= bus &&
686 dev->subordinate->busn_res.end >= bus)
687 goto out;
924b6231 688 }
c7151a8d
WH		 689
690 if (drhd->include_all)
b683b230 691 goto out;
c7151a8d 692 }
b683b230
JL		 693 iommu = NULL;
694out:
0e242612 695 rcu_read_unlock();
c7151a8d 696
b683b230 697 return iommu;
c7151a8d
WH		 698}
699
5331fe6f
WH		 700static void domain_flush_cache(struct dmar_domain *domain,
701 void *addr, int size)
702{
703 if (!domain->iommu_coherency)
704 clflush_cache_range(addr, size);
705}
706
ba395927
KA		 707/* Gets context entry for a given bus and devfn */
708static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
709 u8 bus, u8 devfn)
710{
711 struct root_entry *root;
712 struct context_entry *context;
713 unsigned long phy_addr;
714 unsigned long flags;
715
716 spin_lock_irqsave(&iommu->lock, flags);
717 root = &iommu->root_entry[bus];
718 context = get_context_addr_from_root(root);
719 if (!context) {
4c923d47
SS		 720 context = (struct context_entry *)
721 alloc_pgtable_page(iommu->node);
ba395927
KA		 722 if (!context) {
723 spin_unlock_irqrestore(&iommu->lock, flags);
724 return NULL;
725 }
5b6985ce 726 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 727 phy_addr = virt_to_phys((void *)context);
728 set_root_value(root, phy_addr);
729 set_root_present(root);
730 __iommu_flush_cache(iommu, root, sizeof(*root));
731 }
732 spin_unlock_irqrestore(&iommu->lock, flags);
733 return &context[devfn];
734}
735
736static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
737{
738 struct root_entry *root;
739 struct context_entry *context;
740 int ret;
741 unsigned long flags;
742
743 spin_lock_irqsave(&iommu->lock, flags);
744 root = &iommu->root_entry[bus];
745 context = get_context_addr_from_root(root);
746 if (!context) {
747 ret = 0;
748 goto out;
749 }
c07e7d21 750 ret = context_present(&context[devfn]);
ba395927
KA		 751out:
752 spin_unlock_irqrestore(&iommu->lock, flags);
753 return ret;
754}
755
756static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
757{
758 struct root_entry *root;
759 struct context_entry *context;
760 unsigned long flags;
761
762 spin_lock_irqsave(&iommu->lock, flags);
763 root = &iommu->root_entry[bus];
764 context = get_context_addr_from_root(root);
765 if (context) {
c07e7d21 766 context_clear_entry(&context[devfn]);
ba395927
KA		 767 __iommu_flush_cache(iommu, &context[devfn], \
768 sizeof(*context));
769 }
770 spin_unlock_irqrestore(&iommu->lock, flags);
771}
772
773static void free_context_table(struct intel_iommu *iommu)
774{
775 struct root_entry *root;
776 int i;
777 unsigned long flags;
778 struct context_entry *context;
779
780 spin_lock_irqsave(&iommu->lock, flags);
781 if (!iommu->root_entry) {
782 goto out;
783 }
784 for (i = 0; i < ROOT_ENTRY_NR; i++) {
785 root = &iommu->root_entry[i];
786 context = get_context_addr_from_root(root);
787 if (context)
788 free_pgtable_page(context);
789 }
790 free_pgtable_page(iommu->root_entry);
791 iommu->root_entry = NULL;
792out:
793 spin_unlock_irqrestore(&iommu->lock, flags);
794}
795
b026fd28 796static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 797 unsigned long pfn, int *target_level)
ba395927 798{
b026fd28 799 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 800 struct dma_pte *parent, *pte = NULL;
801 int level = agaw_to_level(domain->agaw);
4399c8bf 802 int offset;
ba395927
KA		 803
804 BUG_ON(!domain->pgd);
f9423606
JS		 805
806 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
807 /* Address beyond IOMMU's addressing capabilities. */
808 return NULL;
809
ba395927
KA		 810 parent = domain->pgd;
811
5cf0a76f 812 while (1) {
ba395927
KA		 813 void *tmp_page;
814
b026fd28 815 offset = pfn_level_offset(pfn, level);
ba395927 816 pte = &parent[offset];
5cf0a76f 817 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 818 break;
5cf0a76f 819 if (level == *target_level)
ba395927
KA		 820 break;
821
19c239ce 822 if (!dma_pte_present(pte)) {
c85994e4
DW		 823 uint64_t pteval;
824
4c923d47 825 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 826
206a73c1 827 if (!tmp_page)
ba395927 828 return NULL;
206a73c1 829
c85994e4 830 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 831 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 832 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
833 /* Someone else set it while we were thinking; use theirs. */
834 free_pgtable_page(tmp_page);
835 } else {
836 dma_pte_addr(pte);
837 domain_flush_cache(domain, pte, sizeof(*pte));
838 }
ba395927 839 }
5cf0a76f
DW		 840 if (level == 1)
841 break;
842
19c239ce 843 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 844 level--;
845 }
846
5cf0a76f
DW		 847 if (!*target_level)
848 *target_level = level;
849
ba395927
KA		 850 return pte;
851}
852
6dd9a7c7 853
ba395927 854/* return address's pte at specific level */
90dcfb5e
DW		 855static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
856 unsigned long pfn,
6dd9a7c7 857 int level, int *large_page)
ba395927
KA		 858{
859 struct dma_pte *parent, *pte = NULL;
860 int total = agaw_to_level(domain->agaw);
861 int offset;
862
863 parent = domain->pgd;
864 while (level <= total) {
90dcfb5e 865 offset = pfn_level_offset(pfn, total);
ba395927
KA		 866 pte = &parent[offset];
867 if (level == total)
868 return pte;
869
6dd9a7c7
YS		 870 if (!dma_pte_present(pte)) {
871 *large_page = total;
ba395927 872 break;
6dd9a7c7
YS		 873 }
874
875 if (pte->val & DMA_PTE_LARGE_PAGE) {
876 *large_page = total;
877 return pte;
878 }
879
19c239ce 880 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 881 total--;
882 }
883 return NULL;
884}
885
ba395927 886/* clear last level pte, a tlb flush should be followed */
5cf0a76f 887static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 888 unsigned long start_pfn,
889 unsigned long last_pfn)
ba395927 890{
04b18e65 891 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 892 unsigned int large_page = 1;
310a5ab9 893 struct dma_pte *first_pte, *pte;
66eae846 894
04b18e65 895 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 896 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 897 BUG_ON(start_pfn > last_pfn);
ba395927 898
04b18e65 899 /* we don't need lock here; nobody else touches the iova range */
59c36286 900 do {
6dd9a7c7
YS		 901 large_page = 1;
902 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 903 if (!pte) {
6dd9a7c7 904 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 905 continue;
906 }
6dd9a7c7 907 do {
310a5ab9 908 dma_clear_pte(pte);
6dd9a7c7 909 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 910 pte++;
75e6bf96
DW		 911 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
912
310a5ab9
DW		 913 domain_flush_cache(domain, first_pte,
914 (void *)pte - (void *)first_pte);
59c36286
DW		 915
916 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 917}
918
3269ee0b
AW		 919static void dma_pte_free_level(struct dmar_domain *domain, int level,
920 struct dma_pte *pte, unsigned long pfn,
921 unsigned long start_pfn, unsigned long last_pfn)
922{
923 pfn = max(start_pfn, pfn);
924 pte = &pte[pfn_level_offset(pfn, level)];
925
926 do {
927 unsigned long level_pfn;
928 struct dma_pte *level_pte;
929
930 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
931 goto next;
932
933 level_pfn = pfn & level_mask(level - 1);
934 level_pte = phys_to_virt(dma_pte_addr(pte));
935
936 if (level > 2)
937 dma_pte_free_level(domain, level - 1, level_pte,
938 level_pfn, start_pfn, last_pfn);
939
940 /* If range covers entire pagetable, free it */
941 if (!(start_pfn > level_pfn ||
08336fd2 942 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 943 dma_clear_pte(pte);
944 domain_flush_cache(domain, pte, sizeof(*pte));
945 free_pgtable_page(level_pte);
946 }
947next:
948 pfn += level_size(level);
949 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
950}
951
ba395927
KA		 952/* free page table pages. last level pte should already be cleared */
953static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 954 unsigned long start_pfn,
955 unsigned long last_pfn)
ba395927 956{
6660c63a 957 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927 958
6660c63a
DW		 959 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
960 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 961 BUG_ON(start_pfn > last_pfn);
ba395927 962
f3a0a52f 963 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 964 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
965 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 966
ba395927 967 /* free pgd */
d794dc9b 968 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 969 free_pgtable_page(domain->pgd);
970 domain->pgd = NULL;
971 }
972}
973
ea8ea460
DW		 974/* When a page at a given level is being unlinked from its parent, we don't
975 need to *modify* it at all. All we need to do is make a list of all the
976 pages which can be freed just as soon as we've flushed the IOTLB and we
977 know the hardware page-walk will no longer touch them.
978 The 'pte' argument is the *parent* PTE, pointing to the page that is to
979 be freed. */
980static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
981 int level, struct dma_pte *pte,
982 struct page *freelist)
983{
984 struct page *pg;
985
986 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
987 pg->freelist = freelist;
988 freelist = pg;
989
990 if (level == 1)
991 return freelist;
992
993 for (pte = page_address(pg); !first_pte_in_page(pte); pte++) {
994 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
995 freelist = dma_pte_list_pagetables(domain, level - 1,
996 pte, freelist);
997 }
998
999 return freelist;
1000}
1001
1002static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1003 struct dma_pte *pte, unsigned long pfn,
1004 unsigned long start_pfn,
1005 unsigned long last_pfn,
1006 struct page *freelist)
1007{
1008 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1009
1010 pfn = max(start_pfn, pfn);
1011 pte = &pte[pfn_level_offset(pfn, level)];
1012
1013 do {
1014 unsigned long level_pfn;
1015
1016 if (!dma_pte_present(pte))
1017 goto next;
1018
1019 level_pfn = pfn & level_mask(level);
1020
1021 /* If range covers entire pagetable, free it */
1022 if (start_pfn <= level_pfn &&
1023 last_pfn >= level_pfn + level_size(level) - 1) {
1024 /* These suborbinate page tables are going away entirely. Don't
1025 bother to clear them; we're just going to *free* them. */
1026 if (level > 1 && !dma_pte_superpage(pte))
1027 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1028
1029 dma_clear_pte(pte);
1030 if (!first_pte)
1031 first_pte = pte;
1032 last_pte = pte;
1033 } else if (level > 1) {
1034 /* Recurse down into a level that isn't *entirely* obsolete */
1035 freelist = dma_pte_clear_level(domain, level - 1,
1036 phys_to_virt(dma_pte_addr(pte)),
1037 level_pfn, start_pfn, last_pfn,
1038 freelist);
1039 }
1040next:
1041 pfn += level_size(level);
1042 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1043
1044 if (first_pte)
1045 domain_flush_cache(domain, first_pte,
1046 (void *)++last_pte - (void *)first_pte);
1047
1048 return freelist;
1049}
1050
1051/* We can't just free the pages because the IOMMU may still be walking
1052 the page tables, and may have cached the intermediate levels. The
1053 pages can only be freed after the IOTLB flush has been done. */
1054struct page *domain_unmap(struct dmar_domain *domain,
1055 unsigned long start_pfn,
1056 unsigned long last_pfn)
1057{
1058 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1059 struct page *freelist = NULL;
1060
1061 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
1062 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1063 BUG_ON(start_pfn > last_pfn);
1064
1065 /* we don't need lock here; nobody else touches the iova range */
1066 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1067 domain->pgd, 0, start_pfn, last_pfn, NULL);
1068
1069 /* free pgd */
1070 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1071 struct page *pgd_page = virt_to_page(domain->pgd);
1072 pgd_page->freelist = freelist;
1073 freelist = pgd_page;
1074
1075 domain->pgd = NULL;
1076 }
1077
1078 return freelist;
1079}
1080
1081void dma_free_pagelist(struct page *freelist)
1082{
1083 struct page *pg;
1084
1085 while ((pg = freelist)) {
1086 freelist = pg->freelist;
1087 free_pgtable_page(page_address(pg));
1088 }
1089}
1090
ba395927
KA		 1091/* iommu handling */
1092static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1093{
1094 struct root_entry *root;
1095 unsigned long flags;
1096
4c923d47 1097 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 1098 if (!root)
1099 return -ENOMEM;
1100
5b6985ce 1101 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1102
1103 spin_lock_irqsave(&iommu->lock, flags);
1104 iommu->root_entry = root;
1105 spin_unlock_irqrestore(&iommu->lock, flags);
1106
1107 return 0;
1108}
1109
ba395927
KA		 1110static void iommu_set_root_entry(struct intel_iommu *iommu)
1111{
1112 void *addr;
c416daa9 1113 u32 sts;
ba395927
KA		 1114 unsigned long flag;
1115
1116 addr = iommu->root_entry;
1117
1f5b3c3f 1118 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1119 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
1120
c416daa9 1121 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1122
1123 /* Make sure hardware complete it */
1124 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1125 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1126
1f5b3c3f 1127 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1128}
1129
1130static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1131{
1132 u32 val;
1133 unsigned long flag;
1134
9af88143 1135 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1136 return;
ba395927 1137
1f5b3c3f 1138 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1139 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1140
1141 /* Make sure hardware complete it */
1142 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1143 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1144
1f5b3c3f 1145 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1146}
1147
1148/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1149static void __iommu_flush_context(struct intel_iommu *iommu,
1150 u16 did, u16 source_id, u8 function_mask,
1151 u64 type)
ba395927
KA		 1152{
1153 u64 val = 0;
1154 unsigned long flag;
1155
ba395927
KA		 1156 switch (type) {
1157 case DMA_CCMD_GLOBAL_INVL:
1158 val = DMA_CCMD_GLOBAL_INVL;
1159 break;
1160 case DMA_CCMD_DOMAIN_INVL:
1161 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1162 break;
1163 case DMA_CCMD_DEVICE_INVL:
1164 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1165 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1166 break;
1167 default:
1168 BUG();
1169 }
1170 val |= DMA_CCMD_ICC;
1171
1f5b3c3f 1172 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1173 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1174
1175 /* Make sure hardware complete it */
1176 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1177 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1178
1f5b3c3f 1179 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1180}
1181
ba395927 1182/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1183static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1184 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1185{
1186 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1187 u64 val = 0, val_iva = 0;
1188 unsigned long flag;
1189
ba395927
KA		 1190 switch (type) {
1191 case DMA_TLB_GLOBAL_FLUSH:
1192 /* global flush doesn't need set IVA_REG */
1193 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1194 break;
1195 case DMA_TLB_DSI_FLUSH:
1196 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1197 break;
1198 case DMA_TLB_PSI_FLUSH:
1199 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1200 /* IH bit is passed in as part of address */
ba395927
KA		 1201 val_iva = size_order | addr;
1202 break;
1203 default:
1204 BUG();
1205 }
1206 /* Note: set drain read/write */
1207#if 0
1208 /*
1209 * This is probably to be super secure.. Looks like we can
1210 * ignore it without any impact.
1211 */
1212 if (cap_read_drain(iommu->cap))
1213 val |= DMA_TLB_READ_DRAIN;
1214#endif
1215 if (cap_write_drain(iommu->cap))
1216 val |= DMA_TLB_WRITE_DRAIN;
1217
1f5b3c3f 1218 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1219 /* Note: Only uses first TLB reg currently */
1220 if (val_iva)
1221 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1222 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1223
1224 /* Make sure hardware complete it */
1225 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1226 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1227
1f5b3c3f 1228 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1229
1230 /* check IOTLB invalidation granularity */
1231 if (DMA_TLB_IAIG(val) == 0)
1232 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1233 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1234 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1235 (unsigned long long)DMA_TLB_IIRG(type),
1236 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1237}
1238
93a23a72
YZ		 1239static struct device_domain_info *iommu_support_dev_iotlb(
1240 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1241{
1242 int found = 0;
1243 unsigned long flags;
1244 struct device_domain_info *info;
1245 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1246
1247 if (!ecap_dev_iotlb_support(iommu->ecap))
1248 return NULL;
1249
1250 if (!iommu->qi)
1251 return NULL;
1252
1253 spin_lock_irqsave(&device_domain_lock, flags);
1254 list_for_each_entry(info, &domain->devices, link)
1255 if (info->bus == bus && info->devfn == devfn) {
1256 found = 1;
1257 break;
1258 }
1259 spin_unlock_irqrestore(&device_domain_lock, flags);
1260
1261 if (!found || !info->dev)
1262 return NULL;
1263
1264 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1265 return NULL;
1266
1267 if (!dmar_find_matched_atsr_unit(info->dev))
1268 return NULL;
1269
1270 info->iommu = iommu;
1271
1272 return info;
1273}
1274
1275static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1276{
93a23a72
YZ		 1277 if (!info)
1278 return;
1279
1280 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1281}
1282
1283static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1284{
1285 if (!info->dev || !pci_ats_enabled(info->dev))
1286 return;
1287
1288 pci_disable_ats(info->dev);
1289}
1290
1291static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1292 u64 addr, unsigned mask)
1293{
1294 u16 sid, qdep;
1295 unsigned long flags;
1296 struct device_domain_info *info;
1297
1298 spin_lock_irqsave(&device_domain_lock, flags);
1299 list_for_each_entry(info, &domain->devices, link) {
1300 if (!info->dev || !pci_ats_enabled(info->dev))
1301 continue;
1302
1303 sid = info->bus << 8 | info->devfn;
1304 qdep = pci_ats_queue_depth(info->dev);
1305 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1306 }
1307 spin_unlock_irqrestore(&device_domain_lock, flags);
1308}
1309
1f0ef2aa 1310static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1311 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1312{
9dd2fe89 1313 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1314 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1315
ba395927
KA		 1316 BUG_ON(pages == 0);
1317
ea8ea460
DW		 1318 if (ih)
1319 ih = 1 << 6;
ba395927 1320 /*
9dd2fe89
YZ		 1321 * Fallback to domain selective flush if no PSI support or the size is
1322 * too big.
ba395927
KA		 1323 * PSI requires page size to be 2 ^ x, and the base address is naturally
1324 * aligned to the size
1325 */
9dd2fe89
YZ		 1326 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1327 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1328 DMA_TLB_DSI_FLUSH);
9dd2fe89 1329 else
ea8ea460 1330 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1331 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1332
1333 /*
82653633
NA		 1334 * In caching mode, changes of pages from non-present to present require
1335 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1336 */
82653633 1337 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1338 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1339}
1340
f8bab735 1341static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1342{
1343 u32 pmen;
1344 unsigned long flags;
1345
1f5b3c3f 1346 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1347 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1348 pmen &= ~DMA_PMEN_EPM;
1349 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1350
1351 /* wait for the protected region status bit to clear */
1352 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1353 readl, !(pmen & DMA_PMEN_PRS), pmen);
1354
1f5b3c3f 1355 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1356}
1357
ba395927
KA		 1358static int iommu_enable_translation(struct intel_iommu *iommu)
1359{
1360 u32 sts;
1361 unsigned long flags;
1362
1f5b3c3f 1363 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1364 iommu->gcmd |= DMA_GCMD_TE;
1365 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1366
1367 /* Make sure hardware complete it */
1368 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1369 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1370
1f5b3c3f 1371 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1372 return 0;
1373}
1374
1375static int iommu_disable_translation(struct intel_iommu *iommu)
1376{
1377 u32 sts;
1378 unsigned long flag;
1379
1f5b3c3f 1380 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1381 iommu->gcmd &= ~DMA_GCMD_TE;
1382 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1383
1384 /* Make sure hardware complete it */
1385 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1386 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1387
1f5b3c3f 1388 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1389 return 0;
1390}
1391
3460a6d9 1392
ba395927
KA		 1393static int iommu_init_domains(struct intel_iommu *iommu)
1394{
1395 unsigned long ndomains;
1396 unsigned long nlongs;
1397
1398 ndomains = cap_ndoms(iommu->cap);
852bdb04
JL		 1399 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1400 iommu->seq_id, ndomains);
ba395927
KA		 1401 nlongs = BITS_TO_LONGS(ndomains);
1402
94a91b50
DD		 1403 spin_lock_init(&iommu->lock);
1404
ba395927
KA		 1405 /* TBD: there might be 64K domains,
1406 * consider other allocation for future chip
1407 */
1408 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1409 if (!iommu->domain_ids) {
852bdb04
JL		 1410 pr_err("IOMMU%d: allocating domain id array failed\n",
1411 iommu->seq_id);
ba395927
KA		 1412 return -ENOMEM;
1413 }
1414 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1415 GFP_KERNEL);
1416 if (!iommu->domains) {
852bdb04
JL		 1417 pr_err("IOMMU%d: allocating domain array failed\n",
1418 iommu->seq_id);
1419 kfree(iommu->domain_ids);
1420 iommu->domain_ids = NULL;
ba395927
KA		 1421 return -ENOMEM;
1422 }
1423
1424 /*
1425 * if Caching mode is set, then invalid translations are tagged
1426 * with domainid 0. Hence we need to pre-allocate it.
1427 */
1428 if (cap_caching_mode(iommu->cap))
1429 set_bit(0, iommu->domain_ids);
1430 return 0;
1431}
ba395927 1432
a868e6b7 1433static void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1434{
1435 struct dmar_domain *domain;
5ced12af 1436 int i, count;
c7151a8d 1437 unsigned long flags;
ba395927 1438
94a91b50 1439 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1440 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1441 /*
1442 * Domain id 0 is reserved for invalid translation
1443 * if hardware supports caching mode.
1444 */
1445 if (cap_caching_mode(iommu->cap) && i == 0)
1446 continue;
1447
94a91b50
DD		 1448 domain = iommu->domains[i];
1449 clear_bit(i, iommu->domain_ids);
1450
1451 spin_lock_irqsave(&domain->iommu_lock, flags);
5ced12af
JL		 1452 count = --domain->iommu_count;
1453 spin_unlock_irqrestore(&domain->iommu_lock, flags);
92d03cc8
JL		 1454 if (count == 0)
1455 domain_exit(domain);
5e98c4b1 1456 }
ba395927
KA		 1457 }
1458
1459 if (iommu->gcmd & DMA_GCMD_TE)
1460 iommu_disable_translation(iommu);
1461
ba395927
KA		 1462 kfree(iommu->domains);
1463 kfree(iommu->domain_ids);
a868e6b7
JL		 1464 iommu->domains = NULL;
1465 iommu->domain_ids = NULL;
ba395927 1466
d9630fe9
WH		 1467 g_iommus[iommu->seq_id] = NULL;
1468
ba395927
KA		 1469 /* free context mapping */
1470 free_context_table(iommu);
ba395927
KA		 1471}
1472
92d03cc8 1473static struct dmar_domain *alloc_domain(bool vm)
ba395927 1474{
92d03cc8
JL		 1475 /* domain id for virtual machine, it won't be set in context */
1476 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1477 struct dmar_domain *domain;
ba395927
KA		 1478
1479 domain = alloc_domain_mem();
1480 if (!domain)
1481 return NULL;
1482
4c923d47 1483 domain->nid = -1;
92d03cc8 1484 domain->iommu_count = 0;
1b198bb0 1485 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
2c2e2c38 1486 domain->flags = 0;
92d03cc8
JL		 1487 spin_lock_init(&domain->iommu_lock);
1488 INIT_LIST_HEAD(&domain->devices);
1489 if (vm) {
1490 domain->id = atomic_inc_return(&vm_domid);
1491 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
1492 }
2c2e2c38
FY		 1493
1494 return domain;
1495}
1496
1497static int iommu_attach_domain(struct dmar_domain *domain,
1498 struct intel_iommu *iommu)
1499{
1500 int num;
1501 unsigned long ndomains;
1502 unsigned long flags;
1503
ba395927
KA		 1504 ndomains = cap_ndoms(iommu->cap);
1505
1506 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1507
ba395927
KA		 1508 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1509 if (num >= ndomains) {
1510 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1511 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1512 return -ENOMEM;
ba395927
KA		 1513 }
1514
ba395927 1515 domain->id = num;
9ebd682e 1516 domain->iommu_count++;
2c2e2c38 1517 set_bit(num, iommu->domain_ids);
1b198bb0 1518 set_bit(iommu->seq_id, domain->iommu_bmp);
ba395927
KA		 1519 iommu->domains[num] = domain;
1520 spin_unlock_irqrestore(&iommu->lock, flags);
1521
2c2e2c38 1522 return 0;
ba395927
KA		 1523}
1524
2c2e2c38
FY		 1525static void iommu_detach_domain(struct dmar_domain *domain,
1526 struct intel_iommu *iommu)
ba395927
KA		 1527{
1528 unsigned long flags;
2c2e2c38 1529 int num, ndomains;
ba395927 1530
8c11e798 1531 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1532 ndomains = cap_ndoms(iommu->cap);
a45946ab 1533 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38 1534 if (iommu->domains[num] == domain) {
92d03cc8
JL		 1535 clear_bit(num, iommu->domain_ids);
1536 iommu->domains[num] = NULL;
2c2e2c38
FY		 1537 break;
1538 }
2c2e2c38 1539 }
8c11e798 1540 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1541}
1542
1543static struct iova_domain reserved_iova_list;
8a443df4 1544static struct lock_class_key reserved_rbtree_key;
ba395927 1545
51a63e67 1546static int dmar_init_reserved_ranges(void)
ba395927
KA		 1547{
1548 struct pci_dev *pdev = NULL;
1549 struct iova *iova;
1550 int i;
ba395927 1551
f661197e 1552 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1553
8a443df4
MG		 1554 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1555 &reserved_rbtree_key);
1556
ba395927
KA		 1557 /* IOAPIC ranges shouldn't be accessed by DMA */
1558 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1559 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1560 if (!iova) {
ba395927 1561 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1562 return -ENODEV;
1563 }
ba395927
KA		 1564
1565 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1566 for_each_pci_dev(pdev) {
1567 struct resource *r;
1568
1569 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1570 r = &pdev->resource[i];
1571 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1572 continue;
1a4a4551
DW		 1573 iova = reserve_iova(&reserved_iova_list,
1574 IOVA_PFN(r->start),
1575 IOVA_PFN(r->end));
51a63e67 1576 if (!iova) {
ba395927 1577 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1578 return -ENODEV;
1579 }
ba395927
KA		 1580 }
1581 }
51a63e67 1582 return 0;
ba395927
KA		 1583}
1584
1585static void domain_reserve_special_ranges(struct dmar_domain *domain)
1586{
1587 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1588}
1589
1590static inline int guestwidth_to_adjustwidth(int gaw)
1591{
1592 int agaw;
1593 int r = (gaw - 12) % 9;
1594
1595 if (r == 0)
1596 agaw = gaw;
1597 else
1598 agaw = gaw + 9 - r;
1599 if (agaw > 64)
1600 agaw = 64;
1601 return agaw;
1602}
1603
1604static int domain_init(struct dmar_domain *domain, int guest_width)
1605{
1606 struct intel_iommu *iommu;
1607 int adjust_width, agaw;
1608 unsigned long sagaw;
1609
f661197e 1610 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927
KA		 1611 domain_reserve_special_ranges(domain);
1612
1613 /* calculate AGAW */
8c11e798 1614 iommu = domain_get_iommu(domain);
ba395927
KA		 1615 if (guest_width > cap_mgaw(iommu->cap))
1616 guest_width = cap_mgaw(iommu->cap);
1617 domain->gaw = guest_width;
1618 adjust_width = guestwidth_to_adjustwidth(guest_width);
1619 agaw = width_to_agaw(adjust_width);
1620 sagaw = cap_sagaw(iommu->cap);
1621 if (!test_bit(agaw, &sagaw)) {
1622 /* hardware doesn't support it, choose a bigger one */
1623 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1624 agaw = find_next_bit(&sagaw, 5, agaw);
1625 if (agaw >= 5)
1626 return -ENODEV;
1627 }
1628 domain->agaw = agaw;
ba395927 1629
8e604097
WH		 1630 if (ecap_coherent(iommu->ecap))
1631 domain->iommu_coherency = 1;
1632 else
1633 domain->iommu_coherency = 0;
1634
58c610bd
SY		 1635 if (ecap_sc_support(iommu->ecap))
1636 domain->iommu_snooping = 1;
1637 else
1638 domain->iommu_snooping = 0;
1639
214e39aa
DW		 1640 if (intel_iommu_superpage)
1641 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1642 else
1643 domain->iommu_superpage = 0;
1644
4c923d47 1645 domain->nid = iommu->node;
c7151a8d 1646
ba395927 1647 /* always allocate the top pgd */
4c923d47 1648 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1649 if (!domain->pgd)
1650 return -ENOMEM;
5b6985ce 1651 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1652 return 0;
1653}
1654
1655static void domain_exit(struct dmar_domain *domain)
1656{
2c2e2c38
FY		 1657 struct dmar_drhd_unit *drhd;
1658 struct intel_iommu *iommu;
ea8ea460 1659 struct page *freelist = NULL;
ba395927
KA		 1660
1661 /* Domain 0 is reserved, so dont process it */
1662 if (!domain)
1663 return;
1664
7b668357
AW		 1665 /* Flush any lazy unmaps that may reference this domain */
1666 if (!intel_iommu_strict)
1667 flush_unmaps_timeout(0);
1668
92d03cc8 1669 /* remove associated devices */
ba395927 1670 domain_remove_dev_info(domain);
92d03cc8 1671
ba395927
KA		 1672 /* destroy iovas */
1673 put_iova_domain(&domain->iovad);
ba395927 1674
ea8ea460 1675 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1676
92d03cc8 1677 /* clear attached or cached domains */
0e242612 1678 rcu_read_lock();
2c2e2c38 1679 for_each_active_iommu(iommu, drhd)
92d03cc8
JL		 1680 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1681 test_bit(iommu->seq_id, domain->iommu_bmp))
2c2e2c38 1682 iommu_detach_domain(domain, iommu);
0e242612 1683 rcu_read_unlock();
2c2e2c38 1684
ea8ea460
DW		 1685 dma_free_pagelist(freelist);
1686
ba395927
KA		 1687 free_domain_mem(domain);
1688}
1689
4ed0d3e6
FY		 1690static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1691 u8 bus, u8 devfn, int translation)
ba395927
KA		 1692{
1693 struct context_entry *context;
ba395927 1694 unsigned long flags;
5331fe6f 1695 struct intel_iommu *iommu;
ea6606b0
WH		 1696 struct dma_pte *pgd;
1697 unsigned long num;
1698 unsigned long ndomains;
1699 int id;
1700 int agaw;
93a23a72 1701 struct device_domain_info *info = NULL;
ba395927
KA		 1702
1703 pr_debug("Set context mapping for %02x:%02x.%d\n",
1704 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1705
ba395927 1706 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1707 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1708 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1709
276dbf99 1710 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1711 if (!iommu)
1712 return -ENODEV;
1713
ba395927
KA		 1714 context = device_to_context_entry(iommu, bus, devfn);
1715 if (!context)
1716 return -ENOMEM;
1717 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1718 if (context_present(context)) {
ba395927
KA		 1719 spin_unlock_irqrestore(&iommu->lock, flags);
1720 return 0;
1721 }
1722
ea6606b0
WH		 1723 id = domain->id;
1724 pgd = domain->pgd;
1725
2c2e2c38
FY		 1726 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1727 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1728 int found = 0;
1729
1730 /* find an available domain id for this device in iommu */
1731 ndomains = cap_ndoms(iommu->cap);
a45946ab 1732 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1733 if (iommu->domains[num] == domain) {
1734 id = num;
1735 found = 1;
1736 break;
1737 }
ea6606b0
WH		 1738 }
1739
1740 if (found == 0) {
1741 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1742 if (num >= ndomains) {
1743 spin_unlock_irqrestore(&iommu->lock, flags);
1744 printk(KERN_ERR "IOMMU: no free domain ids\n");
1745 return -EFAULT;
1746 }
1747
1748 set_bit(num, iommu->domain_ids);
1749 iommu->domains[num] = domain;
1750 id = num;
1751 }
1752
1753 /* Skip top levels of page tables for
1754 * iommu which has less agaw than default.
1672af11 1755 * Unnecessary for PT mode.
ea6606b0 1756 */
1672af11
CW		 1757 if (translation != CONTEXT_TT_PASS_THROUGH) {
1758 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1759 pgd = phys_to_virt(dma_pte_addr(pgd));
1760 if (!dma_pte_present(pgd)) {
1761 spin_unlock_irqrestore(&iommu->lock, flags);
1762 return -ENOMEM;
1763 }
ea6606b0
WH		 1764 }
1765 }
1766 }
1767
1768 context_set_domain_id(context, id);
4ed0d3e6 1769
93a23a72
YZ		 1770 if (translation != CONTEXT_TT_PASS_THROUGH) {
1771 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1772 translation = info ? CONTEXT_TT_DEV_IOTLB :
1773 CONTEXT_TT_MULTI_LEVEL;
1774 }
4ed0d3e6
FY		 1775 /*
1776 * In pass through mode, AW must be programmed to indicate the largest
1777 * AGAW value supported by hardware. And ASR is ignored by hardware.
1778 */
93a23a72 1779 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1780 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1781 else {
1782 context_set_address_root(context, virt_to_phys(pgd));
1783 context_set_address_width(context, iommu->agaw);
1784 }
4ed0d3e6
FY		 1785
1786 context_set_translation_type(context, translation);
c07e7d21
MM		 1787 context_set_fault_enable(context);
1788 context_set_present(context);
5331fe6f 1789 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1790
4c25a2c1
DW		 1791 /*
1792 * It's a non-present to present mapping. If hardware doesn't cache
1793 * non-present entry we only need to flush the write-buffer. If the
1794 * _does_ cache non-present entries, then it does so in the special
1795 * domain #0, which we have to flush:
1796 */
1797 if (cap_caching_mode(iommu->cap)) {
1798 iommu->flush.flush_context(iommu, 0,
1799 (((u16)bus) << 8) | devfn,
1800 DMA_CCMD_MASK_NOBIT,
1801 DMA_CCMD_DEVICE_INVL);
82653633 1802 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1803 } else {
ba395927 1804 iommu_flush_write_buffer(iommu);
4c25a2c1 1805 }
93a23a72 1806 iommu_enable_dev_iotlb(info);
ba395927 1807 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1808
1809 spin_lock_irqsave(&domain->iommu_lock, flags);
1b198bb0 1810 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
c7151a8d 1811 domain->iommu_count++;
4c923d47
SS		 1812 if (domain->iommu_count == 1)
1813 domain->nid = iommu->node;
58c610bd 1814 domain_update_iommu_cap(domain);
c7151a8d
WH		 1815 }
1816 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1817 return 0;
1818}
1819
1820static int
4ed0d3e6
FY		 1821domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1822 int translation)
ba395927
KA		 1823{
1824 int ret;
1825 struct pci_dev *tmp, *parent;
1826
276dbf99 1827 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1828 pdev->bus->number, pdev->devfn,
1829 translation);
ba395927
KA		 1830 if (ret)
1831 return ret;
1832
1833 /* dependent device mapping */
1834 tmp = pci_find_upstream_pcie_bridge(pdev);
1835 if (!tmp)
1836 return 0;
1837 /* Secondary interface's bus number and devfn 0 */
1838 parent = pdev->bus->self;
1839 while (parent != tmp) {
276dbf99
DW		 1840 ret = domain_context_mapping_one(domain,
1841 pci_domain_nr(parent->bus),
1842 parent->bus->number,
4ed0d3e6 1843 parent->devfn, translation);
ba395927
KA		 1844 if (ret)
1845 return ret;
1846 parent = parent->bus->self;
1847 }
45e829ea 1848 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
ba395927 1849 return domain_context_mapping_one(domain,
276dbf99 1850 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1851 tmp->subordinate->number, 0,
1852 translation);
ba395927
KA		 1853 else /* this is a legacy PCI bridge */
1854 return domain_context_mapping_one(domain,
276dbf99
DW		 1855 pci_domain_nr(tmp->bus),
1856 tmp->bus->number,
4ed0d3e6
FY		 1857 tmp->devfn,
1858 translation);
ba395927
KA		 1859}
1860
5331fe6f 1861static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1862{
1863 int ret;
1864 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1865 struct intel_iommu *iommu;
1866
276dbf99
DW		 1867 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1868 pdev->devfn);
5331fe6f
WH		 1869 if (!iommu)
1870 return -ENODEV;
ba395927 1871
276dbf99 1872 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1873 if (!ret)
1874 return ret;
1875 /* dependent device mapping */
1876 tmp = pci_find_upstream_pcie_bridge(pdev);
1877 if (!tmp)
1878 return ret;
1879 /* Secondary interface's bus number and devfn 0 */
1880 parent = pdev->bus->self;
1881 while (parent != tmp) {
8c11e798 1882 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1883 parent->devfn);
ba395927
KA		 1884 if (!ret)
1885 return ret;
1886 parent = parent->bus->self;
1887 }
5f4d91a1 1888 if (pci_is_pcie(tmp))
276dbf99
DW		 1889 return device_context_mapped(iommu, tmp->subordinate->number,
1890 0);
ba395927 1891 else
276dbf99
DW		 1892 return device_context_mapped(iommu, tmp->bus->number,
1893 tmp->devfn);
ba395927
KA		 1894}
1895
f532959b
FY		 1896/* Returns a number of VTD pages, but aligned to MM page size */
1897static inline unsigned long aligned_nrpages(unsigned long host_addr,
1898 size_t size)
1899{
1900 host_addr &= ~PAGE_MASK;
1901 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1902}
1903
6dd9a7c7
YS		 1904/* Return largest possible superpage level for a given mapping */
1905static inline int hardware_largepage_caps(struct dmar_domain *domain,
1906 unsigned long iov_pfn,
1907 unsigned long phy_pfn,
1908 unsigned long pages)
1909{
1910 int support, level = 1;
1911 unsigned long pfnmerge;
1912
1913 support = domain->iommu_superpage;
1914
1915 /* To use a large page, the virtual *and* physical addresses
1916 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1917 of them will mean we have to use smaller pages. So just
1918 merge them and check both at once. */
1919 pfnmerge = iov_pfn | phy_pfn;
1920
1921 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1922 pages >>= VTD_STRIDE_SHIFT;
1923 if (!pages)
1924 break;
1925 pfnmerge >>= VTD_STRIDE_SHIFT;
1926 level++;
1927 support--;
1928 }
1929 return level;
1930}
1931
9051aa02
DW		 1932static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1933 struct scatterlist *sg, unsigned long phys_pfn,
1934 unsigned long nr_pages, int prot)
e1605495
DW		 1935{
1936 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1937 phys_addr_t uninitialized_var(pteval);
e1605495 1938 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1939 unsigned long sg_res;
6dd9a7c7
YS		 1940 unsigned int largepage_lvl = 0;
1941 unsigned long lvl_pages = 0;
e1605495
DW		 1942
1943 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1944
1945 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1946 return -EINVAL;
1947
1948 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1949
9051aa02
DW		 1950 if (sg)
1951 sg_res = 0;
1952 else {
1953 sg_res = nr_pages + 1;
1954 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1955 }
1956
6dd9a7c7 1957 while (nr_pages > 0) {
c85994e4
DW		 1958 uint64_t tmp;
1959
e1605495 1960 if (!sg_res) {
f532959b 1961 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1962 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1963 sg->dma_length = sg->length;
1964 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1965 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1966 }
6dd9a7c7 1967
e1605495 1968 if (!pte) {
6dd9a7c7
YS		 1969 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1970
5cf0a76f 1971 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 1972 if (!pte)
1973 return -ENOMEM;
6dd9a7c7 1974 /* It is large page*/
6491d4d0 1975 if (largepage_lvl > 1) {
6dd9a7c7 1976 pteval |= DMA_PTE_LARGE_PAGE;
6491d4d0
WD		 1977 /* Ensure that old small page tables are removed to make room
1978 for superpage, if they exist. */
1979 dma_pte_clear_range(domain, iov_pfn,
1980 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1981 dma_pte_free_pagetable(domain, iov_pfn,
1982 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1983 } else {
6dd9a7c7 1984 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 1985 }
6dd9a7c7 1986
e1605495
DW		 1987 }
1988 /* We don't need lock here, nobody else
1989 * touches the iova range
1990 */
7766a3fb 1991 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1992 if (tmp) {
1bf20f0d 1993 static int dumps = 5;
c85994e4
DW		 1994 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1995 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1996 if (dumps) {
1997 dumps--;
1998 debug_dma_dump_mappings(NULL);
1999 }
2000 WARN_ON(1);
2001 }
6dd9a7c7
YS		 2002
2003 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2004
2005 BUG_ON(nr_pages < lvl_pages);
2006 BUG_ON(sg_res < lvl_pages);
2007
2008 nr_pages -= lvl_pages;
2009 iov_pfn += lvl_pages;
2010 phys_pfn += lvl_pages;
2011 pteval += lvl_pages * VTD_PAGE_SIZE;
2012 sg_res -= lvl_pages;
2013
2014 /* If the next PTE would be the first in a new page, then we
2015 need to flush the cache on the entries we've just written.
2016 And then we'll need to recalculate 'pte', so clear it and
2017 let it get set again in the if (!pte) block above.
2018
2019 If we're done (!nr_pages) we need to flush the cache too.
2020
2021 Also if we've been setting superpages, we may need to
2022 recalculate 'pte' and switch back to smaller pages for the
2023 end of the mapping, if the trailing size is not enough to
2024 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2025 pte++;
6dd9a7c7
YS		 2026 if (!nr_pages || first_pte_in_page(pte) ||
2027 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2028 domain_flush_cache(domain, first_pte,
2029 (void *)pte - (void *)first_pte);
2030 pte = NULL;
2031 }
6dd9a7c7
YS		 2032
2033 if (!sg_res && nr_pages)
e1605495
DW		 2034 sg = sg_next(sg);
2035 }
2036 return 0;
2037}
2038
9051aa02
DW		 2039static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2040 struct scatterlist *sg, unsigned long nr_pages,
2041 int prot)
ba395927 2042{
9051aa02
DW		 2043 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2044}
6f6a00e4 2045
9051aa02
DW		 2046static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2047 unsigned long phys_pfn, unsigned long nr_pages,
2048 int prot)
2049{
2050 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2051}
2052
c7151a8d 2053static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2054{
c7151a8d
WH		 2055 if (!iommu)
2056 return;
8c11e798
WH		 2057
2058 clear_context_table(iommu, bus, devfn);
2059 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2060 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2061 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2062}
2063
109b9b04
DW		 2064static inline void unlink_domain_info(struct device_domain_info *info)
2065{
2066 assert_spin_locked(&device_domain_lock);
2067 list_del(&info->link);
2068 list_del(&info->global);
2069 if (info->dev)
2070 info->dev->dev.archdata.iommu = NULL;
2071}
2072
ba395927
KA		 2073static void domain_remove_dev_info(struct dmar_domain *domain)
2074{
2075 struct device_domain_info *info;
92d03cc8 2076 unsigned long flags, flags2;
c7151a8d 2077 struct intel_iommu *iommu;
ba395927
KA		 2078
2079 spin_lock_irqsave(&device_domain_lock, flags);
2080 while (!list_empty(&domain->devices)) {
2081 info = list_entry(domain->devices.next,
2082 struct device_domain_info, link);
109b9b04 2083 unlink_domain_info(info);
ba395927
KA		 2084 spin_unlock_irqrestore(&device_domain_lock, flags);
2085
93a23a72 2086 iommu_disable_dev_iotlb(info);
276dbf99 2087 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 2088 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927 2089
92d03cc8
JL		 2090 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
2091 iommu_detach_dependent_devices(iommu, info->dev);
2092 /* clear this iommu in iommu_bmp, update iommu count
2093 * and capabilities
2094 */
2095 spin_lock_irqsave(&domain->iommu_lock, flags2);
2096 if (test_and_clear_bit(iommu->seq_id,
2097 domain->iommu_bmp)) {
2098 domain->iommu_count--;
2099 domain_update_iommu_cap(domain);
2100 }
2101 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
2102 }
2103
2104 free_devinfo_mem(info);
ba395927
KA		 2105 spin_lock_irqsave(&device_domain_lock, flags);
2106 }
2107 spin_unlock_irqrestore(&device_domain_lock, flags);
2108}
2109
2110/*
2111 * find_domain
358dd8ac 2112 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 2113 */
38717946 2114static struct dmar_domain *
ba395927
KA		 2115find_domain(struct pci_dev *pdev)
2116{
2117 struct device_domain_info *info;
2118
2119 /* No lock here, assumes no domain exit in normal case */
358dd8ac 2120 info = pdev->dev.archdata.iommu;
ba395927
KA		 2121 if (info)
2122 return info->domain;
2123 return NULL;
2124}
2125
745f2586
JL		 2126static inline struct dmar_domain *
2127dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2128{
2129 struct device_domain_info *info;
2130
2131 list_for_each_entry(info, &device_domain_list, global)
2132 if (info->segment == segment && info->bus == bus &&
2133 info->devfn == devfn)
2134 return info->domain;
2135
2136 return NULL;
2137}
2138
2139static int dmar_insert_dev_info(int segment, int bus, int devfn,
2140 struct pci_dev *dev, struct dmar_domain **domp)
2141{
2142 struct dmar_domain *found, *domain = *domp;
2143 struct device_domain_info *info;
2144 unsigned long flags;
2145
2146 info = alloc_devinfo_mem();
2147 if (!info)
2148 return -ENOMEM;
2149
2150 info->segment = segment;
2151 info->bus = bus;
2152 info->devfn = devfn;
2153 info->dev = dev;
2154 info->domain = domain;
2155 if (!dev)
2156 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2157
2158 spin_lock_irqsave(&device_domain_lock, flags);
2159 if (dev)
2160 found = find_domain(dev);
2161 else
2162 found = dmar_search_domain_by_dev_info(segment, bus, devfn);
2163 if (found) {
2164 spin_unlock_irqrestore(&device_domain_lock, flags);
2165 free_devinfo_mem(info);
2166 if (found != domain) {
2167 domain_exit(domain);
2168 *domp = found;
2169 }
2170 } else {
2171 list_add(&info->link, &domain->devices);
2172 list_add(&info->global, &device_domain_list);
2173 if (dev)
2174 dev->dev.archdata.iommu = info;
2175 spin_unlock_irqrestore(&device_domain_lock, flags);
2176 }
2177
2178 return 0;
2179}
2180
ba395927
KA		 2181/* domain is initialized */
2182static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
2183{
e85bb5d4 2184 struct dmar_domain *domain, *free = NULL;
ba395927
KA		 2185 struct intel_iommu *iommu;
2186 struct dmar_drhd_unit *drhd;
ba395927
KA		 2187 struct pci_dev *dev_tmp;
2188 unsigned long flags;
2189 int bus = 0, devfn = 0;
276dbf99 2190 int segment;
ba395927
KA		 2191
2192 domain = find_domain(pdev);
2193 if (domain)
2194 return domain;
2195
276dbf99
DW		 2196 segment = pci_domain_nr(pdev->bus);
2197
ba395927
KA		 2198 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
2199 if (dev_tmp) {
5f4d91a1 2200 if (pci_is_pcie(dev_tmp)) {
ba395927
KA		 2201 bus = dev_tmp->subordinate->number;
2202 devfn = 0;
2203 } else {
2204 bus = dev_tmp->bus->number;
2205 devfn = dev_tmp->devfn;
2206 }
2207 spin_lock_irqsave(&device_domain_lock, flags);
745f2586 2208 domain = dmar_search_domain_by_dev_info(segment, bus, devfn);
ba395927
KA		 2209 spin_unlock_irqrestore(&device_domain_lock, flags);
2210 /* pcie-pci bridge already has a domain, uses it */
745f2586 2211 if (domain)
ba395927 2212 goto found_domain;
ba395927
KA		 2213 }
2214
ba395927
KA		 2215 drhd = dmar_find_matched_drhd_unit(pdev);
2216 if (!drhd) {
2217 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
2218 pci_name(pdev));
2219 return NULL;
2220 }
2221 iommu = drhd->iommu;
2222
745f2586 2223 /* Allocate and intialize new domain for the device */
92d03cc8 2224 domain = alloc_domain(false);
745f2586
JL		 2225 if (!domain)
2226 goto error;
2227 if (iommu_attach_domain(domain, iommu)) {
2fe9723d 2228 free_domain_mem(domain);
ba395927 2229 goto error;
2c2e2c38 2230 }
e85bb5d4
JL		 2231 free = domain;
2232 if (domain_init(domain, gaw))
ba395927 2233 goto error;
ba395927
KA		 2234
2235 /* register pcie-to-pci device */
2236 if (dev_tmp) {
e85bb5d4 2237 if (dmar_insert_dev_info(segment, bus, devfn, NULL, &domain))
ba395927 2238 goto error;
e85bb5d4
JL		 2239 else
2240 free = NULL;
ba395927
KA		 2241 }
2242
2243found_domain:
745f2586
JL		 2244 if (dmar_insert_dev_info(segment, pdev->bus->number, pdev->devfn,
2245 pdev, &domain) == 0)
ba395927 2246 return domain;
ba395927 2247error:
e85bb5d4
JL		 2248 if (free)
2249 domain_exit(free);
ba395927
KA		 2250 /* recheck it here, maybe others set it */
2251 return find_domain(pdev);
2252}
2253
2c2e2c38 2254static int iommu_identity_mapping;
e0fc7e0b
DW		 2255#define IDENTMAP_ALL 1
2256#define IDENTMAP_GFX 2
2257#define IDENTMAP_AZALIA 4
2c2e2c38 2258
b213203e
DW		 2259static int iommu_domain_identity_map(struct dmar_domain *domain,
2260 unsigned long long start,
2261 unsigned long long end)
ba395927 2262{
c5395d5c
DW		 2263 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2264 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2265
2266 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2267 dma_to_mm_pfn(last_vpfn))) {
ba395927 2268 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2269 return -ENOMEM;
ba395927
KA		 2270 }
2271
c5395d5c
DW		 2272 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2273 start, end, domain->id);
ba395927
KA		 2274 /*
2275 * RMRR range might have overlap with physical memory range,
2276 * clear it first
2277 */
c5395d5c 2278 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2279
c5395d5c
DW		 2280 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2281 last_vpfn - first_vpfn + 1,
61df7443 2282 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2283}
2284
2285static int iommu_prepare_identity_map(struct pci_dev *pdev,
2286 unsigned long long start,
2287 unsigned long long end)
2288{
2289 struct dmar_domain *domain;
2290 int ret;
2291
c7ab48d2 2292 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2293 if (!domain)
2294 return -ENOMEM;
2295
19943b0e
DW		 2296 /* For _hardware_ passthrough, don't bother. But for software
2297 passthrough, we do it anyway -- it may indicate a memory
2298 range which is reserved in E820, so which didn't get set
2299 up to start with in si_domain */
2300 if (domain == si_domain && hw_pass_through) {
2301 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2302 pci_name(pdev), start, end);
2303 return 0;
2304 }
2305
2306 printk(KERN_INFO
2307 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2308 pci_name(pdev), start, end);
2ff729f5 2309
5595b528
DW		 2310 if (end < start) {
2311 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2312 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2313 dmi_get_system_info(DMI_BIOS_VENDOR),
2314 dmi_get_system_info(DMI_BIOS_VERSION),
2315 dmi_get_system_info(DMI_PRODUCT_VERSION));
2316 ret = -EIO;
2317 goto error;
2318 }
2319
2ff729f5
DW		 2320 if (end >> agaw_to_width(domain->agaw)) {
2321 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2322 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2323 agaw_to_width(domain->agaw),
2324 dmi_get_system_info(DMI_BIOS_VENDOR),
2325 dmi_get_system_info(DMI_BIOS_VERSION),
2326 dmi_get_system_info(DMI_PRODUCT_VERSION));
2327 ret = -EIO;
2328 goto error;
2329 }
19943b0e 2330
b213203e 2331 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2332 if (ret)
2333 goto error;
2334
2335 /* context entry init */
4ed0d3e6 2336 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2337 if (ret)
2338 goto error;
2339
2340 return 0;
2341
2342 error:
ba395927
KA		 2343 domain_exit(domain);
2344 return ret;
ba395927
KA		 2345}
2346
2347static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2348 struct pci_dev *pdev)
2349{
358dd8ac 2350 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 2351 return 0;
2352 return iommu_prepare_identity_map(pdev, rmrr->base_address,
70e535d1 2353 rmrr->end_address);
ba395927
KA		 2354}
2355
d3f13810 2356#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2357static inline void iommu_prepare_isa(void)
2358{
2359 struct pci_dev *pdev;
2360 int ret;
2361
2362 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2363 if (!pdev)
2364 return;
2365
c7ab48d2 2366 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
70e535d1 2367 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2368
2369 if (ret)
c7ab48d2
DW		 2370 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2371 "floppy might not work\n");
49a0429e
KA		 2372
2373}
2374#else
2375static inline void iommu_prepare_isa(void)
2376{
2377 return;
2378}
d3f13810 2379#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2380
2c2e2c38 2381static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2382
071e1374 2383static int __init si_domain_init(int hw)
2c2e2c38
FY		 2384{
2385 struct dmar_drhd_unit *drhd;
2386 struct intel_iommu *iommu;
c7ab48d2 2387 int nid, ret = 0;
2c2e2c38 2388
92d03cc8 2389 si_domain = alloc_domain(false);
2c2e2c38
FY		 2390 if (!si_domain)
2391 return -EFAULT;
2392
92d03cc8
JL		 2393 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2394
2c2e2c38
FY		 2395 for_each_active_iommu(iommu, drhd) {
2396 ret = iommu_attach_domain(si_domain, iommu);
2397 if (ret) {
2398 domain_exit(si_domain);
2399 return -EFAULT;
2400 }
2401 }
2402
2403 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2404 domain_exit(si_domain);
2405 return -EFAULT;
2406 }
2407
9544c003
JL		 2408 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2409 si_domain->id);
2c2e2c38 2410
19943b0e
DW		 2411 if (hw)
2412 return 0;
2413
c7ab48d2 2414 for_each_online_node(nid) {
5dfe8660
TH		 2415 unsigned long start_pfn, end_pfn;
2416 int i;
2417
2418 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2419 ret = iommu_domain_identity_map(si_domain,
2420 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2421 if (ret)
2422 return ret;
2423 }
c7ab48d2
DW		 2424 }
2425
2c2e2c38
FY		 2426 return 0;
2427}
2428
2c2e2c38
FY		 2429static int identity_mapping(struct pci_dev *pdev)
2430{
2431 struct device_domain_info *info;
2432
2433 if (likely(!iommu_identity_mapping))
2434 return 0;
2435
cb452a40
MT		 2436 info = pdev->dev.archdata.iommu;
2437 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2438 return (info->domain == si_domain);
2c2e2c38 2439
2c2e2c38
FY		 2440 return 0;
2441}
2442
2443static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2444 struct pci_dev *pdev,
2445 int translation)
2c2e2c38
FY		 2446{
2447 struct device_domain_info *info;
2448 unsigned long flags;
5fe60f4e 2449 int ret;
2c2e2c38
FY		 2450
2451 info = alloc_devinfo_mem();
2452 if (!info)
2453 return -ENOMEM;
2454
2455 info->segment = pci_domain_nr(pdev->bus);
2456 info->bus = pdev->bus->number;
2457 info->devfn = pdev->devfn;
2458 info->dev = pdev;
2459 info->domain = domain;
2460
2461 spin_lock_irqsave(&device_domain_lock, flags);
2462 list_add(&info->link, &domain->devices);
2463 list_add(&info->global, &device_domain_list);
2464 pdev->dev.archdata.iommu = info;
2465 spin_unlock_irqrestore(&device_domain_lock, flags);
2466
e2ad23d0
DW		 2467 ret = domain_context_mapping(domain, pdev, translation);
2468 if (ret) {
2469 spin_lock_irqsave(&device_domain_lock, flags);
109b9b04 2470 unlink_domain_info(info);
e2ad23d0
DW		 2471 spin_unlock_irqrestore(&device_domain_lock, flags);
2472 free_devinfo_mem(info);
2473 return ret;
2474 }
2475
2c2e2c38
FY		 2476 return 0;
2477}
2478
ea2447f7
TM		 2479static bool device_has_rmrr(struct pci_dev *dev)
2480{
2481 struct dmar_rmrr_unit *rmrr;
b683b230 2482 struct pci_dev *tmp;
ea2447f7
TM		 2483 int i;
2484
0e242612 2485 rcu_read_lock();
ea2447f7 2486 for_each_rmrr_units(rmrr) {
b683b230
JL		 2487 /*
2488 * Return TRUE if this RMRR contains the device that
2489 * is passed in.
2490 */
2491 for_each_active_dev_scope(rmrr->devices,
2492 rmrr->devices_cnt, i, tmp)
2493 if (tmp == dev) {
0e242612 2494 rcu_read_unlock();
ea2447f7 2495 return true;
b683b230 2496 }
ea2447f7 2497 }
0e242612 2498 rcu_read_unlock();
ea2447f7
TM		 2499 return false;
2500}
2501
6941af28
DW		 2502static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2503{
ea2447f7
TM		 2504
2505 /*
2506 * We want to prevent any device associated with an RMRR from
2507 * getting placed into the SI Domain. This is done because
2508 * problems exist when devices are moved in and out of domains
2509 * and their respective RMRR info is lost. We exempt USB devices
2510 * from this process due to their usage of RMRRs that are known
2511 * to not be needed after BIOS hand-off to OS.
2512 */
2513 if (device_has_rmrr(pdev) &&
2514 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2515 return 0;
2516
e0fc7e0b
DW		 2517 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2518 return 1;
2519
2520 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2521 return 1;
2522
2523 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2524 return 0;
6941af28 2525
3dfc813d
DW		 2526 /*
2527 * We want to start off with all devices in the 1:1 domain, and
2528 * take them out later if we find they can't access all of memory.
2529 *
2530 * However, we can't do this for PCI devices behind bridges,
2531 * because all PCI devices behind the same bridge will end up
2532 * with the same source-id on their transactions.
2533 *
2534 * Practically speaking, we can't change things around for these
2535 * devices at run-time, because we can't be sure there'll be no
2536 * DMA transactions in flight for any of their siblings.
2537 *
2538 * So PCI devices (unless they're on the root bus) as well as
2539 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2540 * the 1:1 domain, just in _case_ one of their siblings turns out
2541 * not to be able to map all of memory.
2542 */
5f4d91a1 2543 if (!pci_is_pcie(pdev)) {
3dfc813d
DW		 2544 if (!pci_is_root_bus(pdev->bus))
2545 return 0;
2546 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2547 return 0;
62f87c0e 2548 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d
DW		 2549 return 0;
2550
2551 /*
2552 * At boot time, we don't yet know if devices will be 64-bit capable.
2553 * Assume that they will -- if they turn out not to be, then we can
2554 * take them out of the 1:1 domain later.
2555 */
8fcc5372
CW		 2556 if (!startup) {
2557 /*
2558 * If the device's dma_mask is less than the system's memory
2559 * size then this is not a candidate for identity mapping.
2560 */
2561 u64 dma_mask = pdev->dma_mask;
2562
2563 if (pdev->dev.coherent_dma_mask &&
2564 pdev->dev.coherent_dma_mask < dma_mask)
2565 dma_mask = pdev->dev.coherent_dma_mask;
2566
2567 return dma_mask >= dma_get_required_mask(&pdev->dev);
2568 }
6941af28
DW		 2569
2570 return 1;
2571}
2572
071e1374 2573static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2574{
2c2e2c38
FY		 2575 struct pci_dev *pdev = NULL;
2576 int ret;
2577
19943b0e 2578 ret = si_domain_init(hw);
2c2e2c38
FY		 2579 if (ret)
2580 return -EFAULT;
2581
2c2e2c38 2582 for_each_pci_dev(pdev) {
6941af28 2583 if (iommu_should_identity_map(pdev, 1)) {
5fe60f4e 2584 ret = domain_add_dev_info(si_domain, pdev,
eae460b6
MT		 2585 hw ? CONTEXT_TT_PASS_THROUGH :
2586 CONTEXT_TT_MULTI_LEVEL);
2587 if (ret) {
2588 /* device not associated with an iommu */
2589 if (ret == -ENODEV)
2590 continue;
62edf5dc 2591 return ret;
eae460b6
MT		 2592 }
2593 pr_info("IOMMU: %s identity mapping for device %s\n",
2594 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2595 }
2c2e2c38
FY		 2596 }
2597
2598 return 0;
2599}
2600
b779260b 2601static int __init init_dmars(void)
ba395927
KA		 2602{
2603 struct dmar_drhd_unit *drhd;
2604 struct dmar_rmrr_unit *rmrr;
2605 struct pci_dev *pdev;
2606 struct intel_iommu *iommu;
9d783ba0 2607 int i, ret;
2c2e2c38 2608
ba395927
KA		 2609 /*
2610 * for each drhd
2611 * allocate root
2612 * initialize and program root entry to not present
2613 * endfor
2614 */
2615 for_each_drhd_unit(drhd) {
5e0d2a6f 2616 /*
2617 * lock not needed as this is only incremented in the single
2618 * threaded kernel __init code path all other access are read
2619 * only
2620 */
1b198bb0
MT		 2621 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2622 g_num_of_iommus++;
2623 continue;
2624 }
2625 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2626 IOMMU_UNITS_SUPPORTED);
5e0d2a6f 2627 }
2628
d9630fe9
WH		 2629 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2630 GFP_KERNEL);
2631 if (!g_iommus) {
2632 printk(KERN_ERR "Allocating global iommu array failed\n");
2633 ret = -ENOMEM;
2634 goto error;
2635 }
2636
80b20dd8 2637 deferred_flush = kzalloc(g_num_of_iommus *
2638 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2639 if (!deferred_flush) {
5e0d2a6f 2640 ret = -ENOMEM;
989d51fc 2641 goto free_g_iommus;
5e0d2a6f 2642 }
2643
7c919779 2644 for_each_active_iommu(iommu, drhd) {
d9630fe9 2645 g_iommus[iommu->seq_id] = iommu;
ba395927 2646
e61d98d8
SS		 2647 ret = iommu_init_domains(iommu);
2648 if (ret)
989d51fc 2649 goto free_iommu;
e61d98d8 2650
ba395927
KA		 2651 /*
2652 * TBD:
2653 * we could share the same root & context tables
25985edc 2654 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2655 */
2656 ret = iommu_alloc_root_entry(iommu);
2657 if (ret) {
2658 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
989d51fc 2659 goto free_iommu;
ba395927 2660 }
4ed0d3e6 2661 if (!ecap_pass_through(iommu->ecap))
19943b0e 2662 hw_pass_through = 0;
ba395927
KA		 2663 }
2664
1531a6a6
SS		 2665 /*
2666 * Start from the sane iommu hardware state.
2667 */
7c919779 2668 for_each_active_iommu(iommu, drhd) {
1531a6a6
SS		 2669 /*
2670 * If the queued invalidation is already initialized by us
2671 * (for example, while enabling interrupt-remapping) then
2672 * we got the things already rolling from a sane state.
2673 */
2674 if (iommu->qi)
2675 continue;
2676
2677 /*
2678 * Clear any previous faults.
2679 */
2680 dmar_fault(-1, iommu);
2681 /*
2682 * Disable queued invalidation if supported and already enabled
2683 * before OS handover.
2684 */
2685 dmar_disable_qi(iommu);
2686 }
2687
7c919779 2688 for_each_active_iommu(iommu, drhd) {
a77b67d4
YS		 2689 if (dmar_enable_qi(iommu)) {
2690 /*
2691 * Queued Invalidate not enabled, use Register Based
2692 * Invalidate
2693 */
2694 iommu->flush.flush_context = __iommu_flush_context;
2695 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2696 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2697 "invalidation\n",
680a7524 2698 iommu->seq_id,
b4e0f9eb 2699 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2700 } else {
2701 iommu->flush.flush_context = qi_flush_context;
2702 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2703 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2704 "invalidation\n",
680a7524 2705 iommu->seq_id,
b4e0f9eb 2706 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2707 }
2708 }
2709
19943b0e 2710 if (iommu_pass_through)
e0fc7e0b
DW		 2711 iommu_identity_mapping |= IDENTMAP_ALL;
2712
d3f13810 2713#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2714 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2715#endif
e0fc7e0b
DW		 2716
2717 check_tylersburg_isoch();
2718
ba395927 2719 /*
19943b0e
DW		 2720 * If pass through is not set or not enabled, setup context entries for
2721 * identity mappings for rmrr, gfx, and isa and may fall back to static
2722 * identity mapping if iommu_identity_mapping is set.
ba395927 2723 */
19943b0e
DW		 2724 if (iommu_identity_mapping) {
2725 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2726 if (ret) {
19943b0e 2727 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
989d51fc 2728 goto free_iommu;
ba395927
KA		 2729 }
2730 }
ba395927 2731 /*
19943b0e
DW		 2732 * For each rmrr
2733 * for each dev attached to rmrr
2734 * do
2735 * locate drhd for dev, alloc domain for dev
2736 * allocate free domain
2737 * allocate page table entries for rmrr
2738 * if context not allocated for bus
2739 * allocate and init context
2740 * set present in root table for this bus
2741 * init context with domain, translation etc
2742 * endfor
2743 * endfor
ba395927 2744 */
19943b0e
DW		 2745 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2746 for_each_rmrr_units(rmrr) {
b683b230
JL		 2747 /* some BIOS lists non-exist devices in DMAR table. */
2748 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
2749 i, pdev) {
19943b0e
DW		 2750 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2751 if (ret)
2752 printk(KERN_ERR
2753 "IOMMU: mapping reserved region failed\n");
ba395927 2754 }
4ed0d3e6 2755 }
49a0429e 2756
19943b0e
DW		 2757 iommu_prepare_isa();
2758
ba395927
KA		 2759 /*
2760 * for each drhd
2761 * enable fault log
2762 * global invalidate context cache
2763 * global invalidate iotlb
2764 * enable translation
2765 */
7c919779 2766 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2767 if (drhd->ignored) {
2768 /*
2769 * we always have to disable PMRs or DMA may fail on
2770 * this device
2771 */
2772 if (force_on)
7c919779 2773 iommu_disable_protect_mem_regions(iommu);
ba395927 2774 continue;
51a63e67 2775 }
ba395927
KA		 2776
2777 iommu_flush_write_buffer(iommu);
2778
3460a6d9
KA		 2779 ret = dmar_set_interrupt(iommu);
2780 if (ret)
989d51fc 2781 goto free_iommu;
3460a6d9 2782
ba395927
KA		 2783 iommu_set_root_entry(iommu);
2784
4c25a2c1 2785 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2786 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2787
ba395927
KA		 2788 ret = iommu_enable_translation(iommu);
2789 if (ret)
989d51fc 2790 goto free_iommu;
b94996c9
DW		 2791
2792 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2793 }
2794
2795 return 0;
989d51fc
JL		 2796
2797free_iommu:
7c919779 2798 for_each_active_iommu(iommu, drhd)
a868e6b7 2799 free_dmar_iommu(iommu);
9bdc531e 2800 kfree(deferred_flush);
989d51fc 2801free_g_iommus:
d9630fe9 2802 kfree(g_iommus);
989d51fc 2803error:
ba395927
KA		 2804 return ret;
2805}
2806
5a5e02a6 2807/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2808static struct iova *intel_alloc_iova(struct device *dev,
2809 struct dmar_domain *domain,
2810 unsigned long nrpages, uint64_t dma_mask)
ba395927 2811{
ba395927 2812 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2813 struct iova *iova = NULL;
ba395927 2814
875764de
DW		 2815 /* Restrict dma_mask to the width that the iommu can handle */
2816 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2817
2818 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2819 /*
2820 * First try to allocate an io virtual address in
284901a9 2821 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2822 * from higher range
ba395927 2823 */
875764de
DW		 2824 iova = alloc_iova(&domain->iovad, nrpages,
2825 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2826 if (iova)
2827 return iova;
2828 }
2829 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2830 if (unlikely(!iova)) {
2831 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2832 nrpages, pci_name(pdev));
f76aec76
KA		 2833 return NULL;
2834 }
2835
2836 return iova;
2837}
2838
147202aa 2839static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2840{
2841 struct dmar_domain *domain;
2842 int ret;
2843
2844 domain = get_domain_for_dev(pdev,
2845 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2846 if (!domain) {
2847 printk(KERN_ERR
2848 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2849 return NULL;
ba395927
KA		 2850 }
2851
2852 /* make sure context mapping is ok */
5331fe6f 2853 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2854 ret = domain_context_mapping(domain, pdev,
2855 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2856 if (ret) {
2857 printk(KERN_ERR
2858 "Domain context map for %s failed",
2859 pci_name(pdev));
4fe05bbc 2860 return NULL;
f76aec76 2861 }
ba395927
KA		 2862 }
2863
f76aec76
KA		 2864 return domain;
2865}
2866
147202aa
DW		 2867static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2868{
2869 struct device_domain_info *info;
2870
2871 /* No lock here, assumes no domain exit in normal case */
2872 info = dev->dev.archdata.iommu;
2873 if (likely(info))
2874 return info->domain;
2875
2876 return __get_valid_domain_for_dev(dev);
2877}
2878
2c2e2c38
FY		 2879static int iommu_dummy(struct pci_dev *pdev)
2880{
2881 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2882}
2883
2884/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2885static int iommu_no_mapping(struct device *dev)
2c2e2c38 2886{
73676832 2887 struct pci_dev *pdev;
2c2e2c38
FY		 2888 int found;
2889
dbad0864 2890 if (unlikely(!dev_is_pci(dev)))
73676832
DW		 2891 return 1;
2892
2893 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2894 if (iommu_dummy(pdev))
2895 return 1;
2896
2c2e2c38 2897 if (!iommu_identity_mapping)
1e4c64c4 2898 return 0;
2c2e2c38
FY		 2899
2900 found = identity_mapping(pdev);
2901 if (found) {
6941af28 2902 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2903 return 1;
2904 else {
2905 /*
2906 * 32 bit DMA is removed from si_domain and fall back
2907 * to non-identity mapping.
2908 */
2909 domain_remove_one_dev_info(si_domain, pdev);
2910 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2911 pci_name(pdev));
2912 return 0;
2913 }
2914 } else {
2915 /*
2916 * In case of a detached 64 bit DMA device from vm, the device
2917 * is put into si_domain for identity mapping.
2918 */
6941af28 2919 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2920 int ret;
5fe60f4e
DW		 2921 ret = domain_add_dev_info(si_domain, pdev,
2922 hw_pass_through ?
2923 CONTEXT_TT_PASS_THROUGH :
2924 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2925 if (!ret) {
2926 printk(KERN_INFO "64bit %s uses identity mapping\n",
2927 pci_name(pdev));
2928 return 1;
2929 }
2930 }
2931 }
2932
1e4c64c4 2933 return 0;
2c2e2c38
FY		 2934}
2935
bb9e6d65
FT		 2936static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2937 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2938{
2939 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2940 struct dmar_domain *domain;
5b6985ce 2941 phys_addr_t start_paddr;
f76aec76
KA		 2942 struct iova *iova;
2943 int prot = 0;
6865f0d1 2944 int ret;
8c11e798 2945 struct intel_iommu *iommu;
33041ec0 2946 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2947
2948 BUG_ON(dir == DMA_NONE);
2c2e2c38 2949
73676832 2950 if (iommu_no_mapping(hwdev))
6865f0d1 2951 return paddr;
f76aec76
KA		 2952
2953 domain = get_valid_domain_for_dev(pdev);
2954 if (!domain)
2955 return 0;
2956
8c11e798 2957 iommu = domain_get_iommu(domain);
88cb6a74 2958 size = aligned_nrpages(paddr, size);
f76aec76 2959
c681d0ba 2960 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2961 if (!iova)
2962 goto error;
2963
ba395927
KA		 2964 /*
2965 * Check if DMAR supports zero-length reads on write only
2966 * mappings..
2967 */
2968 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2969 !cap_zlr(iommu->cap))
ba395927
KA		 2970 prot |= DMA_PTE_READ;
2971 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2972 prot |= DMA_PTE_WRITE;
2973 /*
6865f0d1 2974 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2975 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2976 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2977 * is not a big problem
2978 */
0ab36de2 2979 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2980 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2981 if (ret)
2982 goto error;
2983
1f0ef2aa
DW		 2984 /* it's a non-present to present mapping. Only flush if caching mode */
2985 if (cap_caching_mode(iommu->cap))
ea8ea460 2986 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 2987 else
8c11e798 2988 iommu_flush_write_buffer(iommu);
f76aec76 2989
03d6a246
DW		 2990 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2991 start_paddr += paddr & ~PAGE_MASK;
2992 return start_paddr;
ba395927 2993
ba395927 2994error:
f76aec76
KA		 2995 if (iova)
2996 __free_iova(&domain->iovad, iova);
4cf2e75d 2997 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2998 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2999 return 0;
3000}
3001
ffbbef5c
FT		 3002static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3003 unsigned long offset, size_t size,
3004 enum dma_data_direction dir,
3005 struct dma_attrs *attrs)
bb9e6d65 3006{
ffbbef5c
FT		 3007 return __intel_map_single(dev, page_to_phys(page) + offset, size,
3008 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 3009}
3010
5e0d2a6f 3011static void flush_unmaps(void)
3012{
80b20dd8 3013 int i, j;
5e0d2a6f 3014
5e0d2a6f 3015 timer_on = 0;
3016
3017 /* just flush them all */
3018 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3019 struct intel_iommu *iommu = g_iommus[i];
3020 if (!iommu)
3021 continue;
c42d9f32 3022
9dd2fe89
YZ		 3023 if (!deferred_flush[i].next)
3024 continue;
3025
78d5f0f5
NA		 3026 /* In caching mode, global flushes turn emulation expensive */
3027 if (!cap_caching_mode(iommu->cap))
3028 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3029 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3030 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3031 unsigned long mask;
3032 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3033 struct dmar_domain *domain = deferred_flush[i].domain[j];
3034
3035 /* On real hardware multiple invalidations are expensive */
3036 if (cap_caching_mode(iommu->cap))
3037 iommu_flush_iotlb_psi(iommu, domain->id,
ea8ea460
DW		 3038 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1,
3039 !deferred_flush[i].freelist[j], 0);
78d5f0f5
NA		 3040 else {
3041 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
3042 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3043 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3044 }
93a23a72 3045 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3046 if (deferred_flush[i].freelist[j])
3047 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3048 }
9dd2fe89 3049 deferred_flush[i].next = 0;
5e0d2a6f 3050 }
3051
5e0d2a6f 3052 list_size = 0;
5e0d2a6f 3053}
3054
3055static void flush_unmaps_timeout(unsigned long data)
3056{
80b20dd8 3057 unsigned long flags;
3058
3059 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3060 flush_unmaps();
80b20dd8 3061 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3062}
3063
ea8ea460 3064static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3065{
3066 unsigned long flags;
80b20dd8 3067 int next, iommu_id;
8c11e798 3068 struct intel_iommu *iommu;
5e0d2a6f 3069
3070 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3071 if (list_size == HIGH_WATER_MARK)
3072 flush_unmaps();
3073
8c11e798
WH		 3074 iommu = domain_get_iommu(dom);
3075 iommu_id = iommu->seq_id;
c42d9f32 3076
80b20dd8 3077 next = deferred_flush[iommu_id].next;
3078 deferred_flush[iommu_id].domain[next] = dom;
3079 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3080 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3081 deferred_flush[iommu_id].next++;
5e0d2a6f 3082
3083 if (!timer_on) {
3084 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3085 timer_on = 1;
3086 }
3087 list_size++;
3088 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3089}
3090
ffbbef5c
FT		 3091static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3092 size_t size, enum dma_data_direction dir,
3093 struct dma_attrs *attrs)
ba395927 3094{
ba395927 3095 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 3096 struct dmar_domain *domain;
d794dc9b 3097 unsigned long start_pfn, last_pfn;
ba395927 3098 struct iova *iova;
8c11e798 3099 struct intel_iommu *iommu;
ea8ea460 3100 struct page *freelist;
ba395927 3101
73676832 3102 if (iommu_no_mapping(dev))
f76aec76 3103 return;
2c2e2c38 3104
ba395927
KA		 3105 domain = find_domain(pdev);
3106 BUG_ON(!domain);
3107
8c11e798
WH		 3108 iommu = domain_get_iommu(domain);
3109
ba395927 3110 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3111 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3112 (unsigned long long)dev_addr))
ba395927 3113 return;
ba395927 3114
d794dc9b
DW		 3115 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3116 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3117
d794dc9b
DW		 3118 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3119 pci_name(pdev), start_pfn, last_pfn);
ba395927 3120
ea8ea460 3121 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3122
5e0d2a6f 3123 if (intel_iommu_strict) {
03d6a246 3124 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3125 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3126 /* free iova */
3127 __free_iova(&domain->iovad, iova);
ea8ea460 3128 dma_free_pagelist(freelist);
5e0d2a6f 3129 } else {
ea8ea460 3130 add_unmap(domain, iova, freelist);
5e0d2a6f 3131 /*
3132 * queue up the release of the unmap to save the 1/6th of the
3133 * cpu used up by the iotlb flush operation...
3134 */
5e0d2a6f 3135 }
ba395927
KA		 3136}
3137
d7ab5c46 3138static void *intel_alloc_coherent(struct device *hwdev, size_t size,
baa676fc
AP		 3139 dma_addr_t *dma_handle, gfp_t flags,
3140 struct dma_attrs *attrs)
ba395927
KA		 3141{
3142 void *vaddr;
3143 int order;
3144
5b6985ce 3145 size = PAGE_ALIGN(size);
ba395927 3146 order = get_order(size);
e8bb910d
AW		 3147
3148 if (!iommu_no_mapping(hwdev))
3149 flags &= ~(GFP_DMA | GFP_DMA32);
3150 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
3151 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
3152 flags |= GFP_DMA;
3153 else
3154 flags |= GFP_DMA32;
3155 }
ba395927
KA		 3156
3157 vaddr = (void *)__get_free_pages(flags, order);
3158 if (!vaddr)
3159 return NULL;
3160 memset(vaddr, 0, size);
3161
bb9e6d65
FT		 3162 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
3163 DMA_BIDIRECTIONAL,
3164 hwdev->coherent_dma_mask);
ba395927
KA		 3165 if (*dma_handle)
3166 return vaddr;
3167 free_pages((unsigned long)vaddr, order);
3168 return NULL;
3169}
3170
d7ab5c46 3171static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
baa676fc 3172 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3173{
3174 int order;
3175
5b6985ce 3176 size = PAGE_ALIGN(size);
ba395927
KA		 3177 order = get_order(size);
3178
0db9b7ae 3179 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 3180 free_pages((unsigned long)vaddr, order);
3181}
3182
d7ab5c46
FT		 3183static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
3184 int nelems, enum dma_data_direction dir,
3185 struct dma_attrs *attrs)
ba395927 3186{
ba395927
KA		 3187 struct pci_dev *pdev = to_pci_dev(hwdev);
3188 struct dmar_domain *domain;
d794dc9b 3189 unsigned long start_pfn, last_pfn;
f76aec76 3190 struct iova *iova;
8c11e798 3191 struct intel_iommu *iommu;
ea8ea460 3192 struct page *freelist;
ba395927 3193
73676832 3194 if (iommu_no_mapping(hwdev))
ba395927
KA		 3195 return;
3196
3197 domain = find_domain(pdev);
8c11e798
WH		 3198 BUG_ON(!domain);
3199
3200 iommu = domain_get_iommu(domain);
ba395927 3201
c03ab37c 3202 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 3203 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
3204 (unsigned long long)sglist[0].dma_address))
f76aec76 3205 return;
f76aec76 3206
d794dc9b
DW		 3207 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3208 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76 3209
ea8ea460 3210 freelist = domain_unmap(domain, start_pfn, last_pfn);
f76aec76 3211
acea0018
DW		 3212 if (intel_iommu_strict) {
3213 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3214 last_pfn - start_pfn + 1, !freelist, 0);
acea0018
DW		 3215 /* free iova */
3216 __free_iova(&domain->iovad, iova);
ea8ea460 3217 dma_free_pagelist(freelist);
acea0018 3218 } else {
ea8ea460 3219 add_unmap(domain, iova, freelist);
acea0018
DW		 3220 /*
3221 * queue up the release of the unmap to save the 1/6th of the
3222 * cpu used up by the iotlb flush operation...
3223 */
3224 }
ba395927
KA		 3225}
3226
ba395927 3227static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3228 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3229{
3230 int i;
c03ab37c 3231 struct scatterlist *sg;
ba395927 3232
c03ab37c 3233 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3234 BUG_ON(!sg_page(sg));
4cf2e75d 3235 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3236 sg->dma_length = sg->length;
ba395927
KA		 3237 }
3238 return nelems;
3239}
3240
d7ab5c46
FT		 3241static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3242 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3243{
ba395927 3244 int i;
ba395927
KA		 3245 struct pci_dev *pdev = to_pci_dev(hwdev);
3246 struct dmar_domain *domain;
f76aec76
KA		 3247 size_t size = 0;
3248 int prot = 0;
f76aec76
KA		 3249 struct iova *iova = NULL;
3250 int ret;
c03ab37c 3251 struct scatterlist *sg;
b536d24d 3252 unsigned long start_vpfn;
8c11e798 3253 struct intel_iommu *iommu;
ba395927
KA		 3254
3255 BUG_ON(dir == DMA_NONE);
73676832 3256 if (iommu_no_mapping(hwdev))
c03ab37c 3257 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 3258
f76aec76
KA		 3259 domain = get_valid_domain_for_dev(pdev);
3260 if (!domain)
3261 return 0;
3262
8c11e798
WH		 3263 iommu = domain_get_iommu(domain);
3264
b536d24d 3265 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3266 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3267
5a5e02a6
DW		 3268 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3269 pdev->dma_mask);
f76aec76 3270 if (!iova) {
c03ab37c 3271 sglist->dma_length = 0;
f76aec76
KA		 3272 return 0;
3273 }
3274
3275 /*
3276 * Check if DMAR supports zero-length reads on write only
3277 * mappings..
3278 */
3279 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3280 !cap_zlr(iommu->cap))
f76aec76
KA		 3281 prot |= DMA_PTE_READ;
3282 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3283 prot |= DMA_PTE_WRITE;
3284
b536d24d 3285 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3286
f532959b 3287 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3288 if (unlikely(ret)) {
3289 /* clear the page */
3290 dma_pte_clear_range(domain, start_vpfn,
3291 start_vpfn + size - 1);
3292 /* free page tables */
3293 dma_pte_free_pagetable(domain, start_vpfn,
3294 start_vpfn + size - 1);
3295 /* free iova */
3296 __free_iova(&domain->iovad, iova);
3297 return 0;
ba395927
KA		 3298 }
3299
1f0ef2aa
DW		 3300 /* it's a non-present to present mapping. Only flush if caching mode */
3301 if (cap_caching_mode(iommu->cap))
ea8ea460 3302 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3303 else
8c11e798 3304 iommu_flush_write_buffer(iommu);
1f0ef2aa 3305
ba395927
KA		 3306 return nelems;
3307}
3308
dfb805e8
FT		 3309static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3310{
3311 return !dma_addr;
3312}
3313
160c1d8e 3314struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3315 .alloc = intel_alloc_coherent,
3316 .free = intel_free_coherent,
ba395927
KA		 3317 .map_sg = intel_map_sg,
3318 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3319 .map_page = intel_map_page,
3320 .unmap_page = intel_unmap_page,
dfb805e8 3321 .mapping_error = intel_mapping_error,
ba395927
KA		 3322};
3323
3324static inline int iommu_domain_cache_init(void)
3325{
3326 int ret = 0;
3327
3328 iommu_domain_cache = kmem_cache_create("iommu_domain",
3329 sizeof(struct dmar_domain),
3330 0,
3331 SLAB_HWCACHE_ALIGN,
3332
3333 NULL);
3334 if (!iommu_domain_cache) {
3335 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3336 ret = -ENOMEM;
3337 }
3338
3339 return ret;
3340}
3341
3342static inline int iommu_devinfo_cache_init(void)
3343{
3344 int ret = 0;
3345
3346 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3347 sizeof(struct device_domain_info),
3348 0,
3349 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3350 NULL);
3351 if (!iommu_devinfo_cache) {
3352 printk(KERN_ERR "Couldn't create devinfo cache\n");
3353 ret = -ENOMEM;
3354 }
3355
3356 return ret;
3357}
3358
3359static inline int iommu_iova_cache_init(void)
3360{
3361 int ret = 0;
3362
3363 iommu_iova_cache = kmem_cache_create("iommu_iova",
3364 sizeof(struct iova),
3365 0,
3366 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3367 NULL);
3368 if (!iommu_iova_cache) {
3369 printk(KERN_ERR "Couldn't create iova cache\n");
3370 ret = -ENOMEM;
3371 }
3372
3373 return ret;
3374}
3375
3376static int __init iommu_init_mempool(void)
3377{
3378 int ret;
3379 ret = iommu_iova_cache_init();
3380 if (ret)
3381 return ret;
3382
3383 ret = iommu_domain_cache_init();
3384 if (ret)
3385 goto domain_error;
3386
3387 ret = iommu_devinfo_cache_init();
3388 if (!ret)
3389 return ret;
3390
3391 kmem_cache_destroy(iommu_domain_cache);
3392domain_error:
3393 kmem_cache_destroy(iommu_iova_cache);
3394
3395 return -ENOMEM;
3396}
3397
3398static void __init iommu_exit_mempool(void)
3399{
3400 kmem_cache_destroy(iommu_devinfo_cache);
3401 kmem_cache_destroy(iommu_domain_cache);
3402 kmem_cache_destroy(iommu_iova_cache);
3403
3404}
3405
556ab45f
DW		 3406static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3407{
3408 struct dmar_drhd_unit *drhd;
3409 u32 vtbar;
3410 int rc;
3411
3412 /* We know that this device on this chipset has its own IOMMU.
3413 * If we find it under a different IOMMU, then the BIOS is lying
3414 * to us. Hope that the IOMMU for this device is actually
3415 * disabled, and it needs no translation...
3416 */
3417 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3418 if (rc) {
3419 /* "can't" happen */
3420 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3421 return;
3422 }
3423 vtbar &= 0xffff0000;
3424
3425 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3426 drhd = dmar_find_matched_drhd_unit(pdev);
3427 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3428 TAINT_FIRMWARE_WORKAROUND,
3429 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3430 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3431}
3432DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3433
ba395927
KA		 3434static void __init init_no_remapping_devices(void)
3435{
3436 struct dmar_drhd_unit *drhd;
b683b230
JL		 3437 struct pci_dev *dev;
3438 int i;
ba395927
KA		 3439
3440 for_each_drhd_unit(drhd) {
3441 if (!drhd->include_all) {
b683b230
JL		 3442 for_each_active_dev_scope(drhd->devices,
3443 drhd->devices_cnt, i, dev)
3444 break;
ba395927
KA		 3445 /* ignore DMAR unit if no pci devices exist */
3446 if (i == drhd->devices_cnt)
3447 drhd->ignored = 1;
3448 }
3449 }
3450
7c919779 3451 for_each_active_drhd_unit(drhd) {
7c919779 3452 if (drhd->include_all)
ba395927
KA		 3453 continue;
3454
b683b230
JL		 3455 for_each_active_dev_scope(drhd->devices,
3456 drhd->devices_cnt, i, dev)
3457 if (!IS_GFX_DEVICE(dev))
ba395927 3458 break;
ba395927
KA		 3459 if (i < drhd->devices_cnt)
3460 continue;
3461
c0771df8
DW		 3462 /* This IOMMU has *only* gfx devices. Either bypass it or
3463 set the gfx_mapped flag, as appropriate */
3464 if (dmar_map_gfx) {
3465 intel_iommu_gfx_mapped = 1;
3466 } else {
3467 drhd->ignored = 1;
b683b230
JL		 3468 for_each_active_dev_scope(drhd->devices,
3469 drhd->devices_cnt, i, dev)
3470 dev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3471 }
3472 }
3473}
3474
f59c7b69
FY		 3475#ifdef CONFIG_SUSPEND
3476static int init_iommu_hw(void)
3477{
3478 struct dmar_drhd_unit *drhd;
3479 struct intel_iommu *iommu = NULL;
3480
3481 for_each_active_iommu(iommu, drhd)
3482 if (iommu->qi)
3483 dmar_reenable_qi(iommu);
3484
b779260b
JC		 3485 for_each_iommu(iommu, drhd) {
3486 if (drhd->ignored) {
3487 /*
3488 * we always have to disable PMRs or DMA may fail on
3489 * this device
3490 */
3491 if (force_on)
3492 iommu_disable_protect_mem_regions(iommu);
3493 continue;
3494 }
3495
f59c7b69
FY		 3496 iommu_flush_write_buffer(iommu);
3497
3498 iommu_set_root_entry(iommu);
3499
3500 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3501 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3502 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3503 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3504 if (iommu_enable_translation(iommu))
3505 return 1;
b94996c9 3506 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3507 }
3508
3509 return 0;
3510}
3511
3512static void iommu_flush_all(void)
3513{
3514 struct dmar_drhd_unit *drhd;
3515 struct intel_iommu *iommu;
3516
3517 for_each_active_iommu(iommu, drhd) {
3518 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3519 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3520 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3521 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3522 }
3523}
3524
134fac3f 3525static int iommu_suspend(void)
f59c7b69
FY		 3526{
3527 struct dmar_drhd_unit *drhd;
3528 struct intel_iommu *iommu = NULL;
3529 unsigned long flag;
3530
3531 for_each_active_iommu(iommu, drhd) {
3532 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3533 GFP_ATOMIC);
3534 if (!iommu->iommu_state)
3535 goto nomem;
3536 }
3537
3538 iommu_flush_all();
3539
3540 for_each_active_iommu(iommu, drhd) {
3541 iommu_disable_translation(iommu);
3542
1f5b3c3f 3543 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3544
3545 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3546 readl(iommu->reg + DMAR_FECTL_REG);
3547 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3548 readl(iommu->reg + DMAR_FEDATA_REG);
3549 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3550 readl(iommu->reg + DMAR_FEADDR_REG);
3551 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3552 readl(iommu->reg + DMAR_FEUADDR_REG);
3553
1f5b3c3f 3554 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3555 }
3556 return 0;
3557
3558nomem:
3559 for_each_active_iommu(iommu, drhd)
3560 kfree(iommu->iommu_state);
3561
3562 return -ENOMEM;
3563}
3564
134fac3f 3565static void iommu_resume(void)
f59c7b69
FY		 3566{
3567 struct dmar_drhd_unit *drhd;
3568 struct intel_iommu *iommu = NULL;
3569 unsigned long flag;
3570
3571 if (init_iommu_hw()) {
b779260b
JC		 3572 if (force_on)
3573 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3574 else
3575 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3576 return;
f59c7b69
FY		 3577 }
3578
3579 for_each_active_iommu(iommu, drhd) {
3580
1f5b3c3f 3581 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3582
3583 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3584 iommu->reg + DMAR_FECTL_REG);
3585 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3586 iommu->reg + DMAR_FEDATA_REG);
3587 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3588 iommu->reg + DMAR_FEADDR_REG);
3589 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3590 iommu->reg + DMAR_FEUADDR_REG);
3591
1f5b3c3f 3592 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3593 }
3594
3595 for_each_active_iommu(iommu, drhd)
3596 kfree(iommu->iommu_state);
f59c7b69
FY		 3597}
3598
134fac3f 3599static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3600 .resume = iommu_resume,
3601 .suspend = iommu_suspend,
3602};
3603
134fac3f 3604static void __init init_iommu_pm_ops(void)
f59c7b69 3605{
134fac3f 3606 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3607}
3608
3609#else
99592ba4 3610static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3611#endif /* CONFIG_PM */
3612
318fe7df
SS		 3613
3614int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3615{
3616 struct acpi_dmar_reserved_memory *rmrr;
3617 struct dmar_rmrr_unit *rmrru;
3618
3619 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3620 if (!rmrru)
3621 return -ENOMEM;
3622
3623 rmrru->hdr = header;
3624 rmrr = (struct acpi_dmar_reserved_memory *)header;
3625 rmrru->base_address = rmrr->base_address;
3626 rmrru->end_address = rmrr->end_address;
2e455289
JL		 3627 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3628 ((void *)rmrr) + rmrr->header.length,
3629 &rmrru->devices_cnt);
3630 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3631 kfree(rmrru);
3632 return -ENOMEM;
3633 }
318fe7df 3634
2e455289 3635 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 3636
2e455289 3637 return 0;
318fe7df
SS		 3638}
3639
318fe7df
SS		 3640int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3641{
3642 struct acpi_dmar_atsr *atsr;
3643 struct dmar_atsr_unit *atsru;
3644
3645 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3646 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3647 if (!atsru)
3648 return -ENOMEM;
3649
3650 atsru->hdr = hdr;
3651 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 3652 if (!atsru->include_all) {
3653 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3654 (void *)atsr + atsr->header.length,
3655 &atsru->devices_cnt);
3656 if (atsru->devices_cnt && atsru->devices == NULL) {
3657 kfree(atsru);
3658 return -ENOMEM;
3659 }
3660 }
318fe7df 3661
0e242612 3662 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 3663
3664 return 0;
3665}
3666
9bdc531e
JL		 3667static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3668{
3669 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3670 kfree(atsru);
3671}
3672
3673static void intel_iommu_free_dmars(void)
3674{
3675 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3676 struct dmar_atsr_unit *atsru, *atsr_n;
3677
3678 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3679 list_del(&rmrru->list);
3680 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3681 kfree(rmrru);
318fe7df
SS		 3682 }
3683
9bdc531e
JL		 3684 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3685 list_del(&atsru->list);
3686 intel_iommu_free_atsr(atsru);
3687 }
318fe7df
SS		 3688}
3689
3690int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3691{
b683b230 3692 int i, ret = 1;
318fe7df 3693 struct pci_bus *bus;
b683b230 3694 struct pci_dev *bridge = NULL, *tmp;
318fe7df
SS		 3695 struct acpi_dmar_atsr *atsr;
3696 struct dmar_atsr_unit *atsru;
3697
3698 dev = pci_physfn(dev);
318fe7df 3699 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 3700 bridge = bus->self;
318fe7df 3701 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3702 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 3703 return 0;
b5f82ddf 3704 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 3705 break;
318fe7df 3706 }
b5f82ddf
JL		 3707 if (!bridge)
3708 return 0;
318fe7df 3709
0e242612 3710 rcu_read_lock();
b5f82ddf
JL		 3711 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3712 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3713 if (atsr->segment != pci_domain_nr(dev->bus))
3714 continue;
3715
b683b230
JL		 3716 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
3717 if (tmp == bridge)
3718 goto out;
b5f82ddf
JL		 3719
3720 if (atsru->include_all)
b683b230 3721 goto out;
b5f82ddf 3722 }
b683b230
JL		 3723 ret = 0;
3724out:
0e242612 3725 rcu_read_unlock();
318fe7df 3726
b683b230 3727 return ret;
318fe7df
SS		 3728}
3729
59ce0515
JL		 3730int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3731{
3732 int ret = 0;
3733 struct dmar_rmrr_unit *rmrru;
3734 struct dmar_atsr_unit *atsru;
3735 struct acpi_dmar_atsr *atsr;
3736 struct acpi_dmar_reserved_memory *rmrr;
3737
3738 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3739 return 0;
3740
3741 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3742 rmrr = container_of(rmrru->hdr,
3743 struct acpi_dmar_reserved_memory, header);
3744 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3745 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3746 ((void *)rmrr) + rmrr->header.length,
3747 rmrr->segment, rmrru->devices,
3748 rmrru->devices_cnt);
3749 if (ret > 0)
3750 break;
3751 else if(ret < 0)
3752 return ret;
3753 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3754 if (dmar_remove_dev_scope(info, rmrr->segment,
3755 rmrru->devices, rmrru->devices_cnt))
3756 break;
3757 }
3758 }
3759
3760 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3761 if (atsru->include_all)
3762 continue;
3763
3764 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3765 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3766 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
3767 (void *)atsr + atsr->header.length,
3768 atsr->segment, atsru->devices,
3769 atsru->devices_cnt);
3770 if (ret > 0)
3771 break;
3772 else if(ret < 0)
3773 return ret;
3774 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3775 if (dmar_remove_dev_scope(info, atsr->segment,
3776 atsru->devices, atsru->devices_cnt))
3777 break;
3778 }
3779 }
3780
3781 return 0;
3782}
3783
99dcaded
FY		 3784/*
3785 * Here we only respond to action of unbound device from driver.
3786 *
3787 * Added device is not attached to its DMAR domain here yet. That will happen
3788 * when mapping the device to iova.
3789 */
3790static int device_notifier(struct notifier_block *nb,
3791 unsigned long action, void *data)
3792{
3793 struct device *dev = data;
3794 struct pci_dev *pdev = to_pci_dev(dev);
3795 struct dmar_domain *domain;
3796
816997d0 3797 if (iommu_dummy(pdev))
44cd613c
DW		 3798 return 0;
3799
7e7dfab7
JL		 3800 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3801 action != BUS_NOTIFY_DEL_DEVICE)
3802 return 0;
3803
99dcaded
FY		 3804 domain = find_domain(pdev);
3805 if (!domain)
3806 return 0;
3807
3a5670e8 3808 down_read(&dmar_global_lock);
7e7dfab7
JL		 3809 domain_remove_one_dev_info(domain, pdev);
3810 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3811 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3812 list_empty(&domain->devices))
3813 domain_exit(domain);
3a5670e8 3814 up_read(&dmar_global_lock);
a97590e5 3815
99dcaded
FY		 3816 return 0;
3817}
3818
3819static struct notifier_block device_nb = {
3820 .notifier_call = device_notifier,
3821};
3822
75f05569
JL		 3823static int intel_iommu_memory_notifier(struct notifier_block *nb,
3824 unsigned long val, void *v)
3825{
3826 struct memory_notify *mhp = v;
3827 unsigned long long start, end;
3828 unsigned long start_vpfn, last_vpfn;
3829
3830 switch (val) {
3831 case MEM_GOING_ONLINE:
3832 start = mhp->start_pfn << PAGE_SHIFT;
3833 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
3834 if (iommu_domain_identity_map(si_domain, start, end)) {
3835 pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
3836 start, end);
3837 return NOTIFY_BAD;
3838 }
3839 break;
3840
3841 case MEM_OFFLINE:
3842 case MEM_CANCEL_ONLINE:
3843 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
3844 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
3845 while (start_vpfn <= last_vpfn) {
3846 struct iova *iova;
3847 struct dmar_drhd_unit *drhd;
3848 struct intel_iommu *iommu;
ea8ea460 3849 struct page *freelist;
75f05569
JL		 3850
3851 iova = find_iova(&si_domain->iovad, start_vpfn);
3852 if (iova == NULL) {
3853 pr_debug("dmar: failed get IOVA for PFN %lx\n",
3854 start_vpfn);
3855 break;
3856 }
3857
3858 iova = split_and_remove_iova(&si_domain->iovad, iova,
3859 start_vpfn, last_vpfn);
3860 if (iova == NULL) {
3861 pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
3862 start_vpfn, last_vpfn);
3863 return NOTIFY_BAD;
3864 }
3865
ea8ea460
DW		 3866 freelist = domain_unmap(si_domain, iova->pfn_lo,
3867 iova->pfn_hi);
3868
75f05569
JL		 3869 rcu_read_lock();
3870 for_each_active_iommu(iommu, drhd)
3871 iommu_flush_iotlb_psi(iommu, si_domain->id,
3872 iova->pfn_lo,
ea8ea460
DW		 3873 iova->pfn_hi - iova->pfn_lo + 1,
3874 !freelist, 0);
75f05569 3875 rcu_read_unlock();
ea8ea460 3876 dma_free_pagelist(freelist);
75f05569
JL		 3877
3878 start_vpfn = iova->pfn_hi + 1;
3879 free_iova_mem(iova);
3880 }
3881 break;
3882 }
3883
3884 return NOTIFY_OK;
3885}
3886
3887static struct notifier_block intel_iommu_memory_nb = {
3888 .notifier_call = intel_iommu_memory_notifier,
3889 .priority = 0
3890};
3891
ba395927
KA		 3892int __init intel_iommu_init(void)
3893{
9bdc531e 3894 int ret = -ENODEV;
3a93c841 3895 struct dmar_drhd_unit *drhd;
7c919779 3896 struct intel_iommu *iommu;
ba395927 3897
a59b50e9
JC		 3898 /* VT-d is required for a TXT/tboot launch, so enforce that */
3899 force_on = tboot_force_iommu();
3900
3a5670e8
JL		 3901 if (iommu_init_mempool()) {
3902 if (force_on)
3903 panic("tboot: Failed to initialize iommu memory\n");
3904 return -ENOMEM;
3905 }
3906
3907 down_write(&dmar_global_lock);
a59b50e9
JC		 3908 if (dmar_table_init()) {
3909 if (force_on)
3910 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 3911 goto out_free_dmar;
a59b50e9 3912 }
ba395927 3913
3a93c841
TI		 3914 /*
3915 * Disable translation if already enabled prior to OS handover.
3916 */
7c919779 3917 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 3918 if (iommu->gcmd & DMA_GCMD_TE)
3919 iommu_disable_translation(iommu);
3a93c841 3920
c2c7286a 3921 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 3922 if (force_on)
3923 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 3924 goto out_free_dmar;
a59b50e9 3925 }
1886e8a9 3926
75f1cdf1 3927 if (no_iommu || dmar_disabled)
9bdc531e 3928 goto out_free_dmar;
2ae21010 3929
318fe7df
SS		 3930 if (list_empty(&dmar_rmrr_units))
3931 printk(KERN_INFO "DMAR: No RMRR found\n");
3932
3933 if (list_empty(&dmar_atsr_units))
3934 printk(KERN_INFO "DMAR: No ATSR found\n");
3935
51a63e67
JC		 3936 if (dmar_init_reserved_ranges()) {
3937 if (force_on)
3938 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 3939 goto out_free_reserved_range;
51a63e67 3940 }
ba395927
KA		 3941
3942 init_no_remapping_devices();
3943
b779260b 3944 ret = init_dmars();
ba395927 3945 if (ret) {
a59b50e9
JC		 3946 if (force_on)
3947 panic("tboot: Failed to initialize DMARs\n");
ba395927 3948 printk(KERN_ERR "IOMMU: dmar init failed\n");
9bdc531e 3949 goto out_free_reserved_range;
ba395927 3950 }
3a5670e8 3951 up_write(&dmar_global_lock);
ba395927
KA		 3952 printk(KERN_INFO
3953 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3954
5e0d2a6f 3955 init_timer(&unmap_timer);
75f1cdf1
FT		 3956#ifdef CONFIG_SWIOTLB
3957 swiotlb = 0;
3958#endif
19943b0e 3959 dma_ops = &intel_dma_ops;
4ed0d3e6 3960
134fac3f 3961 init_iommu_pm_ops();
a8bcbb0d 3962
4236d97d 3963 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 3964 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 3965 if (si_domain && !hw_pass_through)
3966 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 3967
8bc1f85c
ED		 3968 intel_iommu_enabled = 1;
3969
ba395927 3970 return 0;
9bdc531e
JL		 3971
3972out_free_reserved_range:
3973 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 3974out_free_dmar:
3975 intel_iommu_free_dmars();
3a5670e8
JL		 3976 up_write(&dmar_global_lock);
3977 iommu_exit_mempool();
9bdc531e 3978 return ret;
ba395927 3979}
e820482c 3980
3199aa6b
HW		 3981static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3982 struct pci_dev *pdev)
3983{
3984 struct pci_dev *tmp, *parent;
3985
3986 if (!iommu || !pdev)
3987 return;
3988
3989 /* dependent device detach */
3990 tmp = pci_find_upstream_pcie_bridge(pdev);
3991 /* Secondary interface's bus number and devfn 0 */
3992 if (tmp) {
3993 parent = pdev->bus->self;
3994 while (parent != tmp) {
3995 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3996 parent->devfn);
3199aa6b
HW		 3997 parent = parent->bus->self;
3998 }
45e829ea 3999 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 4000 iommu_detach_dev(iommu,
4001 tmp->subordinate->number, 0);
4002 else /* this is a legacy PCI bridge */
276dbf99
DW		 4003 iommu_detach_dev(iommu, tmp->bus->number,
4004 tmp->devfn);
3199aa6b
HW		 4005 }
4006}
4007
2c2e2c38 4008static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 4009 struct pci_dev *pdev)
4010{
bca2b916 4011 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4012 struct intel_iommu *iommu;
4013 unsigned long flags;
4014 int found = 0;
c7151a8d 4015
276dbf99
DW		 4016 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4017 pdev->devfn);
c7151a8d
WH		 4018 if (!iommu)
4019 return;
4020
4021 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4022 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
8519dc44
MH		 4023 if (info->segment == pci_domain_nr(pdev->bus) &&
4024 info->bus == pdev->bus->number &&
c7151a8d 4025 info->devfn == pdev->devfn) {
109b9b04 4026 unlink_domain_info(info);
c7151a8d
WH		 4027 spin_unlock_irqrestore(&device_domain_lock, flags);
4028
93a23a72 4029 iommu_disable_dev_iotlb(info);
c7151a8d 4030 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 4031 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 4032 free_devinfo_mem(info);
4033
4034 spin_lock_irqsave(&device_domain_lock, flags);
4035
4036 if (found)
4037 break;
4038 else
4039 continue;
4040 }
4041
4042 /* if there is no other devices under the same iommu
4043 * owned by this domain, clear this iommu in iommu_bmp
4044 * update iommu count and coherency
4045 */
276dbf99
DW		 4046 if (iommu == device_to_iommu(info->segment, info->bus,
4047 info->devfn))
c7151a8d
WH		 4048 found = 1;
4049 }
4050
3e7abe25
RD		 4051 spin_unlock_irqrestore(&device_domain_lock, flags);
4052
c7151a8d
WH		 4053 if (found == 0) {
4054 unsigned long tmp_flags;
4055 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
1b198bb0 4056 clear_bit(iommu->seq_id, domain->iommu_bmp);
c7151a8d 4057 domain->iommu_count--;
58c610bd 4058 domain_update_iommu_cap(domain);
c7151a8d 4059 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 4060
9b4554b2
AW		 4061 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
4062 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
4063 spin_lock_irqsave(&iommu->lock, tmp_flags);
4064 clear_bit(domain->id, iommu->domain_ids);
4065 iommu->domains[domain->id] = NULL;
4066 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
4067 }
c7151a8d 4068 }
c7151a8d
WH		 4069}
4070
2c2e2c38 4071static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4072{
4073 int adjust_width;
4074
4075 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 4076 domain_reserve_special_ranges(domain);
4077
4078 /* calculate AGAW */
4079 domain->gaw = guest_width;
4080 adjust_width = guestwidth_to_adjustwidth(guest_width);
4081 domain->agaw = width_to_agaw(adjust_width);
4082
5e98c4b1 4083 domain->iommu_coherency = 0;
c5b15255 4084 domain->iommu_snooping = 0;
6dd9a7c7 4085 domain->iommu_superpage = 0;
fe40f1e0 4086 domain->max_addr = 0;
4c923d47 4087 domain->nid = -1;
5e98c4b1
WH		 4088
4089 /* always allocate the top pgd */
4c923d47 4090 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4091 if (!domain->pgd)
4092 return -ENOMEM;
4093 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4094 return 0;
4095}
4096
5d450806 4097static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 4098{
5d450806 4099 struct dmar_domain *dmar_domain;
38717946 4100
92d03cc8 4101 dmar_domain = alloc_domain(true);
5d450806 4102 if (!dmar_domain) {
38717946 4103 printk(KERN_ERR
5d450806
JR		 4104 "intel_iommu_domain_init: dmar_domain == NULL\n");
4105 return -ENOMEM;
38717946 4106 }
2c2e2c38 4107 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 4108 printk(KERN_ERR
5d450806 4109 "intel_iommu_domain_init() failed\n");
92d03cc8 4110 domain_exit(dmar_domain);
5d450806 4111 return -ENOMEM;
38717946 4112 }
8140a95d 4113 domain_update_iommu_cap(dmar_domain);
5d450806 4114 domain->priv = dmar_domain;
faa3d6f5 4115
8a0e715b
JR		 4116 domain->geometry.aperture_start = 0;
4117 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4118 domain->geometry.force_aperture = true;
4119
5d450806 4120 return 0;
38717946 4121}
38717946 4122
5d450806 4123static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 4124{
5d450806
JR		 4125 struct dmar_domain *dmar_domain = domain->priv;
4126
4127 domain->priv = NULL;
92d03cc8 4128 domain_exit(dmar_domain);
38717946 4129}
38717946 4130
4c5478c9
JR		 4131static int intel_iommu_attach_device(struct iommu_domain *domain,
4132 struct device *dev)
38717946 4133{
4c5478c9
JR		 4134 struct dmar_domain *dmar_domain = domain->priv;
4135 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 4136 struct intel_iommu *iommu;
4137 int addr_width;
faa3d6f5
WH		 4138
4139 /* normally pdev is not mapped */
4140 if (unlikely(domain_context_mapped(pdev))) {
4141 struct dmar_domain *old_domain;
4142
4143 old_domain = find_domain(pdev);
4144 if (old_domain) {
2c2e2c38
FY		 4145 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
4146 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
4147 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 4148 else
4149 domain_remove_dev_info(old_domain);
4150 }
4151 }
4152
276dbf99
DW		 4153 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4154 pdev->devfn);
fe40f1e0
WH		 4155 if (!iommu)
4156 return -ENODEV;
4157
4158 /* check if this iommu agaw is sufficient for max mapped address */
4159 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4160 if (addr_width > cap_mgaw(iommu->cap))
4161 addr_width = cap_mgaw(iommu->cap);
4162
4163 if (dmar_domain->max_addr > (1LL << addr_width)) {
4164 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4165 "sufficient for the mapped address (%llx)\n",
a99c47a2 4166 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4167 return -EFAULT;
4168 }
a99c47a2
TL		 4169 dmar_domain->gaw = addr_width;
4170
4171 /*
4172 * Knock out extra levels of page tables if necessary
4173 */
4174 while (iommu->agaw < dmar_domain->agaw) {
4175 struct dma_pte *pte;
4176
4177 pte = dmar_domain->pgd;
4178 if (dma_pte_present(pte)) {
25cbff16
SY		 4179 dmar_domain->pgd = (struct dma_pte *)
4180 phys_to_virt(dma_pte_addr(pte));
7a661013 4181 free_pgtable_page(pte);
a99c47a2
TL		 4182 }
4183 dmar_domain->agaw--;
4184 }
fe40f1e0 4185
5fe60f4e 4186 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 4187}
38717946 4188
4c5478c9
JR		 4189static void intel_iommu_detach_device(struct iommu_domain *domain,
4190 struct device *dev)
38717946 4191{
4c5478c9
JR		 4192 struct dmar_domain *dmar_domain = domain->priv;
4193 struct pci_dev *pdev = to_pci_dev(dev);
4194
2c2e2c38 4195 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 4196}
c7151a8d 4197
b146a1c9
JR		 4198static int intel_iommu_map(struct iommu_domain *domain,
4199 unsigned long iova, phys_addr_t hpa,
5009065d 4200 size_t size, int iommu_prot)
faa3d6f5 4201{
dde57a21 4202 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 4203 u64 max_addr;
dde57a21 4204 int prot = 0;
faa3d6f5 4205 int ret;
fe40f1e0 4206
dde57a21
JR		 4207 if (iommu_prot & IOMMU_READ)
4208 prot |= DMA_PTE_READ;
4209 if (iommu_prot & IOMMU_WRITE)
4210 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4211 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4212 prot |= DMA_PTE_SNP;
dde57a21 4213
163cc52c 4214 max_addr = iova + size;
dde57a21 4215 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4216 u64 end;
4217
4218 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4219 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4220 if (end < max_addr) {
8954da1f 4221 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4222 "sufficient for the mapped address (%llx)\n",
8954da1f 4223 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4224 return -EFAULT;
4225 }
dde57a21 4226 dmar_domain->max_addr = max_addr;
fe40f1e0 4227 }
ad051221
DW		 4228 /* Round up size to next multiple of PAGE_SIZE, if it and
4229 the low bits of hpa would take us onto the next page */
88cb6a74 4230 size = aligned_nrpages(hpa, size);
ad051221
DW		 4231 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4232 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4233 return ret;
38717946 4234}
38717946 4235
5009065d 4236static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4237 unsigned long iova, size_t size)
38717946 4238{
dde57a21 4239 struct dmar_domain *dmar_domain = domain->priv;
ea8ea460
DW		 4240 struct page *freelist = NULL;
4241 struct intel_iommu *iommu;
4242 unsigned long start_pfn, last_pfn;
4243 unsigned int npages;
4244 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4245
4246 /* Cope with horrid API which requires us to unmap more than the
4247 size argument if it happens to be a large-page mapping. */
4248 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4249 BUG();
4250
4251 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4252 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4253
ea8ea460
DW		 4254 start_pfn = iova >> VTD_PAGE_SHIFT;
4255 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4256
4257 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4258
4259 npages = last_pfn - start_pfn + 1;
4260
4261 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4262 iommu = g_iommus[iommu_id];
4263
4264 /*
4265 * find bit position of dmar_domain
4266 */
4267 ndomains = cap_ndoms(iommu->cap);
4268 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4269 if (iommu->domains[num] == dmar_domain)
4270 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4271 npages, !freelist, 0);
4272 }
4273
4274 }
4275
4276 dma_free_pagelist(freelist);
fe40f1e0 4277
163cc52c
DW		 4278 if (dmar_domain->max_addr == iova + size)
4279 dmar_domain->max_addr = iova;
b146a1c9 4280
5cf0a76f 4281 return size;
38717946 4282}
38717946 4283
d14d6577 4284static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4285 dma_addr_t iova)
38717946 4286{
d14d6577 4287 struct dmar_domain *dmar_domain = domain->priv;
38717946 4288 struct dma_pte *pte;
5cf0a76f 4289 int level = 0;
faa3d6f5 4290 u64 phys = 0;
38717946 4291
5cf0a76f 4292 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4293 if (pte)
faa3d6f5 4294 phys = dma_pte_addr(pte);
38717946 4295
faa3d6f5 4296 return phys;
38717946 4297}
a8bcbb0d 4298
dbb9fd86
SY		 4299static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4300 unsigned long cap)
4301{
4302 struct dmar_domain *dmar_domain = domain->priv;
4303
4304 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4305 return dmar_domain->iommu_snooping;
323f99cb 4306 if (cap == IOMMU_CAP_INTR_REMAP)
95a02e97 4307 return irq_remapping_enabled;
dbb9fd86
SY		 4308
4309 return 0;
4310}
4311
783f157b 4312#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
70ae6f0d 4313
abdfdde2
AW		 4314static int intel_iommu_add_device(struct device *dev)
4315{
4316 struct pci_dev *pdev = to_pci_dev(dev);
3da4af0a 4317 struct pci_dev *bridge, *dma_pdev = NULL;
abdfdde2
AW		 4318 struct iommu_group *group;
4319 int ret;
70ae6f0d 4320
abdfdde2
AW		 4321 if (!device_to_iommu(pci_domain_nr(pdev->bus),
4322 pdev->bus->number, pdev->devfn))
70ae6f0d
AW		 4323 return -ENODEV;
4324
4325 bridge = pci_find_upstream_pcie_bridge(pdev);
4326 if (bridge) {
abdfdde2
AW		 4327 if (pci_is_pcie(bridge))
4328 dma_pdev = pci_get_domain_bus_and_slot(
4329 pci_domain_nr(pdev->bus),
4330 bridge->subordinate->number, 0);
3da4af0a 4331 if (!dma_pdev)
abdfdde2
AW		 4332 dma_pdev = pci_dev_get(bridge);
4333 } else
4334 dma_pdev = pci_dev_get(pdev);
4335
a4ff1fc2 4336 /* Account for quirked devices */
783f157b
AW		 4337 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
4338
a4ff1fc2
AW		 4339 /*
4340 * If it's a multifunction device that does not support our
c14d2690
AW		 4341 * required ACS flags, add to the same group as lowest numbered
4342 * function that also does not suport the required ACS flags.
a4ff1fc2 4343 */
783f157b 4344 if (dma_pdev->multifunction &&
c14d2690
AW		 4345 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
4346 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
4347
4348 for (i = 0; i < 8; i++) {
4349 struct pci_dev *tmp;
4350
4351 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
4352 if (!tmp)
4353 continue;
4354
4355 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
4356 swap_pci_ref(&dma_pdev, tmp);
4357 break;
4358 }
4359 pci_dev_put(tmp);
4360 }
4361 }
783f157b 4362
a4ff1fc2
AW		 4363 /*
4364 * Devices on the root bus go through the iommu. If that's not us,
4365 * find the next upstream device and test ACS up to the root bus.
4366 * Finding the next device may require skipping virtual buses.
4367 */
783f157b 4368 while (!pci_is_root_bus(dma_pdev->bus)) {
a4ff1fc2
AW		 4369 struct pci_bus *bus = dma_pdev->bus;
4370
4371 while (!bus->self) {
4372 if (!pci_is_root_bus(bus))
4373 bus = bus->parent;
4374 else
4375 goto root_bus;
4376 }
4377
4378 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
783f157b
AW		 4379 break;
4380
a4ff1fc2 4381 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
783f157b
AW		 4382 }
4383
a4ff1fc2 4384root_bus:
abdfdde2
AW		 4385 group = iommu_group_get(&dma_pdev->dev);
4386 pci_dev_put(dma_pdev);
4387 if (!group) {
4388 group = iommu_group_alloc();
4389 if (IS_ERR(group))
4390 return PTR_ERR(group);
70ae6f0d
AW		 4391 }
4392
abdfdde2 4393 ret = iommu_group_add_device(group, dev);
bcb71abe 4394
abdfdde2
AW		 4395 iommu_group_put(group);
4396 return ret;
4397}
70ae6f0d 4398
abdfdde2
AW		 4399static void intel_iommu_remove_device(struct device *dev)
4400{
4401 iommu_group_remove_device(dev);
70ae6f0d
AW		 4402}
4403
a8bcbb0d
JR		 4404static struct iommu_ops intel_iommu_ops = {
4405 .domain_init = intel_iommu_domain_init,
4406 .domain_destroy = intel_iommu_domain_destroy,
4407 .attach_dev = intel_iommu_attach_device,
4408 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4409 .map = intel_iommu_map,
4410 .unmap = intel_iommu_unmap,
a8bcbb0d 4411 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4412 .domain_has_cap = intel_iommu_domain_has_cap,
abdfdde2
AW		 4413 .add_device = intel_iommu_add_device,
4414 .remove_device = intel_iommu_remove_device,
6d1c56a9 4415 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4416};
9af88143 4417
9452618e
DV		 4418static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4419{
4420 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4421 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4422 dmar_map_gfx = 0;
4423}
4424
4425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4426DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4430DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4431DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4432
d34d6517 4433static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4434{
4435 /*
4436 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4437 * but needs it. Same seems to hold for the desktop versions.
9af88143
DW		 4438 */
4439 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4440 rwbf_quirk = 1;
4441}
4442
4443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4450
eecfd57f
AJ		 4451#define GGC 0x52
4452#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4453#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4454#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4455#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4456#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4457#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4458#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4459#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4460
d34d6517 4461static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4462{
4463 unsigned short ggc;
4464
eecfd57f 4465 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4466 return;
4467
eecfd57f 4468 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4469 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4470 dmar_map_gfx = 0;
6fbcfb3e
DW		 4471 } else if (dmar_map_gfx) {
4472 /* we have to ensure the gfx device is idle before we flush */
4473 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4474 intel_iommu_strict = 1;
4475 }
9eecabcb
DW		 4476}
4477DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4478DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4479DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4480DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4481
e0fc7e0b
DW		 4482/* On Tylersburg chipsets, some BIOSes have been known to enable the
4483 ISOCH DMAR unit for the Azalia sound device, but not give it any
4484 TLB entries, which causes it to deadlock. Check for that. We do
4485 this in a function called from init_dmars(), instead of in a PCI
4486 quirk, because we don't want to print the obnoxious "BIOS broken"
4487 message if VT-d is actually disabled.
4488*/
4489static void __init check_tylersburg_isoch(void)
4490{
4491 struct pci_dev *pdev;
4492 uint32_t vtisochctrl;
4493
4494 /* If there's no Azalia in the system anyway, forget it. */
4495 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4496 if (!pdev)
4497 return;
4498 pci_dev_put(pdev);
4499
4500 /* System Management Registers. Might be hidden, in which case
4501 we can't do the sanity check. But that's OK, because the
4502 known-broken BIOSes _don't_ actually hide it, so far. */
4503 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4504 if (!pdev)
4505 return;
4506
4507 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4508 pci_dev_put(pdev);
4509 return;
4510 }
4511
4512 pci_dev_put(pdev);
4513
4514 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4515 if (vtisochctrl & 1)
4516 return;
4517
4518 /* Drop all bits other than the number of TLB entries */
4519 vtisochctrl &= 0x1c;
4520
4521 /* If we have the recommended number of TLB entries (16), fine. */
4522 if (vtisochctrl == 0x10)
4523 return;
4524
4525 /* Zero TLB entries? You get to ride the short bus to school. */
4526 if (!vtisochctrl) {
4527 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4528 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4529 dmi_get_system_info(DMI_BIOS_VENDOR),
4530 dmi_get_system_info(DMI_BIOS_VERSION),
4531 dmi_get_system_info(DMI_PRODUCT_VERSION));
4532 iommu_identity_mapping |= IDENTMAP_AZALIA;
4533 return;
4534 }
4535
4536 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4537 vtisochctrl);
4538}
Linux kernel - Deliverables
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