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iommu/vt-d: Handle RMRRs for non-PCI devices
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 18 */
19
20#include <linux/init.h>
21#include <linux/bitmap.h>
5e0d2a6f 22#include <linux/debugfs.h>
54485c30 23#include <linux/export.h>
ba395927
KA		 24#include <linux/slab.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
ba395927
KA		 27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/dmar.h>
30#include <linux/dma-mapping.h>
31#include <linux/mempool.h>
75f05569 32#include <linux/memory.h>
5e0d2a6f 33#include <linux/timer.h>
38717946 34#include <linux/iova.h>
5d450806 35#include <linux/iommu.h>
38717946 36#include <linux/intel-iommu.h>
134fac3f 37#include <linux/syscore_ops.h>
69575d38 38#include <linux/tboot.h>
adb2fe02 39#include <linux/dmi.h>
5cdede24 40#include <linux/pci-ats.h>
0ee332c1 41#include <linux/memblock.h>
8a8f422d 42#include <asm/irq_remapping.h>
ba395927 43#include <asm/cacheflush.h>
46a7fa27 44#include <asm/iommu.h>
ba395927 45
078e1ee2 46#include "irq_remapping.h"
61e015ac 47#include "pci.h"
078e1ee2 48
5b6985ce
FY		 49#define ROOT_SIZE VTD_PAGE_SIZE
50#define CONTEXT_SIZE VTD_PAGE_SIZE
51
ba395927
KA		 52#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
53#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 54#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 55
56#define IOAPIC_RANGE_START (0xfee00000)
57#define IOAPIC_RANGE_END (0xfeefffff)
58#define IOVA_START_ADDR (0x1000)
59
60#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
61
4ed0d3e6 62#define MAX_AGAW_WIDTH 64
5c645b35 63#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 64
2ebe3151
DW		 65#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
67
68/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 73
f27be03b 74#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 75#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 76#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 77
df08cdc7
AM		 78/* page table handling */
79#define LEVEL_STRIDE (9)
80#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
81
6d1c56a9
OBC		 82/*
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
86 * that we support.
87 *
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
91 *
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
94 *
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
97 */
98#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
99
df08cdc7
AM		 100static inline int agaw_to_level(int agaw)
101{
102 return agaw + 2;
103}
104
105static inline int agaw_to_width(int agaw)
106{
5c645b35 107 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 108}
109
110static inline int width_to_agaw(int width)
111{
5c645b35 112 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 113}
114
115static inline unsigned int level_to_offset_bits(int level)
116{
117 return (level - 1) * LEVEL_STRIDE;
118}
119
120static inline int pfn_level_offset(unsigned long pfn, int level)
121{
122 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
123}
124
125static inline unsigned long level_mask(int level)
126{
127 return -1UL << level_to_offset_bits(level);
128}
129
130static inline unsigned long level_size(int level)
131{
132 return 1UL << level_to_offset_bits(level);
133}
134
135static inline unsigned long align_to_level(unsigned long pfn, int level)
136{
137 return (pfn + level_size(level) - 1) & level_mask(level);
138}
fd18de50 139
6dd9a7c7
YS		 140static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
141{
5c645b35 142 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 143}
144
dd4e8319
DW		 145/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
148{
149 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
150}
151
152static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
153{
154 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
155}
156static inline unsigned long page_to_dma_pfn(struct page *pg)
157{
158 return mm_to_dma_pfn(page_to_pfn(pg));
159}
160static inline unsigned long virt_to_dma_pfn(void *p)
161{
162 return page_to_dma_pfn(virt_to_page(p));
163}
164
d9630fe9
WH		 165/* global iommu list, set NULL for ignored DMAR units */
166static struct intel_iommu **g_iommus;
167
e0fc7e0b 168static void __init check_tylersburg_isoch(void);
9af88143
DW		 169static int rwbf_quirk;
170
b779260b
JC		 171/*
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
174 */
175static int force_on = 0;
176
46b08e1a
MM		 177/*
178 * 0: Present
179 * 1-11: Reserved
180 * 12-63: Context Ptr (12 - (haw-1))
181 * 64-127: Reserved
182 */
183struct root_entry {
184 u64 val;
185 u64 rsvd1;
186};
187#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188static inline bool root_present(struct root_entry *root)
189{
190 return (root->val & 1);
191}
192static inline void set_root_present(struct root_entry *root)
193{
194 root->val |= 1;
195}
196static inline void set_root_value(struct root_entry *root, unsigned long value)
197{
198 root->val |= value & VTD_PAGE_MASK;
199}
200
201static inline struct context_entry *
202get_context_addr_from_root(struct root_entry *root)
203{
204 return (struct context_entry *)
205 (root_present(root)?phys_to_virt(
206 root->val & VTD_PAGE_MASK) :
207 NULL);
208}
209
7a8fc25e
MM		 210/*
211 * low 64 bits:
212 * 0: present
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
216 * high 64 bits:
217 * 0-2: address width
218 * 3-6: aval
219 * 8-23: domain id
220 */
221struct context_entry {
222 u64 lo;
223 u64 hi;
224};
c07e7d21
MM		 225
226static inline bool context_present(struct context_entry *context)
227{
228 return (context->lo & 1);
229}
230static inline void context_set_present(struct context_entry *context)
231{
232 context->lo |= 1;
233}
234
235static inline void context_set_fault_enable(struct context_entry *context)
236{
237 context->lo &= (((u64)-1) << 2) | 1;
238}
239
c07e7d21
MM		 240static inline void context_set_translation_type(struct context_entry *context,
241 unsigned long value)
242{
243 context->lo &= (((u64)-1) << 4) | 3;
244 context->lo |= (value & 3) << 2;
245}
246
247static inline void context_set_address_root(struct context_entry *context,
248 unsigned long value)
249{
250 context->lo |= value & VTD_PAGE_MASK;
251}
252
253static inline void context_set_address_width(struct context_entry *context,
254 unsigned long value)
255{
256 context->hi |= value & 7;
257}
258
259static inline void context_set_domain_id(struct context_entry *context,
260 unsigned long value)
261{
262 context->hi |= (value & ((1 << 16) - 1)) << 8;
263}
264
265static inline void context_clear_entry(struct context_entry *context)
266{
267 context->lo = 0;
268 context->hi = 0;
269}
7a8fc25e 270
622ba12a
MM		 271/*
272 * 0: readable
273 * 1: writable
274 * 2-6: reserved
275 * 7: super page
9cf06697
SY		 276 * 8-10: available
277 * 11: snoop behavior
622ba12a
MM		 278 * 12-63: Host physcial address
279 */
280struct dma_pte {
281 u64 val;
282};
622ba12a 283
19c239ce
MM		 284static inline void dma_clear_pte(struct dma_pte *pte)
285{
286 pte->val = 0;
287}
288
19c239ce
MM		 289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
19c239ce
MM		 299static inline bool dma_pte_present(struct dma_pte *pte)
300{
301 return (pte->val & 3) != 0;
302}
622ba12a 303
4399c8bf
AK		 304static inline bool dma_pte_superpage(struct dma_pte *pte)
305{
306 return (pte->val & (1 << 7));
307}
308
75e6bf96
DW		 309static inline int first_pte_in_page(struct dma_pte *pte)
310{
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312}
313
2c2e2c38
FY		 314/*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
19943b0e
DW		 320static struct dmar_domain *si_domain;
321static int hw_pass_through = 1;
2c2e2c38 322
3b5410e7 323/* devices under the same p2p bridge are owned in one domain */
cdc7b837 324#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 325
1ce28feb
WH		 326/* domain represents a virtual machine, more than one devices
327 * across iommus may be owned in one domain, e.g. kvm guest.
328 */
329#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
330
2c2e2c38
FY		 331/* si_domain contains mulitple devices */
332#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
333
1b198bb0
MT		 334/* define the limit of IOMMUs supported in each domain */
335#ifdef CONFIG_X86
336# define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
337#else
338# define IOMMU_UNITS_SUPPORTED 64
339#endif
340
99126f7c
MM		 341struct dmar_domain {
342 int id; /* domain id */
4c923d47 343 int nid; /* node id */
1b198bb0
MT		 344 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
345 /* bitmap of iommus this domain uses*/
99126f7c
MM		 346
347 struct list_head devices; /* all devices' list */
348 struct iova_domain iovad; /* iova's that belong to this domain */
349
350 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 351 int gaw; /* max guest address width */
352
353 /* adjusted guest address width, 0 is level 2 30-bit */
354 int agaw;
355
3b5410e7 356 int flags; /* flags to find out type of domain */
8e604097
WH		 357
358 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 359 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 360 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 361 int iommu_superpage;/* Level of superpages supported:
362 0 == 4KiB (no superpages), 1 == 2MiB,
363 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 364 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 365 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 366};
367
a647dacb
MM		 368/* PCI domain-device relationship */
369struct device_domain_info {
370 struct list_head link; /* link to domain siblings */
371 struct list_head global; /* link to global list */
276dbf99 372 u8 bus; /* PCI bus number */
a647dacb 373 u8 devfn; /* PCI devfn number */
0bcb3e28 374 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 375 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 376 struct dmar_domain *domain; /* pointer to domain */
377};
378
b94e4117
JL		 379struct dmar_rmrr_unit {
380 struct list_head list; /* list of rmrr units */
381 struct acpi_dmar_header *hdr; /* ACPI header */
382 u64 base_address; /* reserved base address*/
383 u64 end_address; /* reserved end address */
832bd858 384 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 385 int devices_cnt; /* target device count */
386};
387
388struct dmar_atsr_unit {
389 struct list_head list; /* list of ATSR units */
390 struct acpi_dmar_header *hdr; /* ACPI header */
832bd858 391 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 392 int devices_cnt; /* target device count */
393 u8 include_all:1; /* include all ports */
394};
395
396static LIST_HEAD(dmar_atsr_units);
397static LIST_HEAD(dmar_rmrr_units);
398
399#define for_each_rmrr_units(rmrr) \
400 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
401
5e0d2a6f 402static void flush_unmaps_timeout(unsigned long data);
403
b707cb02 404static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 405
80b20dd8 406#define HIGH_WATER_MARK 250
407struct deferred_flush_tables {
408 int next;
409 struct iova *iova[HIGH_WATER_MARK];
410 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 411 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 412};
413
414static struct deferred_flush_tables *deferred_flush;
415
5e0d2a6f 416/* bitmap for indexing intel_iommus */
5e0d2a6f 417static int g_num_of_iommus;
418
419static DEFINE_SPINLOCK(async_umap_flush_lock);
420static LIST_HEAD(unmaps_to_do);
421
422static int timer_on;
423static long list_size;
5e0d2a6f 424
92d03cc8 425static void domain_exit(struct dmar_domain *domain);
ba395927 426static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117
JL		 427static void domain_remove_one_dev_info(struct dmar_domain *domain,
428 struct pci_dev *pdev);
92d03cc8 429static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 430 struct device *dev);
ba395927 431
d3f13810 432#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 433int dmar_disabled = 0;
434#else
435int dmar_disabled = 1;
d3f13810 436#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 437
8bc1f85c
ED		 438int intel_iommu_enabled = 0;
439EXPORT_SYMBOL_GPL(intel_iommu_enabled);
440
2d9e667e 441static int dmar_map_gfx = 1;
7d3b03ce 442static int dmar_forcedac;
5e0d2a6f 443static int intel_iommu_strict;
6dd9a7c7 444static int intel_iommu_superpage = 1;
ba395927 445
c0771df8
DW		 446int intel_iommu_gfx_mapped;
447EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
448
ba395927
KA		 449#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
450static DEFINE_SPINLOCK(device_domain_lock);
451static LIST_HEAD(device_domain_list);
452
a8bcbb0d
JR		 453static struct iommu_ops intel_iommu_ops;
454
ba395927
KA		 455static int __init intel_iommu_setup(char *str)
456{
457 if (!str)
458 return -EINVAL;
459 while (*str) {
0cd5c3c8
KM		 460 if (!strncmp(str, "on", 2)) {
461 dmar_disabled = 0;
462 printk(KERN_INFO "Intel-IOMMU: enabled\n");
463 } else if (!strncmp(str, "off", 3)) {
ba395927 464 dmar_disabled = 1;
0cd5c3c8 465 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 466 } else if (!strncmp(str, "igfx_off", 8)) {
467 dmar_map_gfx = 0;
468 printk(KERN_INFO
469 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 470 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 471 printk(KERN_INFO
7d3b03ce
KA		 472 "Intel-IOMMU: Forcing DAC for PCI devices\n");
473 dmar_forcedac = 1;
5e0d2a6f 474 } else if (!strncmp(str, "strict", 6)) {
475 printk(KERN_INFO
476 "Intel-IOMMU: disable batched IOTLB flush\n");
477 intel_iommu_strict = 1;
6dd9a7c7
YS		 478 } else if (!strncmp(str, "sp_off", 6)) {
479 printk(KERN_INFO
480 "Intel-IOMMU: disable supported super page\n");
481 intel_iommu_superpage = 0;
ba395927
KA		 482 }
483
484 str += strcspn(str, ",");
485 while (*str == ',')
486 str++;
487 }
488 return 0;
489}
490__setup("intel_iommu=", intel_iommu_setup);
491
492static struct kmem_cache *iommu_domain_cache;
493static struct kmem_cache *iommu_devinfo_cache;
494static struct kmem_cache *iommu_iova_cache;
495
4c923d47 496static inline void *alloc_pgtable_page(int node)
eb3fa7cb 497{
4c923d47
SS		 498 struct page *page;
499 void *vaddr = NULL;
eb3fa7cb 500
4c923d47
SS		 501 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
502 if (page)
503 vaddr = page_address(page);
eb3fa7cb 504 return vaddr;
ba395927
KA		 505}
506
507static inline void free_pgtable_page(void *vaddr)
508{
509 free_page((unsigned long)vaddr);
510}
511
512static inline void *alloc_domain_mem(void)
513{
354bb65e 514 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 515}
516
38717946 517static void free_domain_mem(void *vaddr)
ba395927
KA		 518{
519 kmem_cache_free(iommu_domain_cache, vaddr);
520}
521
522static inline void * alloc_devinfo_mem(void)
523{
354bb65e 524 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 525}
526
527static inline void free_devinfo_mem(void *vaddr)
528{
529 kmem_cache_free(iommu_devinfo_cache, vaddr);
530}
531
532struct iova *alloc_iova_mem(void)
533{
354bb65e 534 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 535}
536
537void free_iova_mem(struct iova *iova)
538{
539 kmem_cache_free(iommu_iova_cache, iova);
540}
541
1b573683 542
4ed0d3e6 543static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 544{
545 unsigned long sagaw;
546 int agaw = -1;
547
548 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 549 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 550 agaw >= 0; agaw--) {
551 if (test_bit(agaw, &sagaw))
552 break;
553 }
554
555 return agaw;
556}
557
4ed0d3e6
FY		 558/*
559 * Calculate max SAGAW for each iommu.
560 */
561int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
562{
563 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
564}
565
566/*
567 * calculate agaw for each iommu.
568 * "SAGAW" may be different across iommus, use a default agaw, and
569 * get a supported less agaw for iommus that don't support the default agaw.
570 */
571int iommu_calculate_agaw(struct intel_iommu *iommu)
572{
573 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
574}
575
2c2e2c38 576/* This functionin only returns single iommu in a domain */
8c11e798
WH		 577static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
578{
579 int iommu_id;
580
2c2e2c38 581 /* si_domain and vm domain should not get here. */
1ce28feb 582 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 583 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 584
1b198bb0 585 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 586 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
587 return NULL;
588
589 return g_iommus[iommu_id];
590}
591
8e604097
WH		 592static void domain_update_iommu_coherency(struct dmar_domain *domain)
593{
d0501960
DW		 594 struct dmar_drhd_unit *drhd;
595 struct intel_iommu *iommu;
596 int i, found = 0;
2e12bc29 597
d0501960 598 domain->iommu_coherency = 1;
8e604097 599
1b198bb0 600 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
d0501960 601 found = 1;
8e604097
WH		 602 if (!ecap_coherent(g_iommus[i]->ecap)) {
603 domain->iommu_coherency = 0;
604 break;
605 }
8e604097 606 }
d0501960
DW		 607 if (found)
608 return;
609
610 /* No hardware attached; use lowest common denominator */
611 rcu_read_lock();
612 for_each_active_iommu(iommu, drhd) {
613 if (!ecap_coherent(iommu->ecap)) {
614 domain->iommu_coherency = 0;
615 break;
616 }
617 }
618 rcu_read_unlock();
8e604097
WH		 619}
620
58c610bd
SY		 621static void domain_update_iommu_snooping(struct dmar_domain *domain)
622{
623 int i;
624
625 domain->iommu_snooping = 1;
626
1b198bb0 627 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 628 if (!ecap_sc_support(g_iommus[i]->ecap)) {
629 domain->iommu_snooping = 0;
630 break;
631 }
58c610bd
SY		 632 }
633}
634
6dd9a7c7
YS		 635static void domain_update_iommu_superpage(struct dmar_domain *domain)
636{
8140a95d
AK		 637 struct dmar_drhd_unit *drhd;
638 struct intel_iommu *iommu = NULL;
639 int mask = 0xf;
6dd9a7c7
YS		 640
641 if (!intel_iommu_superpage) {
642 domain->iommu_superpage = 0;
643 return;
644 }
645
8140a95d 646 /* set iommu_superpage to the smallest common denominator */
0e242612 647 rcu_read_lock();
8140a95d
AK		 648 for_each_active_iommu(iommu, drhd) {
649 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 650 if (!mask) {
651 break;
652 }
653 }
0e242612
JL		 654 rcu_read_unlock();
655
6dd9a7c7
YS		 656 domain->iommu_superpage = fls(mask);
657}
658
58c610bd
SY		 659/* Some capabilities may be different across iommus */
660static void domain_update_iommu_cap(struct dmar_domain *domain)
661{
662 domain_update_iommu_coherency(domain);
663 domain_update_iommu_snooping(domain);
6dd9a7c7 664 domain_update_iommu_superpage(domain);
58c610bd
SY		 665}
666
156baca8 667static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
c7151a8d
WH		 668{
669 struct dmar_drhd_unit *drhd = NULL;
b683b230 670 struct intel_iommu *iommu;
156baca8
DW		 671 struct device *tmp;
672 struct pci_dev *ptmp, *pdev = NULL;
673 u16 segment;
c7151a8d
WH		 674 int i;
675
156baca8
DW		 676 if (dev_is_pci(dev)) {
677 pdev = to_pci_dev(dev);
678 segment = pci_domain_nr(pdev->bus);
679 } else if (ACPI_COMPANION(dev))
680 dev = &ACPI_COMPANION(dev)->dev;
681
0e242612 682 rcu_read_lock();
b683b230 683 for_each_active_iommu(iommu, drhd) {
156baca8 684 if (pdev && segment != drhd->segment)
276dbf99 685 continue;
c7151a8d 686
b683b230 687 for_each_active_dev_scope(drhd->devices,
156baca8
DW		 688 drhd->devices_cnt, i, tmp) {
689 if (tmp == dev) {
690 *bus = drhd->devices[i].bus;
691 *devfn = drhd->devices[i].devfn;
b683b230 692 goto out;
156baca8
DW		 693 }
694
695 if (!pdev || !dev_is_pci(tmp))
696 continue;
697
698 ptmp = to_pci_dev(tmp);
699 if (ptmp->subordinate &&
700 ptmp->subordinate->number <= pdev->bus->number &&
701 ptmp->subordinate->busn_res.end >= pdev->bus->number)
702 goto got_pdev;
924b6231 703 }
c7151a8d 704
156baca8
DW		 705 if (pdev && drhd->include_all) {
706 got_pdev:
707 *bus = pdev->bus->number;
708 *devfn = pdev->devfn;
b683b230 709 goto out;
156baca8 710 }
c7151a8d 711 }
b683b230 712 iommu = NULL;
156baca8 713 out:
0e242612 714 rcu_read_unlock();
c7151a8d 715
b683b230 716 return iommu;
c7151a8d
WH		 717}
718
5331fe6f
WH		 719static void domain_flush_cache(struct dmar_domain *domain,
720 void *addr, int size)
721{
722 if (!domain->iommu_coherency)
723 clflush_cache_range(addr, size);
724}
725
ba395927
KA		 726/* Gets context entry for a given bus and devfn */
727static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
728 u8 bus, u8 devfn)
729{
730 struct root_entry *root;
731 struct context_entry *context;
732 unsigned long phy_addr;
733 unsigned long flags;
734
735 spin_lock_irqsave(&iommu->lock, flags);
736 root = &iommu->root_entry[bus];
737 context = get_context_addr_from_root(root);
738 if (!context) {
4c923d47
SS		 739 context = (struct context_entry *)
740 alloc_pgtable_page(iommu->node);
ba395927
KA		 741 if (!context) {
742 spin_unlock_irqrestore(&iommu->lock, flags);
743 return NULL;
744 }
5b6985ce 745 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 746 phy_addr = virt_to_phys((void *)context);
747 set_root_value(root, phy_addr);
748 set_root_present(root);
749 __iommu_flush_cache(iommu, root, sizeof(*root));
750 }
751 spin_unlock_irqrestore(&iommu->lock, flags);
752 return &context[devfn];
753}
754
755static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
756{
757 struct root_entry *root;
758 struct context_entry *context;
759 int ret;
760 unsigned long flags;
761
762 spin_lock_irqsave(&iommu->lock, flags);
763 root = &iommu->root_entry[bus];
764 context = get_context_addr_from_root(root);
765 if (!context) {
766 ret = 0;
767 goto out;
768 }
c07e7d21 769 ret = context_present(&context[devfn]);
ba395927
KA		 770out:
771 spin_unlock_irqrestore(&iommu->lock, flags);
772 return ret;
773}
774
775static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
776{
777 struct root_entry *root;
778 struct context_entry *context;
779 unsigned long flags;
780
781 spin_lock_irqsave(&iommu->lock, flags);
782 root = &iommu->root_entry[bus];
783 context = get_context_addr_from_root(root);
784 if (context) {
c07e7d21 785 context_clear_entry(&context[devfn]);
ba395927
KA		 786 __iommu_flush_cache(iommu, &context[devfn], \
787 sizeof(*context));
788 }
789 spin_unlock_irqrestore(&iommu->lock, flags);
790}
791
792static void free_context_table(struct intel_iommu *iommu)
793{
794 struct root_entry *root;
795 int i;
796 unsigned long flags;
797 struct context_entry *context;
798
799 spin_lock_irqsave(&iommu->lock, flags);
800 if (!iommu->root_entry) {
801 goto out;
802 }
803 for (i = 0; i < ROOT_ENTRY_NR; i++) {
804 root = &iommu->root_entry[i];
805 context = get_context_addr_from_root(root);
806 if (context)
807 free_pgtable_page(context);
808 }
809 free_pgtable_page(iommu->root_entry);
810 iommu->root_entry = NULL;
811out:
812 spin_unlock_irqrestore(&iommu->lock, flags);
813}
814
b026fd28 815static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 816 unsigned long pfn, int *target_level)
ba395927 817{
b026fd28 818 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 819 struct dma_pte *parent, *pte = NULL;
820 int level = agaw_to_level(domain->agaw);
4399c8bf 821 int offset;
ba395927
KA		 822
823 BUG_ON(!domain->pgd);
f9423606
JS		 824
825 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
826 /* Address beyond IOMMU's addressing capabilities. */
827 return NULL;
828
ba395927
KA		 829 parent = domain->pgd;
830
5cf0a76f 831 while (1) {
ba395927
KA		 832 void *tmp_page;
833
b026fd28 834 offset = pfn_level_offset(pfn, level);
ba395927 835 pte = &parent[offset];
5cf0a76f 836 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 837 break;
5cf0a76f 838 if (level == *target_level)
ba395927
KA		 839 break;
840
19c239ce 841 if (!dma_pte_present(pte)) {
c85994e4
DW		 842 uint64_t pteval;
843
4c923d47 844 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 845
206a73c1 846 if (!tmp_page)
ba395927 847 return NULL;
206a73c1 848
c85994e4 849 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 850 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 851 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
852 /* Someone else set it while we were thinking; use theirs. */
853 free_pgtable_page(tmp_page);
854 } else {
855 dma_pte_addr(pte);
856 domain_flush_cache(domain, pte, sizeof(*pte));
857 }
ba395927 858 }
5cf0a76f
DW		 859 if (level == 1)
860 break;
861
19c239ce 862 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 863 level--;
864 }
865
5cf0a76f
DW		 866 if (!*target_level)
867 *target_level = level;
868
ba395927
KA		 869 return pte;
870}
871
6dd9a7c7 872
ba395927 873/* return address's pte at specific level */
90dcfb5e
DW		 874static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
875 unsigned long pfn,
6dd9a7c7 876 int level, int *large_page)
ba395927
KA		 877{
878 struct dma_pte *parent, *pte = NULL;
879 int total = agaw_to_level(domain->agaw);
880 int offset;
881
882 parent = domain->pgd;
883 while (level <= total) {
90dcfb5e 884 offset = pfn_level_offset(pfn, total);
ba395927
KA		 885 pte = &parent[offset];
886 if (level == total)
887 return pte;
888
6dd9a7c7
YS		 889 if (!dma_pte_present(pte)) {
890 *large_page = total;
ba395927 891 break;
6dd9a7c7
YS		 892 }
893
894 if (pte->val & DMA_PTE_LARGE_PAGE) {
895 *large_page = total;
896 return pte;
897 }
898
19c239ce 899 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 900 total--;
901 }
902 return NULL;
903}
904
ba395927 905/* clear last level pte, a tlb flush should be followed */
5cf0a76f 906static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 907 unsigned long start_pfn,
908 unsigned long last_pfn)
ba395927 909{
04b18e65 910 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 911 unsigned int large_page = 1;
310a5ab9 912 struct dma_pte *first_pte, *pte;
66eae846 913
04b18e65 914 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 915 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 916 BUG_ON(start_pfn > last_pfn);
ba395927 917
04b18e65 918 /* we don't need lock here; nobody else touches the iova range */
59c36286 919 do {
6dd9a7c7
YS		 920 large_page = 1;
921 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 922 if (!pte) {
6dd9a7c7 923 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 924 continue;
925 }
6dd9a7c7 926 do {
310a5ab9 927 dma_clear_pte(pte);
6dd9a7c7 928 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 929 pte++;
75e6bf96
DW		 930 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
931
310a5ab9
DW		 932 domain_flush_cache(domain, first_pte,
933 (void *)pte - (void *)first_pte);
59c36286
DW		 934
935 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 936}
937
3269ee0b
AW		 938static void dma_pte_free_level(struct dmar_domain *domain, int level,
939 struct dma_pte *pte, unsigned long pfn,
940 unsigned long start_pfn, unsigned long last_pfn)
941{
942 pfn = max(start_pfn, pfn);
943 pte = &pte[pfn_level_offset(pfn, level)];
944
945 do {
946 unsigned long level_pfn;
947 struct dma_pte *level_pte;
948
949 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
950 goto next;
951
952 level_pfn = pfn & level_mask(level - 1);
953 level_pte = phys_to_virt(dma_pte_addr(pte));
954
955 if (level > 2)
956 dma_pte_free_level(domain, level - 1, level_pte,
957 level_pfn, start_pfn, last_pfn);
958
959 /* If range covers entire pagetable, free it */
960 if (!(start_pfn > level_pfn ||
08336fd2 961 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 962 dma_clear_pte(pte);
963 domain_flush_cache(domain, pte, sizeof(*pte));
964 free_pgtable_page(level_pte);
965 }
966next:
967 pfn += level_size(level);
968 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
969}
970
ba395927
KA		 971/* free page table pages. last level pte should already be cleared */
972static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 973 unsigned long start_pfn,
974 unsigned long last_pfn)
ba395927 975{
6660c63a 976 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927 977
6660c63a
DW		 978 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
979 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 980 BUG_ON(start_pfn > last_pfn);
ba395927 981
f3a0a52f 982 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 983 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
984 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 985
ba395927 986 /* free pgd */
d794dc9b 987 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 988 free_pgtable_page(domain->pgd);
989 domain->pgd = NULL;
990 }
991}
992
ea8ea460
DW		 993/* When a page at a given level is being unlinked from its parent, we don't
994 need to *modify* it at all. All we need to do is make a list of all the
995 pages which can be freed just as soon as we've flushed the IOTLB and we
996 know the hardware page-walk will no longer touch them.
997 The 'pte' argument is the *parent* PTE, pointing to the page that is to
998 be freed. */
999static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1000 int level, struct dma_pte *pte,
1001 struct page *freelist)
1002{
1003 struct page *pg;
1004
1005 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1006 pg->freelist = freelist;
1007 freelist = pg;
1008
1009 if (level == 1)
1010 return freelist;
1011
1012 for (pte = page_address(pg); !first_pte_in_page(pte); pte++) {
1013 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1014 freelist = dma_pte_list_pagetables(domain, level - 1,
1015 pte, freelist);
1016 }
1017
1018 return freelist;
1019}
1020
1021static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1022 struct dma_pte *pte, unsigned long pfn,
1023 unsigned long start_pfn,
1024 unsigned long last_pfn,
1025 struct page *freelist)
1026{
1027 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1028
1029 pfn = max(start_pfn, pfn);
1030 pte = &pte[pfn_level_offset(pfn, level)];
1031
1032 do {
1033 unsigned long level_pfn;
1034
1035 if (!dma_pte_present(pte))
1036 goto next;
1037
1038 level_pfn = pfn & level_mask(level);
1039
1040 /* If range covers entire pagetable, free it */
1041 if (start_pfn <= level_pfn &&
1042 last_pfn >= level_pfn + level_size(level) - 1) {
1043 /* These suborbinate page tables are going away entirely. Don't
1044 bother to clear them; we're just going to *free* them. */
1045 if (level > 1 && !dma_pte_superpage(pte))
1046 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1047
1048 dma_clear_pte(pte);
1049 if (!first_pte)
1050 first_pte = pte;
1051 last_pte = pte;
1052 } else if (level > 1) {
1053 /* Recurse down into a level that isn't *entirely* obsolete */
1054 freelist = dma_pte_clear_level(domain, level - 1,
1055 phys_to_virt(dma_pte_addr(pte)),
1056 level_pfn, start_pfn, last_pfn,
1057 freelist);
1058 }
1059next:
1060 pfn += level_size(level);
1061 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1062
1063 if (first_pte)
1064 domain_flush_cache(domain, first_pte,
1065 (void *)++last_pte - (void *)first_pte);
1066
1067 return freelist;
1068}
1069
1070/* We can't just free the pages because the IOMMU may still be walking
1071 the page tables, and may have cached the intermediate levels. The
1072 pages can only be freed after the IOTLB flush has been done. */
1073struct page *domain_unmap(struct dmar_domain *domain,
1074 unsigned long start_pfn,
1075 unsigned long last_pfn)
1076{
1077 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1078 struct page *freelist = NULL;
1079
1080 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
1081 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1082 BUG_ON(start_pfn > last_pfn);
1083
1084 /* we don't need lock here; nobody else touches the iova range */
1085 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1086 domain->pgd, 0, start_pfn, last_pfn, NULL);
1087
1088 /* free pgd */
1089 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1090 struct page *pgd_page = virt_to_page(domain->pgd);
1091 pgd_page->freelist = freelist;
1092 freelist = pgd_page;
1093
1094 domain->pgd = NULL;
1095 }
1096
1097 return freelist;
1098}
1099
1100void dma_free_pagelist(struct page *freelist)
1101{
1102 struct page *pg;
1103
1104 while ((pg = freelist)) {
1105 freelist = pg->freelist;
1106 free_pgtable_page(page_address(pg));
1107 }
1108}
1109
ba395927
KA		 1110/* iommu handling */
1111static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1112{
1113 struct root_entry *root;
1114 unsigned long flags;
1115
4c923d47 1116 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 1117 if (!root)
1118 return -ENOMEM;
1119
5b6985ce 1120 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1121
1122 spin_lock_irqsave(&iommu->lock, flags);
1123 iommu->root_entry = root;
1124 spin_unlock_irqrestore(&iommu->lock, flags);
1125
1126 return 0;
1127}
1128
ba395927
KA		 1129static void iommu_set_root_entry(struct intel_iommu *iommu)
1130{
1131 void *addr;
c416daa9 1132 u32 sts;
ba395927
KA		 1133 unsigned long flag;
1134
1135 addr = iommu->root_entry;
1136
1f5b3c3f 1137 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1138 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
1139
c416daa9 1140 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1141
1142 /* Make sure hardware complete it */
1143 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1144 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1145
1f5b3c3f 1146 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1147}
1148
1149static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1150{
1151 u32 val;
1152 unsigned long flag;
1153
9af88143 1154 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1155 return;
ba395927 1156
1f5b3c3f 1157 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1158 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1159
1160 /* Make sure hardware complete it */
1161 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1162 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1163
1f5b3c3f 1164 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1165}
1166
1167/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1168static void __iommu_flush_context(struct intel_iommu *iommu,
1169 u16 did, u16 source_id, u8 function_mask,
1170 u64 type)
ba395927
KA		 1171{
1172 u64 val = 0;
1173 unsigned long flag;
1174
ba395927
KA		 1175 switch (type) {
1176 case DMA_CCMD_GLOBAL_INVL:
1177 val = DMA_CCMD_GLOBAL_INVL;
1178 break;
1179 case DMA_CCMD_DOMAIN_INVL:
1180 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1181 break;
1182 case DMA_CCMD_DEVICE_INVL:
1183 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1184 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1185 break;
1186 default:
1187 BUG();
1188 }
1189 val |= DMA_CCMD_ICC;
1190
1f5b3c3f 1191 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1192 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1193
1194 /* Make sure hardware complete it */
1195 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1196 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1197
1f5b3c3f 1198 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1199}
1200
ba395927 1201/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1202static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1203 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1204{
1205 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1206 u64 val = 0, val_iva = 0;
1207 unsigned long flag;
1208
ba395927
KA		 1209 switch (type) {
1210 case DMA_TLB_GLOBAL_FLUSH:
1211 /* global flush doesn't need set IVA_REG */
1212 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1213 break;
1214 case DMA_TLB_DSI_FLUSH:
1215 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1216 break;
1217 case DMA_TLB_PSI_FLUSH:
1218 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1219 /* IH bit is passed in as part of address */
ba395927
KA		 1220 val_iva = size_order | addr;
1221 break;
1222 default:
1223 BUG();
1224 }
1225 /* Note: set drain read/write */
1226#if 0
1227 /*
1228 * This is probably to be super secure.. Looks like we can
1229 * ignore it without any impact.
1230 */
1231 if (cap_read_drain(iommu->cap))
1232 val |= DMA_TLB_READ_DRAIN;
1233#endif
1234 if (cap_write_drain(iommu->cap))
1235 val |= DMA_TLB_WRITE_DRAIN;
1236
1f5b3c3f 1237 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1238 /* Note: Only uses first TLB reg currently */
1239 if (val_iva)
1240 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1241 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1242
1243 /* Make sure hardware complete it */
1244 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1245 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1246
1f5b3c3f 1247 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1248
1249 /* check IOTLB invalidation granularity */
1250 if (DMA_TLB_IAIG(val) == 0)
1251 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1252 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1253 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1254 (unsigned long long)DMA_TLB_IIRG(type),
1255 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1256}
1257
64ae892b
DW		 1258static struct device_domain_info *
1259iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1260 u8 bus, u8 devfn)
93a23a72
YZ		 1261{
1262 int found = 0;
1263 unsigned long flags;
1264 struct device_domain_info *info;
0bcb3e28 1265 struct pci_dev *pdev;
93a23a72
YZ		 1266
1267 if (!ecap_dev_iotlb_support(iommu->ecap))
1268 return NULL;
1269
1270 if (!iommu->qi)
1271 return NULL;
1272
1273 spin_lock_irqsave(&device_domain_lock, flags);
1274 list_for_each_entry(info, &domain->devices, link)
1275 if (info->bus == bus && info->devfn == devfn) {
1276 found = 1;
1277 break;
1278 }
1279 spin_unlock_irqrestore(&device_domain_lock, flags);
1280
0bcb3e28 1281 if (!found || !info->dev || !dev_is_pci(info->dev))
93a23a72
YZ		 1282 return NULL;
1283
0bcb3e28
DW		 1284 pdev = to_pci_dev(info->dev);
1285
1286 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
93a23a72
YZ		 1287 return NULL;
1288
0bcb3e28 1289 if (!dmar_find_matched_atsr_unit(pdev))
93a23a72
YZ		 1290 return NULL;
1291
93a23a72
YZ		 1292 return info;
1293}
1294
1295static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1296{
0bcb3e28 1297 if (!info || !dev_is_pci(info->dev))
93a23a72
YZ		 1298 return;
1299
0bcb3e28 1300 pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
93a23a72
YZ		 1301}
1302
1303static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1304{
0bcb3e28
DW		 1305 if (!info->dev || !dev_is_pci(info->dev) ||
1306 !pci_ats_enabled(to_pci_dev(info->dev)))
93a23a72
YZ		 1307 return;
1308
0bcb3e28 1309 pci_disable_ats(to_pci_dev(info->dev));
93a23a72
YZ		 1310}
1311
1312static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1313 u64 addr, unsigned mask)
1314{
1315 u16 sid, qdep;
1316 unsigned long flags;
1317 struct device_domain_info *info;
1318
1319 spin_lock_irqsave(&device_domain_lock, flags);
1320 list_for_each_entry(info, &domain->devices, link) {
0bcb3e28
DW		 1321 struct pci_dev *pdev;
1322 if (!info->dev || !dev_is_pci(info->dev))
1323 continue;
1324
1325 pdev = to_pci_dev(info->dev);
1326 if (!pci_ats_enabled(pdev))
93a23a72
YZ		 1327 continue;
1328
1329 sid = info->bus << 8 | info->devfn;
0bcb3e28 1330 qdep = pci_ats_queue_depth(pdev);
93a23a72
YZ		 1331 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1332 }
1333 spin_unlock_irqrestore(&device_domain_lock, flags);
1334}
1335
1f0ef2aa 1336static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1337 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1338{
9dd2fe89 1339 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1340 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1341
ba395927
KA		 1342 BUG_ON(pages == 0);
1343
ea8ea460
DW		 1344 if (ih)
1345 ih = 1 << 6;
ba395927 1346 /*
9dd2fe89
YZ		 1347 * Fallback to domain selective flush if no PSI support or the size is
1348 * too big.
ba395927
KA		 1349 * PSI requires page size to be 2 ^ x, and the base address is naturally
1350 * aligned to the size
1351 */
9dd2fe89
YZ		 1352 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1353 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1354 DMA_TLB_DSI_FLUSH);
9dd2fe89 1355 else
ea8ea460 1356 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1357 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1358
1359 /*
82653633
NA		 1360 * In caching mode, changes of pages from non-present to present require
1361 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1362 */
82653633 1363 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1364 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1365}
1366
f8bab735 1367static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1368{
1369 u32 pmen;
1370 unsigned long flags;
1371
1f5b3c3f 1372 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1373 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1374 pmen &= ~DMA_PMEN_EPM;
1375 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1376
1377 /* wait for the protected region status bit to clear */
1378 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1379 readl, !(pmen & DMA_PMEN_PRS), pmen);
1380
1f5b3c3f 1381 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1382}
1383
ba395927
KA		 1384static int iommu_enable_translation(struct intel_iommu *iommu)
1385{
1386 u32 sts;
1387 unsigned long flags;
1388
1f5b3c3f 1389 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1390 iommu->gcmd |= DMA_GCMD_TE;
1391 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1392
1393 /* Make sure hardware complete it */
1394 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1395 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1396
1f5b3c3f 1397 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1398 return 0;
1399}
1400
1401static int iommu_disable_translation(struct intel_iommu *iommu)
1402{
1403 u32 sts;
1404 unsigned long flag;
1405
1f5b3c3f 1406 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1407 iommu->gcmd &= ~DMA_GCMD_TE;
1408 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1409
1410 /* Make sure hardware complete it */
1411 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1412 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1413
1f5b3c3f 1414 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1415 return 0;
1416}
1417
3460a6d9 1418
ba395927
KA		 1419static int iommu_init_domains(struct intel_iommu *iommu)
1420{
1421 unsigned long ndomains;
1422 unsigned long nlongs;
1423
1424 ndomains = cap_ndoms(iommu->cap);
852bdb04
JL		 1425 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1426 iommu->seq_id, ndomains);
ba395927
KA		 1427 nlongs = BITS_TO_LONGS(ndomains);
1428
94a91b50
DD		 1429 spin_lock_init(&iommu->lock);
1430
ba395927
KA		 1431 /* TBD: there might be 64K domains,
1432 * consider other allocation for future chip
1433 */
1434 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1435 if (!iommu->domain_ids) {
852bdb04
JL		 1436 pr_err("IOMMU%d: allocating domain id array failed\n",
1437 iommu->seq_id);
ba395927
KA		 1438 return -ENOMEM;
1439 }
1440 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1441 GFP_KERNEL);
1442 if (!iommu->domains) {
852bdb04
JL		 1443 pr_err("IOMMU%d: allocating domain array failed\n",
1444 iommu->seq_id);
1445 kfree(iommu->domain_ids);
1446 iommu->domain_ids = NULL;
ba395927
KA		 1447 return -ENOMEM;
1448 }
1449
1450 /*
1451 * if Caching mode is set, then invalid translations are tagged
1452 * with domainid 0. Hence we need to pre-allocate it.
1453 */
1454 if (cap_caching_mode(iommu->cap))
1455 set_bit(0, iommu->domain_ids);
1456 return 0;
1457}
ba395927 1458
a868e6b7 1459static void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1460{
1461 struct dmar_domain *domain;
5ced12af 1462 int i, count;
c7151a8d 1463 unsigned long flags;
ba395927 1464
94a91b50 1465 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1466 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1467 /*
1468 * Domain id 0 is reserved for invalid translation
1469 * if hardware supports caching mode.
1470 */
1471 if (cap_caching_mode(iommu->cap) && i == 0)
1472 continue;
1473
94a91b50
DD		 1474 domain = iommu->domains[i];
1475 clear_bit(i, iommu->domain_ids);
1476
1477 spin_lock_irqsave(&domain->iommu_lock, flags);
5ced12af
JL		 1478 count = --domain->iommu_count;
1479 spin_unlock_irqrestore(&domain->iommu_lock, flags);
92d03cc8
JL		 1480 if (count == 0)
1481 domain_exit(domain);
5e98c4b1 1482 }
ba395927
KA		 1483 }
1484
1485 if (iommu->gcmd & DMA_GCMD_TE)
1486 iommu_disable_translation(iommu);
1487
ba395927
KA		 1488 kfree(iommu->domains);
1489 kfree(iommu->domain_ids);
a868e6b7
JL		 1490 iommu->domains = NULL;
1491 iommu->domain_ids = NULL;
ba395927 1492
d9630fe9
WH		 1493 g_iommus[iommu->seq_id] = NULL;
1494
ba395927
KA		 1495 /* free context mapping */
1496 free_context_table(iommu);
ba395927
KA		 1497}
1498
92d03cc8 1499static struct dmar_domain *alloc_domain(bool vm)
ba395927 1500{
92d03cc8
JL		 1501 /* domain id for virtual machine, it won't be set in context */
1502 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1503 struct dmar_domain *domain;
ba395927
KA		 1504
1505 domain = alloc_domain_mem();
1506 if (!domain)
1507 return NULL;
1508
4c923d47 1509 domain->nid = -1;
92d03cc8 1510 domain->iommu_count = 0;
1b198bb0 1511 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
2c2e2c38 1512 domain->flags = 0;
92d03cc8
JL		 1513 spin_lock_init(&domain->iommu_lock);
1514 INIT_LIST_HEAD(&domain->devices);
1515 if (vm) {
1516 domain->id = atomic_inc_return(&vm_domid);
1517 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
1518 }
2c2e2c38
FY		 1519
1520 return domain;
1521}
1522
1523static int iommu_attach_domain(struct dmar_domain *domain,
1524 struct intel_iommu *iommu)
1525{
1526 int num;
1527 unsigned long ndomains;
1528 unsigned long flags;
1529
ba395927
KA		 1530 ndomains = cap_ndoms(iommu->cap);
1531
1532 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1533
ba395927
KA		 1534 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1535 if (num >= ndomains) {
1536 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1537 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1538 return -ENOMEM;
ba395927
KA		 1539 }
1540
ba395927 1541 domain->id = num;
9ebd682e 1542 domain->iommu_count++;
2c2e2c38 1543 set_bit(num, iommu->domain_ids);
1b198bb0 1544 set_bit(iommu->seq_id, domain->iommu_bmp);
ba395927
KA		 1545 iommu->domains[num] = domain;
1546 spin_unlock_irqrestore(&iommu->lock, flags);
1547
2c2e2c38 1548 return 0;
ba395927
KA		 1549}
1550
2c2e2c38
FY		 1551static void iommu_detach_domain(struct dmar_domain *domain,
1552 struct intel_iommu *iommu)
ba395927
KA		 1553{
1554 unsigned long flags;
2c2e2c38 1555 int num, ndomains;
ba395927 1556
8c11e798 1557 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1558 ndomains = cap_ndoms(iommu->cap);
a45946ab 1559 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38 1560 if (iommu->domains[num] == domain) {
92d03cc8
JL		 1561 clear_bit(num, iommu->domain_ids);
1562 iommu->domains[num] = NULL;
2c2e2c38
FY		 1563 break;
1564 }
2c2e2c38 1565 }
8c11e798 1566 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1567}
1568
1569static struct iova_domain reserved_iova_list;
8a443df4 1570static struct lock_class_key reserved_rbtree_key;
ba395927 1571
51a63e67 1572static int dmar_init_reserved_ranges(void)
ba395927
KA		 1573{
1574 struct pci_dev *pdev = NULL;
1575 struct iova *iova;
1576 int i;
ba395927 1577
f661197e 1578 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1579
8a443df4
MG		 1580 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1581 &reserved_rbtree_key);
1582
ba395927
KA		 1583 /* IOAPIC ranges shouldn't be accessed by DMA */
1584 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1585 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1586 if (!iova) {
ba395927 1587 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1588 return -ENODEV;
1589 }
ba395927
KA		 1590
1591 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1592 for_each_pci_dev(pdev) {
1593 struct resource *r;
1594
1595 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1596 r = &pdev->resource[i];
1597 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1598 continue;
1a4a4551
DW		 1599 iova = reserve_iova(&reserved_iova_list,
1600 IOVA_PFN(r->start),
1601 IOVA_PFN(r->end));
51a63e67 1602 if (!iova) {
ba395927 1603 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1604 return -ENODEV;
1605 }
ba395927
KA		 1606 }
1607 }
51a63e67 1608 return 0;
ba395927
KA		 1609}
1610
1611static void domain_reserve_special_ranges(struct dmar_domain *domain)
1612{
1613 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1614}
1615
1616static inline int guestwidth_to_adjustwidth(int gaw)
1617{
1618 int agaw;
1619 int r = (gaw - 12) % 9;
1620
1621 if (r == 0)
1622 agaw = gaw;
1623 else
1624 agaw = gaw + 9 - r;
1625 if (agaw > 64)
1626 agaw = 64;
1627 return agaw;
1628}
1629
1630static int domain_init(struct dmar_domain *domain, int guest_width)
1631{
1632 struct intel_iommu *iommu;
1633 int adjust_width, agaw;
1634 unsigned long sagaw;
1635
f661197e 1636 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927
KA		 1637 domain_reserve_special_ranges(domain);
1638
1639 /* calculate AGAW */
8c11e798 1640 iommu = domain_get_iommu(domain);
ba395927
KA		 1641 if (guest_width > cap_mgaw(iommu->cap))
1642 guest_width = cap_mgaw(iommu->cap);
1643 domain->gaw = guest_width;
1644 adjust_width = guestwidth_to_adjustwidth(guest_width);
1645 agaw = width_to_agaw(adjust_width);
1646 sagaw = cap_sagaw(iommu->cap);
1647 if (!test_bit(agaw, &sagaw)) {
1648 /* hardware doesn't support it, choose a bigger one */
1649 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1650 agaw = find_next_bit(&sagaw, 5, agaw);
1651 if (agaw >= 5)
1652 return -ENODEV;
1653 }
1654 domain->agaw = agaw;
ba395927 1655
8e604097
WH		 1656 if (ecap_coherent(iommu->ecap))
1657 domain->iommu_coherency = 1;
1658 else
1659 domain->iommu_coherency = 0;
1660
58c610bd
SY		 1661 if (ecap_sc_support(iommu->ecap))
1662 domain->iommu_snooping = 1;
1663 else
1664 domain->iommu_snooping = 0;
1665
214e39aa
DW		 1666 if (intel_iommu_superpage)
1667 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1668 else
1669 domain->iommu_superpage = 0;
1670
4c923d47 1671 domain->nid = iommu->node;
c7151a8d 1672
ba395927 1673 /* always allocate the top pgd */
4c923d47 1674 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1675 if (!domain->pgd)
1676 return -ENOMEM;
5b6985ce 1677 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1678 return 0;
1679}
1680
1681static void domain_exit(struct dmar_domain *domain)
1682{
2c2e2c38
FY		 1683 struct dmar_drhd_unit *drhd;
1684 struct intel_iommu *iommu;
ea8ea460 1685 struct page *freelist = NULL;
ba395927
KA		 1686
1687 /* Domain 0 is reserved, so dont process it */
1688 if (!domain)
1689 return;
1690
7b668357
AW		 1691 /* Flush any lazy unmaps that may reference this domain */
1692 if (!intel_iommu_strict)
1693 flush_unmaps_timeout(0);
1694
92d03cc8 1695 /* remove associated devices */
ba395927 1696 domain_remove_dev_info(domain);
92d03cc8 1697
ba395927
KA		 1698 /* destroy iovas */
1699 put_iova_domain(&domain->iovad);
ba395927 1700
ea8ea460 1701 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1702
92d03cc8 1703 /* clear attached or cached domains */
0e242612 1704 rcu_read_lock();
2c2e2c38 1705 for_each_active_iommu(iommu, drhd)
92d03cc8
JL		 1706 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1707 test_bit(iommu->seq_id, domain->iommu_bmp))
2c2e2c38 1708 iommu_detach_domain(domain, iommu);
0e242612 1709 rcu_read_unlock();
2c2e2c38 1710
ea8ea460
DW		 1711 dma_free_pagelist(freelist);
1712
ba395927
KA		 1713 free_domain_mem(domain);
1714}
1715
64ae892b
DW		 1716static int domain_context_mapping_one(struct dmar_domain *domain,
1717 struct intel_iommu *iommu,
1718 u8 bus, u8 devfn, int translation)
ba395927
KA		 1719{
1720 struct context_entry *context;
ba395927 1721 unsigned long flags;
ea6606b0
WH		 1722 struct dma_pte *pgd;
1723 unsigned long num;
1724 unsigned long ndomains;
1725 int id;
1726 int agaw;
93a23a72 1727 struct device_domain_info *info = NULL;
ba395927
KA		 1728
1729 pr_debug("Set context mapping for %02x:%02x.%d\n",
1730 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1731
ba395927 1732 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1733 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1734 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1735
ba395927
KA		 1736 context = device_to_context_entry(iommu, bus, devfn);
1737 if (!context)
1738 return -ENOMEM;
1739 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1740 if (context_present(context)) {
ba395927
KA		 1741 spin_unlock_irqrestore(&iommu->lock, flags);
1742 return 0;
1743 }
1744
ea6606b0
WH		 1745 id = domain->id;
1746 pgd = domain->pgd;
1747
2c2e2c38
FY		 1748 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1749 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1750 int found = 0;
1751
1752 /* find an available domain id for this device in iommu */
1753 ndomains = cap_ndoms(iommu->cap);
a45946ab 1754 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1755 if (iommu->domains[num] == domain) {
1756 id = num;
1757 found = 1;
1758 break;
1759 }
ea6606b0
WH		 1760 }
1761
1762 if (found == 0) {
1763 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1764 if (num >= ndomains) {
1765 spin_unlock_irqrestore(&iommu->lock, flags);
1766 printk(KERN_ERR "IOMMU: no free domain ids\n");
1767 return -EFAULT;
1768 }
1769
1770 set_bit(num, iommu->domain_ids);
1771 iommu->domains[num] = domain;
1772 id = num;
1773 }
1774
1775 /* Skip top levels of page tables for
1776 * iommu which has less agaw than default.
1672af11 1777 * Unnecessary for PT mode.
ea6606b0 1778 */
1672af11
CW		 1779 if (translation != CONTEXT_TT_PASS_THROUGH) {
1780 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1781 pgd = phys_to_virt(dma_pte_addr(pgd));
1782 if (!dma_pte_present(pgd)) {
1783 spin_unlock_irqrestore(&iommu->lock, flags);
1784 return -ENOMEM;
1785 }
ea6606b0
WH		 1786 }
1787 }
1788 }
1789
1790 context_set_domain_id(context, id);
4ed0d3e6 1791
93a23a72 1792 if (translation != CONTEXT_TT_PASS_THROUGH) {
64ae892b 1793 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
93a23a72
YZ		 1794 translation = info ? CONTEXT_TT_DEV_IOTLB :
1795 CONTEXT_TT_MULTI_LEVEL;
1796 }
4ed0d3e6
FY		 1797 /*
1798 * In pass through mode, AW must be programmed to indicate the largest
1799 * AGAW value supported by hardware. And ASR is ignored by hardware.
1800 */
93a23a72 1801 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1802 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1803 else {
1804 context_set_address_root(context, virt_to_phys(pgd));
1805 context_set_address_width(context, iommu->agaw);
1806 }
4ed0d3e6
FY		 1807
1808 context_set_translation_type(context, translation);
c07e7d21
MM		 1809 context_set_fault_enable(context);
1810 context_set_present(context);
5331fe6f 1811 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1812
4c25a2c1
DW		 1813 /*
1814 * It's a non-present to present mapping. If hardware doesn't cache
1815 * non-present entry we only need to flush the write-buffer. If the
1816 * _does_ cache non-present entries, then it does so in the special
1817 * domain #0, which we have to flush:
1818 */
1819 if (cap_caching_mode(iommu->cap)) {
1820 iommu->flush.flush_context(iommu, 0,
1821 (((u16)bus) << 8) | devfn,
1822 DMA_CCMD_MASK_NOBIT,
1823 DMA_CCMD_DEVICE_INVL);
82653633 1824 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1825 } else {
ba395927 1826 iommu_flush_write_buffer(iommu);
4c25a2c1 1827 }
93a23a72 1828 iommu_enable_dev_iotlb(info);
ba395927 1829 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1830
1831 spin_lock_irqsave(&domain->iommu_lock, flags);
1b198bb0 1832 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
c7151a8d 1833 domain->iommu_count++;
4c923d47
SS		 1834 if (domain->iommu_count == 1)
1835 domain->nid = iommu->node;
58c610bd 1836 domain_update_iommu_cap(domain);
c7151a8d
WH		 1837 }
1838 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1839 return 0;
1840}
1841
1842static int
e1f167f3
DW		 1843domain_context_mapping(struct dmar_domain *domain, struct device *dev,
1844 int translation)
ba395927
KA		 1845{
1846 int ret;
e1f167f3 1847 struct pci_dev *pdev, *tmp, *parent;
64ae892b 1848 struct intel_iommu *iommu;
156baca8 1849 u8 bus, devfn;
64ae892b 1850
e1f167f3 1851 iommu = device_to_iommu(dev, &bus, &devfn);
64ae892b
DW		 1852 if (!iommu)
1853 return -ENODEV;
ba395927 1854
156baca8 1855 ret = domain_context_mapping_one(domain, iommu, bus, devfn,
4ed0d3e6 1856 translation);
e1f167f3 1857 if (ret || !dev_is_pci(dev))
ba395927
KA		 1858 return ret;
1859
1860 /* dependent device mapping */
e1f167f3 1861 pdev = to_pci_dev(dev);
ba395927
KA		 1862 tmp = pci_find_upstream_pcie_bridge(pdev);
1863 if (!tmp)
1864 return 0;
1865 /* Secondary interface's bus number and devfn 0 */
1866 parent = pdev->bus->self;
1867 while (parent != tmp) {
64ae892b 1868 ret = domain_context_mapping_one(domain, iommu,
276dbf99 1869 parent->bus->number,
4ed0d3e6 1870 parent->devfn, translation);
ba395927
KA		 1871 if (ret)
1872 return ret;
1873 parent = parent->bus->self;
1874 }
45e829ea 1875 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
64ae892b 1876 return domain_context_mapping_one(domain, iommu,
4ed0d3e6
FY		 1877 tmp->subordinate->number, 0,
1878 translation);
ba395927 1879 else /* this is a legacy PCI bridge */
64ae892b 1880 return domain_context_mapping_one(domain, iommu,
276dbf99 1881 tmp->bus->number,
4ed0d3e6
FY		 1882 tmp->devfn,
1883 translation);
ba395927
KA		 1884}
1885
e1f167f3 1886static int domain_context_mapped(struct device *dev)
ba395927
KA		 1887{
1888 int ret;
e1f167f3 1889 struct pci_dev *pdev, *tmp, *parent;
5331fe6f 1890 struct intel_iommu *iommu;
156baca8 1891 u8 bus, devfn;
5331fe6f 1892
e1f167f3 1893 iommu = device_to_iommu(dev, &bus, &devfn);
5331fe6f
WH		 1894 if (!iommu)
1895 return -ENODEV;
ba395927 1896
156baca8 1897 ret = device_context_mapped(iommu, bus, devfn);
e1f167f3 1898 if (!ret || !dev_is_pci(dev))
ba395927 1899 return ret;
e1f167f3 1900
ba395927 1901 /* dependent device mapping */
e1f167f3 1902 pdev = to_pci_dev(dev);
ba395927
KA		 1903 tmp = pci_find_upstream_pcie_bridge(pdev);
1904 if (!tmp)
1905 return ret;
1906 /* Secondary interface's bus number and devfn 0 */
1907 parent = pdev->bus->self;
1908 while (parent != tmp) {
8c11e798 1909 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1910 parent->devfn);
ba395927
KA		 1911 if (!ret)
1912 return ret;
1913 parent = parent->bus->self;
1914 }
5f4d91a1 1915 if (pci_is_pcie(tmp))
276dbf99
DW		 1916 return device_context_mapped(iommu, tmp->subordinate->number,
1917 0);
ba395927 1918 else
276dbf99
DW		 1919 return device_context_mapped(iommu, tmp->bus->number,
1920 tmp->devfn);
ba395927
KA		 1921}
1922
f532959b
FY		 1923/* Returns a number of VTD pages, but aligned to MM page size */
1924static inline unsigned long aligned_nrpages(unsigned long host_addr,
1925 size_t size)
1926{
1927 host_addr &= ~PAGE_MASK;
1928 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1929}
1930
6dd9a7c7
YS		 1931/* Return largest possible superpage level for a given mapping */
1932static inline int hardware_largepage_caps(struct dmar_domain *domain,
1933 unsigned long iov_pfn,
1934 unsigned long phy_pfn,
1935 unsigned long pages)
1936{
1937 int support, level = 1;
1938 unsigned long pfnmerge;
1939
1940 support = domain->iommu_superpage;
1941
1942 /* To use a large page, the virtual *and* physical addresses
1943 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1944 of them will mean we have to use smaller pages. So just
1945 merge them and check both at once. */
1946 pfnmerge = iov_pfn | phy_pfn;
1947
1948 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1949 pages >>= VTD_STRIDE_SHIFT;
1950 if (!pages)
1951 break;
1952 pfnmerge >>= VTD_STRIDE_SHIFT;
1953 level++;
1954 support--;
1955 }
1956 return level;
1957}
1958
9051aa02
DW		 1959static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1960 struct scatterlist *sg, unsigned long phys_pfn,
1961 unsigned long nr_pages, int prot)
e1605495
DW		 1962{
1963 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1964 phys_addr_t uninitialized_var(pteval);
e1605495 1965 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1966 unsigned long sg_res;
6dd9a7c7
YS		 1967 unsigned int largepage_lvl = 0;
1968 unsigned long lvl_pages = 0;
e1605495
DW		 1969
1970 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1971
1972 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1973 return -EINVAL;
1974
1975 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1976
9051aa02
DW		 1977 if (sg)
1978 sg_res = 0;
1979 else {
1980 sg_res = nr_pages + 1;
1981 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1982 }
1983
6dd9a7c7 1984 while (nr_pages > 0) {
c85994e4
DW		 1985 uint64_t tmp;
1986
e1605495 1987 if (!sg_res) {
f532959b 1988 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1989 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1990 sg->dma_length = sg->length;
1991 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1992 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1993 }
6dd9a7c7 1994
e1605495 1995 if (!pte) {
6dd9a7c7
YS		 1996 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1997
5cf0a76f 1998 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 1999 if (!pte)
2000 return -ENOMEM;
6dd9a7c7 2001 /* It is large page*/
6491d4d0 2002 if (largepage_lvl > 1) {
6dd9a7c7 2003 pteval |= DMA_PTE_LARGE_PAGE;
6491d4d0
WD		 2004 /* Ensure that old small page tables are removed to make room
2005 for superpage, if they exist. */
2006 dma_pte_clear_range(domain, iov_pfn,
2007 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
2008 dma_pte_free_pagetable(domain, iov_pfn,
2009 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
2010 } else {
6dd9a7c7 2011 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 2012 }
6dd9a7c7 2013
e1605495
DW		 2014 }
2015 /* We don't need lock here, nobody else
2016 * touches the iova range
2017 */
7766a3fb 2018 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 2019 if (tmp) {
1bf20f0d 2020 static int dumps = 5;
c85994e4
DW		 2021 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2022 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 2023 if (dumps) {
2024 dumps--;
2025 debug_dma_dump_mappings(NULL);
2026 }
2027 WARN_ON(1);
2028 }
6dd9a7c7
YS		 2029
2030 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2031
2032 BUG_ON(nr_pages < lvl_pages);
2033 BUG_ON(sg_res < lvl_pages);
2034
2035 nr_pages -= lvl_pages;
2036 iov_pfn += lvl_pages;
2037 phys_pfn += lvl_pages;
2038 pteval += lvl_pages * VTD_PAGE_SIZE;
2039 sg_res -= lvl_pages;
2040
2041 /* If the next PTE would be the first in a new page, then we
2042 need to flush the cache on the entries we've just written.
2043 And then we'll need to recalculate 'pte', so clear it and
2044 let it get set again in the if (!pte) block above.
2045
2046 If we're done (!nr_pages) we need to flush the cache too.
2047
2048 Also if we've been setting superpages, we may need to
2049 recalculate 'pte' and switch back to smaller pages for the
2050 end of the mapping, if the trailing size is not enough to
2051 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2052 pte++;
6dd9a7c7
YS		 2053 if (!nr_pages || first_pte_in_page(pte) ||
2054 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2055 domain_flush_cache(domain, first_pte,
2056 (void *)pte - (void *)first_pte);
2057 pte = NULL;
2058 }
6dd9a7c7
YS		 2059
2060 if (!sg_res && nr_pages)
e1605495
DW		 2061 sg = sg_next(sg);
2062 }
2063 return 0;
2064}
2065
9051aa02
DW		 2066static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2067 struct scatterlist *sg, unsigned long nr_pages,
2068 int prot)
ba395927 2069{
9051aa02
DW		 2070 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2071}
6f6a00e4 2072
9051aa02
DW		 2073static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2074 unsigned long phys_pfn, unsigned long nr_pages,
2075 int prot)
2076{
2077 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2078}
2079
c7151a8d 2080static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2081{
c7151a8d
WH		 2082 if (!iommu)
2083 return;
8c11e798
WH		 2084
2085 clear_context_table(iommu, bus, devfn);
2086 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2087 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2088 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2089}
2090
109b9b04
DW		 2091static inline void unlink_domain_info(struct device_domain_info *info)
2092{
2093 assert_spin_locked(&device_domain_lock);
2094 list_del(&info->link);
2095 list_del(&info->global);
2096 if (info->dev)
0bcb3e28 2097 info->dev->archdata.iommu = NULL;
109b9b04
DW		 2098}
2099
ba395927
KA		 2100static void domain_remove_dev_info(struct dmar_domain *domain)
2101{
2102 struct device_domain_info *info;
92d03cc8 2103 unsigned long flags, flags2;
ba395927
KA		 2104
2105 spin_lock_irqsave(&device_domain_lock, flags);
2106 while (!list_empty(&domain->devices)) {
2107 info = list_entry(domain->devices.next,
2108 struct device_domain_info, link);
109b9b04 2109 unlink_domain_info(info);
ba395927
KA		 2110 spin_unlock_irqrestore(&device_domain_lock, flags);
2111
93a23a72 2112 iommu_disable_dev_iotlb(info);
7c7faa11 2113 iommu_detach_dev(info->iommu, info->bus, info->devfn);
ba395927 2114
92d03cc8 2115 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
7c7faa11 2116 iommu_detach_dependent_devices(info->iommu, info->dev);
92d03cc8
JL		 2117 /* clear this iommu in iommu_bmp, update iommu count
2118 * and capabilities
2119 */
2120 spin_lock_irqsave(&domain->iommu_lock, flags2);
7c7faa11 2121 if (test_and_clear_bit(info->iommu->seq_id,
92d03cc8
JL		 2122 domain->iommu_bmp)) {
2123 domain->iommu_count--;
2124 domain_update_iommu_cap(domain);
2125 }
2126 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
2127 }
2128
2129 free_devinfo_mem(info);
ba395927
KA		 2130 spin_lock_irqsave(&device_domain_lock, flags);
2131 }
2132 spin_unlock_irqrestore(&device_domain_lock, flags);
2133}
2134
2135/*
2136 * find_domain
1525a29a 2137 * Note: we use struct device->archdata.iommu stores the info
ba395927 2138 */
1525a29a 2139static struct dmar_domain *find_domain(struct device *dev)
ba395927
KA		 2140{
2141 struct device_domain_info *info;
2142
2143 /* No lock here, assumes no domain exit in normal case */
1525a29a 2144 info = dev->archdata.iommu;
ba395927
KA		 2145 if (info)
2146 return info->domain;
2147 return NULL;
2148}
2149
5a8f40e8 2150static inline struct device_domain_info *
745f2586
JL		 2151dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2152{
2153 struct device_domain_info *info;
2154
2155 list_for_each_entry(info, &device_domain_list, global)
41e80dca 2156 if (info->iommu->segment == segment && info->bus == bus &&
745f2586 2157 info->devfn == devfn)
5a8f40e8 2158 return info;
745f2586
JL		 2159
2160 return NULL;
2161}
2162
5a8f40e8 2163static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
41e80dca 2164 int bus, int devfn,
b718cd3d
DW		 2165 struct device *dev,
2166 struct dmar_domain *domain)
745f2586 2167{
5a8f40e8 2168 struct dmar_domain *found = NULL;
745f2586
JL		 2169 struct device_domain_info *info;
2170 unsigned long flags;
2171
2172 info = alloc_devinfo_mem();
2173 if (!info)
b718cd3d 2174 return NULL;
745f2586 2175
745f2586
JL		 2176 info->bus = bus;
2177 info->devfn = devfn;
2178 info->dev = dev;
2179 info->domain = domain;
5a8f40e8 2180 info->iommu = iommu;
745f2586
JL		 2181 if (!dev)
2182 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2183
2184 spin_lock_irqsave(&device_domain_lock, flags);
2185 if (dev)
0bcb3e28 2186 found = find_domain(dev);
5a8f40e8
DW		 2187 else {
2188 struct device_domain_info *info2;
41e80dca 2189 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
5a8f40e8
DW		 2190 if (info2)
2191 found = info2->domain;
2192 }
745f2586
JL		 2193 if (found) {
2194 spin_unlock_irqrestore(&device_domain_lock, flags);
2195 free_devinfo_mem(info);
b718cd3d
DW		 2196 /* Caller must free the original domain */
2197 return found;
745f2586
JL		 2198 }
2199
b718cd3d
DW		 2200 list_add(&info->link, &domain->devices);
2201 list_add(&info->global, &device_domain_list);
2202 if (dev)
2203 dev->archdata.iommu = info;
2204 spin_unlock_irqrestore(&device_domain_lock, flags);
2205
2206 return domain;
745f2586
JL		 2207}
2208
ba395927 2209/* domain is initialized */
146922ec 2210static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
ba395927 2211{
e85bb5d4 2212 struct dmar_domain *domain, *free = NULL;
5a8f40e8
DW		 2213 struct intel_iommu *iommu = NULL;
2214 struct device_domain_info *info;
146922ec 2215 struct pci_dev *dev_tmp = NULL;
ba395927 2216 unsigned long flags;
146922ec 2217 u8 bus, devfn, bridge_bus, bridge_devfn;
ba395927 2218
146922ec 2219 domain = find_domain(dev);
ba395927
KA		 2220 if (domain)
2221 return domain;
2222
146922ec
DW		 2223 if (dev_is_pci(dev)) {
2224 struct pci_dev *pdev = to_pci_dev(dev);
2225 u16 segment;
276dbf99 2226
146922ec
DW		 2227 segment = pci_domain_nr(pdev->bus);
2228 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
2229 if (dev_tmp) {
2230 if (pci_is_pcie(dev_tmp)) {
2231 bridge_bus = dev_tmp->subordinate->number;
2232 bridge_devfn = 0;
2233 } else {
2234 bridge_bus = dev_tmp->bus->number;
2235 bridge_devfn = dev_tmp->devfn;
2236 }
2237 spin_lock_irqsave(&device_domain_lock, flags);
2238 info = dmar_search_domain_by_dev_info(segment, bus, devfn);
2239 if (info) {
2240 iommu = info->iommu;
2241 domain = info->domain;
2242 }
2243 spin_unlock_irqrestore(&device_domain_lock, flags);
2244 /* pcie-pci bridge already has a domain, uses it */
2245 if (info)
2246 goto found_domain;
5a8f40e8 2247 }
ba395927
KA		 2248 }
2249
146922ec
DW		 2250 iommu = device_to_iommu(dev, &bus, &devfn);
2251 if (!iommu)
2252 goto error;
ba395927 2253
146922ec 2254 /* Allocate and initialize new domain for the device */
92d03cc8 2255 domain = alloc_domain(false);
745f2586
JL		 2256 if (!domain)
2257 goto error;
2258 if (iommu_attach_domain(domain, iommu)) {
2fe9723d 2259 free_domain_mem(domain);
ba395927 2260 goto error;
2c2e2c38 2261 }
e85bb5d4
JL		 2262 free = domain;
2263 if (domain_init(domain, gaw))
ba395927 2264 goto error;
ba395927
KA		 2265
2266 /* register pcie-to-pci device */
2267 if (dev_tmp) {
146922ec
DW		 2268 domain = dmar_insert_dev_info(iommu, bridge_bus, bridge_devfn,
2269 NULL, domain);
b718cd3d 2270 if (!domain)
ba395927 2271 goto error;
ba395927
KA		 2272 }
2273
2274found_domain:
146922ec 2275 domain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
ba395927 2276error:
b718cd3d 2277 if (free != domain)
e85bb5d4 2278 domain_exit(free);
b718cd3d
DW		 2279
2280 return domain;
ba395927
KA		 2281}
2282
2c2e2c38 2283static int iommu_identity_mapping;
e0fc7e0b
DW		 2284#define IDENTMAP_ALL 1
2285#define IDENTMAP_GFX 2
2286#define IDENTMAP_AZALIA 4
2c2e2c38 2287
b213203e
DW		 2288static int iommu_domain_identity_map(struct dmar_domain *domain,
2289 unsigned long long start,
2290 unsigned long long end)
ba395927 2291{
c5395d5c
DW		 2292 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2293 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2294
2295 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2296 dma_to_mm_pfn(last_vpfn))) {
ba395927 2297 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2298 return -ENOMEM;
ba395927
KA		 2299 }
2300
c5395d5c
DW		 2301 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2302 start, end, domain->id);
ba395927
KA		 2303 /*
2304 * RMRR range might have overlap with physical memory range,
2305 * clear it first
2306 */
c5395d5c 2307 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2308
c5395d5c
DW		 2309 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2310 last_vpfn - first_vpfn + 1,
61df7443 2311 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2312}
2313
0b9d9753 2314static int iommu_prepare_identity_map(struct device *dev,
b213203e
DW		 2315 unsigned long long start,
2316 unsigned long long end)
2317{
2318 struct dmar_domain *domain;
2319 int ret;
2320
0b9d9753 2321 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2322 if (!domain)
2323 return -ENOMEM;
2324
19943b0e
DW		 2325 /* For _hardware_ passthrough, don't bother. But for software
2326 passthrough, we do it anyway -- it may indicate a memory
2327 range which is reserved in E820, so which didn't get set
2328 up to start with in si_domain */
2329 if (domain == si_domain && hw_pass_through) {
2330 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
0b9d9753 2331 dev_name(dev), start, end);
19943b0e
DW		 2332 return 0;
2333 }
2334
2335 printk(KERN_INFO
2336 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
0b9d9753 2337 dev_name(dev), start, end);
2ff729f5 2338
5595b528
DW		 2339 if (end < start) {
2340 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2341 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2342 dmi_get_system_info(DMI_BIOS_VENDOR),
2343 dmi_get_system_info(DMI_BIOS_VERSION),
2344 dmi_get_system_info(DMI_PRODUCT_VERSION));
2345 ret = -EIO;
2346 goto error;
2347 }
2348
2ff729f5
DW		 2349 if (end >> agaw_to_width(domain->agaw)) {
2350 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2351 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2352 agaw_to_width(domain->agaw),
2353 dmi_get_system_info(DMI_BIOS_VENDOR),
2354 dmi_get_system_info(DMI_BIOS_VERSION),
2355 dmi_get_system_info(DMI_PRODUCT_VERSION));
2356 ret = -EIO;
2357 goto error;
2358 }
19943b0e 2359
b213203e 2360 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2361 if (ret)
2362 goto error;
2363
2364 /* context entry init */
0b9d9753 2365 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2366 if (ret)
2367 goto error;
2368
2369 return 0;
2370
2371 error:
ba395927
KA		 2372 domain_exit(domain);
2373 return ret;
ba395927
KA		 2374}
2375
2376static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
0b9d9753 2377 struct device *dev)
ba395927 2378{
0b9d9753 2379 if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927 2380 return 0;
0b9d9753
DW		 2381 return iommu_prepare_identity_map(dev, rmrr->base_address,
2382 rmrr->end_address);
ba395927
KA		 2383}
2384
d3f13810 2385#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2386static inline void iommu_prepare_isa(void)
2387{
2388 struct pci_dev *pdev;
2389 int ret;
2390
2391 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2392 if (!pdev)
2393 return;
2394
c7ab48d2 2395 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
0b9d9753 2396 ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2397
2398 if (ret)
c7ab48d2
DW		 2399 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2400 "floppy might not work\n");
49a0429e
KA		 2401
2402}
2403#else
2404static inline void iommu_prepare_isa(void)
2405{
2406 return;
2407}
d3f13810 2408#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2409
2c2e2c38 2410static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2411
071e1374 2412static int __init si_domain_init(int hw)
2c2e2c38
FY		 2413{
2414 struct dmar_drhd_unit *drhd;
2415 struct intel_iommu *iommu;
c7ab48d2 2416 int nid, ret = 0;
2c2e2c38 2417
92d03cc8 2418 si_domain = alloc_domain(false);
2c2e2c38
FY		 2419 if (!si_domain)
2420 return -EFAULT;
2421
92d03cc8
JL		 2422 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2423
2c2e2c38
FY		 2424 for_each_active_iommu(iommu, drhd) {
2425 ret = iommu_attach_domain(si_domain, iommu);
2426 if (ret) {
2427 domain_exit(si_domain);
2428 return -EFAULT;
2429 }
2430 }
2431
2432 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2433 domain_exit(si_domain);
2434 return -EFAULT;
2435 }
2436
9544c003
JL		 2437 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2438 si_domain->id);
2c2e2c38 2439
19943b0e
DW		 2440 if (hw)
2441 return 0;
2442
c7ab48d2 2443 for_each_online_node(nid) {
5dfe8660
TH		 2444 unsigned long start_pfn, end_pfn;
2445 int i;
2446
2447 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2448 ret = iommu_domain_identity_map(si_domain,
2449 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2450 if (ret)
2451 return ret;
2452 }
c7ab48d2
DW		 2453 }
2454
2c2e2c38
FY		 2455 return 0;
2456}
2457
9b226624 2458static int identity_mapping(struct device *dev)
2c2e2c38
FY		 2459{
2460 struct device_domain_info *info;
2461
2462 if (likely(!iommu_identity_mapping))
2463 return 0;
2464
9b226624 2465 info = dev->archdata.iommu;
cb452a40
MT		 2466 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2467 return (info->domain == si_domain);
2c2e2c38 2468
2c2e2c38
FY		 2469 return 0;
2470}
2471
2472static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2473 struct pci_dev *pdev,
2474 int translation)
2c2e2c38 2475{
0ac72664 2476 struct dmar_domain *ndomain;
5a8f40e8 2477 struct intel_iommu *iommu;
156baca8 2478 u8 bus, devfn;
5fe60f4e 2479 int ret;
2c2e2c38 2480
156baca8 2481 iommu = device_to_iommu(&pdev->dev, &bus, &devfn);
5a8f40e8
DW		 2482 if (!iommu)
2483 return -ENODEV;
2484
156baca8 2485 ndomain = dmar_insert_dev_info(iommu, bus, devfn, &pdev->dev, domain);
0ac72664
DW		 2486 if (ndomain != domain)
2487 return -EBUSY;
2c2e2c38 2488
e1f167f3 2489 ret = domain_context_mapping(domain, &pdev->dev, translation);
e2ad23d0 2490 if (ret) {
e2f8c5f6 2491 domain_remove_one_dev_info(domain, pdev);
e2ad23d0
DW		 2492 return ret;
2493 }
2494
2c2e2c38
FY		 2495 return 0;
2496}
2497
0b9d9753 2498static bool device_has_rmrr(struct device *dev)
ea2447f7
TM		 2499{
2500 struct dmar_rmrr_unit *rmrr;
832bd858 2501 struct device *tmp;
ea2447f7
TM		 2502 int i;
2503
0e242612 2504 rcu_read_lock();
ea2447f7 2505 for_each_rmrr_units(rmrr) {
b683b230
JL		 2506 /*
2507 * Return TRUE if this RMRR contains the device that
2508 * is passed in.
2509 */
2510 for_each_active_dev_scope(rmrr->devices,
2511 rmrr->devices_cnt, i, tmp)
0b9d9753 2512 if (tmp == dev) {
0e242612 2513 rcu_read_unlock();
ea2447f7 2514 return true;
b683b230 2515 }
ea2447f7 2516 }
0e242612 2517 rcu_read_unlock();
ea2447f7
TM		 2518 return false;
2519}
2520
6941af28
DW		 2521static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2522{
ea2447f7
TM		 2523
2524 /*
2525 * We want to prevent any device associated with an RMRR from
2526 * getting placed into the SI Domain. This is done because
2527 * problems exist when devices are moved in and out of domains
2528 * and their respective RMRR info is lost. We exempt USB devices
2529 * from this process due to their usage of RMRRs that are known
2530 * to not be needed after BIOS hand-off to OS.
2531 */
0b9d9753 2532 if (device_has_rmrr(&pdev->dev) &&
ea2447f7
TM		 2533 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2534 return 0;
2535
e0fc7e0b
DW		 2536 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2537 return 1;
2538
2539 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2540 return 1;
2541
2542 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2543 return 0;
6941af28 2544
3dfc813d
DW		 2545 /*
2546 * We want to start off with all devices in the 1:1 domain, and
2547 * take them out later if we find they can't access all of memory.
2548 *
2549 * However, we can't do this for PCI devices behind bridges,
2550 * because all PCI devices behind the same bridge will end up
2551 * with the same source-id on their transactions.
2552 *
2553 * Practically speaking, we can't change things around for these
2554 * devices at run-time, because we can't be sure there'll be no
2555 * DMA transactions in flight for any of their siblings.
2556 *
2557 * So PCI devices (unless they're on the root bus) as well as
2558 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2559 * the 1:1 domain, just in _case_ one of their siblings turns out
2560 * not to be able to map all of memory.
2561 */
5f4d91a1 2562 if (!pci_is_pcie(pdev)) {
3dfc813d
DW		 2563 if (!pci_is_root_bus(pdev->bus))
2564 return 0;
2565 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2566 return 0;
62f87c0e 2567 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d
DW		 2568 return 0;
2569
2570 /*
2571 * At boot time, we don't yet know if devices will be 64-bit capable.
2572 * Assume that they will -- if they turn out not to be, then we can
2573 * take them out of the 1:1 domain later.
2574 */
8fcc5372
CW		 2575 if (!startup) {
2576 /*
2577 * If the device's dma_mask is less than the system's memory
2578 * size then this is not a candidate for identity mapping.
2579 */
2580 u64 dma_mask = pdev->dma_mask;
2581
2582 if (pdev->dev.coherent_dma_mask &&
2583 pdev->dev.coherent_dma_mask < dma_mask)
2584 dma_mask = pdev->dev.coherent_dma_mask;
2585
2586 return dma_mask >= dma_get_required_mask(&pdev->dev);
2587 }
6941af28
DW		 2588
2589 return 1;
2590}
2591
071e1374 2592static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2593{
2c2e2c38
FY		 2594 struct pci_dev *pdev = NULL;
2595 int ret;
2596
19943b0e 2597 ret = si_domain_init(hw);
2c2e2c38
FY		 2598 if (ret)
2599 return -EFAULT;
2600
2c2e2c38 2601 for_each_pci_dev(pdev) {
6941af28 2602 if (iommu_should_identity_map(pdev, 1)) {
5fe60f4e 2603 ret = domain_add_dev_info(si_domain, pdev,
eae460b6
MT		 2604 hw ? CONTEXT_TT_PASS_THROUGH :
2605 CONTEXT_TT_MULTI_LEVEL);
2606 if (ret) {
2607 /* device not associated with an iommu */
2608 if (ret == -ENODEV)
2609 continue;
62edf5dc 2610 return ret;
eae460b6
MT		 2611 }
2612 pr_info("IOMMU: %s identity mapping for device %s\n",
2613 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2614 }
2c2e2c38
FY		 2615 }
2616
2617 return 0;
2618}
2619
b779260b 2620static int __init init_dmars(void)
ba395927
KA		 2621{
2622 struct dmar_drhd_unit *drhd;
2623 struct dmar_rmrr_unit *rmrr;
832bd858 2624 struct device *dev;
ba395927 2625 struct intel_iommu *iommu;
9d783ba0 2626 int i, ret;
2c2e2c38 2627
ba395927
KA		 2628 /*
2629 * for each drhd
2630 * allocate root
2631 * initialize and program root entry to not present
2632 * endfor
2633 */
2634 for_each_drhd_unit(drhd) {
5e0d2a6f 2635 /*
2636 * lock not needed as this is only incremented in the single
2637 * threaded kernel __init code path all other access are read
2638 * only
2639 */
1b198bb0
MT		 2640 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2641 g_num_of_iommus++;
2642 continue;
2643 }
2644 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2645 IOMMU_UNITS_SUPPORTED);
5e0d2a6f 2646 }
2647
d9630fe9
WH		 2648 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2649 GFP_KERNEL);
2650 if (!g_iommus) {
2651 printk(KERN_ERR "Allocating global iommu array failed\n");
2652 ret = -ENOMEM;
2653 goto error;
2654 }
2655
80b20dd8 2656 deferred_flush = kzalloc(g_num_of_iommus *
2657 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2658 if (!deferred_flush) {
5e0d2a6f 2659 ret = -ENOMEM;
989d51fc 2660 goto free_g_iommus;
5e0d2a6f 2661 }
2662
7c919779 2663 for_each_active_iommu(iommu, drhd) {
d9630fe9 2664 g_iommus[iommu->seq_id] = iommu;
ba395927 2665
e61d98d8
SS		 2666 ret = iommu_init_domains(iommu);
2667 if (ret)
989d51fc 2668 goto free_iommu;
e61d98d8 2669
ba395927
KA		 2670 /*
2671 * TBD:
2672 * we could share the same root & context tables
25985edc 2673 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2674 */
2675 ret = iommu_alloc_root_entry(iommu);
2676 if (ret) {
2677 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
989d51fc 2678 goto free_iommu;
ba395927 2679 }
4ed0d3e6 2680 if (!ecap_pass_through(iommu->ecap))
19943b0e 2681 hw_pass_through = 0;
ba395927
KA		 2682 }
2683
1531a6a6
SS		 2684 /*
2685 * Start from the sane iommu hardware state.
2686 */
7c919779 2687 for_each_active_iommu(iommu, drhd) {
1531a6a6
SS		 2688 /*
2689 * If the queued invalidation is already initialized by us
2690 * (for example, while enabling interrupt-remapping) then
2691 * we got the things already rolling from a sane state.
2692 */
2693 if (iommu->qi)
2694 continue;
2695
2696 /*
2697 * Clear any previous faults.
2698 */
2699 dmar_fault(-1, iommu);
2700 /*
2701 * Disable queued invalidation if supported and already enabled
2702 * before OS handover.
2703 */
2704 dmar_disable_qi(iommu);
2705 }
2706
7c919779 2707 for_each_active_iommu(iommu, drhd) {
a77b67d4
YS		 2708 if (dmar_enable_qi(iommu)) {
2709 /*
2710 * Queued Invalidate not enabled, use Register Based
2711 * Invalidate
2712 */
2713 iommu->flush.flush_context = __iommu_flush_context;
2714 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2715 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2716 "invalidation\n",
680a7524 2717 iommu->seq_id,
b4e0f9eb 2718 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2719 } else {
2720 iommu->flush.flush_context = qi_flush_context;
2721 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2722 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2723 "invalidation\n",
680a7524 2724 iommu->seq_id,
b4e0f9eb 2725 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2726 }
2727 }
2728
19943b0e 2729 if (iommu_pass_through)
e0fc7e0b
DW		 2730 iommu_identity_mapping |= IDENTMAP_ALL;
2731
d3f13810 2732#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2733 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2734#endif
e0fc7e0b
DW		 2735
2736 check_tylersburg_isoch();
2737
ba395927 2738 /*
19943b0e
DW		 2739 * If pass through is not set or not enabled, setup context entries for
2740 * identity mappings for rmrr, gfx, and isa and may fall back to static
2741 * identity mapping if iommu_identity_mapping is set.
ba395927 2742 */
19943b0e
DW		 2743 if (iommu_identity_mapping) {
2744 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2745 if (ret) {
19943b0e 2746 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
989d51fc 2747 goto free_iommu;
ba395927
KA		 2748 }
2749 }
ba395927 2750 /*
19943b0e
DW		 2751 * For each rmrr
2752 * for each dev attached to rmrr
2753 * do
2754 * locate drhd for dev, alloc domain for dev
2755 * allocate free domain
2756 * allocate page table entries for rmrr
2757 * if context not allocated for bus
2758 * allocate and init context
2759 * set present in root table for this bus
2760 * init context with domain, translation etc
2761 * endfor
2762 * endfor
ba395927 2763 */
19943b0e
DW		 2764 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2765 for_each_rmrr_units(rmrr) {
b683b230
JL		 2766 /* some BIOS lists non-exist devices in DMAR table. */
2767 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
832bd858 2768 i, dev) {
0b9d9753 2769 ret = iommu_prepare_rmrr_dev(rmrr, dev);
19943b0e
DW		 2770 if (ret)
2771 printk(KERN_ERR
2772 "IOMMU: mapping reserved region failed\n");
ba395927 2773 }
4ed0d3e6 2774 }
49a0429e 2775
19943b0e
DW		 2776 iommu_prepare_isa();
2777
ba395927
KA		 2778 /*
2779 * for each drhd
2780 * enable fault log
2781 * global invalidate context cache
2782 * global invalidate iotlb
2783 * enable translation
2784 */
7c919779 2785 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2786 if (drhd->ignored) {
2787 /*
2788 * we always have to disable PMRs or DMA may fail on
2789 * this device
2790 */
2791 if (force_on)
7c919779 2792 iommu_disable_protect_mem_regions(iommu);
ba395927 2793 continue;
51a63e67 2794 }
ba395927
KA		 2795
2796 iommu_flush_write_buffer(iommu);
2797
3460a6d9
KA		 2798 ret = dmar_set_interrupt(iommu);
2799 if (ret)
989d51fc 2800 goto free_iommu;
3460a6d9 2801
ba395927
KA		 2802 iommu_set_root_entry(iommu);
2803
4c25a2c1 2804 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2805 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2806
ba395927
KA		 2807 ret = iommu_enable_translation(iommu);
2808 if (ret)
989d51fc 2809 goto free_iommu;
b94996c9
DW		 2810
2811 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2812 }
2813
2814 return 0;
989d51fc
JL		 2815
2816free_iommu:
7c919779 2817 for_each_active_iommu(iommu, drhd)
a868e6b7 2818 free_dmar_iommu(iommu);
9bdc531e 2819 kfree(deferred_flush);
989d51fc 2820free_g_iommus:
d9630fe9 2821 kfree(g_iommus);
989d51fc 2822error:
ba395927
KA		 2823 return ret;
2824}
2825
5a5e02a6 2826/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2827static struct iova *intel_alloc_iova(struct device *dev,
2828 struct dmar_domain *domain,
2829 unsigned long nrpages, uint64_t dma_mask)
ba395927 2830{
ba395927 2831 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2832 struct iova *iova = NULL;
ba395927 2833
875764de
DW		 2834 /* Restrict dma_mask to the width that the iommu can handle */
2835 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2836
2837 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2838 /*
2839 * First try to allocate an io virtual address in
284901a9 2840 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2841 * from higher range
ba395927 2842 */
875764de
DW		 2843 iova = alloc_iova(&domain->iovad, nrpages,
2844 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2845 if (iova)
2846 return iova;
2847 }
2848 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2849 if (unlikely(!iova)) {
2850 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2851 nrpages, pci_name(pdev));
f76aec76
KA		 2852 return NULL;
2853 }
2854
2855 return iova;
2856}
2857
147202aa 2858static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2859{
2860 struct dmar_domain *domain;
2861 int ret;
2862
146922ec 2863 domain = get_domain_for_dev(&pdev->dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
f76aec76
KA		 2864 if (!domain) {
2865 printk(KERN_ERR
2866 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2867 return NULL;
ba395927
KA		 2868 }
2869
2870 /* make sure context mapping is ok */
e1f167f3
DW		 2871 if (unlikely(!domain_context_mapped(&pdev->dev))) {
2872 ret = domain_context_mapping(domain, &pdev->dev,
4ed0d3e6 2873 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2874 if (ret) {
2875 printk(KERN_ERR
2876 "Domain context map for %s failed",
2877 pci_name(pdev));
4fe05bbc 2878 return NULL;
f76aec76 2879 }
ba395927
KA		 2880 }
2881
f76aec76
KA		 2882 return domain;
2883}
2884
147202aa
DW		 2885static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2886{
2887 struct device_domain_info *info;
2888
2889 /* No lock here, assumes no domain exit in normal case */
2890 info = dev->dev.archdata.iommu;
2891 if (likely(info))
2892 return info->domain;
2893
2894 return __get_valid_domain_for_dev(dev);
2895}
2896
3d89194a 2897static int iommu_dummy(struct device *dev)
2c2e2c38 2898{
3d89194a 2899 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2c2e2c38
FY		 2900}
2901
2902/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2903static int iommu_no_mapping(struct device *dev)
2c2e2c38 2904{
73676832 2905 struct pci_dev *pdev;
2c2e2c38
FY		 2906 int found;
2907
dbad0864 2908 if (unlikely(!dev_is_pci(dev)))
73676832
DW		 2909 return 1;
2910
3d89194a 2911 if (iommu_dummy(dev))
1e4c64c4
DW		 2912 return 1;
2913
2c2e2c38 2914 if (!iommu_identity_mapping)
1e4c64c4 2915 return 0;
2c2e2c38 2916
3d89194a 2917 pdev = to_pci_dev(dev);
9b226624 2918 found = identity_mapping(dev);
2c2e2c38 2919 if (found) {
6941af28 2920 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2921 return 1;
2922 else {
2923 /*
2924 * 32 bit DMA is removed from si_domain and fall back
2925 * to non-identity mapping.
2926 */
2927 domain_remove_one_dev_info(si_domain, pdev);
2928 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2929 pci_name(pdev));
2930 return 0;
2931 }
2932 } else {
2933 /*
2934 * In case of a detached 64 bit DMA device from vm, the device
2935 * is put into si_domain for identity mapping.
2936 */
6941af28 2937 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2938 int ret;
5fe60f4e
DW		 2939 ret = domain_add_dev_info(si_domain, pdev,
2940 hw_pass_through ?
2941 CONTEXT_TT_PASS_THROUGH :
2942 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2943 if (!ret) {
2944 printk(KERN_INFO "64bit %s uses identity mapping\n",
2945 pci_name(pdev));
2946 return 1;
2947 }
2948 }
2949 }
2950
1e4c64c4 2951 return 0;
2c2e2c38
FY		 2952}
2953
bb9e6d65
FT		 2954static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2955 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2956{
2957 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2958 struct dmar_domain *domain;
5b6985ce 2959 phys_addr_t start_paddr;
f76aec76
KA		 2960 struct iova *iova;
2961 int prot = 0;
6865f0d1 2962 int ret;
8c11e798 2963 struct intel_iommu *iommu;
33041ec0 2964 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2965
2966 BUG_ON(dir == DMA_NONE);
2c2e2c38 2967
73676832 2968 if (iommu_no_mapping(hwdev))
6865f0d1 2969 return paddr;
f76aec76
KA		 2970
2971 domain = get_valid_domain_for_dev(pdev);
2972 if (!domain)
2973 return 0;
2974
8c11e798 2975 iommu = domain_get_iommu(domain);
88cb6a74 2976 size = aligned_nrpages(paddr, size);
f76aec76 2977
c681d0ba 2978 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2979 if (!iova)
2980 goto error;
2981
ba395927
KA		 2982 /*
2983 * Check if DMAR supports zero-length reads on write only
2984 * mappings..
2985 */
2986 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2987 !cap_zlr(iommu->cap))
ba395927
KA		 2988 prot |= DMA_PTE_READ;
2989 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2990 prot |= DMA_PTE_WRITE;
2991 /*
6865f0d1 2992 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2993 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2994 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2995 * is not a big problem
2996 */
0ab36de2 2997 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2998 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2999 if (ret)
3000 goto error;
3001
1f0ef2aa
DW		 3002 /* it's a non-present to present mapping. Only flush if caching mode */
3003 if (cap_caching_mode(iommu->cap))
ea8ea460 3004 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 3005 else
8c11e798 3006 iommu_flush_write_buffer(iommu);
f76aec76 3007
03d6a246
DW		 3008 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3009 start_paddr += paddr & ~PAGE_MASK;
3010 return start_paddr;
ba395927 3011
ba395927 3012error:
f76aec76
KA		 3013 if (iova)
3014 __free_iova(&domain->iovad, iova);
4cf2e75d 3015 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 3016 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 3017 return 0;
3018}
3019
ffbbef5c
FT		 3020static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3021 unsigned long offset, size_t size,
3022 enum dma_data_direction dir,
3023 struct dma_attrs *attrs)
bb9e6d65 3024{
ffbbef5c
FT		 3025 return __intel_map_single(dev, page_to_phys(page) + offset, size,
3026 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 3027}
3028
5e0d2a6f 3029static void flush_unmaps(void)
3030{
80b20dd8 3031 int i, j;
5e0d2a6f 3032
5e0d2a6f 3033 timer_on = 0;
3034
3035 /* just flush them all */
3036 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3037 struct intel_iommu *iommu = g_iommus[i];
3038 if (!iommu)
3039 continue;
c42d9f32 3040
9dd2fe89
YZ		 3041 if (!deferred_flush[i].next)
3042 continue;
3043
78d5f0f5
NA		 3044 /* In caching mode, global flushes turn emulation expensive */
3045 if (!cap_caching_mode(iommu->cap))
3046 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3047 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3048 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3049 unsigned long mask;
3050 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3051 struct dmar_domain *domain = deferred_flush[i].domain[j];
3052
3053 /* On real hardware multiple invalidations are expensive */
3054 if (cap_caching_mode(iommu->cap))
3055 iommu_flush_iotlb_psi(iommu, domain->id,
ea8ea460
DW		 3056 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1,
3057 !deferred_flush[i].freelist[j], 0);
78d5f0f5
NA		 3058 else {
3059 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
3060 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3061 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3062 }
93a23a72 3063 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3064 if (deferred_flush[i].freelist[j])
3065 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3066 }
9dd2fe89 3067 deferred_flush[i].next = 0;
5e0d2a6f 3068 }
3069
5e0d2a6f 3070 list_size = 0;
5e0d2a6f 3071}
3072
3073static void flush_unmaps_timeout(unsigned long data)
3074{
80b20dd8 3075 unsigned long flags;
3076
3077 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3078 flush_unmaps();
80b20dd8 3079 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3080}
3081
ea8ea460 3082static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3083{
3084 unsigned long flags;
80b20dd8 3085 int next, iommu_id;
8c11e798 3086 struct intel_iommu *iommu;
5e0d2a6f 3087
3088 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3089 if (list_size == HIGH_WATER_MARK)
3090 flush_unmaps();
3091
8c11e798
WH		 3092 iommu = domain_get_iommu(dom);
3093 iommu_id = iommu->seq_id;
c42d9f32 3094
80b20dd8 3095 next = deferred_flush[iommu_id].next;
3096 deferred_flush[iommu_id].domain[next] = dom;
3097 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3098 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3099 deferred_flush[iommu_id].next++;
5e0d2a6f 3100
3101 if (!timer_on) {
3102 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3103 timer_on = 1;
3104 }
3105 list_size++;
3106 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3107}
3108
ffbbef5c
FT		 3109static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3110 size_t size, enum dma_data_direction dir,
3111 struct dma_attrs *attrs)
ba395927 3112{
ba395927 3113 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 3114 struct dmar_domain *domain;
d794dc9b 3115 unsigned long start_pfn, last_pfn;
ba395927 3116 struct iova *iova;
8c11e798 3117 struct intel_iommu *iommu;
ea8ea460 3118 struct page *freelist;
ba395927 3119
73676832 3120 if (iommu_no_mapping(dev))
f76aec76 3121 return;
2c2e2c38 3122
1525a29a 3123 domain = find_domain(dev);
ba395927
KA		 3124 BUG_ON(!domain);
3125
8c11e798
WH		 3126 iommu = domain_get_iommu(domain);
3127
ba395927 3128 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3129 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3130 (unsigned long long)dev_addr))
ba395927 3131 return;
ba395927 3132
d794dc9b
DW		 3133 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3134 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3135
d794dc9b
DW		 3136 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3137 pci_name(pdev), start_pfn, last_pfn);
ba395927 3138
ea8ea460 3139 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3140
5e0d2a6f 3141 if (intel_iommu_strict) {
03d6a246 3142 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3143 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3144 /* free iova */
3145 __free_iova(&domain->iovad, iova);
ea8ea460 3146 dma_free_pagelist(freelist);
5e0d2a6f 3147 } else {
ea8ea460 3148 add_unmap(domain, iova, freelist);
5e0d2a6f 3149 /*
3150 * queue up the release of the unmap to save the 1/6th of the
3151 * cpu used up by the iotlb flush operation...
3152 */
5e0d2a6f 3153 }
ba395927
KA		 3154}
3155
d7ab5c46 3156static void *intel_alloc_coherent(struct device *hwdev, size_t size,
baa676fc
AP		 3157 dma_addr_t *dma_handle, gfp_t flags,
3158 struct dma_attrs *attrs)
ba395927
KA		 3159{
3160 void *vaddr;
3161 int order;
3162
5b6985ce 3163 size = PAGE_ALIGN(size);
ba395927 3164 order = get_order(size);
e8bb910d
AW		 3165
3166 if (!iommu_no_mapping(hwdev))
3167 flags &= ~(GFP_DMA | GFP_DMA32);
3168 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
3169 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
3170 flags |= GFP_DMA;
3171 else
3172 flags |= GFP_DMA32;
3173 }
ba395927
KA		 3174
3175 vaddr = (void *)__get_free_pages(flags, order);
3176 if (!vaddr)
3177 return NULL;
3178 memset(vaddr, 0, size);
3179
bb9e6d65
FT		 3180 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
3181 DMA_BIDIRECTIONAL,
3182 hwdev->coherent_dma_mask);
ba395927
KA		 3183 if (*dma_handle)
3184 return vaddr;
3185 free_pages((unsigned long)vaddr, order);
3186 return NULL;
3187}
3188
d7ab5c46 3189static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
baa676fc 3190 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3191{
3192 int order;
3193
5b6985ce 3194 size = PAGE_ALIGN(size);
ba395927
KA		 3195 order = get_order(size);
3196
0db9b7ae 3197 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 3198 free_pages((unsigned long)vaddr, order);
3199}
3200
d7ab5c46
FT		 3201static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
3202 int nelems, enum dma_data_direction dir,
3203 struct dma_attrs *attrs)
ba395927 3204{
ba395927 3205 struct dmar_domain *domain;
d794dc9b 3206 unsigned long start_pfn, last_pfn;
f76aec76 3207 struct iova *iova;
8c11e798 3208 struct intel_iommu *iommu;
ea8ea460 3209 struct page *freelist;
ba395927 3210
73676832 3211 if (iommu_no_mapping(hwdev))
ba395927
KA		 3212 return;
3213
1525a29a 3214 domain = find_domain(hwdev);
8c11e798
WH		 3215 BUG_ON(!domain);
3216
3217 iommu = domain_get_iommu(domain);
ba395927 3218
c03ab37c 3219 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 3220 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
3221 (unsigned long long)sglist[0].dma_address))
f76aec76 3222 return;
f76aec76 3223
d794dc9b
DW		 3224 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3225 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76 3226
ea8ea460 3227 freelist = domain_unmap(domain, start_pfn, last_pfn);
f76aec76 3228
acea0018
DW		 3229 if (intel_iommu_strict) {
3230 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3231 last_pfn - start_pfn + 1, !freelist, 0);
acea0018
DW		 3232 /* free iova */
3233 __free_iova(&domain->iovad, iova);
ea8ea460 3234 dma_free_pagelist(freelist);
acea0018 3235 } else {
ea8ea460 3236 add_unmap(domain, iova, freelist);
acea0018
DW		 3237 /*
3238 * queue up the release of the unmap to save the 1/6th of the
3239 * cpu used up by the iotlb flush operation...
3240 */
3241 }
ba395927
KA		 3242}
3243
ba395927 3244static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3245 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3246{
3247 int i;
c03ab37c 3248 struct scatterlist *sg;
ba395927 3249
c03ab37c 3250 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3251 BUG_ON(!sg_page(sg));
4cf2e75d 3252 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3253 sg->dma_length = sg->length;
ba395927
KA		 3254 }
3255 return nelems;
3256}
3257
d7ab5c46
FT		 3258static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3259 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3260{
ba395927 3261 int i;
ba395927
KA		 3262 struct pci_dev *pdev = to_pci_dev(hwdev);
3263 struct dmar_domain *domain;
f76aec76
KA		 3264 size_t size = 0;
3265 int prot = 0;
f76aec76
KA		 3266 struct iova *iova = NULL;
3267 int ret;
c03ab37c 3268 struct scatterlist *sg;
b536d24d 3269 unsigned long start_vpfn;
8c11e798 3270 struct intel_iommu *iommu;
ba395927
KA		 3271
3272 BUG_ON(dir == DMA_NONE);
73676832 3273 if (iommu_no_mapping(hwdev))
c03ab37c 3274 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 3275
f76aec76
KA		 3276 domain = get_valid_domain_for_dev(pdev);
3277 if (!domain)
3278 return 0;
3279
8c11e798
WH		 3280 iommu = domain_get_iommu(domain);
3281
b536d24d 3282 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3283 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3284
5a5e02a6
DW		 3285 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3286 pdev->dma_mask);
f76aec76 3287 if (!iova) {
c03ab37c 3288 sglist->dma_length = 0;
f76aec76
KA		 3289 return 0;
3290 }
3291
3292 /*
3293 * Check if DMAR supports zero-length reads on write only
3294 * mappings..
3295 */
3296 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3297 !cap_zlr(iommu->cap))
f76aec76
KA		 3298 prot |= DMA_PTE_READ;
3299 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3300 prot |= DMA_PTE_WRITE;
3301
b536d24d 3302 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3303
f532959b 3304 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3305 if (unlikely(ret)) {
3306 /* clear the page */
3307 dma_pte_clear_range(domain, start_vpfn,
3308 start_vpfn + size - 1);
3309 /* free page tables */
3310 dma_pte_free_pagetable(domain, start_vpfn,
3311 start_vpfn + size - 1);
3312 /* free iova */
3313 __free_iova(&domain->iovad, iova);
3314 return 0;
ba395927
KA		 3315 }
3316
1f0ef2aa
DW		 3317 /* it's a non-present to present mapping. Only flush if caching mode */
3318 if (cap_caching_mode(iommu->cap))
ea8ea460 3319 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3320 else
8c11e798 3321 iommu_flush_write_buffer(iommu);
1f0ef2aa 3322
ba395927
KA		 3323 return nelems;
3324}
3325
dfb805e8
FT		 3326static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3327{
3328 return !dma_addr;
3329}
3330
160c1d8e 3331struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3332 .alloc = intel_alloc_coherent,
3333 .free = intel_free_coherent,
ba395927
KA		 3334 .map_sg = intel_map_sg,
3335 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3336 .map_page = intel_map_page,
3337 .unmap_page = intel_unmap_page,
dfb805e8 3338 .mapping_error = intel_mapping_error,
ba395927
KA		 3339};
3340
3341static inline int iommu_domain_cache_init(void)
3342{
3343 int ret = 0;
3344
3345 iommu_domain_cache = kmem_cache_create("iommu_domain",
3346 sizeof(struct dmar_domain),
3347 0,
3348 SLAB_HWCACHE_ALIGN,
3349
3350 NULL);
3351 if (!iommu_domain_cache) {
3352 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3353 ret = -ENOMEM;
3354 }
3355
3356 return ret;
3357}
3358
3359static inline int iommu_devinfo_cache_init(void)
3360{
3361 int ret = 0;
3362
3363 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3364 sizeof(struct device_domain_info),
3365 0,
3366 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3367 NULL);
3368 if (!iommu_devinfo_cache) {
3369 printk(KERN_ERR "Couldn't create devinfo cache\n");
3370 ret = -ENOMEM;
3371 }
3372
3373 return ret;
3374}
3375
3376static inline int iommu_iova_cache_init(void)
3377{
3378 int ret = 0;
3379
3380 iommu_iova_cache = kmem_cache_create("iommu_iova",
3381 sizeof(struct iova),
3382 0,
3383 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3384 NULL);
3385 if (!iommu_iova_cache) {
3386 printk(KERN_ERR "Couldn't create iova cache\n");
3387 ret = -ENOMEM;
3388 }
3389
3390 return ret;
3391}
3392
3393static int __init iommu_init_mempool(void)
3394{
3395 int ret;
3396 ret = iommu_iova_cache_init();
3397 if (ret)
3398 return ret;
3399
3400 ret = iommu_domain_cache_init();
3401 if (ret)
3402 goto domain_error;
3403
3404 ret = iommu_devinfo_cache_init();
3405 if (!ret)
3406 return ret;
3407
3408 kmem_cache_destroy(iommu_domain_cache);
3409domain_error:
3410 kmem_cache_destroy(iommu_iova_cache);
3411
3412 return -ENOMEM;
3413}
3414
3415static void __init iommu_exit_mempool(void)
3416{
3417 kmem_cache_destroy(iommu_devinfo_cache);
3418 kmem_cache_destroy(iommu_domain_cache);
3419 kmem_cache_destroy(iommu_iova_cache);
3420
3421}
3422
556ab45f
DW		 3423static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3424{
3425 struct dmar_drhd_unit *drhd;
3426 u32 vtbar;
3427 int rc;
3428
3429 /* We know that this device on this chipset has its own IOMMU.
3430 * If we find it under a different IOMMU, then the BIOS is lying
3431 * to us. Hope that the IOMMU for this device is actually
3432 * disabled, and it needs no translation...
3433 */
3434 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3435 if (rc) {
3436 /* "can't" happen */
3437 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3438 return;
3439 }
3440 vtbar &= 0xffff0000;
3441
3442 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3443 drhd = dmar_find_matched_drhd_unit(pdev);
3444 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3445 TAINT_FIRMWARE_WORKAROUND,
3446 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3447 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3448}
3449DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3450
ba395927
KA		 3451static void __init init_no_remapping_devices(void)
3452{
3453 struct dmar_drhd_unit *drhd;
832bd858 3454 struct device *dev;
b683b230 3455 int i;
ba395927
KA		 3456
3457 for_each_drhd_unit(drhd) {
3458 if (!drhd->include_all) {
b683b230
JL		 3459 for_each_active_dev_scope(drhd->devices,
3460 drhd->devices_cnt, i, dev)
3461 break;
832bd858 3462 /* ignore DMAR unit if no devices exist */
ba395927
KA		 3463 if (i == drhd->devices_cnt)
3464 drhd->ignored = 1;
3465 }
3466 }
3467
7c919779 3468 for_each_active_drhd_unit(drhd) {
7c919779 3469 if (drhd->include_all)
ba395927
KA		 3470 continue;
3471
b683b230
JL		 3472 for_each_active_dev_scope(drhd->devices,
3473 drhd->devices_cnt, i, dev)
832bd858 3474 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
ba395927 3475 break;
ba395927
KA		 3476 if (i < drhd->devices_cnt)
3477 continue;
3478
c0771df8
DW		 3479 /* This IOMMU has *only* gfx devices. Either bypass it or
3480 set the gfx_mapped flag, as appropriate */
3481 if (dmar_map_gfx) {
3482 intel_iommu_gfx_mapped = 1;
3483 } else {
3484 drhd->ignored = 1;
b683b230
JL		 3485 for_each_active_dev_scope(drhd->devices,
3486 drhd->devices_cnt, i, dev)
832bd858 3487 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3488 }
3489 }
3490}
3491
f59c7b69
FY		 3492#ifdef CONFIG_SUSPEND
3493static int init_iommu_hw(void)
3494{
3495 struct dmar_drhd_unit *drhd;
3496 struct intel_iommu *iommu = NULL;
3497
3498 for_each_active_iommu(iommu, drhd)
3499 if (iommu->qi)
3500 dmar_reenable_qi(iommu);
3501
b779260b
JC		 3502 for_each_iommu(iommu, drhd) {
3503 if (drhd->ignored) {
3504 /*
3505 * we always have to disable PMRs or DMA may fail on
3506 * this device
3507 */
3508 if (force_on)
3509 iommu_disable_protect_mem_regions(iommu);
3510 continue;
3511 }
3512
f59c7b69
FY		 3513 iommu_flush_write_buffer(iommu);
3514
3515 iommu_set_root_entry(iommu);
3516
3517 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3518 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3519 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3520 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3521 if (iommu_enable_translation(iommu))
3522 return 1;
b94996c9 3523 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3524 }
3525
3526 return 0;
3527}
3528
3529static void iommu_flush_all(void)
3530{
3531 struct dmar_drhd_unit *drhd;
3532 struct intel_iommu *iommu;
3533
3534 for_each_active_iommu(iommu, drhd) {
3535 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3536 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3537 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3538 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3539 }
3540}
3541
134fac3f 3542static int iommu_suspend(void)
f59c7b69
FY		 3543{
3544 struct dmar_drhd_unit *drhd;
3545 struct intel_iommu *iommu = NULL;
3546 unsigned long flag;
3547
3548 for_each_active_iommu(iommu, drhd) {
3549 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3550 GFP_ATOMIC);
3551 if (!iommu->iommu_state)
3552 goto nomem;
3553 }
3554
3555 iommu_flush_all();
3556
3557 for_each_active_iommu(iommu, drhd) {
3558 iommu_disable_translation(iommu);
3559
1f5b3c3f 3560 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3561
3562 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3563 readl(iommu->reg + DMAR_FECTL_REG);
3564 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3565 readl(iommu->reg + DMAR_FEDATA_REG);
3566 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3567 readl(iommu->reg + DMAR_FEADDR_REG);
3568 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3569 readl(iommu->reg + DMAR_FEUADDR_REG);
3570
1f5b3c3f 3571 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3572 }
3573 return 0;
3574
3575nomem:
3576 for_each_active_iommu(iommu, drhd)
3577 kfree(iommu->iommu_state);
3578
3579 return -ENOMEM;
3580}
3581
134fac3f 3582static void iommu_resume(void)
f59c7b69
FY		 3583{
3584 struct dmar_drhd_unit *drhd;
3585 struct intel_iommu *iommu = NULL;
3586 unsigned long flag;
3587
3588 if (init_iommu_hw()) {
b779260b
JC		 3589 if (force_on)
3590 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3591 else
3592 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3593 return;
f59c7b69
FY		 3594 }
3595
3596 for_each_active_iommu(iommu, drhd) {
3597
1f5b3c3f 3598 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3599
3600 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3601 iommu->reg + DMAR_FECTL_REG);
3602 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3603 iommu->reg + DMAR_FEDATA_REG);
3604 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3605 iommu->reg + DMAR_FEADDR_REG);
3606 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3607 iommu->reg + DMAR_FEUADDR_REG);
3608
1f5b3c3f 3609 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3610 }
3611
3612 for_each_active_iommu(iommu, drhd)
3613 kfree(iommu->iommu_state);
f59c7b69
FY		 3614}
3615
134fac3f 3616static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3617 .resume = iommu_resume,
3618 .suspend = iommu_suspend,
3619};
3620
134fac3f 3621static void __init init_iommu_pm_ops(void)
f59c7b69 3622{
134fac3f 3623 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3624}
3625
3626#else
99592ba4 3627static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3628#endif /* CONFIG_PM */
3629
318fe7df
SS		 3630
3631int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3632{
3633 struct acpi_dmar_reserved_memory *rmrr;
3634 struct dmar_rmrr_unit *rmrru;
3635
3636 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3637 if (!rmrru)
3638 return -ENOMEM;
3639
3640 rmrru->hdr = header;
3641 rmrr = (struct acpi_dmar_reserved_memory *)header;
3642 rmrru->base_address = rmrr->base_address;
3643 rmrru->end_address = rmrr->end_address;
2e455289
JL		 3644 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3645 ((void *)rmrr) + rmrr->header.length,
3646 &rmrru->devices_cnt);
3647 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3648 kfree(rmrru);
3649 return -ENOMEM;
3650 }
318fe7df 3651
2e455289 3652 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 3653
2e455289 3654 return 0;
318fe7df
SS		 3655}
3656
318fe7df
SS		 3657int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3658{
3659 struct acpi_dmar_atsr *atsr;
3660 struct dmar_atsr_unit *atsru;
3661
3662 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3663 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3664 if (!atsru)
3665 return -ENOMEM;
3666
3667 atsru->hdr = hdr;
3668 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 3669 if (!atsru->include_all) {
3670 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3671 (void *)atsr + atsr->header.length,
3672 &atsru->devices_cnt);
3673 if (atsru->devices_cnt && atsru->devices == NULL) {
3674 kfree(atsru);
3675 return -ENOMEM;
3676 }
3677 }
318fe7df 3678
0e242612 3679 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 3680
3681 return 0;
3682}
3683
9bdc531e
JL		 3684static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3685{
3686 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3687 kfree(atsru);
3688}
3689
3690static void intel_iommu_free_dmars(void)
3691{
3692 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3693 struct dmar_atsr_unit *atsru, *atsr_n;
3694
3695 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3696 list_del(&rmrru->list);
3697 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3698 kfree(rmrru);
318fe7df
SS		 3699 }
3700
9bdc531e
JL		 3701 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3702 list_del(&atsru->list);
3703 intel_iommu_free_atsr(atsru);
3704 }
318fe7df
SS		 3705}
3706
3707int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3708{
b683b230 3709 int i, ret = 1;
318fe7df 3710 struct pci_bus *bus;
832bd858
DW		 3711 struct pci_dev *bridge = NULL;
3712 struct device *tmp;
318fe7df
SS		 3713 struct acpi_dmar_atsr *atsr;
3714 struct dmar_atsr_unit *atsru;
3715
3716 dev = pci_physfn(dev);
318fe7df 3717 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 3718 bridge = bus->self;
318fe7df 3719 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3720 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 3721 return 0;
b5f82ddf 3722 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 3723 break;
318fe7df 3724 }
b5f82ddf
JL		 3725 if (!bridge)
3726 return 0;
318fe7df 3727
0e242612 3728 rcu_read_lock();
b5f82ddf
JL		 3729 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3730 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3731 if (atsr->segment != pci_domain_nr(dev->bus))
3732 continue;
3733
b683b230 3734 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
832bd858 3735 if (tmp == &bridge->dev)
b683b230 3736 goto out;
b5f82ddf
JL		 3737
3738 if (atsru->include_all)
b683b230 3739 goto out;
b5f82ddf 3740 }
b683b230
JL		 3741 ret = 0;
3742out:
0e242612 3743 rcu_read_unlock();
318fe7df 3744
b683b230 3745 return ret;
318fe7df
SS		 3746}
3747
59ce0515
JL		 3748int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3749{
3750 int ret = 0;
3751 struct dmar_rmrr_unit *rmrru;
3752 struct dmar_atsr_unit *atsru;
3753 struct acpi_dmar_atsr *atsr;
3754 struct acpi_dmar_reserved_memory *rmrr;
3755
3756 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3757 return 0;
3758
3759 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3760 rmrr = container_of(rmrru->hdr,
3761 struct acpi_dmar_reserved_memory, header);
3762 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3763 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3764 ((void *)rmrr) + rmrr->header.length,
3765 rmrr->segment, rmrru->devices,
3766 rmrru->devices_cnt);
3767 if (ret > 0)
3768 break;
3769 else if(ret < 0)
3770 return ret;
3771 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3772 if (dmar_remove_dev_scope(info, rmrr->segment,
3773 rmrru->devices, rmrru->devices_cnt))
3774 break;
3775 }
3776 }
3777
3778 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3779 if (atsru->include_all)
3780 continue;
3781
3782 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3783 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3784 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
3785 (void *)atsr + atsr->header.length,
3786 atsr->segment, atsru->devices,
3787 atsru->devices_cnt);
3788 if (ret > 0)
3789 break;
3790 else if(ret < 0)
3791 return ret;
3792 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3793 if (dmar_remove_dev_scope(info, atsr->segment,
3794 atsru->devices, atsru->devices_cnt))
3795 break;
3796 }
3797 }
3798
3799 return 0;
3800}
3801
99dcaded
FY		 3802/*
3803 * Here we only respond to action of unbound device from driver.
3804 *
3805 * Added device is not attached to its DMAR domain here yet. That will happen
3806 * when mapping the device to iova.
3807 */
3808static int device_notifier(struct notifier_block *nb,
3809 unsigned long action, void *data)
3810{
3811 struct device *dev = data;
3812 struct pci_dev *pdev = to_pci_dev(dev);
3813 struct dmar_domain *domain;
3814
3d89194a 3815 if (iommu_dummy(dev))
44cd613c
DW		 3816 return 0;
3817
7e7dfab7
JL		 3818 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3819 action != BUS_NOTIFY_DEL_DEVICE)
3820 return 0;
3821
1525a29a 3822 domain = find_domain(dev);
99dcaded
FY		 3823 if (!domain)
3824 return 0;
3825
3a5670e8 3826 down_read(&dmar_global_lock);
7e7dfab7
JL		 3827 domain_remove_one_dev_info(domain, pdev);
3828 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3829 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3830 list_empty(&domain->devices))
3831 domain_exit(domain);
3a5670e8 3832 up_read(&dmar_global_lock);
a97590e5 3833
99dcaded
FY		 3834 return 0;
3835}
3836
3837static struct notifier_block device_nb = {
3838 .notifier_call = device_notifier,
3839};
3840
75f05569
JL		 3841static int intel_iommu_memory_notifier(struct notifier_block *nb,
3842 unsigned long val, void *v)
3843{
3844 struct memory_notify *mhp = v;
3845 unsigned long long start, end;
3846 unsigned long start_vpfn, last_vpfn;
3847
3848 switch (val) {
3849 case MEM_GOING_ONLINE:
3850 start = mhp->start_pfn << PAGE_SHIFT;
3851 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
3852 if (iommu_domain_identity_map(si_domain, start, end)) {
3853 pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
3854 start, end);
3855 return NOTIFY_BAD;
3856 }
3857 break;
3858
3859 case MEM_OFFLINE:
3860 case MEM_CANCEL_ONLINE:
3861 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
3862 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
3863 while (start_vpfn <= last_vpfn) {
3864 struct iova *iova;
3865 struct dmar_drhd_unit *drhd;
3866 struct intel_iommu *iommu;
ea8ea460 3867 struct page *freelist;
75f05569
JL		 3868
3869 iova = find_iova(&si_domain->iovad, start_vpfn);
3870 if (iova == NULL) {
3871 pr_debug("dmar: failed get IOVA for PFN %lx\n",
3872 start_vpfn);
3873 break;
3874 }
3875
3876 iova = split_and_remove_iova(&si_domain->iovad, iova,
3877 start_vpfn, last_vpfn);
3878 if (iova == NULL) {
3879 pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
3880 start_vpfn, last_vpfn);
3881 return NOTIFY_BAD;
3882 }
3883
ea8ea460
DW		 3884 freelist = domain_unmap(si_domain, iova->pfn_lo,
3885 iova->pfn_hi);
3886
75f05569
JL		 3887 rcu_read_lock();
3888 for_each_active_iommu(iommu, drhd)
3889 iommu_flush_iotlb_psi(iommu, si_domain->id,
3890 iova->pfn_lo,
ea8ea460
DW		 3891 iova->pfn_hi - iova->pfn_lo + 1,
3892 !freelist, 0);
75f05569 3893 rcu_read_unlock();
ea8ea460 3894 dma_free_pagelist(freelist);
75f05569
JL		 3895
3896 start_vpfn = iova->pfn_hi + 1;
3897 free_iova_mem(iova);
3898 }
3899 break;
3900 }
3901
3902 return NOTIFY_OK;
3903}
3904
3905static struct notifier_block intel_iommu_memory_nb = {
3906 .notifier_call = intel_iommu_memory_notifier,
3907 .priority = 0
3908};
3909
ba395927
KA		 3910int __init intel_iommu_init(void)
3911{
9bdc531e 3912 int ret = -ENODEV;
3a93c841 3913 struct dmar_drhd_unit *drhd;
7c919779 3914 struct intel_iommu *iommu;
ba395927 3915
a59b50e9
JC		 3916 /* VT-d is required for a TXT/tboot launch, so enforce that */
3917 force_on = tboot_force_iommu();
3918
3a5670e8
JL		 3919 if (iommu_init_mempool()) {
3920 if (force_on)
3921 panic("tboot: Failed to initialize iommu memory\n");
3922 return -ENOMEM;
3923 }
3924
3925 down_write(&dmar_global_lock);
a59b50e9
JC		 3926 if (dmar_table_init()) {
3927 if (force_on)
3928 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 3929 goto out_free_dmar;
a59b50e9 3930 }
ba395927 3931
3a93c841
TI		 3932 /*
3933 * Disable translation if already enabled prior to OS handover.
3934 */
7c919779 3935 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 3936 if (iommu->gcmd & DMA_GCMD_TE)
3937 iommu_disable_translation(iommu);
3a93c841 3938
c2c7286a 3939 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 3940 if (force_on)
3941 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 3942 goto out_free_dmar;
a59b50e9 3943 }
1886e8a9 3944
75f1cdf1 3945 if (no_iommu || dmar_disabled)
9bdc531e 3946 goto out_free_dmar;
2ae21010 3947
318fe7df
SS		 3948 if (list_empty(&dmar_rmrr_units))
3949 printk(KERN_INFO "DMAR: No RMRR found\n");
3950
3951 if (list_empty(&dmar_atsr_units))
3952 printk(KERN_INFO "DMAR: No ATSR found\n");
3953
51a63e67
JC		 3954 if (dmar_init_reserved_ranges()) {
3955 if (force_on)
3956 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 3957 goto out_free_reserved_range;
51a63e67 3958 }
ba395927
KA		 3959
3960 init_no_remapping_devices();
3961
b779260b 3962 ret = init_dmars();
ba395927 3963 if (ret) {
a59b50e9
JC		 3964 if (force_on)
3965 panic("tboot: Failed to initialize DMARs\n");
ba395927 3966 printk(KERN_ERR "IOMMU: dmar init failed\n");
9bdc531e 3967 goto out_free_reserved_range;
ba395927 3968 }
3a5670e8 3969 up_write(&dmar_global_lock);
ba395927
KA		 3970 printk(KERN_INFO
3971 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3972
5e0d2a6f 3973 init_timer(&unmap_timer);
75f1cdf1
FT		 3974#ifdef CONFIG_SWIOTLB
3975 swiotlb = 0;
3976#endif
19943b0e 3977 dma_ops = &intel_dma_ops;
4ed0d3e6 3978
134fac3f 3979 init_iommu_pm_ops();
a8bcbb0d 3980
4236d97d 3981 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 3982 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 3983 if (si_domain && !hw_pass_through)
3984 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 3985
8bc1f85c
ED		 3986 intel_iommu_enabled = 1;
3987
ba395927 3988 return 0;
9bdc531e
JL		 3989
3990out_free_reserved_range:
3991 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 3992out_free_dmar:
3993 intel_iommu_free_dmars();
3a5670e8
JL		 3994 up_write(&dmar_global_lock);
3995 iommu_exit_mempool();
9bdc531e 3996 return ret;
ba395927 3997}
e820482c 3998
3199aa6b 3999static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 4000 struct device *dev)
3199aa6b 4001{
0bcb3e28 4002 struct pci_dev *tmp, *parent, *pdev;
3199aa6b 4003
0bcb3e28 4004 if (!iommu || !dev || !dev_is_pci(dev))
3199aa6b
HW		 4005 return;
4006
0bcb3e28
DW		 4007 pdev = to_pci_dev(dev);
4008
3199aa6b
HW		 4009 /* dependent device detach */
4010 tmp = pci_find_upstream_pcie_bridge(pdev);
4011 /* Secondary interface's bus number and devfn 0 */
4012 if (tmp) {
4013 parent = pdev->bus->self;
4014 while (parent != tmp) {
4015 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 4016 parent->devfn);
3199aa6b
HW		 4017 parent = parent->bus->self;
4018 }
45e829ea 4019 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 4020 iommu_detach_dev(iommu,
4021 tmp->subordinate->number, 0);
4022 else /* this is a legacy PCI bridge */
276dbf99
DW		 4023 iommu_detach_dev(iommu, tmp->bus->number,
4024 tmp->devfn);
3199aa6b
HW		 4025 }
4026}
4027
2c2e2c38 4028static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 4029 struct pci_dev *pdev)
4030{
bca2b916 4031 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4032 struct intel_iommu *iommu;
4033 unsigned long flags;
4034 int found = 0;
156baca8 4035 u8 bus, devfn;
c7151a8d 4036
156baca8 4037 iommu = device_to_iommu(&pdev->dev, &bus, &devfn);
c7151a8d
WH		 4038 if (!iommu)
4039 return;
4040
4041 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4042 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
41e80dca 4043 if (info->iommu->segment == pci_domain_nr(pdev->bus) &&
8519dc44 4044 info->bus == pdev->bus->number &&
c7151a8d 4045 info->devfn == pdev->devfn) {
109b9b04 4046 unlink_domain_info(info);
c7151a8d
WH		 4047 spin_unlock_irqrestore(&device_domain_lock, flags);
4048
93a23a72 4049 iommu_disable_dev_iotlb(info);
c7151a8d 4050 iommu_detach_dev(iommu, info->bus, info->devfn);
0bcb3e28 4051 iommu_detach_dependent_devices(iommu, &pdev->dev);
c7151a8d
WH		 4052 free_devinfo_mem(info);
4053
4054 spin_lock_irqsave(&device_domain_lock, flags);
4055
4056 if (found)
4057 break;
4058 else
4059 continue;
4060 }
4061
4062 /* if there is no other devices under the same iommu
4063 * owned by this domain, clear this iommu in iommu_bmp
4064 * update iommu count and coherency
4065 */
8bbc4410 4066 if (info->iommu == iommu)
c7151a8d
WH		 4067 found = 1;
4068 }
4069
3e7abe25
RD		 4070 spin_unlock_irqrestore(&device_domain_lock, flags);
4071
c7151a8d
WH		 4072 if (found == 0) {
4073 unsigned long tmp_flags;
4074 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
1b198bb0 4075 clear_bit(iommu->seq_id, domain->iommu_bmp);
c7151a8d 4076 domain->iommu_count--;
58c610bd 4077 domain_update_iommu_cap(domain);
c7151a8d 4078 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 4079
9b4554b2
AW		 4080 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
4081 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
4082 spin_lock_irqsave(&iommu->lock, tmp_flags);
4083 clear_bit(domain->id, iommu->domain_ids);
4084 iommu->domains[domain->id] = NULL;
4085 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
4086 }
c7151a8d 4087 }
c7151a8d
WH		 4088}
4089
2c2e2c38 4090static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4091{
4092 int adjust_width;
4093
4094 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 4095 domain_reserve_special_ranges(domain);
4096
4097 /* calculate AGAW */
4098 domain->gaw = guest_width;
4099 adjust_width = guestwidth_to_adjustwidth(guest_width);
4100 domain->agaw = width_to_agaw(adjust_width);
4101
5e98c4b1 4102 domain->iommu_coherency = 0;
c5b15255 4103 domain->iommu_snooping = 0;
6dd9a7c7 4104 domain->iommu_superpage = 0;
fe40f1e0 4105 domain->max_addr = 0;
4c923d47 4106 domain->nid = -1;
5e98c4b1
WH		 4107
4108 /* always allocate the top pgd */
4c923d47 4109 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4110 if (!domain->pgd)
4111 return -ENOMEM;
4112 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4113 return 0;
4114}
4115
5d450806 4116static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 4117{
5d450806 4118 struct dmar_domain *dmar_domain;
38717946 4119
92d03cc8 4120 dmar_domain = alloc_domain(true);
5d450806 4121 if (!dmar_domain) {
38717946 4122 printk(KERN_ERR
5d450806
JR		 4123 "intel_iommu_domain_init: dmar_domain == NULL\n");
4124 return -ENOMEM;
38717946 4125 }
2c2e2c38 4126 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 4127 printk(KERN_ERR
5d450806 4128 "intel_iommu_domain_init() failed\n");
92d03cc8 4129 domain_exit(dmar_domain);
5d450806 4130 return -ENOMEM;
38717946 4131 }
8140a95d 4132 domain_update_iommu_cap(dmar_domain);
5d450806 4133 domain->priv = dmar_domain;
faa3d6f5 4134
8a0e715b
JR		 4135 domain->geometry.aperture_start = 0;
4136 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4137 domain->geometry.force_aperture = true;
4138
5d450806 4139 return 0;
38717946 4140}
38717946 4141
5d450806 4142static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 4143{
5d450806
JR		 4144 struct dmar_domain *dmar_domain = domain->priv;
4145
4146 domain->priv = NULL;
92d03cc8 4147 domain_exit(dmar_domain);
38717946 4148}
38717946 4149
4c5478c9
JR		 4150static int intel_iommu_attach_device(struct iommu_domain *domain,
4151 struct device *dev)
38717946 4152{
4c5478c9
JR		 4153 struct dmar_domain *dmar_domain = domain->priv;
4154 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 4155 struct intel_iommu *iommu;
4156 int addr_width;
156baca8 4157 u8 bus, devfn;
faa3d6f5
WH		 4158
4159 /* normally pdev is not mapped */
e1f167f3 4160 if (unlikely(domain_context_mapped(&pdev->dev))) {
faa3d6f5
WH		 4161 struct dmar_domain *old_domain;
4162
1525a29a 4163 old_domain = find_domain(dev);
faa3d6f5 4164 if (old_domain) {
2c2e2c38
FY		 4165 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
4166 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
4167 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 4168 else
4169 domain_remove_dev_info(old_domain);
4170 }
4171 }
4172
156baca8 4173 iommu = device_to_iommu(dev, &bus, &devfn);
fe40f1e0
WH		 4174 if (!iommu)
4175 return -ENODEV;
4176
4177 /* check if this iommu agaw is sufficient for max mapped address */
4178 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4179 if (addr_width > cap_mgaw(iommu->cap))
4180 addr_width = cap_mgaw(iommu->cap);
4181
4182 if (dmar_domain->max_addr > (1LL << addr_width)) {
4183 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4184 "sufficient for the mapped address (%llx)\n",
a99c47a2 4185 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4186 return -EFAULT;
4187 }
a99c47a2
TL		 4188 dmar_domain->gaw = addr_width;
4189
4190 /*
4191 * Knock out extra levels of page tables if necessary
4192 */
4193 while (iommu->agaw < dmar_domain->agaw) {
4194 struct dma_pte *pte;
4195
4196 pte = dmar_domain->pgd;
4197 if (dma_pte_present(pte)) {
25cbff16
SY		 4198 dmar_domain->pgd = (struct dma_pte *)
4199 phys_to_virt(dma_pte_addr(pte));
7a661013 4200 free_pgtable_page(pte);
a99c47a2
TL		 4201 }
4202 dmar_domain->agaw--;
4203 }
fe40f1e0 4204
5fe60f4e 4205 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 4206}
38717946 4207
4c5478c9
JR		 4208static void intel_iommu_detach_device(struct iommu_domain *domain,
4209 struct device *dev)
38717946 4210{
4c5478c9
JR		 4211 struct dmar_domain *dmar_domain = domain->priv;
4212 struct pci_dev *pdev = to_pci_dev(dev);
4213
2c2e2c38 4214 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 4215}
c7151a8d 4216
b146a1c9
JR		 4217static int intel_iommu_map(struct iommu_domain *domain,
4218 unsigned long iova, phys_addr_t hpa,
5009065d 4219 size_t size, int iommu_prot)
faa3d6f5 4220{
dde57a21 4221 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 4222 u64 max_addr;
dde57a21 4223 int prot = 0;
faa3d6f5 4224 int ret;
fe40f1e0 4225
dde57a21
JR		 4226 if (iommu_prot & IOMMU_READ)
4227 prot |= DMA_PTE_READ;
4228 if (iommu_prot & IOMMU_WRITE)
4229 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4230 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4231 prot |= DMA_PTE_SNP;
dde57a21 4232
163cc52c 4233 max_addr = iova + size;
dde57a21 4234 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4235 u64 end;
4236
4237 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4238 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4239 if (end < max_addr) {
8954da1f 4240 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4241 "sufficient for the mapped address (%llx)\n",
8954da1f 4242 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4243 return -EFAULT;
4244 }
dde57a21 4245 dmar_domain->max_addr = max_addr;
fe40f1e0 4246 }
ad051221
DW		 4247 /* Round up size to next multiple of PAGE_SIZE, if it and
4248 the low bits of hpa would take us onto the next page */
88cb6a74 4249 size = aligned_nrpages(hpa, size);
ad051221
DW		 4250 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4251 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4252 return ret;
38717946 4253}
38717946 4254
5009065d 4255static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4256 unsigned long iova, size_t size)
38717946 4257{
dde57a21 4258 struct dmar_domain *dmar_domain = domain->priv;
ea8ea460
DW		 4259 struct page *freelist = NULL;
4260 struct intel_iommu *iommu;
4261 unsigned long start_pfn, last_pfn;
4262 unsigned int npages;
4263 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4264
4265 /* Cope with horrid API which requires us to unmap more than the
4266 size argument if it happens to be a large-page mapping. */
4267 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4268 BUG();
4269
4270 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4271 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4272
ea8ea460
DW		 4273 start_pfn = iova >> VTD_PAGE_SHIFT;
4274 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4275
4276 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4277
4278 npages = last_pfn - start_pfn + 1;
4279
4280 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4281 iommu = g_iommus[iommu_id];
4282
4283 /*
4284 * find bit position of dmar_domain
4285 */
4286 ndomains = cap_ndoms(iommu->cap);
4287 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4288 if (iommu->domains[num] == dmar_domain)
4289 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4290 npages, !freelist, 0);
4291 }
4292
4293 }
4294
4295 dma_free_pagelist(freelist);
fe40f1e0 4296
163cc52c
DW		 4297 if (dmar_domain->max_addr == iova + size)
4298 dmar_domain->max_addr = iova;
b146a1c9 4299
5cf0a76f 4300 return size;
38717946 4301}
38717946 4302
d14d6577 4303static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4304 dma_addr_t iova)
38717946 4305{
d14d6577 4306 struct dmar_domain *dmar_domain = domain->priv;
38717946 4307 struct dma_pte *pte;
5cf0a76f 4308 int level = 0;
faa3d6f5 4309 u64 phys = 0;
38717946 4310
5cf0a76f 4311 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4312 if (pte)
faa3d6f5 4313 phys = dma_pte_addr(pte);
38717946 4314
faa3d6f5 4315 return phys;
38717946 4316}
a8bcbb0d 4317
dbb9fd86
SY		 4318static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4319 unsigned long cap)
4320{
4321 struct dmar_domain *dmar_domain = domain->priv;
4322
4323 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4324 return dmar_domain->iommu_snooping;
323f99cb 4325 if (cap == IOMMU_CAP_INTR_REMAP)
95a02e97 4326 return irq_remapping_enabled;
dbb9fd86
SY		 4327
4328 return 0;
4329}
4330
783f157b 4331#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
70ae6f0d 4332
abdfdde2
AW		 4333static int intel_iommu_add_device(struct device *dev)
4334{
4335 struct pci_dev *pdev = to_pci_dev(dev);
3da4af0a 4336 struct pci_dev *bridge, *dma_pdev = NULL;
abdfdde2
AW		 4337 struct iommu_group *group;
4338 int ret;
156baca8 4339 u8 bus, devfn;
70ae6f0d 4340
156baca8 4341 if (!device_to_iommu(dev, &bus, &devfn))
70ae6f0d
AW		 4342 return -ENODEV;
4343
4344 bridge = pci_find_upstream_pcie_bridge(pdev);
4345 if (bridge) {
abdfdde2
AW		 4346 if (pci_is_pcie(bridge))
4347 dma_pdev = pci_get_domain_bus_and_slot(
4348 pci_domain_nr(pdev->bus),
4349 bridge->subordinate->number, 0);
3da4af0a 4350 if (!dma_pdev)
abdfdde2
AW		 4351 dma_pdev = pci_dev_get(bridge);
4352 } else
4353 dma_pdev = pci_dev_get(pdev);
4354
a4ff1fc2 4355 /* Account for quirked devices */
783f157b
AW		 4356 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
4357
a4ff1fc2
AW		 4358 /*
4359 * If it's a multifunction device that does not support our
c14d2690
AW		 4360 * required ACS flags, add to the same group as lowest numbered
4361 * function that also does not suport the required ACS flags.
a4ff1fc2 4362 */
783f157b 4363 if (dma_pdev->multifunction &&
c14d2690
AW		 4364 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
4365 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
4366
4367 for (i = 0; i < 8; i++) {
4368 struct pci_dev *tmp;
4369
4370 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
4371 if (!tmp)
4372 continue;
4373
4374 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
4375 swap_pci_ref(&dma_pdev, tmp);
4376 break;
4377 }
4378 pci_dev_put(tmp);
4379 }
4380 }
783f157b 4381
a4ff1fc2
AW		 4382 /*
4383 * Devices on the root bus go through the iommu. If that's not us,
4384 * find the next upstream device and test ACS up to the root bus.
4385 * Finding the next device may require skipping virtual buses.
4386 */
783f157b 4387 while (!pci_is_root_bus(dma_pdev->bus)) {
a4ff1fc2
AW		 4388 struct pci_bus *bus = dma_pdev->bus;
4389
4390 while (!bus->self) {
4391 if (!pci_is_root_bus(bus))
4392 bus = bus->parent;
4393 else
4394 goto root_bus;
4395 }
4396
4397 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
783f157b
AW		 4398 break;
4399
a4ff1fc2 4400 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
783f157b
AW		 4401 }
4402
a4ff1fc2 4403root_bus:
abdfdde2
AW		 4404 group = iommu_group_get(&dma_pdev->dev);
4405 pci_dev_put(dma_pdev);
4406 if (!group) {
4407 group = iommu_group_alloc();
4408 if (IS_ERR(group))
4409 return PTR_ERR(group);
70ae6f0d
AW		 4410 }
4411
abdfdde2 4412 ret = iommu_group_add_device(group, dev);
bcb71abe 4413
abdfdde2
AW		 4414 iommu_group_put(group);
4415 return ret;
4416}
70ae6f0d 4417
abdfdde2
AW		 4418static void intel_iommu_remove_device(struct device *dev)
4419{
4420 iommu_group_remove_device(dev);
70ae6f0d
AW		 4421}
4422
a8bcbb0d
JR		 4423static struct iommu_ops intel_iommu_ops = {
4424 .domain_init = intel_iommu_domain_init,
4425 .domain_destroy = intel_iommu_domain_destroy,
4426 .attach_dev = intel_iommu_attach_device,
4427 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4428 .map = intel_iommu_map,
4429 .unmap = intel_iommu_unmap,
a8bcbb0d 4430 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4431 .domain_has_cap = intel_iommu_domain_has_cap,
abdfdde2
AW		 4432 .add_device = intel_iommu_add_device,
4433 .remove_device = intel_iommu_remove_device,
6d1c56a9 4434 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4435};
9af88143 4436
9452618e
DV		 4437static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4438{
4439 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4440 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4441 dmar_map_gfx = 0;
4442}
4443
4444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4451
d34d6517 4452static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4453{
4454 /*
4455 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4456 * but needs it. Same seems to hold for the desktop versions.
9af88143
DW		 4457 */
4458 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4459 rwbf_quirk = 1;
4460}
4461
4462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4469
eecfd57f
AJ		 4470#define GGC 0x52
4471#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4472#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4473#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4474#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4475#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4476#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4477#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4478#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4479
d34d6517 4480static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4481{
4482 unsigned short ggc;
4483
eecfd57f 4484 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4485 return;
4486
eecfd57f 4487 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4488 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4489 dmar_map_gfx = 0;
6fbcfb3e
DW		 4490 } else if (dmar_map_gfx) {
4491 /* we have to ensure the gfx device is idle before we flush */
4492 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4493 intel_iommu_strict = 1;
4494 }
9eecabcb
DW		 4495}
4496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4499DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4500
e0fc7e0b
DW		 4501/* On Tylersburg chipsets, some BIOSes have been known to enable the
4502 ISOCH DMAR unit for the Azalia sound device, but not give it any
4503 TLB entries, which causes it to deadlock. Check for that. We do
4504 this in a function called from init_dmars(), instead of in a PCI
4505 quirk, because we don't want to print the obnoxious "BIOS broken"
4506 message if VT-d is actually disabled.
4507*/
4508static void __init check_tylersburg_isoch(void)
4509{
4510 struct pci_dev *pdev;
4511 uint32_t vtisochctrl;
4512
4513 /* If there's no Azalia in the system anyway, forget it. */
4514 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4515 if (!pdev)
4516 return;
4517 pci_dev_put(pdev);
4518
4519 /* System Management Registers. Might be hidden, in which case
4520 we can't do the sanity check. But that's OK, because the
4521 known-broken BIOSes _don't_ actually hide it, so far. */
4522 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4523 if (!pdev)
4524 return;
4525
4526 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4527 pci_dev_put(pdev);
4528 return;
4529 }
4530
4531 pci_dev_put(pdev);
4532
4533 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4534 if (vtisochctrl & 1)
4535 return;
4536
4537 /* Drop all bits other than the number of TLB entries */
4538 vtisochctrl &= 0x1c;
4539
4540 /* If we have the recommended number of TLB entries (16), fine. */
4541 if (vtisochctrl == 0x10)
4542 return;
4543
4544 /* Zero TLB entries? You get to ride the short bus to school. */
4545 if (!vtisochctrl) {
4546 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4547 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4548 dmi_get_system_info(DMI_BIOS_VENDOR),
4549 dmi_get_system_info(DMI_BIOS_VERSION),
4550 dmi_get_system_info(DMI_PRODUCT_VERSION));
4551 iommu_identity_mapping |= IDENTMAP_AZALIA;
4552 return;
4553 }
4554
4555 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4556 vtisochctrl);
4557}
Linux kernel - Deliverables
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