Commit | Line | Data |
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ba395927 | 1 | /* |
ea8ea460 | 2 | * Copyright © 2006-2014 Intel Corporation. |
ba395927 KA |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
ea8ea460 DW |
13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
14 | * Ashok Raj <ashok.raj@intel.com>, | |
15 | * Shaohua Li <shaohua.li@intel.com>, | |
16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, | |
17 | * Fenghua Yu <fenghua.yu@intel.com> | |
9f10e5bf | 18 | * Joerg Roedel <jroedel@suse.de> |
ba395927 KA |
19 | */ |
20 | ||
9f10e5bf JR |
21 | #define pr_fmt(fmt) "DMAR: " fmt |
22 | ||
ba395927 KA |
23 | #include <linux/init.h> |
24 | #include <linux/bitmap.h> | |
5e0d2a6f | 25 | #include <linux/debugfs.h> |
54485c30 | 26 | #include <linux/export.h> |
ba395927 KA |
27 | #include <linux/slab.h> |
28 | #include <linux/irq.h> | |
29 | #include <linux/interrupt.h> | |
ba395927 KA |
30 | #include <linux/spinlock.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/dmar.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/mempool.h> | |
75f05569 | 35 | #include <linux/memory.h> |
5e0d2a6f | 36 | #include <linux/timer.h> |
38717946 | 37 | #include <linux/iova.h> |
5d450806 | 38 | #include <linux/iommu.h> |
38717946 | 39 | #include <linux/intel-iommu.h> |
134fac3f | 40 | #include <linux/syscore_ops.h> |
69575d38 | 41 | #include <linux/tboot.h> |
adb2fe02 | 42 | #include <linux/dmi.h> |
5cdede24 | 43 | #include <linux/pci-ats.h> |
0ee332c1 | 44 | #include <linux/memblock.h> |
36746436 | 45 | #include <linux/dma-contiguous.h> |
091d42e4 | 46 | #include <linux/crash_dump.h> |
8a8f422d | 47 | #include <asm/irq_remapping.h> |
ba395927 | 48 | #include <asm/cacheflush.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
ba395927 | 50 | |
078e1ee2 JR |
51 | #include "irq_remapping.h" |
52 | ||
5b6985ce FY |
53 | #define ROOT_SIZE VTD_PAGE_SIZE |
54 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
55 | ||
ba395927 | 56 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
18436afd | 57 | #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) |
ba395927 | 58 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
e0fc7e0b | 59 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
ba395927 KA |
60 | |
61 | #define IOAPIC_RANGE_START (0xfee00000) | |
62 | #define IOAPIC_RANGE_END (0xfeefffff) | |
63 | #define IOVA_START_ADDR (0x1000) | |
64 | ||
65 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
66 | ||
4ed0d3e6 | 67 | #define MAX_AGAW_WIDTH 64 |
5c645b35 | 68 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
4ed0d3e6 | 69 | |
2ebe3151 DW |
70 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
71 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) | |
72 | ||
73 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR | |
74 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ | |
75 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ | |
76 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) | |
77 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) | |
ba395927 | 78 | |
1b722500 RM |
79 | /* IO virtual address start page frame number */ |
80 | #define IOVA_START_PFN (1) | |
81 | ||
f27be03b | 82 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 83 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 84 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 85 | |
df08cdc7 AM |
86 | /* page table handling */ |
87 | #define LEVEL_STRIDE (9) | |
88 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
89 | ||
6d1c56a9 OBC |
90 | /* |
91 | * This bitmap is used to advertise the page sizes our hardware support | |
92 | * to the IOMMU core, which will then use this information to split | |
93 | * physically contiguous memory regions it is mapping into page sizes | |
94 | * that we support. | |
95 | * | |
96 | * Traditionally the IOMMU core just handed us the mappings directly, | |
97 | * after making sure the size is an order of a 4KiB page and that the | |
98 | * mapping has natural alignment. | |
99 | * | |
100 | * To retain this behavior, we currently advertise that we support | |
101 | * all page sizes that are an order of 4KiB. | |
102 | * | |
103 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
104 | * we could change this to advertise the real page sizes we support. | |
105 | */ | |
106 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) | |
107 | ||
df08cdc7 AM |
108 | static inline int agaw_to_level(int agaw) |
109 | { | |
110 | return agaw + 2; | |
111 | } | |
112 | ||
113 | static inline int agaw_to_width(int agaw) | |
114 | { | |
5c645b35 | 115 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
df08cdc7 AM |
116 | } |
117 | ||
118 | static inline int width_to_agaw(int width) | |
119 | { | |
5c645b35 | 120 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
df08cdc7 AM |
121 | } |
122 | ||
123 | static inline unsigned int level_to_offset_bits(int level) | |
124 | { | |
125 | return (level - 1) * LEVEL_STRIDE; | |
126 | } | |
127 | ||
128 | static inline int pfn_level_offset(unsigned long pfn, int level) | |
129 | { | |
130 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; | |
131 | } | |
132 | ||
133 | static inline unsigned long level_mask(int level) | |
134 | { | |
135 | return -1UL << level_to_offset_bits(level); | |
136 | } | |
137 | ||
138 | static inline unsigned long level_size(int level) | |
139 | { | |
140 | return 1UL << level_to_offset_bits(level); | |
141 | } | |
142 | ||
143 | static inline unsigned long align_to_level(unsigned long pfn, int level) | |
144 | { | |
145 | return (pfn + level_size(level) - 1) & level_mask(level); | |
146 | } | |
fd18de50 | 147 | |
6dd9a7c7 YS |
148 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
149 | { | |
5c645b35 | 150 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
6dd9a7c7 YS |
151 | } |
152 | ||
dd4e8319 DW |
153 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
154 | are never going to work. */ | |
155 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
156 | { | |
157 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
158 | } | |
159 | ||
160 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
161 | { | |
162 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
163 | } | |
164 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
165 | { | |
166 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
167 | } | |
168 | static inline unsigned long virt_to_dma_pfn(void *p) | |
169 | { | |
170 | return page_to_dma_pfn(virt_to_page(p)); | |
171 | } | |
172 | ||
d9630fe9 WH |
173 | /* global iommu list, set NULL for ignored DMAR units */ |
174 | static struct intel_iommu **g_iommus; | |
175 | ||
e0fc7e0b | 176 | static void __init check_tylersburg_isoch(void); |
9af88143 DW |
177 | static int rwbf_quirk; |
178 | ||
b779260b JC |
179 | /* |
180 | * set to 1 to panic kernel if can't successfully enable VT-d | |
181 | * (used when kernel is launched w/ TXT) | |
182 | */ | |
183 | static int force_on = 0; | |
184 | ||
46b08e1a MM |
185 | /* |
186 | * 0: Present | |
187 | * 1-11: Reserved | |
188 | * 12-63: Context Ptr (12 - (haw-1)) | |
189 | * 64-127: Reserved | |
190 | */ | |
191 | struct root_entry { | |
03ecc32c DW |
192 | u64 lo; |
193 | u64 hi; | |
46b08e1a MM |
194 | }; |
195 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
46b08e1a | 196 | |
091d42e4 JR |
197 | /* |
198 | * Take a root_entry and return the Lower Context Table Pointer (LCTP) | |
199 | * if marked present. | |
200 | */ | |
201 | static phys_addr_t root_entry_lctp(struct root_entry *re) | |
202 | { | |
203 | if (!(re->lo & 1)) | |
204 | return 0; | |
205 | ||
206 | return re->lo & VTD_PAGE_MASK; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Take a root_entry and return the Upper Context Table Pointer (UCTP) | |
211 | * if marked present. | |
212 | */ | |
213 | static phys_addr_t root_entry_uctp(struct root_entry *re) | |
214 | { | |
215 | if (!(re->hi & 1)) | |
216 | return 0; | |
46b08e1a | 217 | |
091d42e4 JR |
218 | return re->hi & VTD_PAGE_MASK; |
219 | } | |
7a8fc25e MM |
220 | /* |
221 | * low 64 bits: | |
222 | * 0: present | |
223 | * 1: fault processing disable | |
224 | * 2-3: translation type | |
225 | * 12-63: address space root | |
226 | * high 64 bits: | |
227 | * 0-2: address width | |
228 | * 3-6: aval | |
229 | * 8-23: domain id | |
230 | */ | |
231 | struct context_entry { | |
232 | u64 lo; | |
233 | u64 hi; | |
234 | }; | |
c07e7d21 | 235 | |
cf484d0e JR |
236 | static inline void context_clear_pasid_enable(struct context_entry *context) |
237 | { | |
238 | context->lo &= ~(1ULL << 11); | |
239 | } | |
240 | ||
241 | static inline bool context_pasid_enabled(struct context_entry *context) | |
242 | { | |
243 | return !!(context->lo & (1ULL << 11)); | |
244 | } | |
245 | ||
246 | static inline void context_set_copied(struct context_entry *context) | |
247 | { | |
248 | context->hi |= (1ull << 3); | |
249 | } | |
250 | ||
251 | static inline bool context_copied(struct context_entry *context) | |
252 | { | |
253 | return !!(context->hi & (1ULL << 3)); | |
254 | } | |
255 | ||
256 | static inline bool __context_present(struct context_entry *context) | |
c07e7d21 MM |
257 | { |
258 | return (context->lo & 1); | |
259 | } | |
cf484d0e JR |
260 | |
261 | static inline bool context_present(struct context_entry *context) | |
262 | { | |
263 | return context_pasid_enabled(context) ? | |
264 | __context_present(context) : | |
265 | __context_present(context) && !context_copied(context); | |
266 | } | |
267 | ||
c07e7d21 MM |
268 | static inline void context_set_present(struct context_entry *context) |
269 | { | |
270 | context->lo |= 1; | |
271 | } | |
272 | ||
273 | static inline void context_set_fault_enable(struct context_entry *context) | |
274 | { | |
275 | context->lo &= (((u64)-1) << 2) | 1; | |
276 | } | |
277 | ||
c07e7d21 MM |
278 | static inline void context_set_translation_type(struct context_entry *context, |
279 | unsigned long value) | |
280 | { | |
281 | context->lo &= (((u64)-1) << 4) | 3; | |
282 | context->lo |= (value & 3) << 2; | |
283 | } | |
284 | ||
285 | static inline void context_set_address_root(struct context_entry *context, | |
286 | unsigned long value) | |
287 | { | |
1a2262f9 | 288 | context->lo &= ~VTD_PAGE_MASK; |
c07e7d21 MM |
289 | context->lo |= value & VTD_PAGE_MASK; |
290 | } | |
291 | ||
292 | static inline void context_set_address_width(struct context_entry *context, | |
293 | unsigned long value) | |
294 | { | |
295 | context->hi |= value & 7; | |
296 | } | |
297 | ||
298 | static inline void context_set_domain_id(struct context_entry *context, | |
299 | unsigned long value) | |
300 | { | |
301 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
302 | } | |
303 | ||
dbcd861f JR |
304 | static inline int context_domain_id(struct context_entry *c) |
305 | { | |
306 | return((c->hi >> 8) & 0xffff); | |
307 | } | |
308 | ||
c07e7d21 MM |
309 | static inline void context_clear_entry(struct context_entry *context) |
310 | { | |
311 | context->lo = 0; | |
312 | context->hi = 0; | |
313 | } | |
7a8fc25e | 314 | |
622ba12a MM |
315 | /* |
316 | * 0: readable | |
317 | * 1: writable | |
318 | * 2-6: reserved | |
319 | * 7: super page | |
9cf06697 SY |
320 | * 8-10: available |
321 | * 11: snoop behavior | |
622ba12a MM |
322 | * 12-63: Host physcial address |
323 | */ | |
324 | struct dma_pte { | |
325 | u64 val; | |
326 | }; | |
622ba12a | 327 | |
19c239ce MM |
328 | static inline void dma_clear_pte(struct dma_pte *pte) |
329 | { | |
330 | pte->val = 0; | |
331 | } | |
332 | ||
19c239ce MM |
333 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
334 | { | |
c85994e4 DW |
335 | #ifdef CONFIG_64BIT |
336 | return pte->val & VTD_PAGE_MASK; | |
337 | #else | |
338 | /* Must have a full atomic 64-bit read */ | |
1a8bd481 | 339 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
c85994e4 | 340 | #endif |
19c239ce MM |
341 | } |
342 | ||
19c239ce MM |
343 | static inline bool dma_pte_present(struct dma_pte *pte) |
344 | { | |
345 | return (pte->val & 3) != 0; | |
346 | } | |
622ba12a | 347 | |
4399c8bf AK |
348 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
349 | { | |
c3c75eb7 | 350 | return (pte->val & DMA_PTE_LARGE_PAGE); |
4399c8bf AK |
351 | } |
352 | ||
75e6bf96 DW |
353 | static inline int first_pte_in_page(struct dma_pte *pte) |
354 | { | |
355 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
356 | } | |
357 | ||
2c2e2c38 FY |
358 | /* |
359 | * This domain is a statically identity mapping domain. | |
360 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
361 | * 2. It maps to each iommu if successful. | |
362 | * 3. Each iommu mapps to this domain if successful. | |
363 | */ | |
19943b0e DW |
364 | static struct dmar_domain *si_domain; |
365 | static int hw_pass_through = 1; | |
2c2e2c38 | 366 | |
28ccce0d JR |
367 | /* |
368 | * Domain represents a virtual machine, more than one devices | |
1ce28feb WH |
369 | * across iommus may be owned in one domain, e.g. kvm guest. |
370 | */ | |
ab8dfe25 | 371 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0) |
1ce28feb | 372 | |
2c2e2c38 | 373 | /* si_domain contains mulitple devices */ |
ab8dfe25 | 374 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1) |
2c2e2c38 | 375 | |
29a27719 JR |
376 | #define for_each_domain_iommu(idx, domain) \ |
377 | for (idx = 0; idx < g_num_of_iommus; idx++) \ | |
378 | if (domain->iommu_refcnt[idx]) | |
379 | ||
99126f7c | 380 | struct dmar_domain { |
4c923d47 | 381 | int nid; /* node id */ |
29a27719 JR |
382 | |
383 | unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED]; | |
384 | /* Refcount of devices per iommu */ | |
385 | ||
99126f7c | 386 | |
c0e8a6c8 JR |
387 | u16 iommu_did[DMAR_UNITS_SUPPORTED]; |
388 | /* Domain ids per IOMMU. Use u16 since | |
389 | * domain ids are 16 bit wide according | |
390 | * to VT-d spec, section 9.3 */ | |
391 | ||
00a77deb | 392 | struct list_head devices; /* all devices' list */ |
99126f7c MM |
393 | struct iova_domain iovad; /* iova's that belong to this domain */ |
394 | ||
395 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
396 | int gaw; /* max guest address width */ |
397 | ||
398 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
399 | int agaw; | |
400 | ||
3b5410e7 | 401 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
402 | |
403 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 404 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d | 405 | int iommu_count; /* reference count of iommu */ |
6dd9a7c7 YS |
406 | int iommu_superpage;/* Level of superpages supported: |
407 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
408 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
fe40f1e0 | 409 | u64 max_addr; /* maximum mapped address */ |
00a77deb JR |
410 | |
411 | struct iommu_domain domain; /* generic domain data structure for | |
412 | iommu core */ | |
99126f7c MM |
413 | }; |
414 | ||
a647dacb MM |
415 | /* PCI domain-device relationship */ |
416 | struct device_domain_info { | |
417 | struct list_head link; /* link to domain siblings */ | |
418 | struct list_head global; /* link to global list */ | |
276dbf99 | 419 | u8 bus; /* PCI bus number */ |
a647dacb | 420 | u8 devfn; /* PCI devfn number */ |
0bcb3e28 | 421 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
93a23a72 | 422 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
423 | struct dmar_domain *domain; /* pointer to domain */ |
424 | }; | |
425 | ||
b94e4117 JL |
426 | struct dmar_rmrr_unit { |
427 | struct list_head list; /* list of rmrr units */ | |
428 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
429 | u64 base_address; /* reserved base address*/ | |
430 | u64 end_address; /* reserved end address */ | |
832bd858 | 431 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
432 | int devices_cnt; /* target device count */ |
433 | }; | |
434 | ||
435 | struct dmar_atsr_unit { | |
436 | struct list_head list; /* list of ATSR units */ | |
437 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
832bd858 | 438 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
439 | int devices_cnt; /* target device count */ |
440 | u8 include_all:1; /* include all ports */ | |
441 | }; | |
442 | ||
443 | static LIST_HEAD(dmar_atsr_units); | |
444 | static LIST_HEAD(dmar_rmrr_units); | |
445 | ||
446 | #define for_each_rmrr_units(rmrr) \ | |
447 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
448 | ||
5e0d2a6f | 449 | static void flush_unmaps_timeout(unsigned long data); |
450 | ||
b707cb02 | 451 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
5e0d2a6f | 452 | |
80b20dd8 | 453 | #define HIGH_WATER_MARK 250 |
454 | struct deferred_flush_tables { | |
455 | int next; | |
456 | struct iova *iova[HIGH_WATER_MARK]; | |
457 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
ea8ea460 | 458 | struct page *freelist[HIGH_WATER_MARK]; |
80b20dd8 | 459 | }; |
460 | ||
461 | static struct deferred_flush_tables *deferred_flush; | |
462 | ||
5e0d2a6f | 463 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 464 | static int g_num_of_iommus; |
465 | ||
466 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
467 | static LIST_HEAD(unmaps_to_do); | |
468 | ||
469 | static int timer_on; | |
470 | static long list_size; | |
5e0d2a6f | 471 | |
92d03cc8 | 472 | static void domain_exit(struct dmar_domain *domain); |
ba395927 | 473 | static void domain_remove_dev_info(struct dmar_domain *domain); |
e6de0f8d JR |
474 | static void dmar_remove_one_dev_info(struct dmar_domain *domain, |
475 | struct device *dev); | |
127c7615 | 476 | static void __dmar_remove_one_dev_info(struct device_domain_info *info); |
2452d9db JR |
477 | static void domain_context_clear(struct intel_iommu *iommu, |
478 | struct device *dev); | |
2a46ddf7 JL |
479 | static int domain_detach_iommu(struct dmar_domain *domain, |
480 | struct intel_iommu *iommu); | |
ba395927 | 481 | |
d3f13810 | 482 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
0cd5c3c8 KM |
483 | int dmar_disabled = 0; |
484 | #else | |
485 | int dmar_disabled = 1; | |
d3f13810 | 486 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
0cd5c3c8 | 487 | |
8bc1f85c ED |
488 | int intel_iommu_enabled = 0; |
489 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); | |
490 | ||
2d9e667e | 491 | static int dmar_map_gfx = 1; |
7d3b03ce | 492 | static int dmar_forcedac; |
5e0d2a6f | 493 | static int intel_iommu_strict; |
6dd9a7c7 | 494 | static int intel_iommu_superpage = 1; |
c83b2f20 DW |
495 | static int intel_iommu_ecs = 1; |
496 | ||
497 | /* We only actually use ECS when PASID support (on the new bit 40) | |
498 | * is also advertised. Some early implementations — the ones with | |
499 | * PASID support on bit 28 — have issues even when we *only* use | |
500 | * extended root/context tables. */ | |
501 | #define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \ | |
502 | ecap_pasid(iommu->ecap)) | |
ba395927 | 503 | |
c0771df8 DW |
504 | int intel_iommu_gfx_mapped; |
505 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); | |
506 | ||
ba395927 KA |
507 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
508 | static DEFINE_SPINLOCK(device_domain_lock); | |
509 | static LIST_HEAD(device_domain_list); | |
510 | ||
b22f6434 | 511 | static const struct iommu_ops intel_iommu_ops; |
a8bcbb0d | 512 | |
4158c2ec JR |
513 | static bool translation_pre_enabled(struct intel_iommu *iommu) |
514 | { | |
515 | return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); | |
516 | } | |
517 | ||
091d42e4 JR |
518 | static void clear_translation_pre_enabled(struct intel_iommu *iommu) |
519 | { | |
520 | iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; | |
521 | } | |
522 | ||
4158c2ec JR |
523 | static void init_translation_status(struct intel_iommu *iommu) |
524 | { | |
525 | u32 gsts; | |
526 | ||
527 | gsts = readl(iommu->reg + DMAR_GSTS_REG); | |
528 | if (gsts & DMA_GSTS_TES) | |
529 | iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; | |
530 | } | |
531 | ||
00a77deb JR |
532 | /* Convert generic 'struct iommu_domain to private struct dmar_domain */ |
533 | static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) | |
534 | { | |
535 | return container_of(dom, struct dmar_domain, domain); | |
536 | } | |
537 | ||
ba395927 KA |
538 | static int __init intel_iommu_setup(char *str) |
539 | { | |
540 | if (!str) | |
541 | return -EINVAL; | |
542 | while (*str) { | |
0cd5c3c8 KM |
543 | if (!strncmp(str, "on", 2)) { |
544 | dmar_disabled = 0; | |
9f10e5bf | 545 | pr_info("IOMMU enabled\n"); |
0cd5c3c8 | 546 | } else if (!strncmp(str, "off", 3)) { |
ba395927 | 547 | dmar_disabled = 1; |
9f10e5bf | 548 | pr_info("IOMMU disabled\n"); |
ba395927 KA |
549 | } else if (!strncmp(str, "igfx_off", 8)) { |
550 | dmar_map_gfx = 0; | |
9f10e5bf | 551 | pr_info("Disable GFX device mapping\n"); |
7d3b03ce | 552 | } else if (!strncmp(str, "forcedac", 8)) { |
9f10e5bf | 553 | pr_info("Forcing DAC for PCI devices\n"); |
7d3b03ce | 554 | dmar_forcedac = 1; |
5e0d2a6f | 555 | } else if (!strncmp(str, "strict", 6)) { |
9f10e5bf | 556 | pr_info("Disable batched IOTLB flush\n"); |
5e0d2a6f | 557 | intel_iommu_strict = 1; |
6dd9a7c7 | 558 | } else if (!strncmp(str, "sp_off", 6)) { |
9f10e5bf | 559 | pr_info("Disable supported super page\n"); |
6dd9a7c7 | 560 | intel_iommu_superpage = 0; |
c83b2f20 DW |
561 | } else if (!strncmp(str, "ecs_off", 7)) { |
562 | printk(KERN_INFO | |
563 | "Intel-IOMMU: disable extended context table support\n"); | |
564 | intel_iommu_ecs = 0; | |
ba395927 KA |
565 | } |
566 | ||
567 | str += strcspn(str, ","); | |
568 | while (*str == ',') | |
569 | str++; | |
570 | } | |
571 | return 0; | |
572 | } | |
573 | __setup("intel_iommu=", intel_iommu_setup); | |
574 | ||
575 | static struct kmem_cache *iommu_domain_cache; | |
576 | static struct kmem_cache *iommu_devinfo_cache; | |
ba395927 | 577 | |
9452d5bf JR |
578 | static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did) |
579 | { | |
8bf47816 JR |
580 | struct dmar_domain **domains; |
581 | int idx = did >> 8; | |
582 | ||
583 | domains = iommu->domains[idx]; | |
584 | if (!domains) | |
585 | return NULL; | |
586 | ||
587 | return domains[did & 0xff]; | |
9452d5bf JR |
588 | } |
589 | ||
590 | static void set_iommu_domain(struct intel_iommu *iommu, u16 did, | |
591 | struct dmar_domain *domain) | |
592 | { | |
8bf47816 JR |
593 | struct dmar_domain **domains; |
594 | int idx = did >> 8; | |
595 | ||
596 | if (!iommu->domains[idx]) { | |
597 | size_t size = 256 * sizeof(struct dmar_domain *); | |
598 | iommu->domains[idx] = kzalloc(size, GFP_ATOMIC); | |
599 | } | |
600 | ||
601 | domains = iommu->domains[idx]; | |
602 | if (WARN_ON(!domains)) | |
603 | return; | |
604 | else | |
605 | domains[did & 0xff] = domain; | |
9452d5bf JR |
606 | } |
607 | ||
4c923d47 | 608 | static inline void *alloc_pgtable_page(int node) |
eb3fa7cb | 609 | { |
4c923d47 SS |
610 | struct page *page; |
611 | void *vaddr = NULL; | |
eb3fa7cb | 612 | |
4c923d47 SS |
613 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
614 | if (page) | |
615 | vaddr = page_address(page); | |
eb3fa7cb | 616 | return vaddr; |
ba395927 KA |
617 | } |
618 | ||
619 | static inline void free_pgtable_page(void *vaddr) | |
620 | { | |
621 | free_page((unsigned long)vaddr); | |
622 | } | |
623 | ||
624 | static inline void *alloc_domain_mem(void) | |
625 | { | |
354bb65e | 626 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
ba395927 KA |
627 | } |
628 | ||
38717946 | 629 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
630 | { |
631 | kmem_cache_free(iommu_domain_cache, vaddr); | |
632 | } | |
633 | ||
634 | static inline void * alloc_devinfo_mem(void) | |
635 | { | |
354bb65e | 636 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
ba395927 KA |
637 | } |
638 | ||
639 | static inline void free_devinfo_mem(void *vaddr) | |
640 | { | |
641 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
642 | } | |
643 | ||
ab8dfe25 JL |
644 | static inline int domain_type_is_vm(struct dmar_domain *domain) |
645 | { | |
646 | return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE; | |
647 | } | |
648 | ||
28ccce0d JR |
649 | static inline int domain_type_is_si(struct dmar_domain *domain) |
650 | { | |
651 | return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY; | |
652 | } | |
653 | ||
ab8dfe25 JL |
654 | static inline int domain_type_is_vm_or_si(struct dmar_domain *domain) |
655 | { | |
656 | return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE | | |
657 | DOMAIN_FLAG_STATIC_IDENTITY); | |
658 | } | |
1b573683 | 659 | |
162d1b10 JL |
660 | static inline int domain_pfn_supported(struct dmar_domain *domain, |
661 | unsigned long pfn) | |
662 | { | |
663 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; | |
664 | ||
665 | return !(addr_width < BITS_PER_LONG && pfn >> addr_width); | |
666 | } | |
667 | ||
4ed0d3e6 | 668 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
669 | { |
670 | unsigned long sagaw; | |
671 | int agaw = -1; | |
672 | ||
673 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 674 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
675 | agaw >= 0; agaw--) { |
676 | if (test_bit(agaw, &sagaw)) | |
677 | break; | |
678 | } | |
679 | ||
680 | return agaw; | |
681 | } | |
682 | ||
4ed0d3e6 FY |
683 | /* |
684 | * Calculate max SAGAW for each iommu. | |
685 | */ | |
686 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
687 | { | |
688 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
689 | } | |
690 | ||
691 | /* | |
692 | * calculate agaw for each iommu. | |
693 | * "SAGAW" may be different across iommus, use a default agaw, and | |
694 | * get a supported less agaw for iommus that don't support the default agaw. | |
695 | */ | |
696 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
697 | { | |
698 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
699 | } | |
700 | ||
2c2e2c38 | 701 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
702 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
703 | { | |
704 | int iommu_id; | |
705 | ||
2c2e2c38 | 706 | /* si_domain and vm domain should not get here. */ |
ab8dfe25 | 707 | BUG_ON(domain_type_is_vm_or_si(domain)); |
29a27719 JR |
708 | for_each_domain_iommu(iommu_id, domain) |
709 | break; | |
710 | ||
8c11e798 WH |
711 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
712 | return NULL; | |
713 | ||
714 | return g_iommus[iommu_id]; | |
715 | } | |
716 | ||
8e604097 WH |
717 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
718 | { | |
d0501960 DW |
719 | struct dmar_drhd_unit *drhd; |
720 | struct intel_iommu *iommu; | |
2f119c78 QL |
721 | bool found = false; |
722 | int i; | |
2e12bc29 | 723 | |
d0501960 | 724 | domain->iommu_coherency = 1; |
8e604097 | 725 | |
29a27719 | 726 | for_each_domain_iommu(i, domain) { |
2f119c78 | 727 | found = true; |
8e604097 WH |
728 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
729 | domain->iommu_coherency = 0; | |
730 | break; | |
731 | } | |
8e604097 | 732 | } |
d0501960 DW |
733 | if (found) |
734 | return; | |
735 | ||
736 | /* No hardware attached; use lowest common denominator */ | |
737 | rcu_read_lock(); | |
738 | for_each_active_iommu(iommu, drhd) { | |
739 | if (!ecap_coherent(iommu->ecap)) { | |
740 | domain->iommu_coherency = 0; | |
741 | break; | |
742 | } | |
743 | } | |
744 | rcu_read_unlock(); | |
8e604097 WH |
745 | } |
746 | ||
161f6934 | 747 | static int domain_update_iommu_snooping(struct intel_iommu *skip) |
58c610bd | 748 | { |
161f6934 JL |
749 | struct dmar_drhd_unit *drhd; |
750 | struct intel_iommu *iommu; | |
751 | int ret = 1; | |
58c610bd | 752 | |
161f6934 JL |
753 | rcu_read_lock(); |
754 | for_each_active_iommu(iommu, drhd) { | |
755 | if (iommu != skip) { | |
756 | if (!ecap_sc_support(iommu->ecap)) { | |
757 | ret = 0; | |
758 | break; | |
759 | } | |
58c610bd | 760 | } |
58c610bd | 761 | } |
161f6934 JL |
762 | rcu_read_unlock(); |
763 | ||
764 | return ret; | |
58c610bd SY |
765 | } |
766 | ||
161f6934 | 767 | static int domain_update_iommu_superpage(struct intel_iommu *skip) |
6dd9a7c7 | 768 | { |
8140a95d | 769 | struct dmar_drhd_unit *drhd; |
161f6934 | 770 | struct intel_iommu *iommu; |
8140a95d | 771 | int mask = 0xf; |
6dd9a7c7 YS |
772 | |
773 | if (!intel_iommu_superpage) { | |
161f6934 | 774 | return 0; |
6dd9a7c7 YS |
775 | } |
776 | ||
8140a95d | 777 | /* set iommu_superpage to the smallest common denominator */ |
0e242612 | 778 | rcu_read_lock(); |
8140a95d | 779 | for_each_active_iommu(iommu, drhd) { |
161f6934 JL |
780 | if (iommu != skip) { |
781 | mask &= cap_super_page_val(iommu->cap); | |
782 | if (!mask) | |
783 | break; | |
6dd9a7c7 YS |
784 | } |
785 | } | |
0e242612 JL |
786 | rcu_read_unlock(); |
787 | ||
161f6934 | 788 | return fls(mask); |
6dd9a7c7 YS |
789 | } |
790 | ||
58c610bd SY |
791 | /* Some capabilities may be different across iommus */ |
792 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
793 | { | |
794 | domain_update_iommu_coherency(domain); | |
161f6934 JL |
795 | domain->iommu_snooping = domain_update_iommu_snooping(NULL); |
796 | domain->iommu_superpage = domain_update_iommu_superpage(NULL); | |
58c610bd SY |
797 | } |
798 | ||
03ecc32c DW |
799 | static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu, |
800 | u8 bus, u8 devfn, int alloc) | |
801 | { | |
802 | struct root_entry *root = &iommu->root_entry[bus]; | |
803 | struct context_entry *context; | |
804 | u64 *entry; | |
805 | ||
c83b2f20 | 806 | if (ecs_enabled(iommu)) { |
03ecc32c DW |
807 | if (devfn >= 0x80) { |
808 | devfn -= 0x80; | |
809 | entry = &root->hi; | |
810 | } | |
811 | devfn *= 2; | |
812 | } | |
813 | entry = &root->lo; | |
814 | if (*entry & 1) | |
815 | context = phys_to_virt(*entry & VTD_PAGE_MASK); | |
816 | else { | |
817 | unsigned long phy_addr; | |
818 | if (!alloc) | |
819 | return NULL; | |
820 | ||
821 | context = alloc_pgtable_page(iommu->node); | |
822 | if (!context) | |
823 | return NULL; | |
824 | ||
825 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); | |
826 | phy_addr = virt_to_phys((void *)context); | |
827 | *entry = phy_addr | 1; | |
828 | __iommu_flush_cache(iommu, entry, sizeof(*entry)); | |
829 | } | |
830 | return &context[devfn]; | |
831 | } | |
832 | ||
4ed6a540 DW |
833 | static int iommu_dummy(struct device *dev) |
834 | { | |
835 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; | |
836 | } | |
837 | ||
156baca8 | 838 | static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) |
c7151a8d WH |
839 | { |
840 | struct dmar_drhd_unit *drhd = NULL; | |
b683b230 | 841 | struct intel_iommu *iommu; |
156baca8 DW |
842 | struct device *tmp; |
843 | struct pci_dev *ptmp, *pdev = NULL; | |
aa4d066a | 844 | u16 segment = 0; |
c7151a8d WH |
845 | int i; |
846 | ||
4ed6a540 DW |
847 | if (iommu_dummy(dev)) |
848 | return NULL; | |
849 | ||
156baca8 DW |
850 | if (dev_is_pci(dev)) { |
851 | pdev = to_pci_dev(dev); | |
852 | segment = pci_domain_nr(pdev->bus); | |
ca5b74d2 | 853 | } else if (has_acpi_companion(dev)) |
156baca8 DW |
854 | dev = &ACPI_COMPANION(dev)->dev; |
855 | ||
0e242612 | 856 | rcu_read_lock(); |
b683b230 | 857 | for_each_active_iommu(iommu, drhd) { |
156baca8 | 858 | if (pdev && segment != drhd->segment) |
276dbf99 | 859 | continue; |
c7151a8d | 860 | |
b683b230 | 861 | for_each_active_dev_scope(drhd->devices, |
156baca8 DW |
862 | drhd->devices_cnt, i, tmp) { |
863 | if (tmp == dev) { | |
864 | *bus = drhd->devices[i].bus; | |
865 | *devfn = drhd->devices[i].devfn; | |
b683b230 | 866 | goto out; |
156baca8 DW |
867 | } |
868 | ||
869 | if (!pdev || !dev_is_pci(tmp)) | |
870 | continue; | |
871 | ||
872 | ptmp = to_pci_dev(tmp); | |
873 | if (ptmp->subordinate && | |
874 | ptmp->subordinate->number <= pdev->bus->number && | |
875 | ptmp->subordinate->busn_res.end >= pdev->bus->number) | |
876 | goto got_pdev; | |
924b6231 | 877 | } |
c7151a8d | 878 | |
156baca8 DW |
879 | if (pdev && drhd->include_all) { |
880 | got_pdev: | |
881 | *bus = pdev->bus->number; | |
882 | *devfn = pdev->devfn; | |
b683b230 | 883 | goto out; |
156baca8 | 884 | } |
c7151a8d | 885 | } |
b683b230 | 886 | iommu = NULL; |
156baca8 | 887 | out: |
0e242612 | 888 | rcu_read_unlock(); |
c7151a8d | 889 | |
b683b230 | 890 | return iommu; |
c7151a8d WH |
891 | } |
892 | ||
5331fe6f WH |
893 | static void domain_flush_cache(struct dmar_domain *domain, |
894 | void *addr, int size) | |
895 | { | |
896 | if (!domain->iommu_coherency) | |
897 | clflush_cache_range(addr, size); | |
898 | } | |
899 | ||
ba395927 KA |
900 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) |
901 | { | |
ba395927 | 902 | struct context_entry *context; |
03ecc32c | 903 | int ret = 0; |
ba395927 KA |
904 | unsigned long flags; |
905 | ||
906 | spin_lock_irqsave(&iommu->lock, flags); | |
03ecc32c DW |
907 | context = iommu_context_addr(iommu, bus, devfn, 0); |
908 | if (context) | |
909 | ret = context_present(context); | |
ba395927 KA |
910 | spin_unlock_irqrestore(&iommu->lock, flags); |
911 | return ret; | |
912 | } | |
913 | ||
914 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
915 | { | |
ba395927 KA |
916 | struct context_entry *context; |
917 | unsigned long flags; | |
918 | ||
919 | spin_lock_irqsave(&iommu->lock, flags); | |
03ecc32c | 920 | context = iommu_context_addr(iommu, bus, devfn, 0); |
ba395927 | 921 | if (context) { |
03ecc32c DW |
922 | context_clear_entry(context); |
923 | __iommu_flush_cache(iommu, context, sizeof(*context)); | |
ba395927 KA |
924 | } |
925 | spin_unlock_irqrestore(&iommu->lock, flags); | |
926 | } | |
927 | ||
928 | static void free_context_table(struct intel_iommu *iommu) | |
929 | { | |
ba395927 KA |
930 | int i; |
931 | unsigned long flags; | |
932 | struct context_entry *context; | |
933 | ||
934 | spin_lock_irqsave(&iommu->lock, flags); | |
935 | if (!iommu->root_entry) { | |
936 | goto out; | |
937 | } | |
938 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
03ecc32c | 939 | context = iommu_context_addr(iommu, i, 0, 0); |
ba395927 KA |
940 | if (context) |
941 | free_pgtable_page(context); | |
03ecc32c | 942 | |
c83b2f20 | 943 | if (!ecs_enabled(iommu)) |
03ecc32c DW |
944 | continue; |
945 | ||
946 | context = iommu_context_addr(iommu, i, 0x80, 0); | |
947 | if (context) | |
948 | free_pgtable_page(context); | |
949 | ||
ba395927 KA |
950 | } |
951 | free_pgtable_page(iommu->root_entry); | |
952 | iommu->root_entry = NULL; | |
953 | out: | |
954 | spin_unlock_irqrestore(&iommu->lock, flags); | |
955 | } | |
956 | ||
b026fd28 | 957 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
5cf0a76f | 958 | unsigned long pfn, int *target_level) |
ba395927 | 959 | { |
ba395927 KA |
960 | struct dma_pte *parent, *pte = NULL; |
961 | int level = agaw_to_level(domain->agaw); | |
4399c8bf | 962 | int offset; |
ba395927 KA |
963 | |
964 | BUG_ON(!domain->pgd); | |
f9423606 | 965 | |
162d1b10 | 966 | if (!domain_pfn_supported(domain, pfn)) |
f9423606 JS |
967 | /* Address beyond IOMMU's addressing capabilities. */ |
968 | return NULL; | |
969 | ||
ba395927 KA |
970 | parent = domain->pgd; |
971 | ||
5cf0a76f | 972 | while (1) { |
ba395927 KA |
973 | void *tmp_page; |
974 | ||
b026fd28 | 975 | offset = pfn_level_offset(pfn, level); |
ba395927 | 976 | pte = &parent[offset]; |
5cf0a76f | 977 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
6dd9a7c7 | 978 | break; |
5cf0a76f | 979 | if (level == *target_level) |
ba395927 KA |
980 | break; |
981 | ||
19c239ce | 982 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
983 | uint64_t pteval; |
984 | ||
4c923d47 | 985 | tmp_page = alloc_pgtable_page(domain->nid); |
ba395927 | 986 | |
206a73c1 | 987 | if (!tmp_page) |
ba395927 | 988 | return NULL; |
206a73c1 | 989 | |
c85994e4 | 990 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
64de5af0 | 991 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
effad4b5 | 992 | if (cmpxchg64(&pte->val, 0ULL, pteval)) |
c85994e4 DW |
993 | /* Someone else set it while we were thinking; use theirs. */ |
994 | free_pgtable_page(tmp_page); | |
effad4b5 | 995 | else |
c85994e4 | 996 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 | 997 | } |
5cf0a76f DW |
998 | if (level == 1) |
999 | break; | |
1000 | ||
19c239ce | 1001 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
1002 | level--; |
1003 | } | |
1004 | ||
5cf0a76f DW |
1005 | if (!*target_level) |
1006 | *target_level = level; | |
1007 | ||
ba395927 KA |
1008 | return pte; |
1009 | } | |
1010 | ||
6dd9a7c7 | 1011 | |
ba395927 | 1012 | /* return address's pte at specific level */ |
90dcfb5e DW |
1013 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
1014 | unsigned long pfn, | |
6dd9a7c7 | 1015 | int level, int *large_page) |
ba395927 KA |
1016 | { |
1017 | struct dma_pte *parent, *pte = NULL; | |
1018 | int total = agaw_to_level(domain->agaw); | |
1019 | int offset; | |
1020 | ||
1021 | parent = domain->pgd; | |
1022 | while (level <= total) { | |
90dcfb5e | 1023 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
1024 | pte = &parent[offset]; |
1025 | if (level == total) | |
1026 | return pte; | |
1027 | ||
6dd9a7c7 YS |
1028 | if (!dma_pte_present(pte)) { |
1029 | *large_page = total; | |
ba395927 | 1030 | break; |
6dd9a7c7 YS |
1031 | } |
1032 | ||
e16922af | 1033 | if (dma_pte_superpage(pte)) { |
6dd9a7c7 YS |
1034 | *large_page = total; |
1035 | return pte; | |
1036 | } | |
1037 | ||
19c239ce | 1038 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
1039 | total--; |
1040 | } | |
1041 | return NULL; | |
1042 | } | |
1043 | ||
ba395927 | 1044 | /* clear last level pte, a tlb flush should be followed */ |
5cf0a76f | 1045 | static void dma_pte_clear_range(struct dmar_domain *domain, |
595badf5 DW |
1046 | unsigned long start_pfn, |
1047 | unsigned long last_pfn) | |
ba395927 | 1048 | { |
6dd9a7c7 | 1049 | unsigned int large_page = 1; |
310a5ab9 | 1050 | struct dma_pte *first_pte, *pte; |
66eae846 | 1051 | |
162d1b10 JL |
1052 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1053 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
59c36286 | 1054 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 1055 | |
04b18e65 | 1056 | /* we don't need lock here; nobody else touches the iova range */ |
59c36286 | 1057 | do { |
6dd9a7c7 YS |
1058 | large_page = 1; |
1059 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); | |
310a5ab9 | 1060 | if (!pte) { |
6dd9a7c7 | 1061 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
310a5ab9 DW |
1062 | continue; |
1063 | } | |
6dd9a7c7 | 1064 | do { |
310a5ab9 | 1065 | dma_clear_pte(pte); |
6dd9a7c7 | 1066 | start_pfn += lvl_to_nr_pages(large_page); |
310a5ab9 | 1067 | pte++; |
75e6bf96 DW |
1068 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
1069 | ||
310a5ab9 DW |
1070 | domain_flush_cache(domain, first_pte, |
1071 | (void *)pte - (void *)first_pte); | |
59c36286 DW |
1072 | |
1073 | } while (start_pfn && start_pfn <= last_pfn); | |
ba395927 KA |
1074 | } |
1075 | ||
3269ee0b AW |
1076 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
1077 | struct dma_pte *pte, unsigned long pfn, | |
1078 | unsigned long start_pfn, unsigned long last_pfn) | |
1079 | { | |
1080 | pfn = max(start_pfn, pfn); | |
1081 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1082 | ||
1083 | do { | |
1084 | unsigned long level_pfn; | |
1085 | struct dma_pte *level_pte; | |
1086 | ||
1087 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) | |
1088 | goto next; | |
1089 | ||
1090 | level_pfn = pfn & level_mask(level - 1); | |
1091 | level_pte = phys_to_virt(dma_pte_addr(pte)); | |
1092 | ||
1093 | if (level > 2) | |
1094 | dma_pte_free_level(domain, level - 1, level_pte, | |
1095 | level_pfn, start_pfn, last_pfn); | |
1096 | ||
1097 | /* If range covers entire pagetable, free it */ | |
1098 | if (!(start_pfn > level_pfn || | |
08336fd2 | 1099 | last_pfn < level_pfn + level_size(level) - 1)) { |
3269ee0b AW |
1100 | dma_clear_pte(pte); |
1101 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
1102 | free_pgtable_page(level_pte); | |
1103 | } | |
1104 | next: | |
1105 | pfn += level_size(level); | |
1106 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1107 | } | |
1108 | ||
ba395927 KA |
1109 | /* free page table pages. last level pte should already be cleared */ |
1110 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
1111 | unsigned long start_pfn, |
1112 | unsigned long last_pfn) | |
ba395927 | 1113 | { |
162d1b10 JL |
1114 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1115 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
59c36286 | 1116 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 1117 | |
d41a4adb JL |
1118 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
1119 | ||
f3a0a52f | 1120 | /* We don't need lock here; nobody else touches the iova range */ |
3269ee0b AW |
1121 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
1122 | domain->pgd, 0, start_pfn, last_pfn); | |
6660c63a | 1123 | |
ba395927 | 1124 | /* free pgd */ |
d794dc9b | 1125 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
1126 | free_pgtable_page(domain->pgd); |
1127 | domain->pgd = NULL; | |
1128 | } | |
1129 | } | |
1130 | ||
ea8ea460 DW |
1131 | /* When a page at a given level is being unlinked from its parent, we don't |
1132 | need to *modify* it at all. All we need to do is make a list of all the | |
1133 | pages which can be freed just as soon as we've flushed the IOTLB and we | |
1134 | know the hardware page-walk will no longer touch them. | |
1135 | The 'pte' argument is the *parent* PTE, pointing to the page that is to | |
1136 | be freed. */ | |
1137 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, | |
1138 | int level, struct dma_pte *pte, | |
1139 | struct page *freelist) | |
1140 | { | |
1141 | struct page *pg; | |
1142 | ||
1143 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); | |
1144 | pg->freelist = freelist; | |
1145 | freelist = pg; | |
1146 | ||
1147 | if (level == 1) | |
1148 | return freelist; | |
1149 | ||
adeb2590 JL |
1150 | pte = page_address(pg); |
1151 | do { | |
ea8ea460 DW |
1152 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
1153 | freelist = dma_pte_list_pagetables(domain, level - 1, | |
1154 | pte, freelist); | |
adeb2590 JL |
1155 | pte++; |
1156 | } while (!first_pte_in_page(pte)); | |
ea8ea460 DW |
1157 | |
1158 | return freelist; | |
1159 | } | |
1160 | ||
1161 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, | |
1162 | struct dma_pte *pte, unsigned long pfn, | |
1163 | unsigned long start_pfn, | |
1164 | unsigned long last_pfn, | |
1165 | struct page *freelist) | |
1166 | { | |
1167 | struct dma_pte *first_pte = NULL, *last_pte = NULL; | |
1168 | ||
1169 | pfn = max(start_pfn, pfn); | |
1170 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1171 | ||
1172 | do { | |
1173 | unsigned long level_pfn; | |
1174 | ||
1175 | if (!dma_pte_present(pte)) | |
1176 | goto next; | |
1177 | ||
1178 | level_pfn = pfn & level_mask(level); | |
1179 | ||
1180 | /* If range covers entire pagetable, free it */ | |
1181 | if (start_pfn <= level_pfn && | |
1182 | last_pfn >= level_pfn + level_size(level) - 1) { | |
1183 | /* These suborbinate page tables are going away entirely. Don't | |
1184 | bother to clear them; we're just going to *free* them. */ | |
1185 | if (level > 1 && !dma_pte_superpage(pte)) | |
1186 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); | |
1187 | ||
1188 | dma_clear_pte(pte); | |
1189 | if (!first_pte) | |
1190 | first_pte = pte; | |
1191 | last_pte = pte; | |
1192 | } else if (level > 1) { | |
1193 | /* Recurse down into a level that isn't *entirely* obsolete */ | |
1194 | freelist = dma_pte_clear_level(domain, level - 1, | |
1195 | phys_to_virt(dma_pte_addr(pte)), | |
1196 | level_pfn, start_pfn, last_pfn, | |
1197 | freelist); | |
1198 | } | |
1199 | next: | |
1200 | pfn += level_size(level); | |
1201 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1202 | ||
1203 | if (first_pte) | |
1204 | domain_flush_cache(domain, first_pte, | |
1205 | (void *)++last_pte - (void *)first_pte); | |
1206 | ||
1207 | return freelist; | |
1208 | } | |
1209 | ||
1210 | /* We can't just free the pages because the IOMMU may still be walking | |
1211 | the page tables, and may have cached the intermediate levels. The | |
1212 | pages can only be freed after the IOTLB flush has been done. */ | |
b690420a JR |
1213 | static struct page *domain_unmap(struct dmar_domain *domain, |
1214 | unsigned long start_pfn, | |
1215 | unsigned long last_pfn) | |
ea8ea460 | 1216 | { |
ea8ea460 DW |
1217 | struct page *freelist = NULL; |
1218 | ||
162d1b10 JL |
1219 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1220 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
ea8ea460 DW |
1221 | BUG_ON(start_pfn > last_pfn); |
1222 | ||
1223 | /* we don't need lock here; nobody else touches the iova range */ | |
1224 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), | |
1225 | domain->pgd, 0, start_pfn, last_pfn, NULL); | |
1226 | ||
1227 | /* free pgd */ | |
1228 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { | |
1229 | struct page *pgd_page = virt_to_page(domain->pgd); | |
1230 | pgd_page->freelist = freelist; | |
1231 | freelist = pgd_page; | |
1232 | ||
1233 | domain->pgd = NULL; | |
1234 | } | |
1235 | ||
1236 | return freelist; | |
1237 | } | |
1238 | ||
b690420a | 1239 | static void dma_free_pagelist(struct page *freelist) |
ea8ea460 DW |
1240 | { |
1241 | struct page *pg; | |
1242 | ||
1243 | while ((pg = freelist)) { | |
1244 | freelist = pg->freelist; | |
1245 | free_pgtable_page(page_address(pg)); | |
1246 | } | |
1247 | } | |
1248 | ||
ba395927 KA |
1249 | /* iommu handling */ |
1250 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
1251 | { | |
1252 | struct root_entry *root; | |
1253 | unsigned long flags; | |
1254 | ||
4c923d47 | 1255 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
ffebeb46 | 1256 | if (!root) { |
9f10e5bf | 1257 | pr_err("Allocating root entry for %s failed\n", |
ffebeb46 | 1258 | iommu->name); |
ba395927 | 1259 | return -ENOMEM; |
ffebeb46 | 1260 | } |
ba395927 | 1261 | |
5b6985ce | 1262 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
1263 | |
1264 | spin_lock_irqsave(&iommu->lock, flags); | |
1265 | iommu->root_entry = root; | |
1266 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
ba395927 KA |
1271 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
1272 | { | |
03ecc32c | 1273 | u64 addr; |
c416daa9 | 1274 | u32 sts; |
ba395927 KA |
1275 | unsigned long flag; |
1276 | ||
03ecc32c | 1277 | addr = virt_to_phys(iommu->root_entry); |
c83b2f20 | 1278 | if (ecs_enabled(iommu)) |
03ecc32c | 1279 | addr |= DMA_RTADDR_RTT; |
ba395927 | 1280 | |
1f5b3c3f | 1281 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
03ecc32c | 1282 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); |
ba395927 | 1283 | |
c416daa9 | 1284 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1285 | |
1286 | /* Make sure hardware complete it */ | |
1287 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1288 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 | 1289 | |
1f5b3c3f | 1290 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1291 | } |
1292 | ||
1293 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
1294 | { | |
1295 | u32 val; | |
1296 | unsigned long flag; | |
1297 | ||
9af88143 | 1298 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 1299 | return; |
ba395927 | 1300 | |
1f5b3c3f | 1301 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
462b60f6 | 1302 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1303 | |
1304 | /* Make sure hardware complete it */ | |
1305 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1306 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 | 1307 | |
1f5b3c3f | 1308 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1309 | } |
1310 | ||
1311 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
1312 | static void __iommu_flush_context(struct intel_iommu *iommu, |
1313 | u16 did, u16 source_id, u8 function_mask, | |
1314 | u64 type) | |
ba395927 KA |
1315 | { |
1316 | u64 val = 0; | |
1317 | unsigned long flag; | |
1318 | ||
ba395927 KA |
1319 | switch (type) { |
1320 | case DMA_CCMD_GLOBAL_INVL: | |
1321 | val = DMA_CCMD_GLOBAL_INVL; | |
1322 | break; | |
1323 | case DMA_CCMD_DOMAIN_INVL: | |
1324 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
1325 | break; | |
1326 | case DMA_CCMD_DEVICE_INVL: | |
1327 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
1328 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
1329 | break; | |
1330 | default: | |
1331 | BUG(); | |
1332 | } | |
1333 | val |= DMA_CCMD_ICC; | |
1334 | ||
1f5b3c3f | 1335 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1336 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
1337 | ||
1338 | /* Make sure hardware complete it */ | |
1339 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
1340 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
1341 | ||
1f5b3c3f | 1342 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1343 | } |
1344 | ||
ba395927 | 1345 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
1346 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
1347 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
1348 | { |
1349 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
1350 | u64 val = 0, val_iva = 0; | |
1351 | unsigned long flag; | |
1352 | ||
ba395927 KA |
1353 | switch (type) { |
1354 | case DMA_TLB_GLOBAL_FLUSH: | |
1355 | /* global flush doesn't need set IVA_REG */ | |
1356 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
1357 | break; | |
1358 | case DMA_TLB_DSI_FLUSH: | |
1359 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
1360 | break; | |
1361 | case DMA_TLB_PSI_FLUSH: | |
1362 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
ea8ea460 | 1363 | /* IH bit is passed in as part of address */ |
ba395927 KA |
1364 | val_iva = size_order | addr; |
1365 | break; | |
1366 | default: | |
1367 | BUG(); | |
1368 | } | |
1369 | /* Note: set drain read/write */ | |
1370 | #if 0 | |
1371 | /* | |
1372 | * This is probably to be super secure.. Looks like we can | |
1373 | * ignore it without any impact. | |
1374 | */ | |
1375 | if (cap_read_drain(iommu->cap)) | |
1376 | val |= DMA_TLB_READ_DRAIN; | |
1377 | #endif | |
1378 | if (cap_write_drain(iommu->cap)) | |
1379 | val |= DMA_TLB_WRITE_DRAIN; | |
1380 | ||
1f5b3c3f | 1381 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1382 | /* Note: Only uses first TLB reg currently */ |
1383 | if (val_iva) | |
1384 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
1385 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
1386 | ||
1387 | /* Make sure hardware complete it */ | |
1388 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
1389 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
1390 | ||
1f5b3c3f | 1391 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1392 | |
1393 | /* check IOTLB invalidation granularity */ | |
1394 | if (DMA_TLB_IAIG(val) == 0) | |
9f10e5bf | 1395 | pr_err("Flush IOTLB failed\n"); |
ba395927 | 1396 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) |
9f10e5bf | 1397 | pr_debug("TLB flush request %Lx, actual %Lx\n", |
5b6985ce FY |
1398 | (unsigned long long)DMA_TLB_IIRG(type), |
1399 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
1400 | } |
1401 | ||
64ae892b DW |
1402 | static struct device_domain_info * |
1403 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, | |
1404 | u8 bus, u8 devfn) | |
93a23a72 | 1405 | { |
2f119c78 | 1406 | bool found = false; |
93a23a72 | 1407 | struct device_domain_info *info; |
0bcb3e28 | 1408 | struct pci_dev *pdev; |
93a23a72 | 1409 | |
55d94043 JR |
1410 | assert_spin_locked(&device_domain_lock); |
1411 | ||
93a23a72 YZ |
1412 | if (!ecap_dev_iotlb_support(iommu->ecap)) |
1413 | return NULL; | |
1414 | ||
1415 | if (!iommu->qi) | |
1416 | return NULL; | |
1417 | ||
93a23a72 | 1418 | list_for_each_entry(info, &domain->devices, link) |
c3b497c6 JL |
1419 | if (info->iommu == iommu && info->bus == bus && |
1420 | info->devfn == devfn) { | |
2f119c78 | 1421 | found = true; |
93a23a72 YZ |
1422 | break; |
1423 | } | |
93a23a72 | 1424 | |
0bcb3e28 | 1425 | if (!found || !info->dev || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1426 | return NULL; |
1427 | ||
0bcb3e28 DW |
1428 | pdev = to_pci_dev(info->dev); |
1429 | ||
1430 | if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS)) | |
93a23a72 YZ |
1431 | return NULL; |
1432 | ||
0bcb3e28 | 1433 | if (!dmar_find_matched_atsr_unit(pdev)) |
93a23a72 YZ |
1434 | return NULL; |
1435 | ||
93a23a72 YZ |
1436 | return info; |
1437 | } | |
1438 | ||
1439 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1440 | { |
0bcb3e28 | 1441 | if (!info || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1442 | return; |
1443 | ||
0bcb3e28 | 1444 | pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT); |
93a23a72 YZ |
1445 | } |
1446 | ||
1447 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1448 | { | |
0bcb3e28 DW |
1449 | if (!info->dev || !dev_is_pci(info->dev) || |
1450 | !pci_ats_enabled(to_pci_dev(info->dev))) | |
93a23a72 YZ |
1451 | return; |
1452 | ||
0bcb3e28 | 1453 | pci_disable_ats(to_pci_dev(info->dev)); |
93a23a72 YZ |
1454 | } |
1455 | ||
1456 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1457 | u64 addr, unsigned mask) | |
1458 | { | |
1459 | u16 sid, qdep; | |
1460 | unsigned long flags; | |
1461 | struct device_domain_info *info; | |
1462 | ||
1463 | spin_lock_irqsave(&device_domain_lock, flags); | |
1464 | list_for_each_entry(info, &domain->devices, link) { | |
0bcb3e28 DW |
1465 | struct pci_dev *pdev; |
1466 | if (!info->dev || !dev_is_pci(info->dev)) | |
1467 | continue; | |
1468 | ||
1469 | pdev = to_pci_dev(info->dev); | |
1470 | if (!pci_ats_enabled(pdev)) | |
93a23a72 YZ |
1471 | continue; |
1472 | ||
1473 | sid = info->bus << 8 | info->devfn; | |
0bcb3e28 | 1474 | qdep = pci_ats_queue_depth(pdev); |
93a23a72 YZ |
1475 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
1476 | } | |
1477 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1478 | } | |
1479 | ||
a1ddcbe9 JR |
1480 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, |
1481 | struct dmar_domain *domain, | |
1482 | unsigned long pfn, unsigned int pages, | |
1483 | int ih, int map) | |
ba395927 | 1484 | { |
9dd2fe89 | 1485 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1486 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
a1ddcbe9 | 1487 | u16 did = domain->iommu_did[iommu->seq_id]; |
ba395927 | 1488 | |
ba395927 KA |
1489 | BUG_ON(pages == 0); |
1490 | ||
ea8ea460 DW |
1491 | if (ih) |
1492 | ih = 1 << 6; | |
ba395927 | 1493 | /* |
9dd2fe89 YZ |
1494 | * Fallback to domain selective flush if no PSI support or the size is |
1495 | * too big. | |
ba395927 KA |
1496 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1497 | * aligned to the size | |
1498 | */ | |
9dd2fe89 YZ |
1499 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1500 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1501 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 | 1502 | else |
ea8ea460 | 1503 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
9dd2fe89 | 1504 | DMA_TLB_PSI_FLUSH); |
bf92df30 YZ |
1505 | |
1506 | /* | |
82653633 NA |
1507 | * In caching mode, changes of pages from non-present to present require |
1508 | * flush. However, device IOTLB doesn't need to be flushed in this case. | |
bf92df30 | 1509 | */ |
82653633 | 1510 | if (!cap_caching_mode(iommu->cap) || !map) |
9452d5bf JR |
1511 | iommu_flush_dev_iotlb(get_iommu_domain(iommu, did), |
1512 | addr, mask); | |
ba395927 KA |
1513 | } |
1514 | ||
f8bab735 | 1515 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1516 | { | |
1517 | u32 pmen; | |
1518 | unsigned long flags; | |
1519 | ||
1f5b3c3f | 1520 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
f8bab735 | 1521 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
1522 | pmen &= ~DMA_PMEN_EPM; | |
1523 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1524 | ||
1525 | /* wait for the protected region status bit to clear */ | |
1526 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1527 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1528 | ||
1f5b3c3f | 1529 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
f8bab735 | 1530 | } |
1531 | ||
2a41ccee | 1532 | static void iommu_enable_translation(struct intel_iommu *iommu) |
ba395927 KA |
1533 | { |
1534 | u32 sts; | |
1535 | unsigned long flags; | |
1536 | ||
1f5b3c3f | 1537 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
c416daa9 DW |
1538 | iommu->gcmd |= DMA_GCMD_TE; |
1539 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1540 | |
1541 | /* Make sure hardware complete it */ | |
1542 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1543 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1544 | |
1f5b3c3f | 1545 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
ba395927 KA |
1546 | } |
1547 | ||
2a41ccee | 1548 | static void iommu_disable_translation(struct intel_iommu *iommu) |
ba395927 KA |
1549 | { |
1550 | u32 sts; | |
1551 | unsigned long flag; | |
1552 | ||
1f5b3c3f | 1553 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1554 | iommu->gcmd &= ~DMA_GCMD_TE; |
1555 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1556 | ||
1557 | /* Make sure hardware complete it */ | |
1558 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1559 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 | 1560 | |
1f5b3c3f | 1561 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1562 | } |
1563 | ||
3460a6d9 | 1564 | |
ba395927 KA |
1565 | static int iommu_init_domains(struct intel_iommu *iommu) |
1566 | { | |
8bf47816 JR |
1567 | u32 ndomains, nlongs; |
1568 | size_t size; | |
ba395927 KA |
1569 | |
1570 | ndomains = cap_ndoms(iommu->cap); | |
8bf47816 | 1571 | pr_debug("%s: Number of Domains supported <%d>\n", |
9f10e5bf | 1572 | iommu->name, ndomains); |
ba395927 KA |
1573 | nlongs = BITS_TO_LONGS(ndomains); |
1574 | ||
94a91b50 DD |
1575 | spin_lock_init(&iommu->lock); |
1576 | ||
ba395927 KA |
1577 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); |
1578 | if (!iommu->domain_ids) { | |
9f10e5bf JR |
1579 | pr_err("%s: Allocating domain id array failed\n", |
1580 | iommu->name); | |
ba395927 KA |
1581 | return -ENOMEM; |
1582 | } | |
8bf47816 JR |
1583 | |
1584 | size = ((ndomains >> 8) + 1) * sizeof(struct dmar_domain **); | |
1585 | iommu->domains = kzalloc(size, GFP_KERNEL); | |
1586 | ||
1587 | if (iommu->domains) { | |
1588 | size = 256 * sizeof(struct dmar_domain *); | |
1589 | iommu->domains[0] = kzalloc(size, GFP_KERNEL); | |
1590 | } | |
1591 | ||
1592 | if (!iommu->domains || !iommu->domains[0]) { | |
9f10e5bf JR |
1593 | pr_err("%s: Allocating domain array failed\n", |
1594 | iommu->name); | |
852bdb04 | 1595 | kfree(iommu->domain_ids); |
8bf47816 | 1596 | kfree(iommu->domains); |
852bdb04 | 1597 | iommu->domain_ids = NULL; |
8bf47816 | 1598 | iommu->domains = NULL; |
ba395927 KA |
1599 | return -ENOMEM; |
1600 | } | |
1601 | ||
8bf47816 JR |
1602 | |
1603 | ||
ba395927 | 1604 | /* |
c0e8a6c8 JR |
1605 | * If Caching mode is set, then invalid translations are tagged |
1606 | * with domain-id 0, hence we need to pre-allocate it. We also | |
1607 | * use domain-id 0 as a marker for non-allocated domain-id, so | |
1608 | * make sure it is not used for a real domain. | |
ba395927 | 1609 | */ |
c0e8a6c8 JR |
1610 | set_bit(0, iommu->domain_ids); |
1611 | ||
ba395927 KA |
1612 | return 0; |
1613 | } | |
ba395927 | 1614 | |
ffebeb46 | 1615 | static void disable_dmar_iommu(struct intel_iommu *iommu) |
ba395927 | 1616 | { |
29a27719 | 1617 | struct device_domain_info *info, *tmp; |
55d94043 | 1618 | unsigned long flags; |
ba395927 | 1619 | |
29a27719 JR |
1620 | if (!iommu->domains || !iommu->domain_ids) |
1621 | return; | |
a4eaa86c | 1622 | |
55d94043 | 1623 | spin_lock_irqsave(&device_domain_lock, flags); |
29a27719 JR |
1624 | list_for_each_entry_safe(info, tmp, &device_domain_list, global) { |
1625 | struct dmar_domain *domain; | |
1626 | ||
1627 | if (info->iommu != iommu) | |
1628 | continue; | |
1629 | ||
1630 | if (!info->dev || !info->domain) | |
1631 | continue; | |
1632 | ||
1633 | domain = info->domain; | |
1634 | ||
e6de0f8d | 1635 | dmar_remove_one_dev_info(domain, info->dev); |
29a27719 JR |
1636 | |
1637 | if (!domain_type_is_vm_or_si(domain)) | |
1638 | domain_exit(domain); | |
ba395927 | 1639 | } |
55d94043 | 1640 | spin_unlock_irqrestore(&device_domain_lock, flags); |
ba395927 KA |
1641 | |
1642 | if (iommu->gcmd & DMA_GCMD_TE) | |
1643 | iommu_disable_translation(iommu); | |
ffebeb46 | 1644 | } |
ba395927 | 1645 | |
ffebeb46 JL |
1646 | static void free_dmar_iommu(struct intel_iommu *iommu) |
1647 | { | |
1648 | if ((iommu->domains) && (iommu->domain_ids)) { | |
8bf47816 JR |
1649 | int elems = (cap_ndoms(iommu->cap) >> 8) + 1; |
1650 | int i; | |
1651 | ||
1652 | for (i = 0; i < elems; i++) | |
1653 | kfree(iommu->domains[i]); | |
ffebeb46 JL |
1654 | kfree(iommu->domains); |
1655 | kfree(iommu->domain_ids); | |
1656 | iommu->domains = NULL; | |
1657 | iommu->domain_ids = NULL; | |
1658 | } | |
ba395927 | 1659 | |
d9630fe9 WH |
1660 | g_iommus[iommu->seq_id] = NULL; |
1661 | ||
ba395927 KA |
1662 | /* free context mapping */ |
1663 | free_context_table(iommu); | |
ba395927 KA |
1664 | } |
1665 | ||
ab8dfe25 | 1666 | static struct dmar_domain *alloc_domain(int flags) |
ba395927 | 1667 | { |
ba395927 | 1668 | struct dmar_domain *domain; |
ba395927 KA |
1669 | |
1670 | domain = alloc_domain_mem(); | |
1671 | if (!domain) | |
1672 | return NULL; | |
1673 | ||
ab8dfe25 | 1674 | memset(domain, 0, sizeof(*domain)); |
4c923d47 | 1675 | domain->nid = -1; |
ab8dfe25 | 1676 | domain->flags = flags; |
92d03cc8 | 1677 | INIT_LIST_HEAD(&domain->devices); |
2c2e2c38 FY |
1678 | |
1679 | return domain; | |
1680 | } | |
1681 | ||
d160aca5 JR |
1682 | /* Must be called with iommu->lock */ |
1683 | static int domain_attach_iommu(struct dmar_domain *domain, | |
fb170fb4 JL |
1684 | struct intel_iommu *iommu) |
1685 | { | |
d160aca5 | 1686 | unsigned long ndomains; |
55d94043 | 1687 | int num; |
c0e8a6c8 | 1688 | |
55d94043 | 1689 | assert_spin_locked(&device_domain_lock); |
d160aca5 | 1690 | assert_spin_locked(&iommu->lock); |
fb170fb4 | 1691 | |
29a27719 JR |
1692 | domain->iommu_refcnt[iommu->seq_id] += 1; |
1693 | domain->iommu_count += 1; | |
1694 | if (domain->iommu_refcnt[iommu->seq_id] == 1) { | |
d160aca5 JR |
1695 | ndomains = cap_ndoms(iommu->cap); |
1696 | num = find_first_zero_bit(iommu->domain_ids, ndomains); | |
1697 | ||
1698 | if (num >= ndomains) { | |
1699 | pr_err("%s: No free domain ids\n", iommu->name); | |
1700 | domain->iommu_refcnt[iommu->seq_id] -= 1; | |
1701 | domain->iommu_count -= 1; | |
55d94043 | 1702 | return -ENOSPC; |
d160aca5 JR |
1703 | } |
1704 | ||
1705 | set_bit(num, iommu->domain_ids); | |
1706 | set_iommu_domain(iommu, num, domain); | |
1707 | ||
1708 | domain->iommu_did[iommu->seq_id] = num; | |
1709 | domain->nid = iommu->node; | |
1710 | ||
fb170fb4 JL |
1711 | domain_update_iommu_cap(domain); |
1712 | } | |
d160aca5 | 1713 | |
55d94043 | 1714 | return 0; |
fb170fb4 JL |
1715 | } |
1716 | ||
1717 | static int domain_detach_iommu(struct dmar_domain *domain, | |
1718 | struct intel_iommu *iommu) | |
1719 | { | |
d160aca5 | 1720 | int num, count = INT_MAX; |
d160aca5 | 1721 | |
55d94043 | 1722 | assert_spin_locked(&device_domain_lock); |
d160aca5 | 1723 | assert_spin_locked(&iommu->lock); |
fb170fb4 | 1724 | |
29a27719 JR |
1725 | domain->iommu_refcnt[iommu->seq_id] -= 1; |
1726 | count = --domain->iommu_count; | |
1727 | if (domain->iommu_refcnt[iommu->seq_id] == 0) { | |
d160aca5 JR |
1728 | num = domain->iommu_did[iommu->seq_id]; |
1729 | clear_bit(num, iommu->domain_ids); | |
1730 | set_iommu_domain(iommu, num, NULL); | |
1731 | ||
fb170fb4 | 1732 | domain_update_iommu_cap(domain); |
c0e8a6c8 | 1733 | domain->iommu_did[iommu->seq_id] = 0; |
fb170fb4 | 1734 | } |
fb170fb4 JL |
1735 | |
1736 | return count; | |
1737 | } | |
1738 | ||
ba395927 | 1739 | static struct iova_domain reserved_iova_list; |
8a443df4 | 1740 | static struct lock_class_key reserved_rbtree_key; |
ba395927 | 1741 | |
51a63e67 | 1742 | static int dmar_init_reserved_ranges(void) |
ba395927 KA |
1743 | { |
1744 | struct pci_dev *pdev = NULL; | |
1745 | struct iova *iova; | |
1746 | int i; | |
ba395927 | 1747 | |
0fb5fe87 RM |
1748 | init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN, |
1749 | DMA_32BIT_PFN); | |
ba395927 | 1750 | |
8a443df4 MG |
1751 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
1752 | &reserved_rbtree_key); | |
1753 | ||
ba395927 KA |
1754 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1755 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1756 | IOVA_PFN(IOAPIC_RANGE_END)); | |
51a63e67 | 1757 | if (!iova) { |
9f10e5bf | 1758 | pr_err("Reserve IOAPIC range failed\n"); |
51a63e67 JC |
1759 | return -ENODEV; |
1760 | } | |
ba395927 KA |
1761 | |
1762 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1763 | for_each_pci_dev(pdev) { | |
1764 | struct resource *r; | |
1765 | ||
1766 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1767 | r = &pdev->resource[i]; | |
1768 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1769 | continue; | |
1a4a4551 DW |
1770 | iova = reserve_iova(&reserved_iova_list, |
1771 | IOVA_PFN(r->start), | |
1772 | IOVA_PFN(r->end)); | |
51a63e67 | 1773 | if (!iova) { |
9f10e5bf | 1774 | pr_err("Reserve iova failed\n"); |
51a63e67 JC |
1775 | return -ENODEV; |
1776 | } | |
ba395927 KA |
1777 | } |
1778 | } | |
51a63e67 | 1779 | return 0; |
ba395927 KA |
1780 | } |
1781 | ||
1782 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1783 | { | |
1784 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1785 | } | |
1786 | ||
1787 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1788 | { | |
1789 | int agaw; | |
1790 | int r = (gaw - 12) % 9; | |
1791 | ||
1792 | if (r == 0) | |
1793 | agaw = gaw; | |
1794 | else | |
1795 | agaw = gaw + 9 - r; | |
1796 | if (agaw > 64) | |
1797 | agaw = 64; | |
1798 | return agaw; | |
1799 | } | |
1800 | ||
dc534b25 JR |
1801 | static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu, |
1802 | int guest_width) | |
ba395927 | 1803 | { |
ba395927 KA |
1804 | int adjust_width, agaw; |
1805 | unsigned long sagaw; | |
1806 | ||
0fb5fe87 RM |
1807 | init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN, |
1808 | DMA_32BIT_PFN); | |
ba395927 KA |
1809 | domain_reserve_special_ranges(domain); |
1810 | ||
1811 | /* calculate AGAW */ | |
ba395927 KA |
1812 | if (guest_width > cap_mgaw(iommu->cap)) |
1813 | guest_width = cap_mgaw(iommu->cap); | |
1814 | domain->gaw = guest_width; | |
1815 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1816 | agaw = width_to_agaw(adjust_width); | |
1817 | sagaw = cap_sagaw(iommu->cap); | |
1818 | if (!test_bit(agaw, &sagaw)) { | |
1819 | /* hardware doesn't support it, choose a bigger one */ | |
9f10e5bf | 1820 | pr_debug("Hardware doesn't support agaw %d\n", agaw); |
ba395927 KA |
1821 | agaw = find_next_bit(&sagaw, 5, agaw); |
1822 | if (agaw >= 5) | |
1823 | return -ENODEV; | |
1824 | } | |
1825 | domain->agaw = agaw; | |
ba395927 | 1826 | |
8e604097 WH |
1827 | if (ecap_coherent(iommu->ecap)) |
1828 | domain->iommu_coherency = 1; | |
1829 | else | |
1830 | domain->iommu_coherency = 0; | |
1831 | ||
58c610bd SY |
1832 | if (ecap_sc_support(iommu->ecap)) |
1833 | domain->iommu_snooping = 1; | |
1834 | else | |
1835 | domain->iommu_snooping = 0; | |
1836 | ||
214e39aa DW |
1837 | if (intel_iommu_superpage) |
1838 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); | |
1839 | else | |
1840 | domain->iommu_superpage = 0; | |
1841 | ||
4c923d47 | 1842 | domain->nid = iommu->node; |
c7151a8d | 1843 | |
ba395927 | 1844 | /* always allocate the top pgd */ |
4c923d47 | 1845 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
ba395927 KA |
1846 | if (!domain->pgd) |
1847 | return -ENOMEM; | |
5b6985ce | 1848 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1849 | return 0; |
1850 | } | |
1851 | ||
1852 | static void domain_exit(struct dmar_domain *domain) | |
1853 | { | |
ea8ea460 | 1854 | struct page *freelist = NULL; |
ba395927 KA |
1855 | |
1856 | /* Domain 0 is reserved, so dont process it */ | |
1857 | if (!domain) | |
1858 | return; | |
1859 | ||
7b668357 AW |
1860 | /* Flush any lazy unmaps that may reference this domain */ |
1861 | if (!intel_iommu_strict) | |
1862 | flush_unmaps_timeout(0); | |
1863 | ||
d160aca5 JR |
1864 | /* Remove associated devices and clear attached or cached domains */ |
1865 | rcu_read_lock(); | |
ba395927 | 1866 | domain_remove_dev_info(domain); |
d160aca5 | 1867 | rcu_read_unlock(); |
92d03cc8 | 1868 | |
ba395927 KA |
1869 | /* destroy iovas */ |
1870 | put_iova_domain(&domain->iovad); | |
ba395927 | 1871 | |
ea8ea460 | 1872 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1873 | |
ea8ea460 DW |
1874 | dma_free_pagelist(freelist); |
1875 | ||
ba395927 KA |
1876 | free_domain_mem(domain); |
1877 | } | |
1878 | ||
64ae892b DW |
1879 | static int domain_context_mapping_one(struct dmar_domain *domain, |
1880 | struct intel_iommu *iommu, | |
28ccce0d | 1881 | u8 bus, u8 devfn) |
ba395927 | 1882 | { |
c6c2cebd | 1883 | u16 did = domain->iommu_did[iommu->seq_id]; |
28ccce0d JR |
1884 | int translation = CONTEXT_TT_MULTI_LEVEL; |
1885 | struct device_domain_info *info = NULL; | |
ba395927 | 1886 | struct context_entry *context; |
ba395927 | 1887 | unsigned long flags; |
ea6606b0 | 1888 | struct dma_pte *pgd; |
55d94043 | 1889 | int ret, agaw; |
28ccce0d | 1890 | |
c6c2cebd JR |
1891 | WARN_ON(did == 0); |
1892 | ||
28ccce0d JR |
1893 | if (hw_pass_through && domain_type_is_si(domain)) |
1894 | translation = CONTEXT_TT_PASS_THROUGH; | |
ba395927 KA |
1895 | |
1896 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1897 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1898 | |
ba395927 | 1899 | BUG_ON(!domain->pgd); |
5331fe6f | 1900 | |
55d94043 JR |
1901 | spin_lock_irqsave(&device_domain_lock, flags); |
1902 | spin_lock(&iommu->lock); | |
1903 | ||
1904 | ret = -ENOMEM; | |
03ecc32c | 1905 | context = iommu_context_addr(iommu, bus, devfn, 1); |
ba395927 | 1906 | if (!context) |
55d94043 JR |
1907 | goto out_unlock; |
1908 | ||
1909 | ret = 0; | |
1910 | if (context_present(context)) | |
1911 | goto out_unlock; | |
ba395927 | 1912 | |
ea6606b0 WH |
1913 | pgd = domain->pgd; |
1914 | ||
de24e553 | 1915 | context_clear_entry(context); |
c6c2cebd | 1916 | context_set_domain_id(context, did); |
4ed0d3e6 | 1917 | |
de24e553 JR |
1918 | /* |
1919 | * Skip top levels of page tables for iommu which has less agaw | |
1920 | * than default. Unnecessary for PT mode. | |
1921 | */ | |
93a23a72 | 1922 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
de24e553 | 1923 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { |
55d94043 | 1924 | ret = -ENOMEM; |
de24e553 | 1925 | pgd = phys_to_virt(dma_pte_addr(pgd)); |
55d94043 JR |
1926 | if (!dma_pte_present(pgd)) |
1927 | goto out_unlock; | |
de24e553 JR |
1928 | } |
1929 | ||
64ae892b | 1930 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
93a23a72 YZ |
1931 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
1932 | CONTEXT_TT_MULTI_LEVEL; | |
de24e553 | 1933 | |
93a23a72 YZ |
1934 | context_set_address_root(context, virt_to_phys(pgd)); |
1935 | context_set_address_width(context, iommu->agaw); | |
de24e553 JR |
1936 | } else { |
1937 | /* | |
1938 | * In pass through mode, AW must be programmed to | |
1939 | * indicate the largest AGAW value supported by | |
1940 | * hardware. And ASR is ignored by hardware. | |
1941 | */ | |
1942 | context_set_address_width(context, iommu->msagaw); | |
93a23a72 | 1943 | } |
4ed0d3e6 FY |
1944 | |
1945 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1946 | context_set_fault_enable(context); |
1947 | context_set_present(context); | |
5331fe6f | 1948 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1949 | |
4c25a2c1 DW |
1950 | /* |
1951 | * It's a non-present to present mapping. If hardware doesn't cache | |
1952 | * non-present entry we only need to flush the write-buffer. If the | |
1953 | * _does_ cache non-present entries, then it does so in the special | |
1954 | * domain #0, which we have to flush: | |
1955 | */ | |
1956 | if (cap_caching_mode(iommu->cap)) { | |
1957 | iommu->flush.flush_context(iommu, 0, | |
1958 | (((u16)bus) << 8) | devfn, | |
1959 | DMA_CCMD_MASK_NOBIT, | |
1960 | DMA_CCMD_DEVICE_INVL); | |
c6c2cebd | 1961 | iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1962 | } else { |
ba395927 | 1963 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1964 | } |
93a23a72 | 1965 | iommu_enable_dev_iotlb(info); |
55d94043 JR |
1966 | |
1967 | ret = 0; | |
1968 | ||
1969 | out_unlock: | |
1970 | spin_unlock(&iommu->lock); | |
1971 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
c7151a8d | 1972 | |
ba395927 KA |
1973 | return 0; |
1974 | } | |
1975 | ||
579305f7 AW |
1976 | struct domain_context_mapping_data { |
1977 | struct dmar_domain *domain; | |
1978 | struct intel_iommu *iommu; | |
579305f7 AW |
1979 | }; |
1980 | ||
1981 | static int domain_context_mapping_cb(struct pci_dev *pdev, | |
1982 | u16 alias, void *opaque) | |
1983 | { | |
1984 | struct domain_context_mapping_data *data = opaque; | |
1985 | ||
1986 | return domain_context_mapping_one(data->domain, data->iommu, | |
28ccce0d | 1987 | PCI_BUS_NUM(alias), alias & 0xff); |
579305f7 AW |
1988 | } |
1989 | ||
ba395927 | 1990 | static int |
28ccce0d | 1991 | domain_context_mapping(struct dmar_domain *domain, struct device *dev) |
ba395927 | 1992 | { |
64ae892b | 1993 | struct intel_iommu *iommu; |
156baca8 | 1994 | u8 bus, devfn; |
579305f7 | 1995 | struct domain_context_mapping_data data; |
64ae892b | 1996 | |
e1f167f3 | 1997 | iommu = device_to_iommu(dev, &bus, &devfn); |
64ae892b DW |
1998 | if (!iommu) |
1999 | return -ENODEV; | |
ba395927 | 2000 | |
579305f7 | 2001 | if (!dev_is_pci(dev)) |
28ccce0d | 2002 | return domain_context_mapping_one(domain, iommu, bus, devfn); |
579305f7 AW |
2003 | |
2004 | data.domain = domain; | |
2005 | data.iommu = iommu; | |
579305f7 AW |
2006 | |
2007 | return pci_for_each_dma_alias(to_pci_dev(dev), | |
2008 | &domain_context_mapping_cb, &data); | |
2009 | } | |
2010 | ||
2011 | static int domain_context_mapped_cb(struct pci_dev *pdev, | |
2012 | u16 alias, void *opaque) | |
2013 | { | |
2014 | struct intel_iommu *iommu = opaque; | |
2015 | ||
2016 | return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); | |
ba395927 KA |
2017 | } |
2018 | ||
e1f167f3 | 2019 | static int domain_context_mapped(struct device *dev) |
ba395927 | 2020 | { |
5331fe6f | 2021 | struct intel_iommu *iommu; |
156baca8 | 2022 | u8 bus, devfn; |
5331fe6f | 2023 | |
e1f167f3 | 2024 | iommu = device_to_iommu(dev, &bus, &devfn); |
5331fe6f WH |
2025 | if (!iommu) |
2026 | return -ENODEV; | |
ba395927 | 2027 | |
579305f7 AW |
2028 | if (!dev_is_pci(dev)) |
2029 | return device_context_mapped(iommu, bus, devfn); | |
e1f167f3 | 2030 | |
579305f7 AW |
2031 | return !pci_for_each_dma_alias(to_pci_dev(dev), |
2032 | domain_context_mapped_cb, iommu); | |
ba395927 KA |
2033 | } |
2034 | ||
f532959b FY |
2035 | /* Returns a number of VTD pages, but aligned to MM page size */ |
2036 | static inline unsigned long aligned_nrpages(unsigned long host_addr, | |
2037 | size_t size) | |
2038 | { | |
2039 | host_addr &= ~PAGE_MASK; | |
2040 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; | |
2041 | } | |
2042 | ||
6dd9a7c7 YS |
2043 | /* Return largest possible superpage level for a given mapping */ |
2044 | static inline int hardware_largepage_caps(struct dmar_domain *domain, | |
2045 | unsigned long iov_pfn, | |
2046 | unsigned long phy_pfn, | |
2047 | unsigned long pages) | |
2048 | { | |
2049 | int support, level = 1; | |
2050 | unsigned long pfnmerge; | |
2051 | ||
2052 | support = domain->iommu_superpage; | |
2053 | ||
2054 | /* To use a large page, the virtual *and* physical addresses | |
2055 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either | |
2056 | of them will mean we have to use smaller pages. So just | |
2057 | merge them and check both at once. */ | |
2058 | pfnmerge = iov_pfn | phy_pfn; | |
2059 | ||
2060 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { | |
2061 | pages >>= VTD_STRIDE_SHIFT; | |
2062 | if (!pages) | |
2063 | break; | |
2064 | pfnmerge >>= VTD_STRIDE_SHIFT; | |
2065 | level++; | |
2066 | support--; | |
2067 | } | |
2068 | return level; | |
2069 | } | |
2070 | ||
9051aa02 DW |
2071 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2072 | struct scatterlist *sg, unsigned long phys_pfn, | |
2073 | unsigned long nr_pages, int prot) | |
e1605495 DW |
2074 | { |
2075 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 2076 | phys_addr_t uninitialized_var(pteval); |
cc4f14aa | 2077 | unsigned long sg_res = 0; |
6dd9a7c7 YS |
2078 | unsigned int largepage_lvl = 0; |
2079 | unsigned long lvl_pages = 0; | |
e1605495 | 2080 | |
162d1b10 | 2081 | BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1)); |
e1605495 DW |
2082 | |
2083 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
2084 | return -EINVAL; | |
2085 | ||
2086 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
2087 | ||
cc4f14aa JL |
2088 | if (!sg) { |
2089 | sg_res = nr_pages; | |
9051aa02 DW |
2090 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; |
2091 | } | |
2092 | ||
6dd9a7c7 | 2093 | while (nr_pages > 0) { |
c85994e4 DW |
2094 | uint64_t tmp; |
2095 | ||
e1605495 | 2096 | if (!sg_res) { |
f532959b | 2097 | sg_res = aligned_nrpages(sg->offset, sg->length); |
e1605495 DW |
2098 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
2099 | sg->dma_length = sg->length; | |
2100 | pteval = page_to_phys(sg_page(sg)) | prot; | |
6dd9a7c7 | 2101 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
e1605495 | 2102 | } |
6dd9a7c7 | 2103 | |
e1605495 | 2104 | if (!pte) { |
6dd9a7c7 YS |
2105 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
2106 | ||
5cf0a76f | 2107 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
e1605495 DW |
2108 | if (!pte) |
2109 | return -ENOMEM; | |
6dd9a7c7 | 2110 | /* It is large page*/ |
6491d4d0 | 2111 | if (largepage_lvl > 1) { |
6dd9a7c7 | 2112 | pteval |= DMA_PTE_LARGE_PAGE; |
d41a4adb JL |
2113 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
2114 | /* | |
2115 | * Ensure that old small page tables are | |
2116 | * removed to make room for superpage, | |
2117 | * if they exist. | |
2118 | */ | |
6491d4d0 | 2119 | dma_pte_free_pagetable(domain, iov_pfn, |
d41a4adb | 2120 | iov_pfn + lvl_pages - 1); |
6491d4d0 | 2121 | } else { |
6dd9a7c7 | 2122 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
6491d4d0 | 2123 | } |
6dd9a7c7 | 2124 | |
e1605495 DW |
2125 | } |
2126 | /* We don't need lock here, nobody else | |
2127 | * touches the iova range | |
2128 | */ | |
7766a3fb | 2129 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 2130 | if (tmp) { |
1bf20f0d | 2131 | static int dumps = 5; |
9f10e5bf JR |
2132 | pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
2133 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
2134 | if (dumps) { |
2135 | dumps--; | |
2136 | debug_dma_dump_mappings(NULL); | |
2137 | } | |
2138 | WARN_ON(1); | |
2139 | } | |
6dd9a7c7 YS |
2140 | |
2141 | lvl_pages = lvl_to_nr_pages(largepage_lvl); | |
2142 | ||
2143 | BUG_ON(nr_pages < lvl_pages); | |
2144 | BUG_ON(sg_res < lvl_pages); | |
2145 | ||
2146 | nr_pages -= lvl_pages; | |
2147 | iov_pfn += lvl_pages; | |
2148 | phys_pfn += lvl_pages; | |
2149 | pteval += lvl_pages * VTD_PAGE_SIZE; | |
2150 | sg_res -= lvl_pages; | |
2151 | ||
2152 | /* If the next PTE would be the first in a new page, then we | |
2153 | need to flush the cache on the entries we've just written. | |
2154 | And then we'll need to recalculate 'pte', so clear it and | |
2155 | let it get set again in the if (!pte) block above. | |
2156 | ||
2157 | If we're done (!nr_pages) we need to flush the cache too. | |
2158 | ||
2159 | Also if we've been setting superpages, we may need to | |
2160 | recalculate 'pte' and switch back to smaller pages for the | |
2161 | end of the mapping, if the trailing size is not enough to | |
2162 | use another superpage (i.e. sg_res < lvl_pages). */ | |
e1605495 | 2163 | pte++; |
6dd9a7c7 YS |
2164 | if (!nr_pages || first_pte_in_page(pte) || |
2165 | (largepage_lvl > 1 && sg_res < lvl_pages)) { | |
e1605495 DW |
2166 | domain_flush_cache(domain, first_pte, |
2167 | (void *)pte - (void *)first_pte); | |
2168 | pte = NULL; | |
2169 | } | |
6dd9a7c7 YS |
2170 | |
2171 | if (!sg_res && nr_pages) | |
e1605495 DW |
2172 | sg = sg_next(sg); |
2173 | } | |
2174 | return 0; | |
2175 | } | |
2176 | ||
9051aa02 DW |
2177 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2178 | struct scatterlist *sg, unsigned long nr_pages, | |
2179 | int prot) | |
ba395927 | 2180 | { |
9051aa02 DW |
2181 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
2182 | } | |
6f6a00e4 | 2183 | |
9051aa02 DW |
2184 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2185 | unsigned long phys_pfn, unsigned long nr_pages, | |
2186 | int prot) | |
2187 | { | |
2188 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
2189 | } |
2190 | ||
2452d9db | 2191 | static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 2192 | { |
c7151a8d WH |
2193 | if (!iommu) |
2194 | return; | |
8c11e798 WH |
2195 | |
2196 | clear_context_table(iommu, bus, devfn); | |
2197 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 2198 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2199 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
2200 | } |
2201 | ||
109b9b04 DW |
2202 | static inline void unlink_domain_info(struct device_domain_info *info) |
2203 | { | |
2204 | assert_spin_locked(&device_domain_lock); | |
2205 | list_del(&info->link); | |
2206 | list_del(&info->global); | |
2207 | if (info->dev) | |
0bcb3e28 | 2208 | info->dev->archdata.iommu = NULL; |
109b9b04 DW |
2209 | } |
2210 | ||
ba395927 KA |
2211 | static void domain_remove_dev_info(struct dmar_domain *domain) |
2212 | { | |
3a74ca01 | 2213 | struct device_domain_info *info, *tmp; |
55d94043 | 2214 | unsigned long flags; |
ba395927 | 2215 | |
55d94043 | 2216 | spin_lock_irqsave(&device_domain_lock, flags); |
76f45fe3 | 2217 | list_for_each_entry_safe(info, tmp, &domain->devices, link) |
127c7615 | 2218 | __dmar_remove_one_dev_info(info); |
55d94043 | 2219 | spin_unlock_irqrestore(&device_domain_lock, flags); |
ba395927 KA |
2220 | } |
2221 | ||
2222 | /* | |
2223 | * find_domain | |
1525a29a | 2224 | * Note: we use struct device->archdata.iommu stores the info |
ba395927 | 2225 | */ |
1525a29a | 2226 | static struct dmar_domain *find_domain(struct device *dev) |
ba395927 KA |
2227 | { |
2228 | struct device_domain_info *info; | |
2229 | ||
2230 | /* No lock here, assumes no domain exit in normal case */ | |
1525a29a | 2231 | info = dev->archdata.iommu; |
ba395927 KA |
2232 | if (info) |
2233 | return info->domain; | |
2234 | return NULL; | |
2235 | } | |
2236 | ||
5a8f40e8 | 2237 | static inline struct device_domain_info * |
745f2586 JL |
2238 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
2239 | { | |
2240 | struct device_domain_info *info; | |
2241 | ||
2242 | list_for_each_entry(info, &device_domain_list, global) | |
41e80dca | 2243 | if (info->iommu->segment == segment && info->bus == bus && |
745f2586 | 2244 | info->devfn == devfn) |
5a8f40e8 | 2245 | return info; |
745f2586 JL |
2246 | |
2247 | return NULL; | |
2248 | } | |
2249 | ||
5db31569 JR |
2250 | static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, |
2251 | int bus, int devfn, | |
2252 | struct device *dev, | |
2253 | struct dmar_domain *domain) | |
745f2586 | 2254 | { |
5a8f40e8 | 2255 | struct dmar_domain *found = NULL; |
745f2586 JL |
2256 | struct device_domain_info *info; |
2257 | unsigned long flags; | |
d160aca5 | 2258 | int ret; |
745f2586 JL |
2259 | |
2260 | info = alloc_devinfo_mem(); | |
2261 | if (!info) | |
b718cd3d | 2262 | return NULL; |
745f2586 | 2263 | |
745f2586 JL |
2264 | info->bus = bus; |
2265 | info->devfn = devfn; | |
2266 | info->dev = dev; | |
2267 | info->domain = domain; | |
5a8f40e8 | 2268 | info->iommu = iommu; |
745f2586 JL |
2269 | |
2270 | spin_lock_irqsave(&device_domain_lock, flags); | |
2271 | if (dev) | |
0bcb3e28 | 2272 | found = find_domain(dev); |
f303e507 JR |
2273 | |
2274 | if (!found) { | |
5a8f40e8 | 2275 | struct device_domain_info *info2; |
41e80dca | 2276 | info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); |
f303e507 JR |
2277 | if (info2) { |
2278 | found = info2->domain; | |
2279 | info2->dev = dev; | |
2280 | } | |
5a8f40e8 | 2281 | } |
f303e507 | 2282 | |
745f2586 JL |
2283 | if (found) { |
2284 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2285 | free_devinfo_mem(info); | |
b718cd3d DW |
2286 | /* Caller must free the original domain */ |
2287 | return found; | |
745f2586 JL |
2288 | } |
2289 | ||
d160aca5 JR |
2290 | spin_lock(&iommu->lock); |
2291 | ret = domain_attach_iommu(domain, iommu); | |
2292 | spin_unlock(&iommu->lock); | |
2293 | ||
2294 | if (ret) { | |
c6c2cebd JR |
2295 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2296 | return NULL; | |
2297 | } | |
c6c2cebd | 2298 | |
b718cd3d DW |
2299 | list_add(&info->link, &domain->devices); |
2300 | list_add(&info->global, &device_domain_list); | |
2301 | if (dev) | |
2302 | dev->archdata.iommu = info; | |
2303 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2304 | ||
cc4e2575 JR |
2305 | if (dev && domain_context_mapping(domain, dev)) { |
2306 | pr_err("Domain context map for %s failed\n", dev_name(dev)); | |
e6de0f8d | 2307 | dmar_remove_one_dev_info(domain, dev); |
cc4e2575 JR |
2308 | return NULL; |
2309 | } | |
2310 | ||
b718cd3d | 2311 | return domain; |
745f2586 JL |
2312 | } |
2313 | ||
579305f7 AW |
2314 | static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque) |
2315 | { | |
2316 | *(u16 *)opaque = alias; | |
2317 | return 0; | |
2318 | } | |
2319 | ||
ba395927 | 2320 | /* domain is initialized */ |
146922ec | 2321 | static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw) |
ba395927 | 2322 | { |
cc4e2575 | 2323 | struct device_domain_info *info = NULL; |
579305f7 AW |
2324 | struct dmar_domain *domain, *tmp; |
2325 | struct intel_iommu *iommu; | |
08a7f456 | 2326 | u16 req_id, dma_alias; |
ba395927 | 2327 | unsigned long flags; |
aa4d066a | 2328 | u8 bus, devfn; |
ba395927 | 2329 | |
146922ec | 2330 | domain = find_domain(dev); |
ba395927 KA |
2331 | if (domain) |
2332 | return domain; | |
2333 | ||
579305f7 AW |
2334 | iommu = device_to_iommu(dev, &bus, &devfn); |
2335 | if (!iommu) | |
2336 | return NULL; | |
2337 | ||
08a7f456 JR |
2338 | req_id = ((u16)bus << 8) | devfn; |
2339 | ||
146922ec DW |
2340 | if (dev_is_pci(dev)) { |
2341 | struct pci_dev *pdev = to_pci_dev(dev); | |
276dbf99 | 2342 | |
579305f7 AW |
2343 | pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias); |
2344 | ||
2345 | spin_lock_irqsave(&device_domain_lock, flags); | |
2346 | info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus), | |
2347 | PCI_BUS_NUM(dma_alias), | |
2348 | dma_alias & 0xff); | |
2349 | if (info) { | |
2350 | iommu = info->iommu; | |
2351 | domain = info->domain; | |
5a8f40e8 | 2352 | } |
579305f7 | 2353 | spin_unlock_irqrestore(&device_domain_lock, flags); |
ba395927 | 2354 | |
579305f7 AW |
2355 | /* DMA alias already has a domain, uses it */ |
2356 | if (info) | |
2357 | goto found_domain; | |
2358 | } | |
ba395927 | 2359 | |
146922ec | 2360 | /* Allocate and initialize new domain for the device */ |
ab8dfe25 | 2361 | domain = alloc_domain(0); |
745f2586 | 2362 | if (!domain) |
579305f7 | 2363 | return NULL; |
dc534b25 | 2364 | if (domain_init(domain, iommu, gaw)) { |
579305f7 AW |
2365 | domain_exit(domain); |
2366 | return NULL; | |
2c2e2c38 | 2367 | } |
ba395927 | 2368 | |
579305f7 | 2369 | /* register PCI DMA alias device */ |
08a7f456 | 2370 | if (req_id != dma_alias && dev_is_pci(dev)) { |
5db31569 JR |
2371 | tmp = dmar_insert_one_dev_info(iommu, PCI_BUS_NUM(dma_alias), |
2372 | dma_alias & 0xff, NULL, domain); | |
579305f7 AW |
2373 | |
2374 | if (!tmp || tmp != domain) { | |
2375 | domain_exit(domain); | |
2376 | domain = tmp; | |
2377 | } | |
2378 | ||
b718cd3d | 2379 | if (!domain) |
579305f7 | 2380 | return NULL; |
ba395927 KA |
2381 | } |
2382 | ||
2383 | found_domain: | |
5db31569 | 2384 | tmp = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); |
579305f7 AW |
2385 | |
2386 | if (!tmp || tmp != domain) { | |
2387 | domain_exit(domain); | |
2388 | domain = tmp; | |
2389 | } | |
b718cd3d DW |
2390 | |
2391 | return domain; | |
ba395927 KA |
2392 | } |
2393 | ||
2c2e2c38 | 2394 | static int iommu_identity_mapping; |
e0fc7e0b DW |
2395 | #define IDENTMAP_ALL 1 |
2396 | #define IDENTMAP_GFX 2 | |
2397 | #define IDENTMAP_AZALIA 4 | |
2c2e2c38 | 2398 | |
b213203e DW |
2399 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
2400 | unsigned long long start, | |
2401 | unsigned long long end) | |
ba395927 | 2402 | { |
c5395d5c DW |
2403 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
2404 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
2405 | ||
2406 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
2407 | dma_to_mm_pfn(last_vpfn))) { | |
9f10e5bf | 2408 | pr_err("Reserving iova failed\n"); |
b213203e | 2409 | return -ENOMEM; |
ba395927 KA |
2410 | } |
2411 | ||
af1089ce | 2412 | pr_debug("Mapping reserved region %llx-%llx\n", start, end); |
ba395927 KA |
2413 | /* |
2414 | * RMRR range might have overlap with physical memory range, | |
2415 | * clear it first | |
2416 | */ | |
c5395d5c | 2417 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 2418 | |
c5395d5c DW |
2419 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
2420 | last_vpfn - first_vpfn + 1, | |
61df7443 | 2421 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
2422 | } |
2423 | ||
0b9d9753 | 2424 | static int iommu_prepare_identity_map(struct device *dev, |
b213203e DW |
2425 | unsigned long long start, |
2426 | unsigned long long end) | |
2427 | { | |
2428 | struct dmar_domain *domain; | |
2429 | int ret; | |
2430 | ||
0b9d9753 | 2431 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
2432 | if (!domain) |
2433 | return -ENOMEM; | |
2434 | ||
19943b0e DW |
2435 | /* For _hardware_ passthrough, don't bother. But for software |
2436 | passthrough, we do it anyway -- it may indicate a memory | |
2437 | range which is reserved in E820, so which didn't get set | |
2438 | up to start with in si_domain */ | |
2439 | if (domain == si_domain && hw_pass_through) { | |
9f10e5bf JR |
2440 | pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", |
2441 | dev_name(dev), start, end); | |
19943b0e DW |
2442 | return 0; |
2443 | } | |
2444 | ||
9f10e5bf JR |
2445 | pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n", |
2446 | dev_name(dev), start, end); | |
2447 | ||
5595b528 DW |
2448 | if (end < start) { |
2449 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" | |
2450 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2451 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2452 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2453 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2454 | ret = -EIO; | |
2455 | goto error; | |
2456 | } | |
2457 | ||
2ff729f5 DW |
2458 | if (end >> agaw_to_width(domain->agaw)) { |
2459 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" | |
2460 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2461 | agaw_to_width(domain->agaw), | |
2462 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2463 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2464 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2465 | ret = -EIO; | |
2466 | goto error; | |
2467 | } | |
19943b0e | 2468 | |
b213203e | 2469 | ret = iommu_domain_identity_map(domain, start, end); |
ba395927 KA |
2470 | if (ret) |
2471 | goto error; | |
2472 | ||
b213203e DW |
2473 | return 0; |
2474 | ||
2475 | error: | |
ba395927 KA |
2476 | domain_exit(domain); |
2477 | return ret; | |
ba395927 KA |
2478 | } |
2479 | ||
2480 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
0b9d9753 | 2481 | struct device *dev) |
ba395927 | 2482 | { |
0b9d9753 | 2483 | if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 | 2484 | return 0; |
0b9d9753 DW |
2485 | return iommu_prepare_identity_map(dev, rmrr->base_address, |
2486 | rmrr->end_address); | |
ba395927 KA |
2487 | } |
2488 | ||
d3f13810 | 2489 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
49a0429e KA |
2490 | static inline void iommu_prepare_isa(void) |
2491 | { | |
2492 | struct pci_dev *pdev; | |
2493 | int ret; | |
2494 | ||
2495 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
2496 | if (!pdev) | |
2497 | return; | |
2498 | ||
9f10e5bf | 2499 | pr_info("Prepare 0-16MiB unity mapping for LPC\n"); |
0b9d9753 | 2500 | ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1); |
49a0429e KA |
2501 | |
2502 | if (ret) | |
9f10e5bf | 2503 | pr_err("Failed to create 0-16MiB identity map - floppy might not work\n"); |
49a0429e | 2504 | |
9b27e82d | 2505 | pci_dev_put(pdev); |
49a0429e KA |
2506 | } |
2507 | #else | |
2508 | static inline void iommu_prepare_isa(void) | |
2509 | { | |
2510 | return; | |
2511 | } | |
d3f13810 | 2512 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
49a0429e | 2513 | |
2c2e2c38 | 2514 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 | 2515 | |
071e1374 | 2516 | static int __init si_domain_init(int hw) |
2c2e2c38 | 2517 | { |
c7ab48d2 | 2518 | int nid, ret = 0; |
2c2e2c38 | 2519 | |
ab8dfe25 | 2520 | si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY); |
2c2e2c38 FY |
2521 | if (!si_domain) |
2522 | return -EFAULT; | |
2523 | ||
2c2e2c38 FY |
2524 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
2525 | domain_exit(si_domain); | |
2526 | return -EFAULT; | |
2527 | } | |
2528 | ||
0dc79715 | 2529 | pr_debug("Identity mapping domain allocated\n"); |
2c2e2c38 | 2530 | |
19943b0e DW |
2531 | if (hw) |
2532 | return 0; | |
2533 | ||
c7ab48d2 | 2534 | for_each_online_node(nid) { |
5dfe8660 TH |
2535 | unsigned long start_pfn, end_pfn; |
2536 | int i; | |
2537 | ||
2538 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { | |
2539 | ret = iommu_domain_identity_map(si_domain, | |
2540 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); | |
2541 | if (ret) | |
2542 | return ret; | |
2543 | } | |
c7ab48d2 DW |
2544 | } |
2545 | ||
2c2e2c38 FY |
2546 | return 0; |
2547 | } | |
2548 | ||
9b226624 | 2549 | static int identity_mapping(struct device *dev) |
2c2e2c38 FY |
2550 | { |
2551 | struct device_domain_info *info; | |
2552 | ||
2553 | if (likely(!iommu_identity_mapping)) | |
2554 | return 0; | |
2555 | ||
9b226624 | 2556 | info = dev->archdata.iommu; |
cb452a40 MT |
2557 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
2558 | return (info->domain == si_domain); | |
2c2e2c38 | 2559 | |
2c2e2c38 FY |
2560 | return 0; |
2561 | } | |
2562 | ||
28ccce0d | 2563 | static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) |
2c2e2c38 | 2564 | { |
0ac72664 | 2565 | struct dmar_domain *ndomain; |
5a8f40e8 | 2566 | struct intel_iommu *iommu; |
156baca8 | 2567 | u8 bus, devfn; |
2c2e2c38 | 2568 | |
5913c9bf | 2569 | iommu = device_to_iommu(dev, &bus, &devfn); |
5a8f40e8 DW |
2570 | if (!iommu) |
2571 | return -ENODEV; | |
2572 | ||
5db31569 | 2573 | ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); |
0ac72664 DW |
2574 | if (ndomain != domain) |
2575 | return -EBUSY; | |
2c2e2c38 FY |
2576 | |
2577 | return 0; | |
2578 | } | |
2579 | ||
0b9d9753 | 2580 | static bool device_has_rmrr(struct device *dev) |
ea2447f7 TM |
2581 | { |
2582 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2583 | struct device *tmp; |
ea2447f7 TM |
2584 | int i; |
2585 | ||
0e242612 | 2586 | rcu_read_lock(); |
ea2447f7 | 2587 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
2588 | /* |
2589 | * Return TRUE if this RMRR contains the device that | |
2590 | * is passed in. | |
2591 | */ | |
2592 | for_each_active_dev_scope(rmrr->devices, | |
2593 | rmrr->devices_cnt, i, tmp) | |
0b9d9753 | 2594 | if (tmp == dev) { |
0e242612 | 2595 | rcu_read_unlock(); |
ea2447f7 | 2596 | return true; |
b683b230 | 2597 | } |
ea2447f7 | 2598 | } |
0e242612 | 2599 | rcu_read_unlock(); |
ea2447f7 TM |
2600 | return false; |
2601 | } | |
2602 | ||
c875d2c1 AW |
2603 | /* |
2604 | * There are a couple cases where we need to restrict the functionality of | |
2605 | * devices associated with RMRRs. The first is when evaluating a device for | |
2606 | * identity mapping because problems exist when devices are moved in and out | |
2607 | * of domains and their respective RMRR information is lost. This means that | |
2608 | * a device with associated RMRRs will never be in a "passthrough" domain. | |
2609 | * The second is use of the device through the IOMMU API. This interface | |
2610 | * expects to have full control of the IOVA space for the device. We cannot | |
2611 | * satisfy both the requirement that RMRR access is maintained and have an | |
2612 | * unencumbered IOVA space. We also have no ability to quiesce the device's | |
2613 | * use of the RMRR space or even inform the IOMMU API user of the restriction. | |
2614 | * We therefore prevent devices associated with an RMRR from participating in | |
2615 | * the IOMMU API, which eliminates them from device assignment. | |
2616 | * | |
2617 | * In both cases we assume that PCI USB devices with RMRRs have them largely | |
2618 | * for historical reasons and that the RMRR space is not actively used post | |
2619 | * boot. This exclusion may change if vendors begin to abuse it. | |
18436afd DW |
2620 | * |
2621 | * The same exception is made for graphics devices, with the requirement that | |
2622 | * any use of the RMRR regions will be torn down before assigning the device | |
2623 | * to a guest. | |
c875d2c1 AW |
2624 | */ |
2625 | static bool device_is_rmrr_locked(struct device *dev) | |
2626 | { | |
2627 | if (!device_has_rmrr(dev)) | |
2628 | return false; | |
2629 | ||
2630 | if (dev_is_pci(dev)) { | |
2631 | struct pci_dev *pdev = to_pci_dev(dev); | |
2632 | ||
18436afd | 2633 | if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev)) |
c875d2c1 AW |
2634 | return false; |
2635 | } | |
2636 | ||
2637 | return true; | |
2638 | } | |
2639 | ||
3bdb2591 | 2640 | static int iommu_should_identity_map(struct device *dev, int startup) |
6941af28 | 2641 | { |
ea2447f7 | 2642 | |
3bdb2591 DW |
2643 | if (dev_is_pci(dev)) { |
2644 | struct pci_dev *pdev = to_pci_dev(dev); | |
ea2447f7 | 2645 | |
c875d2c1 | 2646 | if (device_is_rmrr_locked(dev)) |
3bdb2591 | 2647 | return 0; |
e0fc7e0b | 2648 | |
3bdb2591 DW |
2649 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
2650 | return 1; | |
e0fc7e0b | 2651 | |
3bdb2591 DW |
2652 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
2653 | return 1; | |
6941af28 | 2654 | |
3bdb2591 | 2655 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
3dfc813d | 2656 | return 0; |
3bdb2591 DW |
2657 | |
2658 | /* | |
2659 | * We want to start off with all devices in the 1:1 domain, and | |
2660 | * take them out later if we find they can't access all of memory. | |
2661 | * | |
2662 | * However, we can't do this for PCI devices behind bridges, | |
2663 | * because all PCI devices behind the same bridge will end up | |
2664 | * with the same source-id on their transactions. | |
2665 | * | |
2666 | * Practically speaking, we can't change things around for these | |
2667 | * devices at run-time, because we can't be sure there'll be no | |
2668 | * DMA transactions in flight for any of their siblings. | |
2669 | * | |
2670 | * So PCI devices (unless they're on the root bus) as well as | |
2671 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of | |
2672 | * the 1:1 domain, just in _case_ one of their siblings turns out | |
2673 | * not to be able to map all of memory. | |
2674 | */ | |
2675 | if (!pci_is_pcie(pdev)) { | |
2676 | if (!pci_is_root_bus(pdev->bus)) | |
2677 | return 0; | |
2678 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) | |
2679 | return 0; | |
2680 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
3dfc813d | 2681 | return 0; |
3bdb2591 DW |
2682 | } else { |
2683 | if (device_has_rmrr(dev)) | |
2684 | return 0; | |
2685 | } | |
3dfc813d | 2686 | |
3bdb2591 | 2687 | /* |
3dfc813d | 2688 | * At boot time, we don't yet know if devices will be 64-bit capable. |
3bdb2591 | 2689 | * Assume that they will — if they turn out not to be, then we can |
3dfc813d DW |
2690 | * take them out of the 1:1 domain later. |
2691 | */ | |
8fcc5372 CW |
2692 | if (!startup) { |
2693 | /* | |
2694 | * If the device's dma_mask is less than the system's memory | |
2695 | * size then this is not a candidate for identity mapping. | |
2696 | */ | |
3bdb2591 | 2697 | u64 dma_mask = *dev->dma_mask; |
8fcc5372 | 2698 | |
3bdb2591 DW |
2699 | if (dev->coherent_dma_mask && |
2700 | dev->coherent_dma_mask < dma_mask) | |
2701 | dma_mask = dev->coherent_dma_mask; | |
8fcc5372 | 2702 | |
3bdb2591 | 2703 | return dma_mask >= dma_get_required_mask(dev); |
8fcc5372 | 2704 | } |
6941af28 DW |
2705 | |
2706 | return 1; | |
2707 | } | |
2708 | ||
cf04eee8 DW |
2709 | static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw) |
2710 | { | |
2711 | int ret; | |
2712 | ||
2713 | if (!iommu_should_identity_map(dev, 1)) | |
2714 | return 0; | |
2715 | ||
28ccce0d | 2716 | ret = domain_add_dev_info(si_domain, dev); |
cf04eee8 | 2717 | if (!ret) |
9f10e5bf JR |
2718 | pr_info("%s identity mapping for device %s\n", |
2719 | hw ? "Hardware" : "Software", dev_name(dev)); | |
cf04eee8 DW |
2720 | else if (ret == -ENODEV) |
2721 | /* device not associated with an iommu */ | |
2722 | ret = 0; | |
2723 | ||
2724 | return ret; | |
2725 | } | |
2726 | ||
2727 | ||
071e1374 | 2728 | static int __init iommu_prepare_static_identity_mapping(int hw) |
2c2e2c38 | 2729 | { |
2c2e2c38 | 2730 | struct pci_dev *pdev = NULL; |
cf04eee8 DW |
2731 | struct dmar_drhd_unit *drhd; |
2732 | struct intel_iommu *iommu; | |
2733 | struct device *dev; | |
2734 | int i; | |
2735 | int ret = 0; | |
2c2e2c38 | 2736 | |
2c2e2c38 | 2737 | for_each_pci_dev(pdev) { |
cf04eee8 DW |
2738 | ret = dev_prepare_static_identity_mapping(&pdev->dev, hw); |
2739 | if (ret) | |
2740 | return ret; | |
2741 | } | |
2742 | ||
2743 | for_each_active_iommu(iommu, drhd) | |
2744 | for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) { | |
2745 | struct acpi_device_physical_node *pn; | |
2746 | struct acpi_device *adev; | |
2747 | ||
2748 | if (dev->bus != &acpi_bus_type) | |
2749 | continue; | |
86080ccc | 2750 | |
cf04eee8 DW |
2751 | adev= to_acpi_device(dev); |
2752 | mutex_lock(&adev->physical_node_lock); | |
2753 | list_for_each_entry(pn, &adev->physical_node_list, node) { | |
2754 | ret = dev_prepare_static_identity_mapping(pn->dev, hw); | |
2755 | if (ret) | |
2756 | break; | |
eae460b6 | 2757 | } |
cf04eee8 DW |
2758 | mutex_unlock(&adev->physical_node_lock); |
2759 | if (ret) | |
2760 | return ret; | |
62edf5dc | 2761 | } |
2c2e2c38 FY |
2762 | |
2763 | return 0; | |
2764 | } | |
2765 | ||
ffebeb46 JL |
2766 | static void intel_iommu_init_qi(struct intel_iommu *iommu) |
2767 | { | |
2768 | /* | |
2769 | * Start from the sane iommu hardware state. | |
2770 | * If the queued invalidation is already initialized by us | |
2771 | * (for example, while enabling interrupt-remapping) then | |
2772 | * we got the things already rolling from a sane state. | |
2773 | */ | |
2774 | if (!iommu->qi) { | |
2775 | /* | |
2776 | * Clear any previous faults. | |
2777 | */ | |
2778 | dmar_fault(-1, iommu); | |
2779 | /* | |
2780 | * Disable queued invalidation if supported and already enabled | |
2781 | * before OS handover. | |
2782 | */ | |
2783 | dmar_disable_qi(iommu); | |
2784 | } | |
2785 | ||
2786 | if (dmar_enable_qi(iommu)) { | |
2787 | /* | |
2788 | * Queued Invalidate not enabled, use Register Based Invalidate | |
2789 | */ | |
2790 | iommu->flush.flush_context = __iommu_flush_context; | |
2791 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
9f10e5bf | 2792 | pr_info("%s: Using Register based invalidation\n", |
ffebeb46 JL |
2793 | iommu->name); |
2794 | } else { | |
2795 | iommu->flush.flush_context = qi_flush_context; | |
2796 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
9f10e5bf | 2797 | pr_info("%s: Using Queued invalidation\n", iommu->name); |
ffebeb46 JL |
2798 | } |
2799 | } | |
2800 | ||
091d42e4 | 2801 | static int copy_context_table(struct intel_iommu *iommu, |
543c8dcf | 2802 | struct root_entry __iomem *old_re, |
091d42e4 JR |
2803 | struct context_entry **tbl, |
2804 | int bus, bool ext) | |
2805 | { | |
dbcd861f | 2806 | int tbl_idx, pos = 0, idx, devfn, ret = 0, did; |
543c8dcf JR |
2807 | struct context_entry __iomem *old_ce = NULL; |
2808 | struct context_entry *new_ce = NULL, ce; | |
2809 | struct root_entry re; | |
091d42e4 JR |
2810 | phys_addr_t old_ce_phys; |
2811 | ||
2812 | tbl_idx = ext ? bus * 2 : bus; | |
543c8dcf | 2813 | memcpy_fromio(&re, old_re, sizeof(re)); |
091d42e4 JR |
2814 | |
2815 | for (devfn = 0; devfn < 256; devfn++) { | |
2816 | /* First calculate the correct index */ | |
2817 | idx = (ext ? devfn * 2 : devfn) % 256; | |
2818 | ||
2819 | if (idx == 0) { | |
2820 | /* First save what we may have and clean up */ | |
2821 | if (new_ce) { | |
2822 | tbl[tbl_idx] = new_ce; | |
2823 | __iommu_flush_cache(iommu, new_ce, | |
2824 | VTD_PAGE_SIZE); | |
2825 | pos = 1; | |
2826 | } | |
2827 | ||
2828 | if (old_ce) | |
2829 | iounmap(old_ce); | |
2830 | ||
2831 | ret = 0; | |
2832 | if (devfn < 0x80) | |
543c8dcf | 2833 | old_ce_phys = root_entry_lctp(&re); |
091d42e4 | 2834 | else |
543c8dcf | 2835 | old_ce_phys = root_entry_uctp(&re); |
091d42e4 JR |
2836 | |
2837 | if (!old_ce_phys) { | |
2838 | if (ext && devfn == 0) { | |
2839 | /* No LCTP, try UCTP */ | |
2840 | devfn = 0x7f; | |
2841 | continue; | |
2842 | } else { | |
2843 | goto out; | |
2844 | } | |
2845 | } | |
2846 | ||
2847 | ret = -ENOMEM; | |
2848 | old_ce = ioremap_cache(old_ce_phys, PAGE_SIZE); | |
2849 | if (!old_ce) | |
2850 | goto out; | |
2851 | ||
2852 | new_ce = alloc_pgtable_page(iommu->node); | |
2853 | if (!new_ce) | |
2854 | goto out_unmap; | |
2855 | ||
2856 | ret = 0; | |
2857 | } | |
2858 | ||
2859 | /* Now copy the context entry */ | |
543c8dcf | 2860 | memcpy_fromio(&ce, old_ce + idx, sizeof(ce)); |
091d42e4 | 2861 | |
cf484d0e | 2862 | if (!__context_present(&ce)) |
091d42e4 JR |
2863 | continue; |
2864 | ||
dbcd861f JR |
2865 | did = context_domain_id(&ce); |
2866 | if (did >= 0 && did < cap_ndoms(iommu->cap)) | |
2867 | set_bit(did, iommu->domain_ids); | |
2868 | ||
cf484d0e JR |
2869 | /* |
2870 | * We need a marker for copied context entries. This | |
2871 | * marker needs to work for the old format as well as | |
2872 | * for extended context entries. | |
2873 | * | |
2874 | * Bit 67 of the context entry is used. In the old | |
2875 | * format this bit is available to software, in the | |
2876 | * extended format it is the PGE bit, but PGE is ignored | |
2877 | * by HW if PASIDs are disabled (and thus still | |
2878 | * available). | |
2879 | * | |
2880 | * So disable PASIDs first and then mark the entry | |
2881 | * copied. This means that we don't copy PASID | |
2882 | * translations from the old kernel, but this is fine as | |
2883 | * faults there are not fatal. | |
2884 | */ | |
2885 | context_clear_pasid_enable(&ce); | |
2886 | context_set_copied(&ce); | |
2887 | ||
091d42e4 JR |
2888 | new_ce[idx] = ce; |
2889 | } | |
2890 | ||
2891 | tbl[tbl_idx + pos] = new_ce; | |
2892 | ||
2893 | __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE); | |
2894 | ||
2895 | out_unmap: | |
2896 | iounmap(old_ce); | |
2897 | ||
2898 | out: | |
2899 | return ret; | |
2900 | } | |
2901 | ||
2902 | static int copy_translation_tables(struct intel_iommu *iommu) | |
2903 | { | |
543c8dcf | 2904 | struct root_entry __iomem *old_rt; |
091d42e4 | 2905 | struct context_entry **ctxt_tbls; |
091d42e4 JR |
2906 | phys_addr_t old_rt_phys; |
2907 | int ctxt_table_entries; | |
2908 | unsigned long flags; | |
2909 | u64 rtaddr_reg; | |
2910 | int bus, ret; | |
c3361f2f | 2911 | bool new_ext, ext; |
091d42e4 JR |
2912 | |
2913 | rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); | |
2914 | ext = !!(rtaddr_reg & DMA_RTADDR_RTT); | |
c3361f2f JR |
2915 | new_ext = !!ecap_ecs(iommu->ecap); |
2916 | ||
2917 | /* | |
2918 | * The RTT bit can only be changed when translation is disabled, | |
2919 | * but disabling translation means to open a window for data | |
2920 | * corruption. So bail out and don't copy anything if we would | |
2921 | * have to change the bit. | |
2922 | */ | |
2923 | if (new_ext != ext) | |
2924 | return -EINVAL; | |
091d42e4 JR |
2925 | |
2926 | old_rt_phys = rtaddr_reg & VTD_PAGE_MASK; | |
2927 | if (!old_rt_phys) | |
2928 | return -EINVAL; | |
2929 | ||
2930 | old_rt = ioremap_cache(old_rt_phys, PAGE_SIZE); | |
2931 | if (!old_rt) | |
2932 | return -ENOMEM; | |
2933 | ||
2934 | /* This is too big for the stack - allocate it from slab */ | |
2935 | ctxt_table_entries = ext ? 512 : 256; | |
2936 | ret = -ENOMEM; | |
2937 | ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL); | |
2938 | if (!ctxt_tbls) | |
2939 | goto out_unmap; | |
2940 | ||
2941 | for (bus = 0; bus < 256; bus++) { | |
2942 | ret = copy_context_table(iommu, &old_rt[bus], | |
2943 | ctxt_tbls, bus, ext); | |
2944 | if (ret) { | |
2945 | pr_err("%s: Failed to copy context table for bus %d\n", | |
2946 | iommu->name, bus); | |
2947 | continue; | |
2948 | } | |
2949 | } | |
2950 | ||
2951 | spin_lock_irqsave(&iommu->lock, flags); | |
2952 | ||
2953 | /* Context tables are copied, now write them to the root_entry table */ | |
2954 | for (bus = 0; bus < 256; bus++) { | |
2955 | int idx = ext ? bus * 2 : bus; | |
2956 | u64 val; | |
2957 | ||
2958 | if (ctxt_tbls[idx]) { | |
2959 | val = virt_to_phys(ctxt_tbls[idx]) | 1; | |
2960 | iommu->root_entry[bus].lo = val; | |
2961 | } | |
2962 | ||
2963 | if (!ext || !ctxt_tbls[idx + 1]) | |
2964 | continue; | |
2965 | ||
2966 | val = virt_to_phys(ctxt_tbls[idx + 1]) | 1; | |
2967 | iommu->root_entry[bus].hi = val; | |
2968 | } | |
2969 | ||
2970 | spin_unlock_irqrestore(&iommu->lock, flags); | |
2971 | ||
2972 | kfree(ctxt_tbls); | |
2973 | ||
2974 | __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE); | |
2975 | ||
2976 | ret = 0; | |
2977 | ||
2978 | out_unmap: | |
2979 | iounmap(old_rt); | |
2980 | ||
2981 | return ret; | |
2982 | } | |
2983 | ||
b779260b | 2984 | static int __init init_dmars(void) |
ba395927 KA |
2985 | { |
2986 | struct dmar_drhd_unit *drhd; | |
2987 | struct dmar_rmrr_unit *rmrr; | |
a87f4918 | 2988 | bool copied_tables = false; |
832bd858 | 2989 | struct device *dev; |
ba395927 | 2990 | struct intel_iommu *iommu; |
9d783ba0 | 2991 | int i, ret; |
2c2e2c38 | 2992 | |
ba395927 KA |
2993 | /* |
2994 | * for each drhd | |
2995 | * allocate root | |
2996 | * initialize and program root entry to not present | |
2997 | * endfor | |
2998 | */ | |
2999 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 3000 | /* |
3001 | * lock not needed as this is only incremented in the single | |
3002 | * threaded kernel __init code path all other access are read | |
3003 | * only | |
3004 | */ | |
78d8e704 | 3005 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) { |
1b198bb0 MT |
3006 | g_num_of_iommus++; |
3007 | continue; | |
3008 | } | |
9f10e5bf | 3009 | pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED); |
5e0d2a6f | 3010 | } |
3011 | ||
ffebeb46 JL |
3012 | /* Preallocate enough resources for IOMMU hot-addition */ |
3013 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) | |
3014 | g_num_of_iommus = DMAR_UNITS_SUPPORTED; | |
3015 | ||
d9630fe9 WH |
3016 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
3017 | GFP_KERNEL); | |
3018 | if (!g_iommus) { | |
9f10e5bf | 3019 | pr_err("Allocating global iommu array failed\n"); |
d9630fe9 WH |
3020 | ret = -ENOMEM; |
3021 | goto error; | |
3022 | } | |
3023 | ||
80b20dd8 | 3024 | deferred_flush = kzalloc(g_num_of_iommus * |
3025 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
3026 | if (!deferred_flush) { | |
5e0d2a6f | 3027 | ret = -ENOMEM; |
989d51fc | 3028 | goto free_g_iommus; |
5e0d2a6f | 3029 | } |
3030 | ||
7c919779 | 3031 | for_each_active_iommu(iommu, drhd) { |
d9630fe9 | 3032 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 3033 | |
b63d80d1 JR |
3034 | intel_iommu_init_qi(iommu); |
3035 | ||
e61d98d8 SS |
3036 | ret = iommu_init_domains(iommu); |
3037 | if (ret) | |
989d51fc | 3038 | goto free_iommu; |
e61d98d8 | 3039 | |
4158c2ec JR |
3040 | init_translation_status(iommu); |
3041 | ||
091d42e4 JR |
3042 | if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { |
3043 | iommu_disable_translation(iommu); | |
3044 | clear_translation_pre_enabled(iommu); | |
3045 | pr_warn("Translation was enabled for %s but we are not in kdump mode\n", | |
3046 | iommu->name); | |
3047 | } | |
4158c2ec | 3048 | |
ba395927 KA |
3049 | /* |
3050 | * TBD: | |
3051 | * we could share the same root & context tables | |
25985edc | 3052 | * among all IOMMU's. Need to Split it later. |
ba395927 KA |
3053 | */ |
3054 | ret = iommu_alloc_root_entry(iommu); | |
ffebeb46 | 3055 | if (ret) |
989d51fc | 3056 | goto free_iommu; |
5f0a7f76 | 3057 | |
091d42e4 JR |
3058 | if (translation_pre_enabled(iommu)) { |
3059 | pr_info("Translation already enabled - trying to copy translation structures\n"); | |
3060 | ||
3061 | ret = copy_translation_tables(iommu); | |
3062 | if (ret) { | |
3063 | /* | |
3064 | * We found the IOMMU with translation | |
3065 | * enabled - but failed to copy over the | |
3066 | * old root-entry table. Try to proceed | |
3067 | * by disabling translation now and | |
3068 | * allocating a clean root-entry table. | |
3069 | * This might cause DMAR faults, but | |
3070 | * probably the dump will still succeed. | |
3071 | */ | |
3072 | pr_err("Failed to copy translation tables from previous kernel for %s\n", | |
3073 | iommu->name); | |
3074 | iommu_disable_translation(iommu); | |
3075 | clear_translation_pre_enabled(iommu); | |
3076 | } else { | |
3077 | pr_info("Copied translation tables from previous kernel for %s\n", | |
3078 | iommu->name); | |
a87f4918 | 3079 | copied_tables = true; |
091d42e4 JR |
3080 | } |
3081 | } | |
3082 | ||
5f0a7f76 JR |
3083 | iommu_flush_write_buffer(iommu); |
3084 | iommu_set_root_entry(iommu); | |
3085 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); | |
3086 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); | |
3087 | ||
4ed0d3e6 | 3088 | if (!ecap_pass_through(iommu->ecap)) |
19943b0e | 3089 | hw_pass_through = 0; |
ba395927 KA |
3090 | } |
3091 | ||
19943b0e | 3092 | if (iommu_pass_through) |
e0fc7e0b DW |
3093 | iommu_identity_mapping |= IDENTMAP_ALL; |
3094 | ||
d3f13810 | 3095 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
e0fc7e0b | 3096 | iommu_identity_mapping |= IDENTMAP_GFX; |
19943b0e | 3097 | #endif |
e0fc7e0b | 3098 | |
86080ccc JR |
3099 | if (iommu_identity_mapping) { |
3100 | ret = si_domain_init(hw_pass_through); | |
3101 | if (ret) | |
3102 | goto free_iommu; | |
3103 | } | |
3104 | ||
e0fc7e0b DW |
3105 | check_tylersburg_isoch(); |
3106 | ||
a87f4918 JR |
3107 | /* |
3108 | * If we copied translations from a previous kernel in the kdump | |
3109 | * case, we can not assign the devices to domains now, as that | |
3110 | * would eliminate the old mappings. So skip this part and defer | |
3111 | * the assignment to device driver initialization time. | |
3112 | */ | |
3113 | if (copied_tables) | |
3114 | goto domains_done; | |
3115 | ||
ba395927 | 3116 | /* |
19943b0e DW |
3117 | * If pass through is not set or not enabled, setup context entries for |
3118 | * identity mappings for rmrr, gfx, and isa and may fall back to static | |
3119 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 3120 | */ |
19943b0e DW |
3121 | if (iommu_identity_mapping) { |
3122 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); | |
4ed0d3e6 | 3123 | if (ret) { |
9f10e5bf | 3124 | pr_crit("Failed to setup IOMMU pass-through\n"); |
989d51fc | 3125 | goto free_iommu; |
ba395927 KA |
3126 | } |
3127 | } | |
ba395927 | 3128 | /* |
19943b0e DW |
3129 | * For each rmrr |
3130 | * for each dev attached to rmrr | |
3131 | * do | |
3132 | * locate drhd for dev, alloc domain for dev | |
3133 | * allocate free domain | |
3134 | * allocate page table entries for rmrr | |
3135 | * if context not allocated for bus | |
3136 | * allocate and init context | |
3137 | * set present in root table for this bus | |
3138 | * init context with domain, translation etc | |
3139 | * endfor | |
3140 | * endfor | |
ba395927 | 3141 | */ |
9f10e5bf | 3142 | pr_info("Setting RMRR:\n"); |
19943b0e | 3143 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
3144 | /* some BIOS lists non-exist devices in DMAR table. */ |
3145 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, | |
832bd858 | 3146 | i, dev) { |
0b9d9753 | 3147 | ret = iommu_prepare_rmrr_dev(rmrr, dev); |
19943b0e | 3148 | if (ret) |
9f10e5bf | 3149 | pr_err("Mapping reserved region failed\n"); |
ba395927 | 3150 | } |
4ed0d3e6 | 3151 | } |
49a0429e | 3152 | |
19943b0e DW |
3153 | iommu_prepare_isa(); |
3154 | ||
a87f4918 JR |
3155 | domains_done: |
3156 | ||
ba395927 KA |
3157 | /* |
3158 | * for each drhd | |
3159 | * enable fault log | |
3160 | * global invalidate context cache | |
3161 | * global invalidate iotlb | |
3162 | * enable translation | |
3163 | */ | |
7c919779 | 3164 | for_each_iommu(iommu, drhd) { |
51a63e67 JC |
3165 | if (drhd->ignored) { |
3166 | /* | |
3167 | * we always have to disable PMRs or DMA may fail on | |
3168 | * this device | |
3169 | */ | |
3170 | if (force_on) | |
7c919779 | 3171 | iommu_disable_protect_mem_regions(iommu); |
ba395927 | 3172 | continue; |
51a63e67 | 3173 | } |
ba395927 KA |
3174 | |
3175 | iommu_flush_write_buffer(iommu); | |
3176 | ||
3460a6d9 KA |
3177 | ret = dmar_set_interrupt(iommu); |
3178 | if (ret) | |
989d51fc | 3179 | goto free_iommu; |
3460a6d9 | 3180 | |
8939ddf6 JR |
3181 | if (!translation_pre_enabled(iommu)) |
3182 | iommu_enable_translation(iommu); | |
3183 | ||
b94996c9 | 3184 | iommu_disable_protect_mem_regions(iommu); |
ba395927 KA |
3185 | } |
3186 | ||
3187 | return 0; | |
989d51fc JL |
3188 | |
3189 | free_iommu: | |
ffebeb46 JL |
3190 | for_each_active_iommu(iommu, drhd) { |
3191 | disable_dmar_iommu(iommu); | |
a868e6b7 | 3192 | free_dmar_iommu(iommu); |
ffebeb46 | 3193 | } |
9bdc531e | 3194 | kfree(deferred_flush); |
989d51fc | 3195 | free_g_iommus: |
d9630fe9 | 3196 | kfree(g_iommus); |
989d51fc | 3197 | error: |
ba395927 KA |
3198 | return ret; |
3199 | } | |
3200 | ||
5a5e02a6 | 3201 | /* This takes a number of _MM_ pages, not VTD pages */ |
875764de DW |
3202 | static struct iova *intel_alloc_iova(struct device *dev, |
3203 | struct dmar_domain *domain, | |
3204 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 3205 | { |
ba395927 | 3206 | struct iova *iova = NULL; |
ba395927 | 3207 | |
875764de DW |
3208 | /* Restrict dma_mask to the width that the iommu can handle */ |
3209 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
3210 | ||
3211 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
3212 | /* |
3213 | * First try to allocate an io virtual address in | |
284901a9 | 3214 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 3215 | * from higher range |
ba395927 | 3216 | */ |
875764de DW |
3217 | iova = alloc_iova(&domain->iovad, nrpages, |
3218 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
3219 | if (iova) | |
3220 | return iova; | |
3221 | } | |
3222 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
3223 | if (unlikely(!iova)) { | |
9f10e5bf | 3224 | pr_err("Allocating %ld-page iova for %s failed", |
207e3592 | 3225 | nrpages, dev_name(dev)); |
f76aec76 KA |
3226 | return NULL; |
3227 | } | |
3228 | ||
3229 | return iova; | |
3230 | } | |
3231 | ||
d4b709f4 | 3232 | static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev) |
f76aec76 KA |
3233 | { |
3234 | struct dmar_domain *domain; | |
f76aec76 | 3235 | |
d4b709f4 | 3236 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
f76aec76 | 3237 | if (!domain) { |
9f10e5bf | 3238 | pr_err("Allocating domain for %s failed\n", |
d4b709f4 | 3239 | dev_name(dev)); |
4fe05bbc | 3240 | return NULL; |
ba395927 KA |
3241 | } |
3242 | ||
f76aec76 KA |
3243 | return domain; |
3244 | } | |
3245 | ||
d4b709f4 | 3246 | static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev) |
147202aa DW |
3247 | { |
3248 | struct device_domain_info *info; | |
3249 | ||
3250 | /* No lock here, assumes no domain exit in normal case */ | |
d4b709f4 | 3251 | info = dev->archdata.iommu; |
147202aa DW |
3252 | if (likely(info)) |
3253 | return info->domain; | |
3254 | ||
3255 | return __get_valid_domain_for_dev(dev); | |
3256 | } | |
3257 | ||
ecb509ec | 3258 | /* Check if the dev needs to go through non-identity map and unmap process.*/ |
73676832 | 3259 | static int iommu_no_mapping(struct device *dev) |
2c2e2c38 FY |
3260 | { |
3261 | int found; | |
3262 | ||
3d89194a | 3263 | if (iommu_dummy(dev)) |
1e4c64c4 DW |
3264 | return 1; |
3265 | ||
2c2e2c38 | 3266 | if (!iommu_identity_mapping) |
1e4c64c4 | 3267 | return 0; |
2c2e2c38 | 3268 | |
9b226624 | 3269 | found = identity_mapping(dev); |
2c2e2c38 | 3270 | if (found) { |
ecb509ec | 3271 | if (iommu_should_identity_map(dev, 0)) |
2c2e2c38 FY |
3272 | return 1; |
3273 | else { | |
3274 | /* | |
3275 | * 32 bit DMA is removed from si_domain and fall back | |
3276 | * to non-identity mapping. | |
3277 | */ | |
e6de0f8d | 3278 | dmar_remove_one_dev_info(si_domain, dev); |
9f10e5bf JR |
3279 | pr_info("32bit %s uses non-identity mapping\n", |
3280 | dev_name(dev)); | |
2c2e2c38 FY |
3281 | return 0; |
3282 | } | |
3283 | } else { | |
3284 | /* | |
3285 | * In case of a detached 64 bit DMA device from vm, the device | |
3286 | * is put into si_domain for identity mapping. | |
3287 | */ | |
ecb509ec | 3288 | if (iommu_should_identity_map(dev, 0)) { |
2c2e2c38 | 3289 | int ret; |
28ccce0d | 3290 | ret = domain_add_dev_info(si_domain, dev); |
2c2e2c38 | 3291 | if (!ret) { |
9f10e5bf JR |
3292 | pr_info("64bit %s uses identity mapping\n", |
3293 | dev_name(dev)); | |
2c2e2c38 FY |
3294 | return 1; |
3295 | } | |
3296 | } | |
3297 | } | |
3298 | ||
1e4c64c4 | 3299 | return 0; |
2c2e2c38 FY |
3300 | } |
3301 | ||
5040a918 | 3302 | static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr, |
bb9e6d65 | 3303 | size_t size, int dir, u64 dma_mask) |
f76aec76 | 3304 | { |
f76aec76 | 3305 | struct dmar_domain *domain; |
5b6985ce | 3306 | phys_addr_t start_paddr; |
f76aec76 KA |
3307 | struct iova *iova; |
3308 | int prot = 0; | |
6865f0d1 | 3309 | int ret; |
8c11e798 | 3310 | struct intel_iommu *iommu; |
33041ec0 | 3311 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
f76aec76 KA |
3312 | |
3313 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 3314 | |
5040a918 | 3315 | if (iommu_no_mapping(dev)) |
6865f0d1 | 3316 | return paddr; |
f76aec76 | 3317 | |
5040a918 | 3318 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3319 | if (!domain) |
3320 | return 0; | |
3321 | ||
8c11e798 | 3322 | iommu = domain_get_iommu(domain); |
88cb6a74 | 3323 | size = aligned_nrpages(paddr, size); |
f76aec76 | 3324 | |
5040a918 | 3325 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask); |
f76aec76 KA |
3326 | if (!iova) |
3327 | goto error; | |
3328 | ||
ba395927 KA |
3329 | /* |
3330 | * Check if DMAR supports zero-length reads on write only | |
3331 | * mappings.. | |
3332 | */ | |
3333 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3334 | !cap_zlr(iommu->cap)) |
ba395927 KA |
3335 | prot |= DMA_PTE_READ; |
3336 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3337 | prot |= DMA_PTE_WRITE; | |
3338 | /* | |
6865f0d1 | 3339 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 3340 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 3341 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
3342 | * is not a big problem |
3343 | */ | |
0ab36de2 | 3344 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
33041ec0 | 3345 | mm_to_dma_pfn(paddr_pfn), size, prot); |
ba395927 KA |
3346 | if (ret) |
3347 | goto error; | |
3348 | ||
1f0ef2aa DW |
3349 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3350 | if (cap_caching_mode(iommu->cap)) | |
a1ddcbe9 JR |
3351 | iommu_flush_iotlb_psi(iommu, domain, |
3352 | mm_to_dma_pfn(iova->pfn_lo), | |
3353 | size, 0, 1); | |
1f0ef2aa | 3354 | else |
8c11e798 | 3355 | iommu_flush_write_buffer(iommu); |
f76aec76 | 3356 | |
03d6a246 DW |
3357 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
3358 | start_paddr += paddr & ~PAGE_MASK; | |
3359 | return start_paddr; | |
ba395927 | 3360 | |
ba395927 | 3361 | error: |
f76aec76 KA |
3362 | if (iova) |
3363 | __free_iova(&domain->iovad, iova); | |
9f10e5bf | 3364 | pr_err("Device %s request: %zx@%llx dir %d --- failed\n", |
5040a918 | 3365 | dev_name(dev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
3366 | return 0; |
3367 | } | |
3368 | ||
ffbbef5c FT |
3369 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
3370 | unsigned long offset, size_t size, | |
3371 | enum dma_data_direction dir, | |
3372 | struct dma_attrs *attrs) | |
bb9e6d65 | 3373 | { |
ffbbef5c | 3374 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
46333e37 | 3375 | dir, *dev->dma_mask); |
bb9e6d65 FT |
3376 | } |
3377 | ||
5e0d2a6f | 3378 | static void flush_unmaps(void) |
3379 | { | |
80b20dd8 | 3380 | int i, j; |
5e0d2a6f | 3381 | |
5e0d2a6f | 3382 | timer_on = 0; |
3383 | ||
3384 | /* just flush them all */ | |
3385 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
3386 | struct intel_iommu *iommu = g_iommus[i]; |
3387 | if (!iommu) | |
3388 | continue; | |
c42d9f32 | 3389 | |
9dd2fe89 YZ |
3390 | if (!deferred_flush[i].next) |
3391 | continue; | |
3392 | ||
78d5f0f5 NA |
3393 | /* In caching mode, global flushes turn emulation expensive */ |
3394 | if (!cap_caching_mode(iommu->cap)) | |
3395 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 3396 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 3397 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
3398 | unsigned long mask; |
3399 | struct iova *iova = deferred_flush[i].iova[j]; | |
78d5f0f5 NA |
3400 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
3401 | ||
3402 | /* On real hardware multiple invalidations are expensive */ | |
3403 | if (cap_caching_mode(iommu->cap)) | |
a1ddcbe9 | 3404 | iommu_flush_iotlb_psi(iommu, domain, |
a156ef99 | 3405 | iova->pfn_lo, iova_size(iova), |
ea8ea460 | 3406 | !deferred_flush[i].freelist[j], 0); |
78d5f0f5 | 3407 | else { |
a156ef99 | 3408 | mask = ilog2(mm_to_dma_pfn(iova_size(iova))); |
78d5f0f5 NA |
3409 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], |
3410 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); | |
3411 | } | |
93a23a72 | 3412 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
ea8ea460 DW |
3413 | if (deferred_flush[i].freelist[j]) |
3414 | dma_free_pagelist(deferred_flush[i].freelist[j]); | |
80b20dd8 | 3415 | } |
9dd2fe89 | 3416 | deferred_flush[i].next = 0; |
5e0d2a6f | 3417 | } |
3418 | ||
5e0d2a6f | 3419 | list_size = 0; |
5e0d2a6f | 3420 | } |
3421 | ||
3422 | static void flush_unmaps_timeout(unsigned long data) | |
3423 | { | |
80b20dd8 | 3424 | unsigned long flags; |
3425 | ||
3426 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 3427 | flush_unmaps(); |
80b20dd8 | 3428 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 3429 | } |
3430 | ||
ea8ea460 | 3431 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
5e0d2a6f | 3432 | { |
3433 | unsigned long flags; | |
80b20dd8 | 3434 | int next, iommu_id; |
8c11e798 | 3435 | struct intel_iommu *iommu; |
5e0d2a6f | 3436 | |
3437 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 3438 | if (list_size == HIGH_WATER_MARK) |
3439 | flush_unmaps(); | |
3440 | ||
8c11e798 WH |
3441 | iommu = domain_get_iommu(dom); |
3442 | iommu_id = iommu->seq_id; | |
c42d9f32 | 3443 | |
80b20dd8 | 3444 | next = deferred_flush[iommu_id].next; |
3445 | deferred_flush[iommu_id].domain[next] = dom; | |
3446 | deferred_flush[iommu_id].iova[next] = iova; | |
ea8ea460 | 3447 | deferred_flush[iommu_id].freelist[next] = freelist; |
80b20dd8 | 3448 | deferred_flush[iommu_id].next++; |
5e0d2a6f | 3449 | |
3450 | if (!timer_on) { | |
3451 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
3452 | timer_on = 1; | |
3453 | } | |
3454 | list_size++; | |
3455 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
3456 | } | |
3457 | ||
d41a4adb | 3458 | static void intel_unmap(struct device *dev, dma_addr_t dev_addr) |
ba395927 | 3459 | { |
f76aec76 | 3460 | struct dmar_domain *domain; |
d794dc9b | 3461 | unsigned long start_pfn, last_pfn; |
ba395927 | 3462 | struct iova *iova; |
8c11e798 | 3463 | struct intel_iommu *iommu; |
ea8ea460 | 3464 | struct page *freelist; |
ba395927 | 3465 | |
73676832 | 3466 | if (iommu_no_mapping(dev)) |
f76aec76 | 3467 | return; |
2c2e2c38 | 3468 | |
1525a29a | 3469 | domain = find_domain(dev); |
ba395927 KA |
3470 | BUG_ON(!domain); |
3471 | ||
8c11e798 WH |
3472 | iommu = domain_get_iommu(domain); |
3473 | ||
ba395927 | 3474 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
3475 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
3476 | (unsigned long long)dev_addr)) | |
ba395927 | 3477 | return; |
ba395927 | 3478 | |
d794dc9b DW |
3479 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3480 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 3481 | |
d794dc9b | 3482 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
207e3592 | 3483 | dev_name(dev), start_pfn, last_pfn); |
ba395927 | 3484 | |
ea8ea460 | 3485 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
d794dc9b | 3486 | |
5e0d2a6f | 3487 | if (intel_iommu_strict) { |
a1ddcbe9 | 3488 | iommu_flush_iotlb_psi(iommu, domain, start_pfn, |
ea8ea460 | 3489 | last_pfn - start_pfn + 1, !freelist, 0); |
5e0d2a6f | 3490 | /* free iova */ |
3491 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3492 | dma_free_pagelist(freelist); |
5e0d2a6f | 3493 | } else { |
ea8ea460 | 3494 | add_unmap(domain, iova, freelist); |
5e0d2a6f | 3495 | /* |
3496 | * queue up the release of the unmap to save the 1/6th of the | |
3497 | * cpu used up by the iotlb flush operation... | |
3498 | */ | |
5e0d2a6f | 3499 | } |
ba395927 KA |
3500 | } |
3501 | ||
d41a4adb JL |
3502 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
3503 | size_t size, enum dma_data_direction dir, | |
3504 | struct dma_attrs *attrs) | |
3505 | { | |
3506 | intel_unmap(dev, dev_addr); | |
3507 | } | |
3508 | ||
5040a918 | 3509 | static void *intel_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
3510 | dma_addr_t *dma_handle, gfp_t flags, |
3511 | struct dma_attrs *attrs) | |
ba395927 | 3512 | { |
36746436 | 3513 | struct page *page = NULL; |
ba395927 KA |
3514 | int order; |
3515 | ||
5b6985ce | 3516 | size = PAGE_ALIGN(size); |
ba395927 | 3517 | order = get_order(size); |
e8bb910d | 3518 | |
5040a918 | 3519 | if (!iommu_no_mapping(dev)) |
e8bb910d | 3520 | flags &= ~(GFP_DMA | GFP_DMA32); |
5040a918 DW |
3521 | else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) { |
3522 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) | |
e8bb910d AW |
3523 | flags |= GFP_DMA; |
3524 | else | |
3525 | flags |= GFP_DMA32; | |
3526 | } | |
ba395927 | 3527 | |
36746436 AM |
3528 | if (flags & __GFP_WAIT) { |
3529 | unsigned int count = size >> PAGE_SHIFT; | |
3530 | ||
3531 | page = dma_alloc_from_contiguous(dev, count, order); | |
3532 | if (page && iommu_no_mapping(dev) && | |
3533 | page_to_phys(page) + size > dev->coherent_dma_mask) { | |
3534 | dma_release_from_contiguous(dev, page, count); | |
3535 | page = NULL; | |
3536 | } | |
3537 | } | |
3538 | ||
3539 | if (!page) | |
3540 | page = alloc_pages(flags, order); | |
3541 | if (!page) | |
ba395927 | 3542 | return NULL; |
36746436 | 3543 | memset(page_address(page), 0, size); |
ba395927 | 3544 | |
36746436 | 3545 | *dma_handle = __intel_map_single(dev, page_to_phys(page), size, |
bb9e6d65 | 3546 | DMA_BIDIRECTIONAL, |
5040a918 | 3547 | dev->coherent_dma_mask); |
ba395927 | 3548 | if (*dma_handle) |
36746436 AM |
3549 | return page_address(page); |
3550 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
3551 | __free_pages(page, order); | |
3552 | ||
ba395927 KA |
3553 | return NULL; |
3554 | } | |
3555 | ||
5040a918 | 3556 | static void intel_free_coherent(struct device *dev, size_t size, void *vaddr, |
baa676fc | 3557 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
ba395927 KA |
3558 | { |
3559 | int order; | |
36746436 | 3560 | struct page *page = virt_to_page(vaddr); |
ba395927 | 3561 | |
5b6985ce | 3562 | size = PAGE_ALIGN(size); |
ba395927 KA |
3563 | order = get_order(size); |
3564 | ||
d41a4adb | 3565 | intel_unmap(dev, dma_handle); |
36746436 AM |
3566 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
3567 | __free_pages(page, order); | |
ba395927 KA |
3568 | } |
3569 | ||
5040a918 | 3570 | static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist, |
d7ab5c46 FT |
3571 | int nelems, enum dma_data_direction dir, |
3572 | struct dma_attrs *attrs) | |
ba395927 | 3573 | { |
d41a4adb | 3574 | intel_unmap(dev, sglist[0].dma_address); |
ba395927 KA |
3575 | } |
3576 | ||
ba395927 | 3577 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 3578 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
3579 | { |
3580 | int i; | |
c03ab37c | 3581 | struct scatterlist *sg; |
ba395927 | 3582 | |
c03ab37c | 3583 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 3584 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 3585 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 3586 | sg->dma_length = sg->length; |
ba395927 KA |
3587 | } |
3588 | return nelems; | |
3589 | } | |
3590 | ||
5040a918 | 3591 | static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, |
d7ab5c46 | 3592 | enum dma_data_direction dir, struct dma_attrs *attrs) |
ba395927 | 3593 | { |
ba395927 | 3594 | int i; |
ba395927 | 3595 | struct dmar_domain *domain; |
f76aec76 KA |
3596 | size_t size = 0; |
3597 | int prot = 0; | |
f76aec76 KA |
3598 | struct iova *iova = NULL; |
3599 | int ret; | |
c03ab37c | 3600 | struct scatterlist *sg; |
b536d24d | 3601 | unsigned long start_vpfn; |
8c11e798 | 3602 | struct intel_iommu *iommu; |
ba395927 KA |
3603 | |
3604 | BUG_ON(dir == DMA_NONE); | |
5040a918 DW |
3605 | if (iommu_no_mapping(dev)) |
3606 | return intel_nontranslate_map_sg(dev, sglist, nelems, dir); | |
ba395927 | 3607 | |
5040a918 | 3608 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3609 | if (!domain) |
3610 | return 0; | |
3611 | ||
8c11e798 WH |
3612 | iommu = domain_get_iommu(domain); |
3613 | ||
b536d24d | 3614 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 3615 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 3616 | |
5040a918 DW |
3617 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), |
3618 | *dev->dma_mask); | |
f76aec76 | 3619 | if (!iova) { |
c03ab37c | 3620 | sglist->dma_length = 0; |
f76aec76 KA |
3621 | return 0; |
3622 | } | |
3623 | ||
3624 | /* | |
3625 | * Check if DMAR supports zero-length reads on write only | |
3626 | * mappings.. | |
3627 | */ | |
3628 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3629 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
3630 | prot |= DMA_PTE_READ; |
3631 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3632 | prot |= DMA_PTE_WRITE; | |
3633 | ||
b536d24d | 3634 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 | 3635 | |
f532959b | 3636 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
e1605495 | 3637 | if (unlikely(ret)) { |
e1605495 DW |
3638 | dma_pte_free_pagetable(domain, start_vpfn, |
3639 | start_vpfn + size - 1); | |
e1605495 DW |
3640 | __free_iova(&domain->iovad, iova); |
3641 | return 0; | |
ba395927 KA |
3642 | } |
3643 | ||
1f0ef2aa DW |
3644 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3645 | if (cap_caching_mode(iommu->cap)) | |
a1ddcbe9 | 3646 | iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1); |
1f0ef2aa | 3647 | else |
8c11e798 | 3648 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 3649 | |
ba395927 KA |
3650 | return nelems; |
3651 | } | |
3652 | ||
dfb805e8 FT |
3653 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
3654 | { | |
3655 | return !dma_addr; | |
3656 | } | |
3657 | ||
160c1d8e | 3658 | struct dma_map_ops intel_dma_ops = { |
baa676fc AP |
3659 | .alloc = intel_alloc_coherent, |
3660 | .free = intel_free_coherent, | |
ba395927 KA |
3661 | .map_sg = intel_map_sg, |
3662 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
3663 | .map_page = intel_map_page, |
3664 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 3665 | .mapping_error = intel_mapping_error, |
ba395927 KA |
3666 | }; |
3667 | ||
3668 | static inline int iommu_domain_cache_init(void) | |
3669 | { | |
3670 | int ret = 0; | |
3671 | ||
3672 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
3673 | sizeof(struct dmar_domain), | |
3674 | 0, | |
3675 | SLAB_HWCACHE_ALIGN, | |
3676 | ||
3677 | NULL); | |
3678 | if (!iommu_domain_cache) { | |
9f10e5bf | 3679 | pr_err("Couldn't create iommu_domain cache\n"); |
ba395927 KA |
3680 | ret = -ENOMEM; |
3681 | } | |
3682 | ||
3683 | return ret; | |
3684 | } | |
3685 | ||
3686 | static inline int iommu_devinfo_cache_init(void) | |
3687 | { | |
3688 | int ret = 0; | |
3689 | ||
3690 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
3691 | sizeof(struct device_domain_info), | |
3692 | 0, | |
3693 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3694 | NULL); |
3695 | if (!iommu_devinfo_cache) { | |
9f10e5bf | 3696 | pr_err("Couldn't create devinfo cache\n"); |
ba395927 KA |
3697 | ret = -ENOMEM; |
3698 | } | |
3699 | ||
3700 | return ret; | |
3701 | } | |
3702 | ||
ba395927 KA |
3703 | static int __init iommu_init_mempool(void) |
3704 | { | |
3705 | int ret; | |
3706 | ret = iommu_iova_cache_init(); | |
3707 | if (ret) | |
3708 | return ret; | |
3709 | ||
3710 | ret = iommu_domain_cache_init(); | |
3711 | if (ret) | |
3712 | goto domain_error; | |
3713 | ||
3714 | ret = iommu_devinfo_cache_init(); | |
3715 | if (!ret) | |
3716 | return ret; | |
3717 | ||
3718 | kmem_cache_destroy(iommu_domain_cache); | |
3719 | domain_error: | |
85b45456 | 3720 | iommu_iova_cache_destroy(); |
ba395927 KA |
3721 | |
3722 | return -ENOMEM; | |
3723 | } | |
3724 | ||
3725 | static void __init iommu_exit_mempool(void) | |
3726 | { | |
3727 | kmem_cache_destroy(iommu_devinfo_cache); | |
3728 | kmem_cache_destroy(iommu_domain_cache); | |
85b45456 | 3729 | iommu_iova_cache_destroy(); |
ba395927 KA |
3730 | } |
3731 | ||
556ab45f DW |
3732 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
3733 | { | |
3734 | struct dmar_drhd_unit *drhd; | |
3735 | u32 vtbar; | |
3736 | int rc; | |
3737 | ||
3738 | /* We know that this device on this chipset has its own IOMMU. | |
3739 | * If we find it under a different IOMMU, then the BIOS is lying | |
3740 | * to us. Hope that the IOMMU for this device is actually | |
3741 | * disabled, and it needs no translation... | |
3742 | */ | |
3743 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); | |
3744 | if (rc) { | |
3745 | /* "can't" happen */ | |
3746 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); | |
3747 | return; | |
3748 | } | |
3749 | vtbar &= 0xffff0000; | |
3750 | ||
3751 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ | |
3752 | drhd = dmar_find_matched_drhd_unit(pdev); | |
3753 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, | |
3754 | TAINT_FIRMWARE_WORKAROUND, | |
3755 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) | |
3756 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; | |
3757 | } | |
3758 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); | |
3759 | ||
ba395927 KA |
3760 | static void __init init_no_remapping_devices(void) |
3761 | { | |
3762 | struct dmar_drhd_unit *drhd; | |
832bd858 | 3763 | struct device *dev; |
b683b230 | 3764 | int i; |
ba395927 KA |
3765 | |
3766 | for_each_drhd_unit(drhd) { | |
3767 | if (!drhd->include_all) { | |
b683b230 JL |
3768 | for_each_active_dev_scope(drhd->devices, |
3769 | drhd->devices_cnt, i, dev) | |
3770 | break; | |
832bd858 | 3771 | /* ignore DMAR unit if no devices exist */ |
ba395927 KA |
3772 | if (i == drhd->devices_cnt) |
3773 | drhd->ignored = 1; | |
3774 | } | |
3775 | } | |
3776 | ||
7c919779 | 3777 | for_each_active_drhd_unit(drhd) { |
7c919779 | 3778 | if (drhd->include_all) |
ba395927 KA |
3779 | continue; |
3780 | ||
b683b230 JL |
3781 | for_each_active_dev_scope(drhd->devices, |
3782 | drhd->devices_cnt, i, dev) | |
832bd858 | 3783 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
ba395927 | 3784 | break; |
ba395927 KA |
3785 | if (i < drhd->devices_cnt) |
3786 | continue; | |
3787 | ||
c0771df8 DW |
3788 | /* This IOMMU has *only* gfx devices. Either bypass it or |
3789 | set the gfx_mapped flag, as appropriate */ | |
3790 | if (dmar_map_gfx) { | |
3791 | intel_iommu_gfx_mapped = 1; | |
3792 | } else { | |
3793 | drhd->ignored = 1; | |
b683b230 JL |
3794 | for_each_active_dev_scope(drhd->devices, |
3795 | drhd->devices_cnt, i, dev) | |
832bd858 | 3796 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
3797 | } |
3798 | } | |
3799 | } | |
3800 | ||
f59c7b69 FY |
3801 | #ifdef CONFIG_SUSPEND |
3802 | static int init_iommu_hw(void) | |
3803 | { | |
3804 | struct dmar_drhd_unit *drhd; | |
3805 | struct intel_iommu *iommu = NULL; | |
3806 | ||
3807 | for_each_active_iommu(iommu, drhd) | |
3808 | if (iommu->qi) | |
3809 | dmar_reenable_qi(iommu); | |
3810 | ||
b779260b JC |
3811 | for_each_iommu(iommu, drhd) { |
3812 | if (drhd->ignored) { | |
3813 | /* | |
3814 | * we always have to disable PMRs or DMA may fail on | |
3815 | * this device | |
3816 | */ | |
3817 | if (force_on) | |
3818 | iommu_disable_protect_mem_regions(iommu); | |
3819 | continue; | |
3820 | } | |
3821 | ||
f59c7b69 FY |
3822 | iommu_flush_write_buffer(iommu); |
3823 | ||
3824 | iommu_set_root_entry(iommu); | |
3825 | ||
3826 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3827 | DMA_CCMD_GLOBAL_INVL); |
2a41ccee JL |
3828 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
3829 | iommu_enable_translation(iommu); | |
b94996c9 | 3830 | iommu_disable_protect_mem_regions(iommu); |
f59c7b69 FY |
3831 | } |
3832 | ||
3833 | return 0; | |
3834 | } | |
3835 | ||
3836 | static void iommu_flush_all(void) | |
3837 | { | |
3838 | struct dmar_drhd_unit *drhd; | |
3839 | struct intel_iommu *iommu; | |
3840 | ||
3841 | for_each_active_iommu(iommu, drhd) { | |
3842 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3843 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3844 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3845 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3846 | } |
3847 | } | |
3848 | ||
134fac3f | 3849 | static int iommu_suspend(void) |
f59c7b69 FY |
3850 | { |
3851 | struct dmar_drhd_unit *drhd; | |
3852 | struct intel_iommu *iommu = NULL; | |
3853 | unsigned long flag; | |
3854 | ||
3855 | for_each_active_iommu(iommu, drhd) { | |
3856 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3857 | GFP_ATOMIC); | |
3858 | if (!iommu->iommu_state) | |
3859 | goto nomem; | |
3860 | } | |
3861 | ||
3862 | iommu_flush_all(); | |
3863 | ||
3864 | for_each_active_iommu(iommu, drhd) { | |
3865 | iommu_disable_translation(iommu); | |
3866 | ||
1f5b3c3f | 3867 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3868 | |
3869 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3870 | readl(iommu->reg + DMAR_FECTL_REG); | |
3871 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3872 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3873 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3874 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3875 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3876 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3877 | ||
1f5b3c3f | 3878 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3879 | } |
3880 | return 0; | |
3881 | ||
3882 | nomem: | |
3883 | for_each_active_iommu(iommu, drhd) | |
3884 | kfree(iommu->iommu_state); | |
3885 | ||
3886 | return -ENOMEM; | |
3887 | } | |
3888 | ||
134fac3f | 3889 | static void iommu_resume(void) |
f59c7b69 FY |
3890 | { |
3891 | struct dmar_drhd_unit *drhd; | |
3892 | struct intel_iommu *iommu = NULL; | |
3893 | unsigned long flag; | |
3894 | ||
3895 | if (init_iommu_hw()) { | |
b779260b JC |
3896 | if (force_on) |
3897 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); | |
3898 | else | |
3899 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
134fac3f | 3900 | return; |
f59c7b69 FY |
3901 | } |
3902 | ||
3903 | for_each_active_iommu(iommu, drhd) { | |
3904 | ||
1f5b3c3f | 3905 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3906 | |
3907 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3908 | iommu->reg + DMAR_FECTL_REG); | |
3909 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3910 | iommu->reg + DMAR_FEDATA_REG); | |
3911 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3912 | iommu->reg + DMAR_FEADDR_REG); | |
3913 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3914 | iommu->reg + DMAR_FEUADDR_REG); | |
3915 | ||
1f5b3c3f | 3916 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3917 | } |
3918 | ||
3919 | for_each_active_iommu(iommu, drhd) | |
3920 | kfree(iommu->iommu_state); | |
f59c7b69 FY |
3921 | } |
3922 | ||
134fac3f | 3923 | static struct syscore_ops iommu_syscore_ops = { |
f59c7b69 FY |
3924 | .resume = iommu_resume, |
3925 | .suspend = iommu_suspend, | |
3926 | }; | |
3927 | ||
134fac3f | 3928 | static void __init init_iommu_pm_ops(void) |
f59c7b69 | 3929 | { |
134fac3f | 3930 | register_syscore_ops(&iommu_syscore_ops); |
f59c7b69 FY |
3931 | } |
3932 | ||
3933 | #else | |
99592ba4 | 3934 | static inline void init_iommu_pm_ops(void) {} |
f59c7b69 FY |
3935 | #endif /* CONFIG_PM */ |
3936 | ||
318fe7df | 3937 | |
c2a0b538 | 3938 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg) |
318fe7df SS |
3939 | { |
3940 | struct acpi_dmar_reserved_memory *rmrr; | |
3941 | struct dmar_rmrr_unit *rmrru; | |
3942 | ||
3943 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); | |
3944 | if (!rmrru) | |
3945 | return -ENOMEM; | |
3946 | ||
3947 | rmrru->hdr = header; | |
3948 | rmrr = (struct acpi_dmar_reserved_memory *)header; | |
3949 | rmrru->base_address = rmrr->base_address; | |
3950 | rmrru->end_address = rmrr->end_address; | |
2e455289 JL |
3951 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
3952 | ((void *)rmrr) + rmrr->header.length, | |
3953 | &rmrru->devices_cnt); | |
3954 | if (rmrru->devices_cnt && rmrru->devices == NULL) { | |
3955 | kfree(rmrru); | |
3956 | return -ENOMEM; | |
3957 | } | |
318fe7df | 3958 | |
2e455289 | 3959 | list_add(&rmrru->list, &dmar_rmrr_units); |
318fe7df | 3960 | |
2e455289 | 3961 | return 0; |
318fe7df SS |
3962 | } |
3963 | ||
6b197249 JL |
3964 | static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr) |
3965 | { | |
3966 | struct dmar_atsr_unit *atsru; | |
3967 | struct acpi_dmar_atsr *tmp; | |
3968 | ||
3969 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { | |
3970 | tmp = (struct acpi_dmar_atsr *)atsru->hdr; | |
3971 | if (atsr->segment != tmp->segment) | |
3972 | continue; | |
3973 | if (atsr->header.length != tmp->header.length) | |
3974 | continue; | |
3975 | if (memcmp(atsr, tmp, atsr->header.length) == 0) | |
3976 | return atsru; | |
3977 | } | |
3978 | ||
3979 | return NULL; | |
3980 | } | |
3981 | ||
3982 | int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg) | |
318fe7df SS |
3983 | { |
3984 | struct acpi_dmar_atsr *atsr; | |
3985 | struct dmar_atsr_unit *atsru; | |
3986 | ||
6b197249 JL |
3987 | if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled) |
3988 | return 0; | |
3989 | ||
318fe7df | 3990 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
6b197249 JL |
3991 | atsru = dmar_find_atsr(atsr); |
3992 | if (atsru) | |
3993 | return 0; | |
3994 | ||
3995 | atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL); | |
318fe7df SS |
3996 | if (!atsru) |
3997 | return -ENOMEM; | |
3998 | ||
6b197249 JL |
3999 | /* |
4000 | * If memory is allocated from slab by ACPI _DSM method, we need to | |
4001 | * copy the memory content because the memory buffer will be freed | |
4002 | * on return. | |
4003 | */ | |
4004 | atsru->hdr = (void *)(atsru + 1); | |
4005 | memcpy(atsru->hdr, hdr, hdr->length); | |
318fe7df | 4006 | atsru->include_all = atsr->flags & 0x1; |
2e455289 JL |
4007 | if (!atsru->include_all) { |
4008 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), | |
4009 | (void *)atsr + atsr->header.length, | |
4010 | &atsru->devices_cnt); | |
4011 | if (atsru->devices_cnt && atsru->devices == NULL) { | |
4012 | kfree(atsru); | |
4013 | return -ENOMEM; | |
4014 | } | |
4015 | } | |
318fe7df | 4016 | |
0e242612 | 4017 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
318fe7df SS |
4018 | |
4019 | return 0; | |
4020 | } | |
4021 | ||
9bdc531e JL |
4022 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
4023 | { | |
4024 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); | |
4025 | kfree(atsru); | |
4026 | } | |
4027 | ||
6b197249 JL |
4028 | int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
4029 | { | |
4030 | struct acpi_dmar_atsr *atsr; | |
4031 | struct dmar_atsr_unit *atsru; | |
4032 | ||
4033 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
4034 | atsru = dmar_find_atsr(atsr); | |
4035 | if (atsru) { | |
4036 | list_del_rcu(&atsru->list); | |
4037 | synchronize_rcu(); | |
4038 | intel_iommu_free_atsr(atsru); | |
4039 | } | |
4040 | ||
4041 | return 0; | |
4042 | } | |
4043 | ||
4044 | int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg) | |
4045 | { | |
4046 | int i; | |
4047 | struct device *dev; | |
4048 | struct acpi_dmar_atsr *atsr; | |
4049 | struct dmar_atsr_unit *atsru; | |
4050 | ||
4051 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
4052 | atsru = dmar_find_atsr(atsr); | |
4053 | if (!atsru) | |
4054 | return 0; | |
4055 | ||
4056 | if (!atsru->include_all && atsru->devices && atsru->devices_cnt) | |
4057 | for_each_active_dev_scope(atsru->devices, atsru->devices_cnt, | |
4058 | i, dev) | |
4059 | return -EBUSY; | |
4060 | ||
4061 | return 0; | |
4062 | } | |
4063 | ||
ffebeb46 JL |
4064 | static int intel_iommu_add(struct dmar_drhd_unit *dmaru) |
4065 | { | |
4066 | int sp, ret = 0; | |
4067 | struct intel_iommu *iommu = dmaru->iommu; | |
4068 | ||
4069 | if (g_iommus[iommu->seq_id]) | |
4070 | return 0; | |
4071 | ||
4072 | if (hw_pass_through && !ecap_pass_through(iommu->ecap)) { | |
9f10e5bf | 4073 | pr_warn("%s: Doesn't support hardware pass through.\n", |
ffebeb46 JL |
4074 | iommu->name); |
4075 | return -ENXIO; | |
4076 | } | |
4077 | if (!ecap_sc_support(iommu->ecap) && | |
4078 | domain_update_iommu_snooping(iommu)) { | |
9f10e5bf | 4079 | pr_warn("%s: Doesn't support snooping.\n", |
ffebeb46 JL |
4080 | iommu->name); |
4081 | return -ENXIO; | |
4082 | } | |
4083 | sp = domain_update_iommu_superpage(iommu) - 1; | |
4084 | if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { | |
9f10e5bf | 4085 | pr_warn("%s: Doesn't support large page.\n", |
ffebeb46 JL |
4086 | iommu->name); |
4087 | return -ENXIO; | |
4088 | } | |
4089 | ||
4090 | /* | |
4091 | * Disable translation if already enabled prior to OS handover. | |
4092 | */ | |
4093 | if (iommu->gcmd & DMA_GCMD_TE) | |
4094 | iommu_disable_translation(iommu); | |
4095 | ||
4096 | g_iommus[iommu->seq_id] = iommu; | |
4097 | ret = iommu_init_domains(iommu); | |
4098 | if (ret == 0) | |
4099 | ret = iommu_alloc_root_entry(iommu); | |
4100 | if (ret) | |
4101 | goto out; | |
4102 | ||
4103 | if (dmaru->ignored) { | |
4104 | /* | |
4105 | * we always have to disable PMRs or DMA may fail on this device | |
4106 | */ | |
4107 | if (force_on) | |
4108 | iommu_disable_protect_mem_regions(iommu); | |
4109 | return 0; | |
4110 | } | |
4111 | ||
4112 | intel_iommu_init_qi(iommu); | |
4113 | iommu_flush_write_buffer(iommu); | |
4114 | ret = dmar_set_interrupt(iommu); | |
4115 | if (ret) | |
4116 | goto disable_iommu; | |
4117 | ||
4118 | iommu_set_root_entry(iommu); | |
4119 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); | |
4120 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); | |
4121 | iommu_enable_translation(iommu); | |
4122 | ||
ffebeb46 JL |
4123 | iommu_disable_protect_mem_regions(iommu); |
4124 | return 0; | |
4125 | ||
4126 | disable_iommu: | |
4127 | disable_dmar_iommu(iommu); | |
4128 | out: | |
4129 | free_dmar_iommu(iommu); | |
4130 | return ret; | |
4131 | } | |
4132 | ||
6b197249 JL |
4133 | int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
4134 | { | |
ffebeb46 JL |
4135 | int ret = 0; |
4136 | struct intel_iommu *iommu = dmaru->iommu; | |
4137 | ||
4138 | if (!intel_iommu_enabled) | |
4139 | return 0; | |
4140 | if (iommu == NULL) | |
4141 | return -EINVAL; | |
4142 | ||
4143 | if (insert) { | |
4144 | ret = intel_iommu_add(dmaru); | |
4145 | } else { | |
4146 | disable_dmar_iommu(iommu); | |
4147 | free_dmar_iommu(iommu); | |
4148 | } | |
4149 | ||
4150 | return ret; | |
6b197249 JL |
4151 | } |
4152 | ||
9bdc531e JL |
4153 | static void intel_iommu_free_dmars(void) |
4154 | { | |
4155 | struct dmar_rmrr_unit *rmrru, *rmrr_n; | |
4156 | struct dmar_atsr_unit *atsru, *atsr_n; | |
4157 | ||
4158 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { | |
4159 | list_del(&rmrru->list); | |
4160 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); | |
4161 | kfree(rmrru); | |
318fe7df SS |
4162 | } |
4163 | ||
9bdc531e JL |
4164 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
4165 | list_del(&atsru->list); | |
4166 | intel_iommu_free_atsr(atsru); | |
4167 | } | |
318fe7df SS |
4168 | } |
4169 | ||
4170 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) | |
4171 | { | |
b683b230 | 4172 | int i, ret = 1; |
318fe7df | 4173 | struct pci_bus *bus; |
832bd858 DW |
4174 | struct pci_dev *bridge = NULL; |
4175 | struct device *tmp; | |
318fe7df SS |
4176 | struct acpi_dmar_atsr *atsr; |
4177 | struct dmar_atsr_unit *atsru; | |
4178 | ||
4179 | dev = pci_physfn(dev); | |
318fe7df | 4180 | for (bus = dev->bus; bus; bus = bus->parent) { |
b5f82ddf | 4181 | bridge = bus->self; |
318fe7df | 4182 | if (!bridge || !pci_is_pcie(bridge) || |
62f87c0e | 4183 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
318fe7df | 4184 | return 0; |
b5f82ddf | 4185 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
318fe7df | 4186 | break; |
318fe7df | 4187 | } |
b5f82ddf JL |
4188 | if (!bridge) |
4189 | return 0; | |
318fe7df | 4190 | |
0e242612 | 4191 | rcu_read_lock(); |
b5f82ddf JL |
4192 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
4193 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
4194 | if (atsr->segment != pci_domain_nr(dev->bus)) | |
4195 | continue; | |
4196 | ||
b683b230 | 4197 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
832bd858 | 4198 | if (tmp == &bridge->dev) |
b683b230 | 4199 | goto out; |
b5f82ddf JL |
4200 | |
4201 | if (atsru->include_all) | |
b683b230 | 4202 | goto out; |
b5f82ddf | 4203 | } |
b683b230 JL |
4204 | ret = 0; |
4205 | out: | |
0e242612 | 4206 | rcu_read_unlock(); |
318fe7df | 4207 | |
b683b230 | 4208 | return ret; |
318fe7df SS |
4209 | } |
4210 | ||
59ce0515 JL |
4211 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
4212 | { | |
4213 | int ret = 0; | |
4214 | struct dmar_rmrr_unit *rmrru; | |
4215 | struct dmar_atsr_unit *atsru; | |
4216 | struct acpi_dmar_atsr *atsr; | |
4217 | struct acpi_dmar_reserved_memory *rmrr; | |
4218 | ||
4219 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) | |
4220 | return 0; | |
4221 | ||
4222 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { | |
4223 | rmrr = container_of(rmrru->hdr, | |
4224 | struct acpi_dmar_reserved_memory, header); | |
4225 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
4226 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), | |
4227 | ((void *)rmrr) + rmrr->header.length, | |
4228 | rmrr->segment, rmrru->devices, | |
4229 | rmrru->devices_cnt); | |
27e24950 | 4230 | if(ret < 0) |
59ce0515 JL |
4231 | return ret; |
4232 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
27e24950 JL |
4233 | dmar_remove_dev_scope(info, rmrr->segment, |
4234 | rmrru->devices, rmrru->devices_cnt); | |
59ce0515 JL |
4235 | } |
4236 | } | |
4237 | ||
4238 | list_for_each_entry(atsru, &dmar_atsr_units, list) { | |
4239 | if (atsru->include_all) | |
4240 | continue; | |
4241 | ||
4242 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
4243 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
4244 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), | |
4245 | (void *)atsr + atsr->header.length, | |
4246 | atsr->segment, atsru->devices, | |
4247 | atsru->devices_cnt); | |
4248 | if (ret > 0) | |
4249 | break; | |
4250 | else if(ret < 0) | |
4251 | return ret; | |
4252 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
4253 | if (dmar_remove_dev_scope(info, atsr->segment, | |
4254 | atsru->devices, atsru->devices_cnt)) | |
4255 | break; | |
4256 | } | |
4257 | } | |
4258 | ||
4259 | return 0; | |
4260 | } | |
4261 | ||
99dcaded FY |
4262 | /* |
4263 | * Here we only respond to action of unbound device from driver. | |
4264 | * | |
4265 | * Added device is not attached to its DMAR domain here yet. That will happen | |
4266 | * when mapping the device to iova. | |
4267 | */ | |
4268 | static int device_notifier(struct notifier_block *nb, | |
4269 | unsigned long action, void *data) | |
4270 | { | |
4271 | struct device *dev = data; | |
99dcaded FY |
4272 | struct dmar_domain *domain; |
4273 | ||
3d89194a | 4274 | if (iommu_dummy(dev)) |
44cd613c DW |
4275 | return 0; |
4276 | ||
1196c2fb | 4277 | if (action != BUS_NOTIFY_REMOVED_DEVICE) |
7e7dfab7 JL |
4278 | return 0; |
4279 | ||
1525a29a | 4280 | domain = find_domain(dev); |
99dcaded FY |
4281 | if (!domain) |
4282 | return 0; | |
4283 | ||
e6de0f8d | 4284 | dmar_remove_one_dev_info(domain, dev); |
ab8dfe25 | 4285 | if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices)) |
7e7dfab7 | 4286 | domain_exit(domain); |
a97590e5 | 4287 | |
99dcaded FY |
4288 | return 0; |
4289 | } | |
4290 | ||
4291 | static struct notifier_block device_nb = { | |
4292 | .notifier_call = device_notifier, | |
4293 | }; | |
4294 | ||
75f05569 JL |
4295 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
4296 | unsigned long val, void *v) | |
4297 | { | |
4298 | struct memory_notify *mhp = v; | |
4299 | unsigned long long start, end; | |
4300 | unsigned long start_vpfn, last_vpfn; | |
4301 | ||
4302 | switch (val) { | |
4303 | case MEM_GOING_ONLINE: | |
4304 | start = mhp->start_pfn << PAGE_SHIFT; | |
4305 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; | |
4306 | if (iommu_domain_identity_map(si_domain, start, end)) { | |
9f10e5bf | 4307 | pr_warn("Failed to build identity map for [%llx-%llx]\n", |
75f05569 JL |
4308 | start, end); |
4309 | return NOTIFY_BAD; | |
4310 | } | |
4311 | break; | |
4312 | ||
4313 | case MEM_OFFLINE: | |
4314 | case MEM_CANCEL_ONLINE: | |
4315 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); | |
4316 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); | |
4317 | while (start_vpfn <= last_vpfn) { | |
4318 | struct iova *iova; | |
4319 | struct dmar_drhd_unit *drhd; | |
4320 | struct intel_iommu *iommu; | |
ea8ea460 | 4321 | struct page *freelist; |
75f05569 JL |
4322 | |
4323 | iova = find_iova(&si_domain->iovad, start_vpfn); | |
4324 | if (iova == NULL) { | |
9f10e5bf | 4325 | pr_debug("Failed get IOVA for PFN %lx\n", |
75f05569 JL |
4326 | start_vpfn); |
4327 | break; | |
4328 | } | |
4329 | ||
4330 | iova = split_and_remove_iova(&si_domain->iovad, iova, | |
4331 | start_vpfn, last_vpfn); | |
4332 | if (iova == NULL) { | |
9f10e5bf | 4333 | pr_warn("Failed to split IOVA PFN [%lx-%lx]\n", |
75f05569 JL |
4334 | start_vpfn, last_vpfn); |
4335 | return NOTIFY_BAD; | |
4336 | } | |
4337 | ||
ea8ea460 DW |
4338 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
4339 | iova->pfn_hi); | |
4340 | ||
75f05569 JL |
4341 | rcu_read_lock(); |
4342 | for_each_active_iommu(iommu, drhd) | |
a1ddcbe9 | 4343 | iommu_flush_iotlb_psi(iommu, si_domain, |
a156ef99 | 4344 | iova->pfn_lo, iova_size(iova), |
ea8ea460 | 4345 | !freelist, 0); |
75f05569 | 4346 | rcu_read_unlock(); |
ea8ea460 | 4347 | dma_free_pagelist(freelist); |
75f05569 JL |
4348 | |
4349 | start_vpfn = iova->pfn_hi + 1; | |
4350 | free_iova_mem(iova); | |
4351 | } | |
4352 | break; | |
4353 | } | |
4354 | ||
4355 | return NOTIFY_OK; | |
4356 | } | |
4357 | ||
4358 | static struct notifier_block intel_iommu_memory_nb = { | |
4359 | .notifier_call = intel_iommu_memory_notifier, | |
4360 | .priority = 0 | |
4361 | }; | |
4362 | ||
a5459cfe AW |
4363 | |
4364 | static ssize_t intel_iommu_show_version(struct device *dev, | |
4365 | struct device_attribute *attr, | |
4366 | char *buf) | |
4367 | { | |
4368 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4369 | u32 ver = readl(iommu->reg + DMAR_VER_REG); | |
4370 | return sprintf(buf, "%d:%d\n", | |
4371 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver)); | |
4372 | } | |
4373 | static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL); | |
4374 | ||
4375 | static ssize_t intel_iommu_show_address(struct device *dev, | |
4376 | struct device_attribute *attr, | |
4377 | char *buf) | |
4378 | { | |
4379 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4380 | return sprintf(buf, "%llx\n", iommu->reg_phys); | |
4381 | } | |
4382 | static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL); | |
4383 | ||
4384 | static ssize_t intel_iommu_show_cap(struct device *dev, | |
4385 | struct device_attribute *attr, | |
4386 | char *buf) | |
4387 | { | |
4388 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4389 | return sprintf(buf, "%llx\n", iommu->cap); | |
4390 | } | |
4391 | static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL); | |
4392 | ||
4393 | static ssize_t intel_iommu_show_ecap(struct device *dev, | |
4394 | struct device_attribute *attr, | |
4395 | char *buf) | |
4396 | { | |
4397 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4398 | return sprintf(buf, "%llx\n", iommu->ecap); | |
4399 | } | |
4400 | static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL); | |
4401 | ||
2238c082 AW |
4402 | static ssize_t intel_iommu_show_ndoms(struct device *dev, |
4403 | struct device_attribute *attr, | |
4404 | char *buf) | |
4405 | { | |
4406 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4407 | return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap)); | |
4408 | } | |
4409 | static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL); | |
4410 | ||
4411 | static ssize_t intel_iommu_show_ndoms_used(struct device *dev, | |
4412 | struct device_attribute *attr, | |
4413 | char *buf) | |
4414 | { | |
4415 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4416 | return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids, | |
4417 | cap_ndoms(iommu->cap))); | |
4418 | } | |
4419 | static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL); | |
4420 | ||
a5459cfe AW |
4421 | static struct attribute *intel_iommu_attrs[] = { |
4422 | &dev_attr_version.attr, | |
4423 | &dev_attr_address.attr, | |
4424 | &dev_attr_cap.attr, | |
4425 | &dev_attr_ecap.attr, | |
2238c082 AW |
4426 | &dev_attr_domains_supported.attr, |
4427 | &dev_attr_domains_used.attr, | |
a5459cfe AW |
4428 | NULL, |
4429 | }; | |
4430 | ||
4431 | static struct attribute_group intel_iommu_group = { | |
4432 | .name = "intel-iommu", | |
4433 | .attrs = intel_iommu_attrs, | |
4434 | }; | |
4435 | ||
4436 | const struct attribute_group *intel_iommu_groups[] = { | |
4437 | &intel_iommu_group, | |
4438 | NULL, | |
4439 | }; | |
4440 | ||
ba395927 KA |
4441 | int __init intel_iommu_init(void) |
4442 | { | |
9bdc531e | 4443 | int ret = -ENODEV; |
3a93c841 | 4444 | struct dmar_drhd_unit *drhd; |
7c919779 | 4445 | struct intel_iommu *iommu; |
ba395927 | 4446 | |
a59b50e9 JC |
4447 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
4448 | force_on = tboot_force_iommu(); | |
4449 | ||
3a5670e8 JL |
4450 | if (iommu_init_mempool()) { |
4451 | if (force_on) | |
4452 | panic("tboot: Failed to initialize iommu memory\n"); | |
4453 | return -ENOMEM; | |
4454 | } | |
4455 | ||
4456 | down_write(&dmar_global_lock); | |
a59b50e9 JC |
4457 | if (dmar_table_init()) { |
4458 | if (force_on) | |
4459 | panic("tboot: Failed to initialize DMAR table\n"); | |
9bdc531e | 4460 | goto out_free_dmar; |
a59b50e9 | 4461 | } |
ba395927 | 4462 | |
c2c7286a | 4463 | if (dmar_dev_scope_init() < 0) { |
a59b50e9 JC |
4464 | if (force_on) |
4465 | panic("tboot: Failed to initialize DMAR device scope\n"); | |
9bdc531e | 4466 | goto out_free_dmar; |
a59b50e9 | 4467 | } |
1886e8a9 | 4468 | |
75f1cdf1 | 4469 | if (no_iommu || dmar_disabled) |
9bdc531e | 4470 | goto out_free_dmar; |
2ae21010 | 4471 | |
318fe7df | 4472 | if (list_empty(&dmar_rmrr_units)) |
9f10e5bf | 4473 | pr_info("No RMRR found\n"); |
318fe7df SS |
4474 | |
4475 | if (list_empty(&dmar_atsr_units)) | |
9f10e5bf | 4476 | pr_info("No ATSR found\n"); |
318fe7df | 4477 | |
51a63e67 JC |
4478 | if (dmar_init_reserved_ranges()) { |
4479 | if (force_on) | |
4480 | panic("tboot: Failed to reserve iommu ranges\n"); | |
3a5670e8 | 4481 | goto out_free_reserved_range; |
51a63e67 | 4482 | } |
ba395927 KA |
4483 | |
4484 | init_no_remapping_devices(); | |
4485 | ||
b779260b | 4486 | ret = init_dmars(); |
ba395927 | 4487 | if (ret) { |
a59b50e9 JC |
4488 | if (force_on) |
4489 | panic("tboot: Failed to initialize DMARs\n"); | |
9f10e5bf | 4490 | pr_err("Initialization failed\n"); |
9bdc531e | 4491 | goto out_free_reserved_range; |
ba395927 | 4492 | } |
3a5670e8 | 4493 | up_write(&dmar_global_lock); |
9f10e5bf | 4494 | pr_info("Intel(R) Virtualization Technology for Directed I/O\n"); |
ba395927 | 4495 | |
5e0d2a6f | 4496 | init_timer(&unmap_timer); |
75f1cdf1 FT |
4497 | #ifdef CONFIG_SWIOTLB |
4498 | swiotlb = 0; | |
4499 | #endif | |
19943b0e | 4500 | dma_ops = &intel_dma_ops; |
4ed0d3e6 | 4501 | |
134fac3f | 4502 | init_iommu_pm_ops(); |
a8bcbb0d | 4503 | |
a5459cfe AW |
4504 | for_each_active_iommu(iommu, drhd) |
4505 | iommu->iommu_dev = iommu_device_create(NULL, iommu, | |
4506 | intel_iommu_groups, | |
2439d4aa | 4507 | "%s", iommu->name); |
a5459cfe | 4508 | |
4236d97d | 4509 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
99dcaded | 4510 | bus_register_notifier(&pci_bus_type, &device_nb); |
75f05569 JL |
4511 | if (si_domain && !hw_pass_through) |
4512 | register_memory_notifier(&intel_iommu_memory_nb); | |
99dcaded | 4513 | |
8bc1f85c ED |
4514 | intel_iommu_enabled = 1; |
4515 | ||
ba395927 | 4516 | return 0; |
9bdc531e JL |
4517 | |
4518 | out_free_reserved_range: | |
4519 | put_iova_domain(&reserved_iova_list); | |
9bdc531e JL |
4520 | out_free_dmar: |
4521 | intel_iommu_free_dmars(); | |
3a5670e8 JL |
4522 | up_write(&dmar_global_lock); |
4523 | iommu_exit_mempool(); | |
9bdc531e | 4524 | return ret; |
ba395927 | 4525 | } |
e820482c | 4526 | |
2452d9db | 4527 | static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque) |
579305f7 AW |
4528 | { |
4529 | struct intel_iommu *iommu = opaque; | |
4530 | ||
2452d9db | 4531 | domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); |
579305f7 AW |
4532 | return 0; |
4533 | } | |
4534 | ||
4535 | /* | |
4536 | * NB - intel-iommu lacks any sort of reference counting for the users of | |
4537 | * dependent devices. If multiple endpoints have intersecting dependent | |
4538 | * devices, unbinding the driver from any one of them will possibly leave | |
4539 | * the others unable to operate. | |
4540 | */ | |
2452d9db | 4541 | static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) |
3199aa6b | 4542 | { |
0bcb3e28 | 4543 | if (!iommu || !dev || !dev_is_pci(dev)) |
3199aa6b HW |
4544 | return; |
4545 | ||
2452d9db | 4546 | pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); |
3199aa6b HW |
4547 | } |
4548 | ||
127c7615 | 4549 | static void __dmar_remove_one_dev_info(struct device_domain_info *info) |
c7151a8d | 4550 | { |
c7151a8d WH |
4551 | struct intel_iommu *iommu; |
4552 | unsigned long flags; | |
c7151a8d | 4553 | |
55d94043 JR |
4554 | assert_spin_locked(&device_domain_lock); |
4555 | ||
127c7615 | 4556 | if (WARN_ON(!info)) |
c7151a8d WH |
4557 | return; |
4558 | ||
127c7615 | 4559 | iommu = info->iommu; |
c7151a8d | 4560 | |
127c7615 JR |
4561 | if (info->dev) { |
4562 | iommu_disable_dev_iotlb(info); | |
4563 | domain_context_clear(iommu, info->dev); | |
4564 | } | |
c7151a8d | 4565 | |
b608ac3b | 4566 | unlink_domain_info(info); |
3e7abe25 | 4567 | |
d160aca5 | 4568 | spin_lock_irqsave(&iommu->lock, flags); |
127c7615 | 4569 | domain_detach_iommu(info->domain, iommu); |
d160aca5 | 4570 | spin_unlock_irqrestore(&iommu->lock, flags); |
127c7615 JR |
4571 | |
4572 | free_devinfo_mem(info); | |
c7151a8d WH |
4573 | } |
4574 | ||
55d94043 JR |
4575 | static void dmar_remove_one_dev_info(struct dmar_domain *domain, |
4576 | struct device *dev) | |
4577 | { | |
127c7615 | 4578 | struct device_domain_info *info; |
55d94043 JR |
4579 | unsigned long flags; |
4580 | ||
4581 | spin_lock_irqsave(&device_domain_lock, flags); | |
127c7615 JR |
4582 | info = dev->archdata.iommu; |
4583 | __dmar_remove_one_dev_info(info); | |
55d94043 JR |
4584 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4585 | } | |
4586 | ||
2c2e2c38 | 4587 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
4588 | { |
4589 | int adjust_width; | |
4590 | ||
0fb5fe87 RM |
4591 | init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN, |
4592 | DMA_32BIT_PFN); | |
5e98c4b1 WH |
4593 | domain_reserve_special_ranges(domain); |
4594 | ||
4595 | /* calculate AGAW */ | |
4596 | domain->gaw = guest_width; | |
4597 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
4598 | domain->agaw = width_to_agaw(adjust_width); | |
4599 | ||
5e98c4b1 | 4600 | domain->iommu_coherency = 0; |
c5b15255 | 4601 | domain->iommu_snooping = 0; |
6dd9a7c7 | 4602 | domain->iommu_superpage = 0; |
fe40f1e0 | 4603 | domain->max_addr = 0; |
5e98c4b1 WH |
4604 | |
4605 | /* always allocate the top pgd */ | |
4c923d47 | 4606 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
5e98c4b1 WH |
4607 | if (!domain->pgd) |
4608 | return -ENOMEM; | |
4609 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
4610 | return 0; | |
4611 | } | |
4612 | ||
00a77deb | 4613 | static struct iommu_domain *intel_iommu_domain_alloc(unsigned type) |
38717946 | 4614 | { |
5d450806 | 4615 | struct dmar_domain *dmar_domain; |
00a77deb JR |
4616 | struct iommu_domain *domain; |
4617 | ||
4618 | if (type != IOMMU_DOMAIN_UNMANAGED) | |
4619 | return NULL; | |
38717946 | 4620 | |
ab8dfe25 | 4621 | dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE); |
5d450806 | 4622 | if (!dmar_domain) { |
9f10e5bf | 4623 | pr_err("Can't allocate dmar_domain\n"); |
00a77deb | 4624 | return NULL; |
38717946 | 4625 | } |
2c2e2c38 | 4626 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
9f10e5bf | 4627 | pr_err("Domain initialization failed\n"); |
92d03cc8 | 4628 | domain_exit(dmar_domain); |
00a77deb | 4629 | return NULL; |
38717946 | 4630 | } |
8140a95d | 4631 | domain_update_iommu_cap(dmar_domain); |
faa3d6f5 | 4632 | |
00a77deb | 4633 | domain = &dmar_domain->domain; |
8a0e715b JR |
4634 | domain->geometry.aperture_start = 0; |
4635 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); | |
4636 | domain->geometry.force_aperture = true; | |
4637 | ||
00a77deb | 4638 | return domain; |
38717946 | 4639 | } |
38717946 | 4640 | |
00a77deb | 4641 | static void intel_iommu_domain_free(struct iommu_domain *domain) |
38717946 | 4642 | { |
00a77deb | 4643 | domain_exit(to_dmar_domain(domain)); |
38717946 | 4644 | } |
38717946 | 4645 | |
4c5478c9 JR |
4646 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
4647 | struct device *dev) | |
38717946 | 4648 | { |
00a77deb | 4649 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
fe40f1e0 WH |
4650 | struct intel_iommu *iommu; |
4651 | int addr_width; | |
156baca8 | 4652 | u8 bus, devfn; |
faa3d6f5 | 4653 | |
c875d2c1 AW |
4654 | if (device_is_rmrr_locked(dev)) { |
4655 | dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n"); | |
4656 | return -EPERM; | |
4657 | } | |
4658 | ||
7207d8f9 DW |
4659 | /* normally dev is not mapped */ |
4660 | if (unlikely(domain_context_mapped(dev))) { | |
faa3d6f5 WH |
4661 | struct dmar_domain *old_domain; |
4662 | ||
1525a29a | 4663 | old_domain = find_domain(dev); |
faa3d6f5 | 4664 | if (old_domain) { |
d160aca5 | 4665 | rcu_read_lock(); |
de7e8886 | 4666 | dmar_remove_one_dev_info(old_domain, dev); |
d160aca5 | 4667 | rcu_read_unlock(); |
62c22167 JR |
4668 | |
4669 | if (!domain_type_is_vm_or_si(old_domain) && | |
4670 | list_empty(&old_domain->devices)) | |
4671 | domain_exit(old_domain); | |
faa3d6f5 WH |
4672 | } |
4673 | } | |
4674 | ||
156baca8 | 4675 | iommu = device_to_iommu(dev, &bus, &devfn); |
fe40f1e0 WH |
4676 | if (!iommu) |
4677 | return -ENODEV; | |
4678 | ||
4679 | /* check if this iommu agaw is sufficient for max mapped address */ | |
4680 | addr_width = agaw_to_width(iommu->agaw); | |
a99c47a2 TL |
4681 | if (addr_width > cap_mgaw(iommu->cap)) |
4682 | addr_width = cap_mgaw(iommu->cap); | |
4683 | ||
4684 | if (dmar_domain->max_addr > (1LL << addr_width)) { | |
9f10e5bf | 4685 | pr_err("%s: iommu width (%d) is not " |
fe40f1e0 | 4686 | "sufficient for the mapped address (%llx)\n", |
a99c47a2 | 4687 | __func__, addr_width, dmar_domain->max_addr); |
fe40f1e0 WH |
4688 | return -EFAULT; |
4689 | } | |
a99c47a2 TL |
4690 | dmar_domain->gaw = addr_width; |
4691 | ||
4692 | /* | |
4693 | * Knock out extra levels of page tables if necessary | |
4694 | */ | |
4695 | while (iommu->agaw < dmar_domain->agaw) { | |
4696 | struct dma_pte *pte; | |
4697 | ||
4698 | pte = dmar_domain->pgd; | |
4699 | if (dma_pte_present(pte)) { | |
25cbff16 SY |
4700 | dmar_domain->pgd = (struct dma_pte *) |
4701 | phys_to_virt(dma_pte_addr(pte)); | |
7a661013 | 4702 | free_pgtable_page(pte); |
a99c47a2 TL |
4703 | } |
4704 | dmar_domain->agaw--; | |
4705 | } | |
fe40f1e0 | 4706 | |
28ccce0d | 4707 | return domain_add_dev_info(dmar_domain, dev); |
38717946 | 4708 | } |
38717946 | 4709 | |
4c5478c9 JR |
4710 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
4711 | struct device *dev) | |
38717946 | 4712 | { |
e6de0f8d | 4713 | dmar_remove_one_dev_info(to_dmar_domain(domain), dev); |
faa3d6f5 | 4714 | } |
c7151a8d | 4715 | |
b146a1c9 JR |
4716 | static int intel_iommu_map(struct iommu_domain *domain, |
4717 | unsigned long iova, phys_addr_t hpa, | |
5009065d | 4718 | size_t size, int iommu_prot) |
faa3d6f5 | 4719 | { |
00a77deb | 4720 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
fe40f1e0 | 4721 | u64 max_addr; |
dde57a21 | 4722 | int prot = 0; |
faa3d6f5 | 4723 | int ret; |
fe40f1e0 | 4724 | |
dde57a21 JR |
4725 | if (iommu_prot & IOMMU_READ) |
4726 | prot |= DMA_PTE_READ; | |
4727 | if (iommu_prot & IOMMU_WRITE) | |
4728 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
4729 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
4730 | prot |= DMA_PTE_SNP; | |
dde57a21 | 4731 | |
163cc52c | 4732 | max_addr = iova + size; |
dde57a21 | 4733 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
4734 | u64 end; |
4735 | ||
4736 | /* check if minimum agaw is sufficient for mapped address */ | |
8954da1f | 4737 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
fe40f1e0 | 4738 | if (end < max_addr) { |
9f10e5bf | 4739 | pr_err("%s: iommu width (%d) is not " |
fe40f1e0 | 4740 | "sufficient for the mapped address (%llx)\n", |
8954da1f | 4741 | __func__, dmar_domain->gaw, max_addr); |
fe40f1e0 WH |
4742 | return -EFAULT; |
4743 | } | |
dde57a21 | 4744 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 4745 | } |
ad051221 DW |
4746 | /* Round up size to next multiple of PAGE_SIZE, if it and |
4747 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 4748 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
4749 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
4750 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 4751 | return ret; |
38717946 | 4752 | } |
38717946 | 4753 | |
5009065d | 4754 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
ea8ea460 | 4755 | unsigned long iova, size_t size) |
38717946 | 4756 | { |
00a77deb | 4757 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
ea8ea460 DW |
4758 | struct page *freelist = NULL; |
4759 | struct intel_iommu *iommu; | |
4760 | unsigned long start_pfn, last_pfn; | |
4761 | unsigned int npages; | |
42e8c186 | 4762 | int iommu_id, level = 0; |
5cf0a76f DW |
4763 | |
4764 | /* Cope with horrid API which requires us to unmap more than the | |
4765 | size argument if it happens to be a large-page mapping. */ | |
dc02e46e | 4766 | BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)); |
5cf0a76f DW |
4767 | |
4768 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) | |
4769 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); | |
4b99d352 | 4770 | |
ea8ea460 DW |
4771 | start_pfn = iova >> VTD_PAGE_SHIFT; |
4772 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; | |
4773 | ||
4774 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); | |
4775 | ||
4776 | npages = last_pfn - start_pfn + 1; | |
4777 | ||
29a27719 | 4778 | for_each_domain_iommu(iommu_id, dmar_domain) { |
a1ddcbe9 JR |
4779 | iommu = g_iommus[iommu_id]; |
4780 | ||
42e8c186 JR |
4781 | iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain, |
4782 | start_pfn, npages, !freelist, 0); | |
ea8ea460 DW |
4783 | } |
4784 | ||
4785 | dma_free_pagelist(freelist); | |
fe40f1e0 | 4786 | |
163cc52c DW |
4787 | if (dmar_domain->max_addr == iova + size) |
4788 | dmar_domain->max_addr = iova; | |
b146a1c9 | 4789 | |
5cf0a76f | 4790 | return size; |
38717946 | 4791 | } |
38717946 | 4792 | |
d14d6577 | 4793 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
bb5547ac | 4794 | dma_addr_t iova) |
38717946 | 4795 | { |
00a77deb | 4796 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
38717946 | 4797 | struct dma_pte *pte; |
5cf0a76f | 4798 | int level = 0; |
faa3d6f5 | 4799 | u64 phys = 0; |
38717946 | 4800 | |
5cf0a76f | 4801 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
38717946 | 4802 | if (pte) |
faa3d6f5 | 4803 | phys = dma_pte_addr(pte); |
38717946 | 4804 | |
faa3d6f5 | 4805 | return phys; |
38717946 | 4806 | } |
a8bcbb0d | 4807 | |
5d587b8d | 4808 | static bool intel_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 4809 | { |
dbb9fd86 | 4810 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
5d587b8d | 4811 | return domain_update_iommu_snooping(NULL) == 1; |
323f99cb | 4812 | if (cap == IOMMU_CAP_INTR_REMAP) |
5d587b8d | 4813 | return irq_remapping_enabled == 1; |
dbb9fd86 | 4814 | |
5d587b8d | 4815 | return false; |
dbb9fd86 SY |
4816 | } |
4817 | ||
abdfdde2 AW |
4818 | static int intel_iommu_add_device(struct device *dev) |
4819 | { | |
a5459cfe | 4820 | struct intel_iommu *iommu; |
abdfdde2 | 4821 | struct iommu_group *group; |
156baca8 | 4822 | u8 bus, devfn; |
70ae6f0d | 4823 | |
a5459cfe AW |
4824 | iommu = device_to_iommu(dev, &bus, &devfn); |
4825 | if (!iommu) | |
70ae6f0d AW |
4826 | return -ENODEV; |
4827 | ||
a5459cfe | 4828 | iommu_device_link(iommu->iommu_dev, dev); |
a4ff1fc2 | 4829 | |
e17f9ff4 | 4830 | group = iommu_group_get_for_dev(dev); |
783f157b | 4831 | |
e17f9ff4 AW |
4832 | if (IS_ERR(group)) |
4833 | return PTR_ERR(group); | |
bcb71abe | 4834 | |
abdfdde2 | 4835 | iommu_group_put(group); |
e17f9ff4 | 4836 | return 0; |
abdfdde2 | 4837 | } |
70ae6f0d | 4838 | |
abdfdde2 AW |
4839 | static void intel_iommu_remove_device(struct device *dev) |
4840 | { | |
a5459cfe AW |
4841 | struct intel_iommu *iommu; |
4842 | u8 bus, devfn; | |
4843 | ||
4844 | iommu = device_to_iommu(dev, &bus, &devfn); | |
4845 | if (!iommu) | |
4846 | return; | |
4847 | ||
abdfdde2 | 4848 | iommu_group_remove_device(dev); |
a5459cfe AW |
4849 | |
4850 | iommu_device_unlink(iommu->iommu_dev, dev); | |
70ae6f0d AW |
4851 | } |
4852 | ||
b22f6434 | 4853 | static const struct iommu_ops intel_iommu_ops = { |
5d587b8d | 4854 | .capable = intel_iommu_capable, |
00a77deb JR |
4855 | .domain_alloc = intel_iommu_domain_alloc, |
4856 | .domain_free = intel_iommu_domain_free, | |
a8bcbb0d JR |
4857 | .attach_dev = intel_iommu_attach_device, |
4858 | .detach_dev = intel_iommu_detach_device, | |
b146a1c9 JR |
4859 | .map = intel_iommu_map, |
4860 | .unmap = intel_iommu_unmap, | |
315786eb | 4861 | .map_sg = default_iommu_map_sg, |
a8bcbb0d | 4862 | .iova_to_phys = intel_iommu_iova_to_phys, |
abdfdde2 AW |
4863 | .add_device = intel_iommu_add_device, |
4864 | .remove_device = intel_iommu_remove_device, | |
6d1c56a9 | 4865 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
a8bcbb0d | 4866 | }; |
9af88143 | 4867 | |
9452618e DV |
4868 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
4869 | { | |
4870 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ | |
9f10e5bf | 4871 | pr_info("Disabling IOMMU for graphics on this chipset\n"); |
9452618e DV |
4872 | dmar_map_gfx = 0; |
4873 | } | |
4874 | ||
4875 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); | |
4876 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); | |
4877 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); | |
4878 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); | |
4879 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); | |
4880 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); | |
4881 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); | |
4882 | ||
d34d6517 | 4883 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
9af88143 DW |
4884 | { |
4885 | /* | |
4886 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
210561ff | 4887 | * but needs it. Same seems to hold for the desktop versions. |
9af88143 | 4888 | */ |
9f10e5bf | 4889 | pr_info("Forcing write-buffer flush capability\n"); |
9af88143 DW |
4890 | rwbf_quirk = 1; |
4891 | } | |
4892 | ||
4893 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); | |
210561ff DV |
4894 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
4895 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); | |
4896 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); | |
4897 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); | |
4898 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); | |
4899 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); | |
e0fc7e0b | 4900 | |
eecfd57f AJ |
4901 | #define GGC 0x52 |
4902 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) | |
4903 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) | |
4904 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) | |
4905 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) | |
4906 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) | |
4907 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) | |
4908 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) | |
4909 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) | |
4910 | ||
d34d6517 | 4911 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
9eecabcb DW |
4912 | { |
4913 | unsigned short ggc; | |
4914 | ||
eecfd57f | 4915 | if (pci_read_config_word(dev, GGC, &ggc)) |
9eecabcb DW |
4916 | return; |
4917 | ||
eecfd57f | 4918 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
9f10e5bf | 4919 | pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
9eecabcb | 4920 | dmar_map_gfx = 0; |
6fbcfb3e DW |
4921 | } else if (dmar_map_gfx) { |
4922 | /* we have to ensure the gfx device is idle before we flush */ | |
9f10e5bf | 4923 | pr_info("Disabling batched IOTLB flush on Ironlake\n"); |
6fbcfb3e DW |
4924 | intel_iommu_strict = 1; |
4925 | } | |
9eecabcb DW |
4926 | } |
4927 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); | |
4928 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); | |
4929 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); | |
4930 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); | |
4931 | ||
e0fc7e0b DW |
4932 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
4933 | ISOCH DMAR unit for the Azalia sound device, but not give it any | |
4934 | TLB entries, which causes it to deadlock. Check for that. We do | |
4935 | this in a function called from init_dmars(), instead of in a PCI | |
4936 | quirk, because we don't want to print the obnoxious "BIOS broken" | |
4937 | message if VT-d is actually disabled. | |
4938 | */ | |
4939 | static void __init check_tylersburg_isoch(void) | |
4940 | { | |
4941 | struct pci_dev *pdev; | |
4942 | uint32_t vtisochctrl; | |
4943 | ||
4944 | /* If there's no Azalia in the system anyway, forget it. */ | |
4945 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); | |
4946 | if (!pdev) | |
4947 | return; | |
4948 | pci_dev_put(pdev); | |
4949 | ||
4950 | /* System Management Registers. Might be hidden, in which case | |
4951 | we can't do the sanity check. But that's OK, because the | |
4952 | known-broken BIOSes _don't_ actually hide it, so far. */ | |
4953 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); | |
4954 | if (!pdev) | |
4955 | return; | |
4956 | ||
4957 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { | |
4958 | pci_dev_put(pdev); | |
4959 | return; | |
4960 | } | |
4961 | ||
4962 | pci_dev_put(pdev); | |
4963 | ||
4964 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ | |
4965 | if (vtisochctrl & 1) | |
4966 | return; | |
4967 | ||
4968 | /* Drop all bits other than the number of TLB entries */ | |
4969 | vtisochctrl &= 0x1c; | |
4970 | ||
4971 | /* If we have the recommended number of TLB entries (16), fine. */ | |
4972 | if (vtisochctrl == 0x10) | |
4973 | return; | |
4974 | ||
4975 | /* Zero TLB entries? You get to ride the short bus to school. */ | |
4976 | if (!vtisochctrl) { | |
4977 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" | |
4978 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
4979 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
4980 | dmi_get_system_info(DMI_BIOS_VERSION), | |
4981 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
4982 | iommu_identity_mapping |= IDENTMAP_AZALIA; | |
4983 | return; | |
4984 | } | |
9f10e5bf JR |
4985 | |
4986 | pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", | |
e0fc7e0b DW |
4987 | vtisochctrl); |
4988 | } |