Commit | Line | Data |
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8a94ade4 DW |
1 | /* |
2 | * Copyright © 2015 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * Authors: David Woodhouse <dwmw2@infradead.org> | |
14 | */ | |
15 | ||
16 | #include <linux/intel-iommu.h> | |
2f26e0a9 DW |
17 | #include <linux/mmu_notifier.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/intel-svm.h> | |
21 | #include <linux/rculist.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/pci-ats.h> | |
a222a7f0 DW |
24 | #include <linux/dmar.h> |
25 | #include <linux/interrupt.h> | |
26 | ||
27 | static irqreturn_t prq_event_thread(int irq, void *d); | |
2f26e0a9 DW |
28 | |
29 | struct pasid_entry { | |
30 | u64 val; | |
31 | }; | |
8a94ade4 | 32 | |
907fea34 DW |
33 | struct pasid_state_entry { |
34 | u64 val; | |
35 | }; | |
36 | ||
8a94ade4 DW |
37 | int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) |
38 | { | |
39 | struct page *pages; | |
40 | int order; | |
41 | ||
42 | order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT; | |
43 | if (order < 0) | |
44 | order = 0; | |
45 | ||
46 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); | |
47 | if (!pages) { | |
48 | pr_warn("IOMMU: %s: Failed to allocate PASID table\n", | |
49 | iommu->name); | |
50 | return -ENOMEM; | |
51 | } | |
52 | iommu->pasid_table = page_address(pages); | |
53 | pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order); | |
54 | ||
55 | if (ecap_dis(iommu->ecap)) { | |
56 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); | |
57 | if (pages) | |
58 | iommu->pasid_state_table = page_address(pages); | |
59 | else | |
60 | pr_warn("IOMMU: %s: Failed to allocate PASID state table\n", | |
61 | iommu->name); | |
62 | } | |
63 | ||
2f26e0a9 DW |
64 | idr_init(&iommu->pasid_idr); |
65 | ||
8a94ade4 DW |
66 | return 0; |
67 | } | |
68 | ||
69 | int intel_svm_free_pasid_tables(struct intel_iommu *iommu) | |
70 | { | |
71 | int order; | |
72 | ||
73 | order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT; | |
74 | if (order < 0) | |
75 | order = 0; | |
76 | ||
77 | if (iommu->pasid_table) { | |
78 | free_pages((unsigned long)iommu->pasid_table, order); | |
79 | iommu->pasid_table = NULL; | |
80 | } | |
81 | if (iommu->pasid_state_table) { | |
82 | free_pages((unsigned long)iommu->pasid_state_table, order); | |
83 | iommu->pasid_state_table = NULL; | |
84 | } | |
2f26e0a9 | 85 | idr_destroy(&iommu->pasid_idr); |
8a94ade4 DW |
86 | return 0; |
87 | } | |
2f26e0a9 | 88 | |
a222a7f0 DW |
89 | #define PRQ_ORDER 0 |
90 | ||
91 | int intel_svm_enable_prq(struct intel_iommu *iommu) | |
92 | { | |
93 | struct page *pages; | |
94 | int irq, ret; | |
95 | ||
96 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER); | |
97 | if (!pages) { | |
98 | pr_warn("IOMMU: %s: Failed to allocate page request queue\n", | |
99 | iommu->name); | |
100 | return -ENOMEM; | |
101 | } | |
102 | iommu->prq = page_address(pages); | |
103 | ||
104 | irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu); | |
105 | if (irq <= 0) { | |
106 | pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n", | |
107 | iommu->name); | |
108 | ret = -EINVAL; | |
109 | err: | |
110 | free_pages((unsigned long)iommu->prq, PRQ_ORDER); | |
111 | iommu->prq = NULL; | |
112 | return ret; | |
113 | } | |
114 | iommu->pr_irq = irq; | |
115 | ||
116 | snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id); | |
117 | ||
118 | ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT, | |
119 | iommu->prq_name, iommu); | |
120 | if (ret) { | |
121 | pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n", | |
122 | iommu->name); | |
123 | dmar_free_hwirq(irq); | |
124 | goto err; | |
125 | } | |
126 | dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); | |
127 | dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); | |
128 | dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | int intel_svm_finish_prq(struct intel_iommu *iommu) | |
134 | { | |
135 | dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); | |
136 | dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); | |
137 | dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); | |
138 | ||
139 | free_irq(iommu->pr_irq, iommu); | |
140 | dmar_free_hwirq(iommu->pr_irq); | |
141 | iommu->pr_irq = 0; | |
142 | ||
143 | free_pages((unsigned long)iommu->prq, PRQ_ORDER); | |
144 | iommu->prq = NULL; | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
2f26e0a9 DW |
149 | static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev, |
150 | unsigned long address, int pages, int ih) | |
151 | { | |
152 | struct qi_desc desc; | |
153 | int mask = ilog2(__roundup_pow_of_two(pages)); | |
154 | ||
155 | if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap) || | |
156 | mask > cap_max_amask_val(svm->iommu->cap)) { | |
157 | desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) | | |
158 | QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE; | |
159 | desc.high = 0; | |
160 | } else { | |
161 | desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) | | |
162 | QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE; | |
163 | desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(1) | | |
164 | QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask); | |
165 | } | |
166 | ||
167 | qi_submit_sync(&desc, svm->iommu); | |
168 | ||
169 | if (sdev->dev_iotlb) { | |
170 | desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) | | |
171 | QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE; | |
172 | if (mask) { | |
173 | unsigned long adr, delta; | |
174 | ||
175 | /* Least significant zero bits in the address indicate the | |
176 | * range of the request. So mask them out according to the | |
177 | * size. */ | |
178 | adr = address & ((1<<(VTD_PAGE_SHIFT + mask)) - 1); | |
179 | ||
180 | /* Now ensure that we round down further if the original | |
181 | * request was not aligned w.r.t. its size */ | |
182 | delta = address - adr; | |
183 | if (delta + (pages << VTD_PAGE_SHIFT) >= (1 << (VTD_PAGE_SHIFT + mask))) | |
184 | adr &= ~(1 << (VTD_PAGE_SHIFT + mask)); | |
185 | desc.high = QI_DEV_EIOTLB_ADDR(adr) | QI_DEV_EIOTLB_SIZE; | |
186 | } else { | |
187 | desc.high = QI_DEV_EIOTLB_ADDR(address); | |
188 | } | |
189 | qi_submit_sync(&desc, svm->iommu); | |
190 | } | |
191 | } | |
192 | ||
193 | static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address, | |
194 | int pages, int ih) | |
195 | { | |
196 | struct intel_svm_dev *sdev; | |
197 | ||
907fea34 DW |
198 | /* Try deferred invalidate if available */ |
199 | if (svm->iommu->pasid_state_table && | |
200 | !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63)) | |
201 | return; | |
202 | ||
2f26e0a9 DW |
203 | rcu_read_lock(); |
204 | list_for_each_entry_rcu(sdev, &svm->devs, list) | |
205 | intel_flush_svm_range_dev(svm, sdev, address, pages, ih); | |
206 | rcu_read_unlock(); | |
207 | } | |
208 | ||
209 | static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm, | |
210 | unsigned long address, pte_t pte) | |
211 | { | |
212 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
213 | ||
214 | intel_flush_svm_range(svm, address, 1, 1); | |
215 | } | |
216 | ||
217 | static void intel_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm, | |
218 | unsigned long address) | |
219 | { | |
220 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
221 | ||
222 | intel_flush_svm_range(svm, address, 1, 1); | |
223 | } | |
224 | ||
225 | /* Pages have been freed at this point */ | |
226 | static void intel_invalidate_range(struct mmu_notifier *mn, | |
227 | struct mm_struct *mm, | |
228 | unsigned long start, unsigned long end) | |
229 | { | |
230 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
231 | ||
232 | intel_flush_svm_range(svm, start, | |
233 | (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT , 0); | |
234 | } | |
235 | ||
236 | ||
237 | static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev) | |
238 | { | |
239 | struct qi_desc desc; | |
240 | ||
241 | desc.high = 0; | |
242 | desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(svm->pasid); | |
243 | ||
244 | qi_submit_sync(&desc, svm->iommu); | |
245 | } | |
246 | ||
247 | static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) | |
248 | { | |
249 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
250 | ||
251 | svm->iommu->pasid_table[svm->pasid].val = 0; | |
252 | ||
253 | /* There's no need to do any flush because we can't get here if there | |
254 | * are any devices left anyway. */ | |
255 | WARN_ON(!list_empty(&svm->devs)); | |
256 | } | |
257 | ||
258 | static const struct mmu_notifier_ops intel_mmuops = { | |
259 | .release = intel_mm_release, | |
260 | .change_pte = intel_change_pte, | |
261 | .invalidate_page = intel_invalidate_page, | |
262 | .invalidate_range = intel_invalidate_range, | |
263 | }; | |
264 | ||
265 | static DEFINE_MUTEX(pasid_mutex); | |
266 | ||
0204a496 | 267 | int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops) |
2f26e0a9 DW |
268 | { |
269 | struct intel_iommu *iommu = intel_svm_device_to_iommu(dev); | |
270 | struct intel_svm_dev *sdev; | |
271 | struct intel_svm *svm = NULL; | |
272 | int pasid_max; | |
273 | int ret; | |
274 | ||
275 | BUG_ON(pasid && !current->mm); | |
276 | ||
277 | if (WARN_ON(!iommu)) | |
278 | return -EINVAL; | |
279 | ||
280 | if (dev_is_pci(dev)) { | |
281 | pasid_max = pci_max_pasids(to_pci_dev(dev)); | |
282 | if (pasid_max < 0) | |
283 | return -EINVAL; | |
284 | } else | |
285 | pasid_max = 1 << 20; | |
286 | ||
287 | mutex_lock(&pasid_mutex); | |
569e4f77 | 288 | if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) { |
2f26e0a9 DW |
289 | int i; |
290 | ||
291 | idr_for_each_entry(&iommu->pasid_idr, svm, i) { | |
569e4f77 DW |
292 | if (svm->mm != current->mm || |
293 | (svm->flags & SVM_FLAG_PRIVATE_PASID)) | |
2f26e0a9 DW |
294 | continue; |
295 | ||
296 | if (svm->pasid >= pasid_max) { | |
297 | dev_warn(dev, | |
298 | "Limited PASID width. Cannot use existing PASID %d\n", | |
299 | svm->pasid); | |
300 | ret = -ENOSPC; | |
301 | goto out; | |
302 | } | |
303 | ||
304 | list_for_each_entry(sdev, &svm->devs, list) { | |
305 | if (dev == sdev->dev) { | |
0204a496 DW |
306 | if (sdev->ops != ops) { |
307 | ret = -EBUSY; | |
308 | goto out; | |
309 | } | |
2f26e0a9 DW |
310 | sdev->users++; |
311 | goto success; | |
312 | } | |
313 | } | |
314 | ||
315 | break; | |
316 | } | |
317 | } | |
318 | ||
319 | sdev = kzalloc(sizeof(*sdev), GFP_KERNEL); | |
320 | if (!sdev) { | |
321 | ret = -ENOMEM; | |
322 | goto out; | |
323 | } | |
324 | sdev->dev = dev; | |
325 | ||
326 | ret = intel_iommu_enable_pasid(iommu, sdev); | |
327 | if (ret || !pasid) { | |
328 | /* If they don't actually want to assign a PASID, this is | |
329 | * just an enabling check/preparation. */ | |
330 | kfree(sdev); | |
331 | goto out; | |
332 | } | |
333 | /* Finish the setup now we know we're keeping it */ | |
334 | sdev->users = 1; | |
0204a496 | 335 | sdev->ops = ops; |
2f26e0a9 DW |
336 | init_rcu_head(&sdev->rcu); |
337 | ||
338 | if (!svm) { | |
339 | svm = kzalloc(sizeof(*svm), GFP_KERNEL); | |
340 | if (!svm) { | |
341 | ret = -ENOMEM; | |
342 | kfree(sdev); | |
343 | goto out; | |
344 | } | |
345 | svm->iommu = iommu; | |
346 | ||
347 | if (pasid_max > 2 << ecap_pss(iommu->ecap)) | |
348 | pasid_max = 2 << ecap_pss(iommu->ecap); | |
349 | ||
350 | ret = idr_alloc(&iommu->pasid_idr, svm, 0, pasid_max - 1, | |
351 | GFP_KERNEL); | |
352 | if (ret < 0) { | |
353 | kfree(svm); | |
354 | goto out; | |
355 | } | |
356 | svm->pasid = ret; | |
357 | svm->notifier.ops = &intel_mmuops; | |
358 | svm->mm = get_task_mm(current); | |
569e4f77 | 359 | svm->flags = flags; |
2f26e0a9 DW |
360 | INIT_LIST_HEAD_RCU(&svm->devs); |
361 | ret = -ENOMEM; | |
362 | if (!svm->mm || (ret = mmu_notifier_register(&svm->notifier, svm->mm))) { | |
363 | idr_remove(&svm->iommu->pasid_idr, svm->pasid); | |
364 | kfree(svm); | |
365 | kfree(sdev); | |
366 | goto out; | |
367 | } | |
368 | iommu->pasid_table[svm->pasid].val = (u64)__pa(svm->mm->pgd) | 1; | |
369 | wmb(); | |
370 | } | |
371 | list_add_rcu(&sdev->list, &svm->devs); | |
372 | ||
373 | success: | |
374 | *pasid = svm->pasid; | |
375 | ret = 0; | |
376 | out: | |
377 | mutex_unlock(&pasid_mutex); | |
378 | return ret; | |
379 | } | |
380 | EXPORT_SYMBOL_GPL(intel_svm_bind_mm); | |
381 | ||
382 | int intel_svm_unbind_mm(struct device *dev, int pasid) | |
383 | { | |
384 | struct intel_svm_dev *sdev; | |
385 | struct intel_iommu *iommu; | |
386 | struct intel_svm *svm; | |
387 | int ret = -EINVAL; | |
388 | ||
389 | mutex_lock(&pasid_mutex); | |
390 | iommu = intel_svm_device_to_iommu(dev); | |
391 | if (!iommu || !iommu->pasid_table) | |
392 | goto out; | |
393 | ||
394 | svm = idr_find(&iommu->pasid_idr, pasid); | |
395 | if (!svm) | |
396 | goto out; | |
397 | ||
398 | list_for_each_entry(sdev, &svm->devs, list) { | |
399 | if (dev == sdev->dev) { | |
400 | ret = 0; | |
401 | sdev->users--; | |
402 | if (!sdev->users) { | |
403 | list_del_rcu(&sdev->list); | |
404 | /* Flush the PASID cache and IOTLB for this device. | |
405 | * Note that we do depend on the hardware *not* using | |
406 | * the PASID any more. Just as we depend on other | |
407 | * devices never using PASIDs that they have no right | |
408 | * to use. We have a *shared* PASID table, because it's | |
409 | * large and has to be physically contiguous. So it's | |
410 | * hard to be as defensive as we might like. */ | |
411 | intel_flush_pasid_dev(svm, sdev); | |
412 | intel_flush_svm_range_dev(svm, sdev, 0, -1, 0); | |
413 | kfree_rcu(sdev, rcu); | |
414 | ||
415 | if (list_empty(&svm->devs)) { | |
416 | mmu_notifier_unregister(&svm->notifier, svm->mm); | |
417 | ||
418 | idr_remove(&svm->iommu->pasid_idr, svm->pasid); | |
419 | mmput(svm->mm); | |
420 | /* We mandate that no page faults may be outstanding | |
421 | * for the PASID when intel_svm_unbind_mm() is called. | |
422 | * If that is not obeyed, subtle errors will happen. | |
423 | * Let's make them less subtle... */ | |
424 | memset(svm, 0x6b, sizeof(*svm)); | |
425 | kfree(svm); | |
426 | } | |
427 | } | |
428 | break; | |
429 | } | |
430 | } | |
431 | out: | |
432 | mutex_unlock(&pasid_mutex); | |
433 | ||
434 | return ret; | |
435 | } | |
436 | EXPORT_SYMBOL_GPL(intel_svm_unbind_mm); | |
a222a7f0 DW |
437 | |
438 | /* Page request queue descriptor */ | |
439 | struct page_req_dsc { | |
440 | u64 srr:1; | |
441 | u64 bof:1; | |
442 | u64 pasid_present:1; | |
443 | u64 lpig:1; | |
444 | u64 pasid:20; | |
445 | u64 bus:8; | |
446 | u64 private:23; | |
447 | u64 prg_index:9; | |
448 | u64 rd_req:1; | |
449 | u64 wr_req:1; | |
450 | u64 exe_req:1; | |
451 | u64 priv_req:1; | |
452 | u64 devfn:8; | |
453 | u64 addr:52; | |
454 | }; | |
455 | ||
456 | #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10) | |
457 | static irqreturn_t prq_event_thread(int irq, void *d) | |
458 | { | |
459 | struct intel_iommu *iommu = d; | |
460 | struct intel_svm *svm = NULL; | |
461 | int head, tail, handled = 0; | |
462 | ||
463 | tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; | |
464 | head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; | |
465 | while (head != tail) { | |
0204a496 | 466 | struct intel_svm_dev *sdev; |
a222a7f0 DW |
467 | struct vm_area_struct *vma; |
468 | struct page_req_dsc *req; | |
469 | struct qi_desc resp; | |
470 | int ret, result; | |
471 | u64 address; | |
472 | ||
473 | handled = 1; | |
474 | ||
475 | req = &iommu->prq[head / sizeof(*req)]; | |
476 | ||
477 | result = QI_RESP_FAILURE; | |
478 | address = req->addr << PAGE_SHIFT; | |
479 | if (!req->pasid_present) { | |
480 | pr_err("%s: Page request without PASID: %08llx %08llx\n", | |
481 | iommu->name, ((unsigned long long *)req)[0], | |
482 | ((unsigned long long *)req)[1]); | |
483 | goto bad_req; | |
484 | } | |
485 | ||
486 | if (!svm || svm->pasid != req->pasid) { | |
487 | rcu_read_lock(); | |
488 | svm = idr_find(&iommu->pasid_idr, req->pasid); | |
489 | /* It *can't* go away, because the driver is not permitted | |
490 | * to unbind the mm while any page faults are outstanding. | |
491 | * So we only need RCU to protect the internal idr code. */ | |
492 | rcu_read_unlock(); | |
493 | ||
494 | if (!svm) { | |
495 | pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n", | |
496 | iommu->name, req->pasid, ((unsigned long long *)req)[0], | |
497 | ((unsigned long long *)req)[1]); | |
498 | goto bad_req; | |
499 | } | |
500 | } | |
501 | ||
502 | result = QI_RESP_INVALID; | |
503 | down_read(&svm->mm->mmap_sem); | |
504 | vma = find_extend_vma(svm->mm, address); | |
505 | if (!vma || address < vma->vm_start) | |
506 | goto invalid; | |
507 | ||
508 | ret = handle_mm_fault(svm->mm, vma, address, | |
509 | req->wr_req ? FAULT_FLAG_WRITE : 0); | |
510 | if (ret & VM_FAULT_ERROR) | |
511 | goto invalid; | |
512 | ||
513 | result = QI_RESP_SUCCESS; | |
514 | invalid: | |
515 | up_read(&svm->mm->mmap_sem); | |
516 | bad_req: | |
517 | /* Accounting for major/minor faults? */ | |
0204a496 DW |
518 | rcu_read_lock(); |
519 | list_for_each_entry_rcu(sdev, &svm->devs, list) { | |
520 | if (sdev->sid == PCI_DEVID(req->bus, req->devfn)); | |
521 | break; | |
522 | } | |
523 | /* Other devices can go away, but the drivers are not permitted | |
524 | * to unbind while any page faults might be in flight. So it's | |
525 | * OK to drop the 'lock' here now we have it. */ | |
526 | rcu_read_unlock(); | |
527 | ||
528 | if (WARN_ON(&sdev->list == &svm->devs)) | |
529 | sdev = NULL; | |
530 | ||
531 | if (sdev && sdev->ops && sdev->ops->fault_cb) { | |
532 | int rwxp = (req->rd_req << 3) | (req->wr_req << 2) | | |
533 | (req->wr_req << 1) | (req->exe_req); | |
534 | sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result); | |
535 | } | |
a222a7f0 DW |
536 | |
537 | if (req->lpig) { | |
538 | /* Page Group Response */ | |
539 | resp.low = QI_PGRP_PASID(req->pasid) | | |
540 | QI_PGRP_DID((req->bus << 8) | req->devfn) | | |
541 | QI_PGRP_PASID_P(req->pasid_present) | | |
542 | QI_PGRP_RESP_TYPE; | |
543 | resp.high = QI_PGRP_IDX(req->prg_index) | | |
544 | QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result); | |
545 | ||
546 | qi_submit_sync(&resp, svm->iommu); | |
547 | } else if (req->srr) { | |
548 | /* Page Stream Response */ | |
549 | resp.low = QI_PSTRM_IDX(req->prg_index) | | |
550 | QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) | | |
551 | QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE; | |
552 | resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) | | |
553 | QI_PSTRM_RESP_CODE(result); | |
554 | ||
555 | qi_submit_sync(&resp, svm->iommu); | |
556 | } | |
557 | ||
558 | head = (head + sizeof(*req)) & PRQ_RING_MASK; | |
559 | } | |
560 | ||
561 | dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); | |
562 | ||
563 | return IRQ_RETVAL(handled); | |
564 | } |