Commit | Line | Data |
---|---|---|
5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
ad3ad3f6 | 9 | #include <asm/io_apic.h> |
17483a1f | 10 | #include <asm/smp.h> |
6d652ea1 | 11 | #include <asm/cpu.h> |
38717946 | 12 | #include <linux/intel-iommu.h> |
46f06b72 | 13 | #include <acpi/acpi.h> |
f007e99c | 14 | #include <asm/pci-direct.h> |
ad3ad3f6 | 15 | |
eef93fdb JR |
16 | struct ioapic_scope { |
17 | struct intel_iommu *iommu; | |
18 | unsigned int id; | |
19 | unsigned int bus; /* PCI bus number */ | |
20 | unsigned int devfn; /* PCI devfn number */ | |
21 | }; | |
22 | ||
23 | struct hpet_scope { | |
24 | struct intel_iommu *iommu; | |
25 | u8 id; | |
26 | unsigned int bus; | |
27 | unsigned int devfn; | |
28 | }; | |
29 | ||
30 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) | |
31 | ||
ad3ad3f6 | 32 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b SS |
33 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
34 | static int ir_ioapic_num, ir_hpet_num; | |
2ae21010 SS |
35 | int intr_remapping_enabled; |
36 | ||
03ea8155 | 37 | static int disable_intremap; |
d1423d56 | 38 | static int disable_sourceid_checking; |
41750d31 | 39 | static int no_x2apic_optout; |
d1423d56 | 40 | |
03ea8155 WH |
41 | static __init int setup_nointremap(char *str) |
42 | { | |
43 | disable_intremap = 1; | |
44 | return 0; | |
45 | } | |
46 | early_param("nointremap", setup_nointremap); | |
47 | ||
d1423d56 CW |
48 | static __init int setup_intremap(char *str) |
49 | { | |
50 | if (!str) | |
51 | return -EINVAL; | |
52 | ||
41750d31 SS |
53 | while (*str) { |
54 | if (!strncmp(str, "on", 2)) | |
55 | disable_intremap = 0; | |
56 | else if (!strncmp(str, "off", 3)) | |
57 | disable_intremap = 1; | |
58 | else if (!strncmp(str, "nosid", 5)) | |
59 | disable_sourceid_checking = 1; | |
60 | else if (!strncmp(str, "no_x2apic_optout", 16)) | |
61 | no_x2apic_optout = 1; | |
62 | ||
63 | str += strcspn(str, ","); | |
64 | while (*str == ',') | |
65 | str++; | |
66 | } | |
d1423d56 CW |
67 | |
68 | return 0; | |
69 | } | |
70 | early_param("intremap", setup_intremap); | |
71 | ||
96f8e98b | 72 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
d585d060 | 73 | |
e420dfb4 YL |
74 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
75 | { | |
dced35ae | 76 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
349d6767 | 77 | return cfg ? &cfg->irq_2_iommu : NULL; |
0b8f1efa YL |
78 | } |
79 | ||
b6fcb33a SS |
80 | int get_irte(int irq, struct irte *entry) |
81 | { | |
d585d060 | 82 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 83 | unsigned long flags; |
d585d060 | 84 | int index; |
b6fcb33a | 85 | |
d585d060 | 86 | if (!entry || !irq_iommu) |
b6fcb33a SS |
87 | return -1; |
88 | ||
96f8e98b | 89 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 90 | |
e420dfb4 YL |
91 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
92 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 93 | |
96f8e98b | 94 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
95 | return 0; |
96 | } | |
97 | ||
98 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |
99 | { | |
100 | struct ir_table *table = iommu->ir_table; | |
d585d060 | 101 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a SS |
102 | u16 index, start_index; |
103 | unsigned int mask = 0; | |
4c5502b1 | 104 | unsigned long flags; |
b6fcb33a SS |
105 | int i; |
106 | ||
d585d060 | 107 | if (!count || !irq_iommu) |
e420dfb4 | 108 | return -1; |
e420dfb4 | 109 | |
b6fcb33a SS |
110 | /* |
111 | * start the IRTE search from index 0. | |
112 | */ | |
113 | index = start_index = 0; | |
114 | ||
115 | if (count > 1) { | |
116 | count = __roundup_pow_of_two(count); | |
117 | mask = ilog2(count); | |
118 | } | |
119 | ||
120 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
121 | printk(KERN_ERR | |
122 | "Requested mask %x exceeds the max invalidation handle" | |
123 | " mask value %Lx\n", mask, | |
124 | ecap_max_handle_mask(iommu->ecap)); | |
125 | return -1; | |
126 | } | |
127 | ||
96f8e98b | 128 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a SS |
129 | do { |
130 | for (i = index; i < index + count; i++) | |
131 | if (table->base[i].present) | |
132 | break; | |
133 | /* empty index found */ | |
134 | if (i == index + count) | |
135 | break; | |
136 | ||
137 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
138 | ||
139 | if (index == start_index) { | |
96f8e98b | 140 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
141 | printk(KERN_ERR "can't allocate an IRTE\n"); |
142 | return -1; | |
143 | } | |
144 | } while (1); | |
145 | ||
146 | for (i = index; i < index + count; i++) | |
147 | table->base[i].present = 1; | |
148 | ||
e420dfb4 YL |
149 | irq_iommu->iommu = iommu; |
150 | irq_iommu->irte_index = index; | |
151 | irq_iommu->sub_handle = 0; | |
152 | irq_iommu->irte_mask = mask; | |
b6fcb33a | 153 | |
96f8e98b | 154 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
155 | |
156 | return index; | |
157 | } | |
158 | ||
704126ad | 159 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
160 | { |
161 | struct qi_desc desc; | |
162 | ||
163 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
164 | | QI_IEC_SELECTIVE; | |
165 | desc.high = 0; | |
166 | ||
704126ad | 167 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
168 | } |
169 | ||
170 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
171 | { | |
d585d060 | 172 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 173 | unsigned long flags; |
d585d060 | 174 | int index; |
b6fcb33a | 175 | |
d585d060 | 176 | if (!irq_iommu) |
b6fcb33a | 177 | return -1; |
b6fcb33a | 178 | |
96f8e98b | 179 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
180 | *sub_handle = irq_iommu->sub_handle; |
181 | index = irq_iommu->irte_index; | |
96f8e98b | 182 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
183 | return index; |
184 | } | |
185 | ||
186 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |
187 | { | |
d585d060 | 188 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 189 | unsigned long flags; |
e420dfb4 | 190 | |
d585d060 | 191 | if (!irq_iommu) |
0b8f1efa | 192 | return -1; |
d585d060 | 193 | |
96f8e98b | 194 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
0b8f1efa | 195 | |
e420dfb4 YL |
196 | irq_iommu->iommu = iommu; |
197 | irq_iommu->irte_index = index; | |
198 | irq_iommu->sub_handle = subhandle; | |
199 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 200 | |
96f8e98b | 201 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
202 | |
203 | return 0; | |
204 | } | |
205 | ||
b6fcb33a SS |
206 | int modify_irte(int irq, struct irte *irte_modified) |
207 | { | |
d585d060 | 208 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a | 209 | struct intel_iommu *iommu; |
4c5502b1 | 210 | unsigned long flags; |
d585d060 TG |
211 | struct irte *irte; |
212 | int rc, index; | |
b6fcb33a | 213 | |
d585d060 | 214 | if (!irq_iommu) |
b6fcb33a | 215 | return -1; |
d585d060 | 216 | |
96f8e98b | 217 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 218 | |
e420dfb4 | 219 | iommu = irq_iommu->iommu; |
b6fcb33a | 220 | |
e420dfb4 | 221 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
222 | irte = &iommu->ir_table->base[index]; |
223 | ||
c513b67e LT |
224 | set_64bit(&irte->low, irte_modified->low); |
225 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
226 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
227 | ||
704126ad | 228 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 229 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
230 | |
231 | return rc; | |
b6fcb33a SS |
232 | } |
233 | ||
20f3097b SS |
234 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
235 | { | |
236 | int i; | |
237 | ||
238 | for (i = 0; i < MAX_HPET_TBS; i++) | |
239 | if (ir_hpet[i].id == hpet_id) | |
240 | return ir_hpet[i].iommu; | |
241 | return NULL; | |
242 | } | |
243 | ||
89027d35 SS |
244 | struct intel_iommu *map_ioapic_to_ir(int apic) |
245 | { | |
246 | int i; | |
247 | ||
248 | for (i = 0; i < MAX_IO_APICS; i++) | |
249 | if (ir_ioapic[i].id == apic) | |
250 | return ir_ioapic[i].iommu; | |
251 | return NULL; | |
252 | } | |
253 | ||
75c46fa6 SS |
254 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
255 | { | |
256 | struct dmar_drhd_unit *drhd; | |
257 | ||
258 | drhd = dmar_find_matched_drhd_unit(dev); | |
259 | if (!drhd) | |
260 | return NULL; | |
261 | ||
262 | return drhd->iommu; | |
263 | } | |
264 | ||
c4658b4e WH |
265 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
266 | { | |
267 | struct irte *start, *entry, *end; | |
268 | struct intel_iommu *iommu; | |
269 | int index; | |
270 | ||
271 | if (irq_iommu->sub_handle) | |
272 | return 0; | |
273 | ||
274 | iommu = irq_iommu->iommu; | |
275 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
276 | ||
277 | start = iommu->ir_table->base + index; | |
278 | end = start + (1 << irq_iommu->irte_mask); | |
279 | ||
280 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
281 | set_64bit(&entry->low, 0); |
282 | set_64bit(&entry->high, 0); | |
c4658b4e WH |
283 | } |
284 | ||
285 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
286 | } | |
287 | ||
b6fcb33a SS |
288 | int free_irte(int irq) |
289 | { | |
d585d060 | 290 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 291 | unsigned long flags; |
d585d060 | 292 | int rc; |
b6fcb33a | 293 | |
d585d060 | 294 | if (!irq_iommu) |
b6fcb33a | 295 | return -1; |
d585d060 | 296 | |
96f8e98b | 297 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 298 | |
c4658b4e | 299 | rc = clear_entries(irq_iommu); |
b6fcb33a | 300 | |
e420dfb4 YL |
301 | irq_iommu->iommu = NULL; |
302 | irq_iommu->irte_index = 0; | |
303 | irq_iommu->sub_handle = 0; | |
304 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 305 | |
96f8e98b | 306 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 307 | |
704126ad | 308 | return rc; |
b6fcb33a SS |
309 | } |
310 | ||
f007e99c WH |
311 | /* |
312 | * source validation type | |
313 | */ | |
314 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 315 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
316 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
317 | ||
318 | /* | |
319 | * source-id qualifier | |
320 | */ | |
321 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
322 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
323 | * the third least significant bit | |
324 | */ | |
325 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
326 | * the second and third least significant bits | |
327 | */ | |
328 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
329 | * the least three significant bits | |
330 | */ | |
331 | ||
332 | /* | |
333 | * set SVT, SQ and SID fields of irte to verify | |
334 | * source ids of interrupt requests | |
335 | */ | |
336 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
337 | unsigned int sq, unsigned int sid) | |
338 | { | |
d1423d56 CW |
339 | if (disable_sourceid_checking) |
340 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
341 | irte->svt = svt; |
342 | irte->sq = sq; | |
343 | irte->sid = sid; | |
344 | } | |
345 | ||
346 | int set_ioapic_sid(struct irte *irte, int apic) | |
347 | { | |
348 | int i; | |
349 | u16 sid = 0; | |
350 | ||
351 | if (!irte) | |
352 | return -1; | |
353 | ||
354 | for (i = 0; i < MAX_IO_APICS; i++) { | |
355 | if (ir_ioapic[i].id == apic) { | |
356 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; | |
357 | break; | |
358 | } | |
359 | } | |
360 | ||
361 | if (sid == 0) { | |
362 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
363 | return -1; | |
364 | } | |
365 | ||
366 | set_irte_sid(irte, 1, 0, sid); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
20f3097b SS |
371 | int set_hpet_sid(struct irte *irte, u8 id) |
372 | { | |
373 | int i; | |
374 | u16 sid = 0; | |
375 | ||
376 | if (!irte) | |
377 | return -1; | |
378 | ||
379 | for (i = 0; i < MAX_HPET_TBS; i++) { | |
380 | if (ir_hpet[i].id == id) { | |
381 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; | |
382 | break; | |
383 | } | |
384 | } | |
385 | ||
386 | if (sid == 0) { | |
387 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
388 | return -1; | |
389 | } | |
390 | ||
391 | /* | |
392 | * Should really use SQ_ALL_16. Some platforms are broken. | |
393 | * While we figure out the right quirks for these broken platforms, use | |
394 | * SQ_13_IGNORE_3 for now. | |
395 | */ | |
396 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
f007e99c WH |
401 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
402 | { | |
403 | struct pci_dev *bridge; | |
404 | ||
405 | if (!irte || !dev) | |
406 | return -1; | |
407 | ||
408 | /* PCIe device or Root Complex integrated PCI device */ | |
5f4d91a1 | 409 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
f007e99c WH |
410 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
411 | (dev->bus->number << 8) | dev->devfn); | |
412 | return 0; | |
413 | } | |
414 | ||
415 | bridge = pci_find_upstream_pcie_bridge(dev); | |
416 | if (bridge) { | |
45e829ea | 417 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
f007e99c WH |
418 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
419 | (bridge->bus->number << 8) | dev->bus->number); | |
420 | else /* this is a legacy PCI bridge */ | |
421 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
422 | (bridge->bus->number << 8) | bridge->devfn); | |
423 | } | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
2ae21010 SS |
428 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
429 | { | |
430 | u64 addr; | |
c416daa9 | 431 | u32 sts; |
2ae21010 SS |
432 | unsigned long flags; |
433 | ||
434 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
435 | ||
1f5b3c3f | 436 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
437 | |
438 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
439 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
440 | ||
441 | /* Set interrupt-remapping table pointer */ | |
161fde08 | 442 | iommu->gcmd |= DMA_GCMD_SIRTP; |
c416daa9 | 443 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
444 | |
445 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
446 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 447 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
448 | |
449 | /* | |
450 | * global invalidation of interrupt entry cache before enabling | |
451 | * interrupt-remapping. | |
452 | */ | |
453 | qi_global_iec(iommu); | |
454 | ||
1f5b3c3f | 455 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
456 | |
457 | /* Enable interrupt-remapping */ | |
2ae21010 | 458 | iommu->gcmd |= DMA_GCMD_IRE; |
c416daa9 | 459 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
460 | |
461 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
462 | readl, (sts & DMA_GSTS_IRES), sts); | |
463 | ||
1f5b3c3f | 464 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
465 | } |
466 | ||
467 | ||
468 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) | |
469 | { | |
470 | struct ir_table *ir_table; | |
471 | struct page *pages; | |
472 | ||
473 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
fa4b57cc | 474 | GFP_ATOMIC); |
2ae21010 SS |
475 | |
476 | if (!iommu->ir_table) | |
477 | return -ENOMEM; | |
478 | ||
824cd75b SS |
479 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
480 | INTR_REMAP_PAGE_ORDER); | |
2ae21010 SS |
481 | |
482 | if (!pages) { | |
483 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
484 | INTR_REMAP_PAGE_ORDER); | |
485 | kfree(iommu->ir_table); | |
486 | return -ENOMEM; | |
487 | } | |
488 | ||
489 | ir_table->base = page_address(pages); | |
490 | ||
491 | iommu_set_intr_remapping(iommu, mode); | |
492 | return 0; | |
493 | } | |
494 | ||
eba67e5d SS |
495 | /* |
496 | * Disable Interrupt Remapping. | |
497 | */ | |
b24696bc | 498 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
499 | { |
500 | unsigned long flags; | |
501 | u32 sts; | |
502 | ||
503 | if (!ecap_ir_support(iommu->ecap)) | |
504 | return; | |
505 | ||
b24696bc FY |
506 | /* |
507 | * global invalidation of interrupt entry cache before disabling | |
508 | * interrupt-remapping. | |
509 | */ | |
510 | qi_global_iec(iommu); | |
511 | ||
1f5b3c3f | 512 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
513 | |
514 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
515 | if (!(sts & DMA_GSTS_IRES)) | |
516 | goto end; | |
517 | ||
518 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
519 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
520 | ||
521 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
522 | readl, !(sts & DMA_GSTS_IRES), sts); | |
523 | ||
524 | end: | |
1f5b3c3f | 525 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
526 | } |
527 | ||
41750d31 SS |
528 | static int __init dmar_x2apic_optout(void) |
529 | { | |
530 | struct acpi_table_dmar *dmar; | |
531 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
532 | if (!dmar || no_x2apic_optout) | |
533 | return 0; | |
534 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
535 | } | |
536 | ||
93758238 WH |
537 | int __init intr_remapping_supported(void) |
538 | { | |
539 | struct dmar_drhd_unit *drhd; | |
540 | ||
03ea8155 WH |
541 | if (disable_intremap) |
542 | return 0; | |
543 | ||
074835f0 YS |
544 | if (!dmar_ir_support()) |
545 | return 0; | |
546 | ||
93758238 WH |
547 | for_each_drhd_unit(drhd) { |
548 | struct intel_iommu *iommu = drhd->iommu; | |
549 | ||
550 | if (!ecap_ir_support(iommu->ecap)) | |
551 | return 0; | |
552 | } | |
553 | ||
554 | return 1; | |
555 | } | |
556 | ||
41750d31 | 557 | int __init enable_intr_remapping(void) |
2ae21010 SS |
558 | { |
559 | struct dmar_drhd_unit *drhd; | |
560 | int setup = 0; | |
41750d31 | 561 | int eim = 0; |
2ae21010 | 562 | |
e936d077 YS |
563 | if (parse_ioapics_under_ir() != 1) { |
564 | printk(KERN_INFO "Not enable interrupt remapping\n"); | |
565 | return -1; | |
566 | } | |
567 | ||
41750d31 SS |
568 | if (x2apic_supported()) { |
569 | eim = !dmar_x2apic_optout(); | |
570 | WARN(!eim, KERN_WARNING | |
571 | "Your BIOS is broken and requested that x2apic be disabled\n" | |
572 | "This will leave your machine vulnerable to irq-injection attacks\n" | |
573 | "Use 'intremap=no_x2apic_optout' to override BIOS request\n"); | |
574 | } | |
575 | ||
1531a6a6 SS |
576 | for_each_drhd_unit(drhd) { |
577 | struct intel_iommu *iommu = drhd->iommu; | |
578 | ||
34aaaa94 HW |
579 | /* |
580 | * If the queued invalidation is already initialized, | |
581 | * shouldn't disable it. | |
582 | */ | |
583 | if (iommu->qi) | |
584 | continue; | |
585 | ||
1531a6a6 SS |
586 | /* |
587 | * Clear previous faults. | |
588 | */ | |
589 | dmar_fault(-1, iommu); | |
590 | ||
591 | /* | |
592 | * Disable intr remapping and queued invalidation, if already | |
593 | * enabled prior to OS handover. | |
594 | */ | |
b24696bc | 595 | iommu_disable_intr_remapping(iommu); |
1531a6a6 SS |
596 | |
597 | dmar_disable_qi(iommu); | |
598 | } | |
599 | ||
2ae21010 SS |
600 | /* |
601 | * check for the Interrupt-remapping support | |
602 | */ | |
603 | for_each_drhd_unit(drhd) { | |
604 | struct intel_iommu *iommu = drhd->iommu; | |
605 | ||
606 | if (!ecap_ir_support(iommu->ecap)) | |
607 | continue; | |
608 | ||
609 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
610 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
611 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
612 | return -1; | |
613 | } | |
614 | } | |
615 | ||
616 | /* | |
617 | * Enable queued invalidation for all the DRHD's. | |
618 | */ | |
619 | for_each_drhd_unit(drhd) { | |
620 | int ret; | |
621 | struct intel_iommu *iommu = drhd->iommu; | |
622 | ret = dmar_enable_qi(iommu); | |
623 | ||
624 | if (ret) { | |
625 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
626 | " invalidation, ecap %Lx, ret %d\n", | |
627 | drhd->reg_base_addr, iommu->ecap, ret); | |
628 | return -1; | |
629 | } | |
630 | } | |
631 | ||
632 | /* | |
633 | * Setup Interrupt-remapping for all the DRHD's now. | |
634 | */ | |
635 | for_each_drhd_unit(drhd) { | |
636 | struct intel_iommu *iommu = drhd->iommu; | |
637 | ||
638 | if (!ecap_ir_support(iommu->ecap)) | |
639 | continue; | |
640 | ||
641 | if (setup_intr_remapping(iommu, eim)) | |
642 | goto error; | |
643 | ||
644 | setup = 1; | |
645 | } | |
646 | ||
647 | if (!setup) | |
648 | goto error; | |
649 | ||
650 | intr_remapping_enabled = 1; | |
41750d31 | 651 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 652 | |
41750d31 | 653 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
654 | |
655 | error: | |
656 | /* | |
657 | * handle error condition gracefully here! | |
658 | */ | |
659 | return -1; | |
660 | } | |
ad3ad3f6 | 661 | |
20f3097b SS |
662 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
663 | struct intel_iommu *iommu) | |
664 | { | |
665 | struct acpi_dmar_pci_path *path; | |
666 | u8 bus; | |
667 | int count; | |
668 | ||
669 | bus = scope->bus; | |
670 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
671 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
672 | / sizeof(struct acpi_dmar_pci_path); | |
673 | ||
674 | while (--count > 0) { | |
675 | /* | |
676 | * Access PCI directly due to the PCI | |
677 | * subsystem isn't initialized yet. | |
678 | */ | |
679 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
680 | PCI_SECONDARY_BUS); | |
681 | path++; | |
682 | } | |
683 | ir_hpet[ir_hpet_num].bus = bus; | |
684 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
685 | ir_hpet[ir_hpet_num].iommu = iommu; | |
686 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; | |
687 | ir_hpet_num++; | |
688 | } | |
689 | ||
f007e99c WH |
690 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
691 | struct intel_iommu *iommu) | |
692 | { | |
693 | struct acpi_dmar_pci_path *path; | |
694 | u8 bus; | |
695 | int count; | |
696 | ||
697 | bus = scope->bus; | |
698 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
699 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
700 | / sizeof(struct acpi_dmar_pci_path); | |
701 | ||
702 | while (--count > 0) { | |
703 | /* | |
704 | * Access PCI directly due to the PCI | |
705 | * subsystem isn't initialized yet. | |
706 | */ | |
707 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
708 | PCI_SECONDARY_BUS); | |
709 | path++; | |
710 | } | |
711 | ||
712 | ir_ioapic[ir_ioapic_num].bus = bus; | |
713 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
714 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
715 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
716 | ir_ioapic_num++; | |
717 | } | |
718 | ||
20f3097b SS |
719 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
720 | struct intel_iommu *iommu) | |
ad3ad3f6 SS |
721 | { |
722 | struct acpi_dmar_hardware_unit *drhd; | |
723 | struct acpi_dmar_device_scope *scope; | |
724 | void *start, *end; | |
725 | ||
726 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
727 | ||
728 | start = (void *)(drhd + 1); | |
729 | end = ((void *)drhd) + header->length; | |
730 | ||
731 | while (start < end) { | |
732 | scope = start; | |
733 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
734 | if (ir_ioapic_num == MAX_IO_APICS) { | |
735 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
736 | return -1; | |
737 | } | |
738 | ||
680a7524 YL |
739 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
740 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, | |
741 | drhd->address, iommu->seq_id); | |
ad3ad3f6 | 742 | |
f007e99c | 743 | ir_parse_one_ioapic_scope(scope, iommu); |
20f3097b SS |
744 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
745 | if (ir_hpet_num == MAX_HPET_TBS) { | |
746 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); | |
747 | return -1; | |
748 | } | |
749 | ||
750 | printk(KERN_INFO "HPET id %d under DRHD base" | |
751 | " 0x%Lx\n", scope->enumeration_id, | |
752 | drhd->address); | |
753 | ||
754 | ir_parse_one_hpet_scope(scope, iommu); | |
ad3ad3f6 SS |
755 | } |
756 | start += scope->length; | |
757 | } | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | /* | |
763 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
764 | * hardware unit. | |
765 | */ | |
766 | int __init parse_ioapics_under_ir(void) | |
767 | { | |
768 | struct dmar_drhd_unit *drhd; | |
769 | int ir_supported = 0; | |
770 | ||
771 | for_each_drhd_unit(drhd) { | |
772 | struct intel_iommu *iommu = drhd->iommu; | |
773 | ||
774 | if (ecap_ir_support(iommu->ecap)) { | |
20f3097b | 775 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
776 | return -1; |
777 | ||
778 | ir_supported = 1; | |
779 | } | |
780 | } | |
781 | ||
782 | if (ir_supported && ir_ioapic_num != nr_ioapics) { | |
783 | printk(KERN_WARNING | |
784 | "Not all IO-APIC's listed under remapping hardware\n"); | |
785 | return -1; | |
786 | } | |
787 | ||
788 | return ir_supported; | |
789 | } | |
b24696bc | 790 | |
61ed26e3 | 791 | int __init ir_dev_scope_init(void) |
c2c7286a SS |
792 | { |
793 | if (!intr_remapping_enabled) | |
794 | return 0; | |
795 | ||
796 | return dmar_dev_scope_init(); | |
797 | } | |
798 | rootfs_initcall(ir_dev_scope_init); | |
799 | ||
b24696bc FY |
800 | void disable_intr_remapping(void) |
801 | { | |
802 | struct dmar_drhd_unit *drhd; | |
803 | struct intel_iommu *iommu = NULL; | |
804 | ||
805 | /* | |
806 | * Disable Interrupt-remapping for all the DRHD's now. | |
807 | */ | |
808 | for_each_iommu(iommu, drhd) { | |
809 | if (!ecap_ir_support(iommu->ecap)) | |
810 | continue; | |
811 | ||
812 | iommu_disable_intr_remapping(iommu); | |
813 | } | |
814 | } | |
815 | ||
816 | int reenable_intr_remapping(int eim) | |
817 | { | |
818 | struct dmar_drhd_unit *drhd; | |
819 | int setup = 0; | |
820 | struct intel_iommu *iommu = NULL; | |
821 | ||
822 | for_each_iommu(iommu, drhd) | |
823 | if (iommu->qi) | |
824 | dmar_reenable_qi(iommu); | |
825 | ||
826 | /* | |
827 | * Setup Interrupt-remapping for all the DRHD's now. | |
828 | */ | |
829 | for_each_iommu(iommu, drhd) { | |
830 | if (!ecap_ir_support(iommu->ecap)) | |
831 | continue; | |
832 | ||
833 | /* Set up interrupt remapping for iommu.*/ | |
834 | iommu_set_intr_remapping(iommu, eim); | |
835 | setup = 1; | |
836 | } | |
837 | ||
838 | if (!setup) | |
839 | goto error; | |
840 | ||
841 | return 0; | |
842 | ||
843 | error: | |
844 | /* | |
845 | * handle error condition gracefully here! | |
846 | */ | |
847 | return -1; | |
848 | } | |
849 |