Commit | Line | Data |
---|---|---|
5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
8b48463f LZ |
9 | #include <linux/intel-iommu.h> |
10 | #include <linux/acpi.h> | |
b106ee63 | 11 | #include <linux/irqdomain.h> |
ad3ad3f6 | 12 | #include <asm/io_apic.h> |
17483a1f | 13 | #include <asm/smp.h> |
6d652ea1 | 14 | #include <asm/cpu.h> |
8a8f422d | 15 | #include <asm/irq_remapping.h> |
f007e99c | 16 | #include <asm/pci-direct.h> |
5e2b930b | 17 | #include <asm/msidef.h> |
ad3ad3f6 | 18 | |
8a8f422d | 19 | #include "irq_remapping.h" |
736baef4 | 20 | |
eef93fdb JR |
21 | struct ioapic_scope { |
22 | struct intel_iommu *iommu; | |
23 | unsigned int id; | |
24 | unsigned int bus; /* PCI bus number */ | |
25 | unsigned int devfn; /* PCI devfn number */ | |
26 | }; | |
27 | ||
28 | struct hpet_scope { | |
29 | struct intel_iommu *iommu; | |
30 | u8 id; | |
31 | unsigned int bus; | |
32 | unsigned int devfn; | |
33 | }; | |
34 | ||
099c5c03 JL |
35 | struct irq_2_iommu { |
36 | struct intel_iommu *iommu; | |
37 | u16 irte_index; | |
38 | u16 sub_handle; | |
39 | u8 irte_mask; | |
40 | }; | |
41 | ||
b106ee63 JL |
42 | struct intel_ir_data { |
43 | struct irq_2_iommu irq_2_iommu; | |
44 | struct irte irte_entry; | |
45 | union { | |
46 | struct msi_msg msi_entry; | |
47 | }; | |
48 | }; | |
49 | ||
eef93fdb | 50 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) |
13d09b66 | 51 | #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) |
eef93fdb | 52 | |
13d09b66 | 53 | static int __read_mostly eim_mode; |
ad3ad3f6 | 54 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b | 55 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
d1423d56 | 56 | |
3a5670e8 JL |
57 | /* |
58 | * Lock ordering: | |
59 | * ->dmar_global_lock | |
60 | * ->irq_2_ir_lock | |
61 | * ->qi->q_lock | |
62 | * ->iommu->register_lock | |
63 | * Note: | |
64 | * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called | |
65 | * in single-threaded environment with interrupt disabled, so no need to tabke | |
66 | * the dmar_global_lock. | |
67 | */ | |
96f8e98b | 68 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
b106ee63 | 69 | static struct irq_domain_ops intel_ir_domain_ops; |
d585d060 | 70 | |
694835dc JL |
71 | static int __init parse_ioapics_under_ir(void); |
72 | ||
8dedf4cf JL |
73 | static int alloc_irte(struct intel_iommu *iommu, int irq, |
74 | struct irq_2_iommu *irq_iommu, u16 count) | |
b6fcb33a SS |
75 | { |
76 | struct ir_table *table = iommu->ir_table; | |
b6fcb33a | 77 | unsigned int mask = 0; |
4c5502b1 | 78 | unsigned long flags; |
9f4c7448 | 79 | int index; |
b6fcb33a | 80 | |
d585d060 | 81 | if (!count || !irq_iommu) |
e420dfb4 | 82 | return -1; |
e420dfb4 | 83 | |
b6fcb33a SS |
84 | if (count > 1) { |
85 | count = __roundup_pow_of_two(count); | |
86 | mask = ilog2(count); | |
87 | } | |
88 | ||
89 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
90 | printk(KERN_ERR | |
91 | "Requested mask %x exceeds the max invalidation handle" | |
92 | " mask value %Lx\n", mask, | |
93 | ecap_max_handle_mask(iommu->ecap)); | |
94 | return -1; | |
95 | } | |
96 | ||
96f8e98b | 97 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
360eb3c5 JL |
98 | index = bitmap_find_free_region(table->bitmap, |
99 | INTR_REMAP_TABLE_ENTRIES, mask); | |
100 | if (index < 0) { | |
101 | pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); | |
102 | } else { | |
360eb3c5 JL |
103 | irq_iommu->iommu = iommu; |
104 | irq_iommu->irte_index = index; | |
105 | irq_iommu->sub_handle = 0; | |
106 | irq_iommu->irte_mask = mask; | |
107 | } | |
96f8e98b | 108 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
109 | |
110 | return index; | |
111 | } | |
112 | ||
704126ad | 113 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
114 | { |
115 | struct qi_desc desc; | |
116 | ||
117 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
118 | | QI_IEC_SELECTIVE; | |
119 | desc.high = 0; | |
120 | ||
704126ad | 121 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
122 | } |
123 | ||
8dedf4cf JL |
124 | static int modify_irte(struct irq_2_iommu *irq_iommu, |
125 | struct irte *irte_modified) | |
b6fcb33a | 126 | { |
b6fcb33a | 127 | struct intel_iommu *iommu; |
4c5502b1 | 128 | unsigned long flags; |
d585d060 TG |
129 | struct irte *irte; |
130 | int rc, index; | |
b6fcb33a | 131 | |
d585d060 | 132 | if (!irq_iommu) |
b6fcb33a | 133 | return -1; |
d585d060 | 134 | |
96f8e98b | 135 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 136 | |
e420dfb4 | 137 | iommu = irq_iommu->iommu; |
b6fcb33a | 138 | |
e420dfb4 | 139 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
140 | irte = &iommu->ir_table->base[index]; |
141 | ||
c513b67e LT |
142 | set_64bit(&irte->low, irte_modified->low); |
143 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
144 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
145 | ||
704126ad | 146 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 147 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
148 | |
149 | return rc; | |
b6fcb33a SS |
150 | } |
151 | ||
263b5e86 | 152 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
153 | { |
154 | int i; | |
155 | ||
156 | for (i = 0; i < MAX_HPET_TBS; i++) | |
a7a3dad9 | 157 | if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) |
20f3097b SS |
158 | return ir_hpet[i].iommu; |
159 | return NULL; | |
160 | } | |
161 | ||
263b5e86 | 162 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
163 | { |
164 | int i; | |
165 | ||
166 | for (i = 0; i < MAX_IO_APICS; i++) | |
a7a3dad9 | 167 | if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) |
89027d35 SS |
168 | return ir_ioapic[i].iommu; |
169 | return NULL; | |
170 | } | |
171 | ||
263b5e86 | 172 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
173 | { |
174 | struct dmar_drhd_unit *drhd; | |
175 | ||
176 | drhd = dmar_find_matched_drhd_unit(dev); | |
177 | if (!drhd) | |
178 | return NULL; | |
179 | ||
180 | return drhd->iommu; | |
181 | } | |
182 | ||
c4658b4e WH |
183 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
184 | { | |
185 | struct irte *start, *entry, *end; | |
186 | struct intel_iommu *iommu; | |
187 | int index; | |
188 | ||
189 | if (irq_iommu->sub_handle) | |
190 | return 0; | |
191 | ||
192 | iommu = irq_iommu->iommu; | |
8dedf4cf | 193 | index = irq_iommu->irte_index; |
c4658b4e WH |
194 | |
195 | start = iommu->ir_table->base + index; | |
196 | end = start + (1 << irq_iommu->irte_mask); | |
197 | ||
198 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
199 | set_64bit(&entry->low, 0); |
200 | set_64bit(&entry->high, 0); | |
c4658b4e | 201 | } |
360eb3c5 JL |
202 | bitmap_release_region(iommu->ir_table->bitmap, index, |
203 | irq_iommu->irte_mask); | |
c4658b4e WH |
204 | |
205 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
206 | } | |
207 | ||
f007e99c WH |
208 | /* |
209 | * source validation type | |
210 | */ | |
211 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 212 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
213 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
214 | ||
215 | /* | |
216 | * source-id qualifier | |
217 | */ | |
218 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
219 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
220 | * the third least significant bit | |
221 | */ | |
222 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
223 | * the second and third least significant bits | |
224 | */ | |
225 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
226 | * the least three significant bits | |
227 | */ | |
228 | ||
229 | /* | |
230 | * set SVT, SQ and SID fields of irte to verify | |
231 | * source ids of interrupt requests | |
232 | */ | |
233 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
234 | unsigned int sq, unsigned int sid) | |
235 | { | |
d1423d56 CW |
236 | if (disable_sourceid_checking) |
237 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
238 | irte->svt = svt; |
239 | irte->sq = sq; | |
240 | irte->sid = sid; | |
241 | } | |
242 | ||
263b5e86 | 243 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
244 | { |
245 | int i; | |
246 | u16 sid = 0; | |
247 | ||
248 | if (!irte) | |
249 | return -1; | |
250 | ||
3a5670e8 | 251 | down_read(&dmar_global_lock); |
f007e99c | 252 | for (i = 0; i < MAX_IO_APICS; i++) { |
a7a3dad9 | 253 | if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { |
f007e99c WH |
254 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
255 | break; | |
256 | } | |
257 | } | |
3a5670e8 | 258 | up_read(&dmar_global_lock); |
f007e99c WH |
259 | |
260 | if (sid == 0) { | |
261 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
262 | return -1; | |
263 | } | |
264 | ||
2fe2c602 | 265 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); |
f007e99c WH |
266 | |
267 | return 0; | |
268 | } | |
269 | ||
263b5e86 | 270 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
271 | { |
272 | int i; | |
273 | u16 sid = 0; | |
274 | ||
275 | if (!irte) | |
276 | return -1; | |
277 | ||
3a5670e8 | 278 | down_read(&dmar_global_lock); |
20f3097b | 279 | for (i = 0; i < MAX_HPET_TBS; i++) { |
a7a3dad9 | 280 | if (ir_hpet[i].iommu && ir_hpet[i].id == id) { |
20f3097b SS |
281 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
282 | break; | |
283 | } | |
284 | } | |
3a5670e8 | 285 | up_read(&dmar_global_lock); |
20f3097b SS |
286 | |
287 | if (sid == 0) { | |
288 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
289 | return -1; | |
290 | } | |
291 | ||
292 | /* | |
293 | * Should really use SQ_ALL_16. Some platforms are broken. | |
294 | * While we figure out the right quirks for these broken platforms, use | |
295 | * SQ_13_IGNORE_3 for now. | |
296 | */ | |
297 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
579305f7 AW |
302 | struct set_msi_sid_data { |
303 | struct pci_dev *pdev; | |
304 | u16 alias; | |
305 | }; | |
306 | ||
307 | static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) | |
308 | { | |
309 | struct set_msi_sid_data *data = opaque; | |
310 | ||
311 | data->pdev = pdev; | |
312 | data->alias = alias; | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
263b5e86 | 317 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c | 318 | { |
579305f7 | 319 | struct set_msi_sid_data data; |
f007e99c WH |
320 | |
321 | if (!irte || !dev) | |
322 | return -1; | |
323 | ||
579305f7 | 324 | pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); |
f007e99c | 325 | |
579305f7 AW |
326 | /* |
327 | * DMA alias provides us with a PCI device and alias. The only case | |
328 | * where the it will return an alias on a different bus than the | |
329 | * device is the case of a PCIe-to-PCI bridge, where the alias is for | |
330 | * the subordinate bus. In this case we can only verify the bus. | |
331 | * | |
332 | * If the alias device is on a different bus than our source device | |
333 | * then we have a topology based alias, use it. | |
334 | * | |
335 | * Otherwise, the alias is for a device DMA quirk and we cannot | |
336 | * assume that MSI uses the same requester ID. Therefore use the | |
337 | * original device. | |
338 | */ | |
339 | if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) | |
340 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | |
341 | PCI_DEVID(PCI_BUS_NUM(data.alias), | |
342 | dev->bus->number)); | |
343 | else if (data.pdev->bus->number != dev->bus->number) | |
344 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); | |
345 | else | |
346 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
347 | PCI_DEVID(dev->bus->number, dev->devfn)); | |
f007e99c WH |
348 | |
349 | return 0; | |
350 | } | |
351 | ||
95a02e97 | 352 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
353 | { |
354 | u64 addr; | |
c416daa9 | 355 | u32 sts; |
2ae21010 SS |
356 | unsigned long flags; |
357 | ||
358 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
359 | ||
1f5b3c3f | 360 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
361 | |
362 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
363 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
364 | ||
365 | /* Set interrupt-remapping table pointer */ | |
f63ef690 | 366 | writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
367 | |
368 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
369 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 370 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
371 | |
372 | /* | |
373 | * global invalidation of interrupt entry cache before enabling | |
374 | * interrupt-remapping. | |
375 | */ | |
376 | qi_global_iec(iommu); | |
377 | ||
1f5b3c3f | 378 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
379 | |
380 | /* Enable interrupt-remapping */ | |
2ae21010 | 381 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 382 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 383 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
384 | |
385 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
386 | readl, (sts & DMA_GSTS_IRES), sts); | |
387 | ||
af8d102f AL |
388 | /* |
389 | * With CFI clear in the Global Command register, we should be | |
390 | * protected from dangerous (i.e. compatibility) interrupts | |
391 | * regardless of x2apic status. Check just to be sure. | |
392 | */ | |
393 | if (sts & DMA_GSTS_CFIS) | |
394 | WARN(1, KERN_WARNING | |
395 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
396 | "you are vulnerable to IRQ injection.\n"); | |
397 | ||
1f5b3c3f | 398 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
399 | } |
400 | ||
a7a3dad9 | 401 | static int intel_setup_irq_remapping(struct intel_iommu *iommu) |
2ae21010 SS |
402 | { |
403 | struct ir_table *ir_table; | |
404 | struct page *pages; | |
360eb3c5 | 405 | unsigned long *bitmap; |
2ae21010 | 406 | |
a7a3dad9 JL |
407 | if (iommu->ir_table) |
408 | return 0; | |
2ae21010 | 409 | |
e3a981d6 | 410 | ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); |
a7a3dad9 | 411 | if (!ir_table) |
2ae21010 SS |
412 | return -ENOMEM; |
413 | ||
e3a981d6 | 414 | pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, |
824cd75b | 415 | INTR_REMAP_PAGE_ORDER); |
2ae21010 | 416 | if (!pages) { |
360eb3c5 JL |
417 | pr_err("IR%d: failed to allocate pages of order %d\n", |
418 | iommu->seq_id, INTR_REMAP_PAGE_ORDER); | |
a7a3dad9 | 419 | goto out_free_table; |
2ae21010 SS |
420 | } |
421 | ||
360eb3c5 JL |
422 | bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES), |
423 | sizeof(long), GFP_ATOMIC); | |
424 | if (bitmap == NULL) { | |
425 | pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); | |
a7a3dad9 | 426 | goto out_free_pages; |
360eb3c5 JL |
427 | } |
428 | ||
b106ee63 JL |
429 | iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(), |
430 | 0, INTR_REMAP_TABLE_ENTRIES, | |
431 | NULL, &intel_ir_domain_ops, | |
432 | iommu); | |
433 | if (!iommu->ir_domain) { | |
434 | pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); | |
435 | goto out_free_bitmap; | |
436 | } | |
437 | iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
438 | ||
2ae21010 | 439 | ir_table->base = page_address(pages); |
360eb3c5 | 440 | ir_table->bitmap = bitmap; |
a7a3dad9 | 441 | iommu->ir_table = ir_table; |
2ae21010 | 442 | return 0; |
a7a3dad9 | 443 | |
b106ee63 JL |
444 | out_free_bitmap: |
445 | kfree(bitmap); | |
a7a3dad9 JL |
446 | out_free_pages: |
447 | __free_pages(pages, INTR_REMAP_PAGE_ORDER); | |
448 | out_free_table: | |
449 | kfree(ir_table); | |
450 | return -ENOMEM; | |
451 | } | |
452 | ||
453 | static void intel_teardown_irq_remapping(struct intel_iommu *iommu) | |
454 | { | |
455 | if (iommu && iommu->ir_table) { | |
b106ee63 JL |
456 | if (iommu->ir_msi_domain) { |
457 | irq_domain_remove(iommu->ir_msi_domain); | |
458 | iommu->ir_msi_domain = NULL; | |
459 | } | |
460 | if (iommu->ir_domain) { | |
461 | irq_domain_remove(iommu->ir_domain); | |
462 | iommu->ir_domain = NULL; | |
463 | } | |
a7a3dad9 JL |
464 | free_pages((unsigned long)iommu->ir_table->base, |
465 | INTR_REMAP_PAGE_ORDER); | |
466 | kfree(iommu->ir_table->bitmap); | |
467 | kfree(iommu->ir_table); | |
468 | iommu->ir_table = NULL; | |
469 | } | |
2ae21010 SS |
470 | } |
471 | ||
eba67e5d SS |
472 | /* |
473 | * Disable Interrupt Remapping. | |
474 | */ | |
95a02e97 | 475 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
476 | { |
477 | unsigned long flags; | |
478 | u32 sts; | |
479 | ||
480 | if (!ecap_ir_support(iommu->ecap)) | |
481 | return; | |
482 | ||
b24696bc FY |
483 | /* |
484 | * global invalidation of interrupt entry cache before disabling | |
485 | * interrupt-remapping. | |
486 | */ | |
487 | qi_global_iec(iommu); | |
488 | ||
1f5b3c3f | 489 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
490 | |
491 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
492 | if (!(sts & DMA_GSTS_IRES)) | |
493 | goto end; | |
494 | ||
495 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
496 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
497 | ||
498 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
499 | readl, !(sts & DMA_GSTS_IRES), sts); | |
500 | ||
501 | end: | |
1f5b3c3f | 502 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
503 | } |
504 | ||
41750d31 SS |
505 | static int __init dmar_x2apic_optout(void) |
506 | { | |
507 | struct acpi_table_dmar *dmar; | |
508 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
509 | if (!dmar || no_x2apic_optout) | |
510 | return 0; | |
511 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
512 | } | |
513 | ||
11190302 TG |
514 | static void __init intel_cleanup_irq_remapping(void) |
515 | { | |
516 | struct dmar_drhd_unit *drhd; | |
517 | struct intel_iommu *iommu; | |
518 | ||
519 | for_each_iommu(iommu, drhd) { | |
520 | if (ecap_ir_support(iommu->ecap)) { | |
521 | iommu_disable_irq_remapping(iommu); | |
522 | intel_teardown_irq_remapping(iommu); | |
523 | } | |
524 | } | |
525 | ||
526 | if (x2apic_supported()) | |
527 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); | |
528 | } | |
529 | ||
530 | static int __init intel_prepare_irq_remapping(void) | |
2ae21010 SS |
531 | { |
532 | struct dmar_drhd_unit *drhd; | |
7c919779 | 533 | struct intel_iommu *iommu; |
2ae21010 | 534 | |
2966d956 JL |
535 | if (irq_remap_broken) { |
536 | printk(KERN_WARNING | |
537 | "This system BIOS has enabled interrupt remapping\n" | |
538 | "on a chipset that contains an erratum making that\n" | |
539 | "feature unstable. To maintain system stability\n" | |
540 | "interrupt remapping is being disabled. Please\n" | |
541 | "contact your BIOS vendor for an update\n"); | |
542 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
2966d956 JL |
543 | return -ENODEV; |
544 | } | |
545 | ||
11190302 | 546 | if (dmar_table_init() < 0) |
2966d956 JL |
547 | return -ENODEV; |
548 | ||
549 | if (!dmar_ir_support()) | |
550 | return -ENODEV; | |
af8d102f | 551 | |
e936d077 | 552 | if (parse_ioapics_under_ir() != 1) { |
11190302 | 553 | printk(KERN_INFO "Not enabling interrupt remapping\n"); |
af8d102f | 554 | goto error; |
e936d077 YS |
555 | } |
556 | ||
69cf1d8a | 557 | /* First make sure all IOMMUs support IRQ remapping */ |
2966d956 | 558 | for_each_iommu(iommu, drhd) |
69cf1d8a JR |
559 | if (!ecap_ir_support(iommu->ecap)) |
560 | goto error; | |
561 | ||
562 | /* Do the allocations early */ | |
563 | for_each_iommu(iommu, drhd) | |
564 | if (intel_setup_irq_remapping(iommu)) | |
11190302 | 565 | goto error; |
69cf1d8a | 566 | |
11190302 | 567 | return 0; |
2966d956 | 568 | |
11190302 TG |
569 | error: |
570 | intel_cleanup_irq_remapping(); | |
2966d956 | 571 | return -ENODEV; |
11190302 TG |
572 | } |
573 | ||
574 | static int __init intel_enable_irq_remapping(void) | |
575 | { | |
576 | struct dmar_drhd_unit *drhd; | |
577 | struct intel_iommu *iommu; | |
2f119c78 | 578 | bool setup = false; |
11190302 TG |
579 | int eim = 0; |
580 | ||
581 | if (x2apic_supported()) { | |
41750d31 | 582 | eim = !dmar_x2apic_optout(); |
af8d102f | 583 | if (!eim) |
68c1b89c | 584 | pr_info("x2apic is disabled because BIOS sets x2apic opt out bit. You can use 'intremap=no_x2apic_optout' to override the BIOS setting.\n"); |
41750d31 SS |
585 | } |
586 | ||
7c919779 | 587 | for_each_iommu(iommu, drhd) { |
34aaaa94 HW |
588 | /* |
589 | * If the queued invalidation is already initialized, | |
590 | * shouldn't disable it. | |
591 | */ | |
592 | if (iommu->qi) | |
593 | continue; | |
594 | ||
1531a6a6 SS |
595 | /* |
596 | * Clear previous faults. | |
597 | */ | |
598 | dmar_fault(-1, iommu); | |
599 | ||
600 | /* | |
601 | * Disable intr remapping and queued invalidation, if already | |
602 | * enabled prior to OS handover. | |
603 | */ | |
95a02e97 | 604 | iommu_disable_irq_remapping(iommu); |
1531a6a6 SS |
605 | |
606 | dmar_disable_qi(iommu); | |
607 | } | |
608 | ||
2ae21010 SS |
609 | /* |
610 | * check for the Interrupt-remapping support | |
611 | */ | |
69cf1d8a | 612 | for_each_iommu(iommu, drhd) |
2ae21010 SS |
613 | if (eim && !ecap_eim_support(iommu->ecap)) { |
614 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
615 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
13d09b66 | 616 | eim = 0; |
2ae21010 | 617 | } |
13d09b66 JL |
618 | eim_mode = eim; |
619 | if (eim) | |
620 | pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); | |
2ae21010 SS |
621 | |
622 | /* | |
623 | * Enable queued invalidation for all the DRHD's. | |
624 | */ | |
7c919779 JL |
625 | for_each_iommu(iommu, drhd) { |
626 | int ret = dmar_enable_qi(iommu); | |
2ae21010 SS |
627 | |
628 | if (ret) { | |
629 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
630 | " invalidation, ecap %Lx, ret %d\n", | |
631 | drhd->reg_base_addr, iommu->ecap, ret); | |
af8d102f | 632 | goto error; |
2ae21010 SS |
633 | } |
634 | } | |
635 | ||
636 | /* | |
637 | * Setup Interrupt-remapping for all the DRHD's now. | |
638 | */ | |
7c919779 | 639 | for_each_iommu(iommu, drhd) { |
a7a3dad9 | 640 | iommu_set_irq_remapping(iommu, eim); |
2f119c78 | 641 | setup = true; |
2ae21010 SS |
642 | } |
643 | ||
644 | if (!setup) | |
645 | goto error; | |
646 | ||
95a02e97 | 647 | irq_remapping_enabled = 1; |
afcc8a40 | 648 | |
41750d31 | 649 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 650 | |
41750d31 | 651 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
652 | |
653 | error: | |
11190302 | 654 | intel_cleanup_irq_remapping(); |
2ae21010 SS |
655 | return -1; |
656 | } | |
ad3ad3f6 | 657 | |
a7a3dad9 JL |
658 | static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
659 | struct intel_iommu *iommu, | |
660 | struct acpi_dmar_hardware_unit *drhd) | |
20f3097b SS |
661 | { |
662 | struct acpi_dmar_pci_path *path; | |
663 | u8 bus; | |
a7a3dad9 | 664 | int count, free = -1; |
20f3097b SS |
665 | |
666 | bus = scope->bus; | |
667 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
668 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
669 | / sizeof(struct acpi_dmar_pci_path); | |
670 | ||
671 | while (--count > 0) { | |
672 | /* | |
673 | * Access PCI directly due to the PCI | |
674 | * subsystem isn't initialized yet. | |
675 | */ | |
fa5f508f | 676 | bus = read_pci_config_byte(bus, path->device, path->function, |
20f3097b SS |
677 | PCI_SECONDARY_BUS); |
678 | path++; | |
679 | } | |
a7a3dad9 JL |
680 | |
681 | for (count = 0; count < MAX_HPET_TBS; count++) { | |
682 | if (ir_hpet[count].iommu == iommu && | |
683 | ir_hpet[count].id == scope->enumeration_id) | |
684 | return 0; | |
685 | else if (ir_hpet[count].iommu == NULL && free == -1) | |
686 | free = count; | |
687 | } | |
688 | if (free == -1) { | |
689 | pr_warn("Exceeded Max HPET blocks\n"); | |
690 | return -ENOSPC; | |
691 | } | |
692 | ||
693 | ir_hpet[free].iommu = iommu; | |
694 | ir_hpet[free].id = scope->enumeration_id; | |
695 | ir_hpet[free].bus = bus; | |
696 | ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); | |
697 | pr_info("HPET id %d under DRHD base 0x%Lx\n", | |
698 | scope->enumeration_id, drhd->address); | |
699 | ||
700 | return 0; | |
20f3097b SS |
701 | } |
702 | ||
a7a3dad9 JL |
703 | static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
704 | struct intel_iommu *iommu, | |
705 | struct acpi_dmar_hardware_unit *drhd) | |
f007e99c WH |
706 | { |
707 | struct acpi_dmar_pci_path *path; | |
708 | u8 bus; | |
a7a3dad9 | 709 | int count, free = -1; |
f007e99c WH |
710 | |
711 | bus = scope->bus; | |
712 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
713 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
714 | / sizeof(struct acpi_dmar_pci_path); | |
715 | ||
716 | while (--count > 0) { | |
717 | /* | |
718 | * Access PCI directly due to the PCI | |
719 | * subsystem isn't initialized yet. | |
720 | */ | |
fa5f508f | 721 | bus = read_pci_config_byte(bus, path->device, path->function, |
f007e99c WH |
722 | PCI_SECONDARY_BUS); |
723 | path++; | |
724 | } | |
725 | ||
a7a3dad9 JL |
726 | for (count = 0; count < MAX_IO_APICS; count++) { |
727 | if (ir_ioapic[count].iommu == iommu && | |
728 | ir_ioapic[count].id == scope->enumeration_id) | |
729 | return 0; | |
730 | else if (ir_ioapic[count].iommu == NULL && free == -1) | |
731 | free = count; | |
732 | } | |
733 | if (free == -1) { | |
734 | pr_warn("Exceeded Max IO APICS\n"); | |
735 | return -ENOSPC; | |
736 | } | |
737 | ||
738 | ir_ioapic[free].bus = bus; | |
739 | ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); | |
740 | ir_ioapic[free].iommu = iommu; | |
741 | ir_ioapic[free].id = scope->enumeration_id; | |
742 | pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", | |
743 | scope->enumeration_id, drhd->address, iommu->seq_id); | |
744 | ||
745 | return 0; | |
f007e99c WH |
746 | } |
747 | ||
20f3097b SS |
748 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
749 | struct intel_iommu *iommu) | |
ad3ad3f6 | 750 | { |
a7a3dad9 | 751 | int ret = 0; |
ad3ad3f6 SS |
752 | struct acpi_dmar_hardware_unit *drhd; |
753 | struct acpi_dmar_device_scope *scope; | |
754 | void *start, *end; | |
755 | ||
756 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
ad3ad3f6 SS |
757 | start = (void *)(drhd + 1); |
758 | end = ((void *)drhd) + header->length; | |
759 | ||
a7a3dad9 | 760 | while (start < end && ret == 0) { |
ad3ad3f6 | 761 | scope = start; |
a7a3dad9 JL |
762 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) |
763 | ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); | |
764 | else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) | |
765 | ret = ir_parse_one_hpet_scope(scope, iommu, drhd); | |
766 | start += scope->length; | |
767 | } | |
ad3ad3f6 | 768 | |
a7a3dad9 JL |
769 | return ret; |
770 | } | |
20f3097b | 771 | |
a7a3dad9 JL |
772 | static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) |
773 | { | |
774 | int i; | |
20f3097b | 775 | |
a7a3dad9 JL |
776 | for (i = 0; i < MAX_HPET_TBS; i++) |
777 | if (ir_hpet[i].iommu == iommu) | |
778 | ir_hpet[i].iommu = NULL; | |
ad3ad3f6 | 779 | |
a7a3dad9 JL |
780 | for (i = 0; i < MAX_IO_APICS; i++) |
781 | if (ir_ioapic[i].iommu == iommu) | |
782 | ir_ioapic[i].iommu = NULL; | |
ad3ad3f6 SS |
783 | } |
784 | ||
785 | /* | |
786 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
787 | * hardware unit. | |
788 | */ | |
694835dc | 789 | static int __init parse_ioapics_under_ir(void) |
ad3ad3f6 SS |
790 | { |
791 | struct dmar_drhd_unit *drhd; | |
7c919779 | 792 | struct intel_iommu *iommu; |
2f119c78 | 793 | bool ir_supported = false; |
32ab31e0 | 794 | int ioapic_idx; |
ad3ad3f6 | 795 | |
7c919779 | 796 | for_each_iommu(iommu, drhd) |
ad3ad3f6 | 797 | if (ecap_ir_support(iommu->ecap)) { |
20f3097b | 798 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
799 | return -1; |
800 | ||
2f119c78 | 801 | ir_supported = true; |
ad3ad3f6 | 802 | } |
ad3ad3f6 | 803 | |
32ab31e0 SF |
804 | if (!ir_supported) |
805 | return 0; | |
806 | ||
807 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
808 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
809 | if (!map_ioapic_to_ir(ioapic_id)) { | |
810 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
811 | "interrupt remapping will be disabled\n", | |
812 | ioapic_id); | |
813 | return -1; | |
814 | } | |
ad3ad3f6 SS |
815 | } |
816 | ||
32ab31e0 | 817 | return 1; |
ad3ad3f6 | 818 | } |
b24696bc | 819 | |
6a7885c4 | 820 | static int __init ir_dev_scope_init(void) |
c2c7286a | 821 | { |
3a5670e8 JL |
822 | int ret; |
823 | ||
95a02e97 | 824 | if (!irq_remapping_enabled) |
c2c7286a SS |
825 | return 0; |
826 | ||
3a5670e8 JL |
827 | down_write(&dmar_global_lock); |
828 | ret = dmar_dev_scope_init(); | |
829 | up_write(&dmar_global_lock); | |
830 | ||
831 | return ret; | |
c2c7286a SS |
832 | } |
833 | rootfs_initcall(ir_dev_scope_init); | |
834 | ||
95a02e97 | 835 | static void disable_irq_remapping(void) |
b24696bc FY |
836 | { |
837 | struct dmar_drhd_unit *drhd; | |
838 | struct intel_iommu *iommu = NULL; | |
839 | ||
840 | /* | |
841 | * Disable Interrupt-remapping for all the DRHD's now. | |
842 | */ | |
843 | for_each_iommu(iommu, drhd) { | |
844 | if (!ecap_ir_support(iommu->ecap)) | |
845 | continue; | |
846 | ||
95a02e97 | 847 | iommu_disable_irq_remapping(iommu); |
b24696bc FY |
848 | } |
849 | } | |
850 | ||
95a02e97 | 851 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
852 | { |
853 | struct dmar_drhd_unit *drhd; | |
2f119c78 | 854 | bool setup = false; |
b24696bc FY |
855 | struct intel_iommu *iommu = NULL; |
856 | ||
857 | for_each_iommu(iommu, drhd) | |
858 | if (iommu->qi) | |
859 | dmar_reenable_qi(iommu); | |
860 | ||
861 | /* | |
862 | * Setup Interrupt-remapping for all the DRHD's now. | |
863 | */ | |
864 | for_each_iommu(iommu, drhd) { | |
865 | if (!ecap_ir_support(iommu->ecap)) | |
866 | continue; | |
867 | ||
868 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 869 | iommu_set_irq_remapping(iommu, eim); |
2f119c78 | 870 | setup = true; |
b24696bc FY |
871 | } |
872 | ||
873 | if (!setup) | |
874 | goto error; | |
875 | ||
876 | return 0; | |
877 | ||
878 | error: | |
879 | /* | |
880 | * handle error condition gracefully here! | |
881 | */ | |
882 | return -1; | |
883 | } | |
884 | ||
3c6e5675 | 885 | static void prepare_irte(struct irte *irte, int vector, unsigned int dest) |
0c3f173a JR |
886 | { |
887 | memset(irte, 0, sizeof(*irte)); | |
888 | ||
889 | irte->present = 1; | |
890 | irte->dst_mode = apic->irq_dest_mode; | |
891 | /* | |
892 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
893 | * actual level or edge trigger will be setup in the IO-APIC | |
894 | * RTE. This will help simplify level triggered irq migration. | |
895 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
896 | * irq migration in the presence of interrupt-remapping. | |
897 | */ | |
898 | irte->trigger_mode = 0; | |
899 | irte->dlvry_mode = apic->irq_delivery_mode; | |
900 | irte->vector = vector; | |
901 | irte->dest_id = IRTE_DEST(dest); | |
902 | irte->redir_hint = 1; | |
903 | } | |
904 | ||
b106ee63 JL |
905 | static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info) |
906 | { | |
907 | struct intel_iommu *iommu = NULL; | |
908 | ||
909 | if (!info) | |
910 | return NULL; | |
911 | ||
912 | switch (info->type) { | |
913 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
914 | iommu = map_ioapic_to_ir(info->ioapic_id); | |
915 | break; | |
916 | case X86_IRQ_ALLOC_TYPE_HPET: | |
917 | iommu = map_hpet_to_ir(info->hpet_id); | |
918 | break; | |
919 | case X86_IRQ_ALLOC_TYPE_MSI: | |
920 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
921 | iommu = map_dev_to_ir(info->msi_dev); | |
922 | break; | |
923 | default: | |
924 | BUG_ON(1); | |
925 | break; | |
926 | } | |
927 | ||
928 | return iommu ? iommu->ir_domain : NULL; | |
929 | } | |
930 | ||
931 | static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info) | |
932 | { | |
933 | struct intel_iommu *iommu; | |
934 | ||
935 | if (!info) | |
936 | return NULL; | |
937 | ||
938 | switch (info->type) { | |
939 | case X86_IRQ_ALLOC_TYPE_MSI: | |
940 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
941 | iommu = map_dev_to_ir(info->msi_dev); | |
942 | if (iommu) | |
943 | return iommu->ir_msi_domain; | |
944 | break; | |
945 | default: | |
946 | break; | |
947 | } | |
948 | ||
949 | return NULL; | |
950 | } | |
951 | ||
736baef4 | 952 | struct irq_remap_ops intel_irq_remap_ops = { |
11190302 | 953 | .prepare = intel_prepare_irq_remapping, |
95a02e97 SS |
954 | .enable = intel_enable_irq_remapping, |
955 | .disable = disable_irq_remapping, | |
956 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 957 | .enable_faulting = enable_drhd_fault_handling, |
b106ee63 JL |
958 | .get_ir_irq_domain = intel_get_ir_irq_domain, |
959 | .get_irq_domain = intel_get_irq_domain, | |
960 | }; | |
961 | ||
962 | /* | |
963 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
964 | * | |
965 | * For both level and edge triggered, irq migration is a simple atomic | |
966 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
967 | * | |
968 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
969 | * updated vector information), by using a virtual vector (io-apic pin number). | |
970 | * Real vector that is used for interrupting cpu will be coming from | |
971 | * the interrupt-remapping table entry. | |
972 | * | |
973 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
974 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
975 | */ | |
976 | static int | |
977 | intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
978 | bool force) | |
979 | { | |
980 | struct intel_ir_data *ir_data = data->chip_data; | |
981 | struct irte *irte = &ir_data->irte_entry; | |
982 | struct irq_cfg *cfg = irqd_cfg(data); | |
983 | struct irq_data *parent = data->parent_data; | |
984 | int ret; | |
985 | ||
986 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
987 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
988 | return ret; | |
989 | ||
990 | /* | |
991 | * Atomically updates the IRTE with the new destination, vector | |
992 | * and flushes the interrupt entry cache. | |
993 | */ | |
994 | irte->vector = cfg->vector; | |
995 | irte->dest_id = IRTE_DEST(cfg->dest_apicid); | |
996 | modify_irte(&ir_data->irq_2_iommu, irte); | |
997 | ||
998 | /* | |
999 | * After this point, all the interrupts will start arriving | |
1000 | * at the new destination. So, time to cleanup the previous | |
1001 | * vector allocation. | |
1002 | */ | |
c6c2002b | 1003 | send_cleanup_vector(cfg); |
b106ee63 JL |
1004 | |
1005 | return IRQ_SET_MASK_OK_DONE; | |
1006 | } | |
1007 | ||
1008 | static void intel_ir_compose_msi_msg(struct irq_data *irq_data, | |
1009 | struct msi_msg *msg) | |
1010 | { | |
1011 | struct intel_ir_data *ir_data = irq_data->chip_data; | |
1012 | ||
1013 | *msg = ir_data->msi_entry; | |
1014 | } | |
1015 | ||
1016 | static struct irq_chip intel_ir_chip = { | |
1017 | .irq_ack = ir_ack_apic_edge, | |
1018 | .irq_set_affinity = intel_ir_set_affinity, | |
1019 | .irq_compose_msi_msg = intel_ir_compose_msi_msg, | |
1020 | }; | |
1021 | ||
1022 | static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, | |
1023 | struct irq_cfg *irq_cfg, | |
1024 | struct irq_alloc_info *info, | |
1025 | int index, int sub_handle) | |
1026 | { | |
1027 | struct IR_IO_APIC_route_entry *entry; | |
1028 | struct irte *irte = &data->irte_entry; | |
1029 | struct msi_msg *msg = &data->msi_entry; | |
1030 | ||
1031 | prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); | |
1032 | switch (info->type) { | |
1033 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
1034 | /* Set source-id of interrupt request */ | |
1035 | set_ioapic_sid(irte, info->ioapic_id); | |
1036 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", | |
1037 | info->ioapic_id, irte->present, irte->fpd, | |
1038 | irte->dst_mode, irte->redir_hint, | |
1039 | irte->trigger_mode, irte->dlvry_mode, | |
1040 | irte->avail, irte->vector, irte->dest_id, | |
1041 | irte->sid, irte->sq, irte->svt); | |
1042 | ||
1043 | entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry; | |
1044 | info->ioapic_entry = NULL; | |
1045 | memset(entry, 0, sizeof(*entry)); | |
1046 | entry->index2 = (index >> 15) & 0x1; | |
1047 | entry->zero = 0; | |
1048 | entry->format = 1; | |
1049 | entry->index = (index & 0x7fff); | |
1050 | /* | |
1051 | * IO-APIC RTE will be configured with virtual vector. | |
1052 | * irq handler will do the explicit EOI to the io-apic. | |
1053 | */ | |
1054 | entry->vector = info->ioapic_pin; | |
1055 | entry->mask = 0; /* enable IRQ */ | |
1056 | entry->trigger = info->ioapic_trigger; | |
1057 | entry->polarity = info->ioapic_polarity; | |
1058 | if (info->ioapic_trigger) | |
1059 | entry->mask = 1; /* Mask level triggered irqs. */ | |
1060 | break; | |
1061 | ||
1062 | case X86_IRQ_ALLOC_TYPE_HPET: | |
1063 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1064 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1065 | if (info->type == X86_IRQ_ALLOC_TYPE_HPET) | |
1066 | set_hpet_sid(irte, info->hpet_id); | |
1067 | else | |
1068 | set_msi_sid(irte, info->msi_dev); | |
1069 | ||
1070 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1071 | msg->data = sub_handle; | |
1072 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1073 | MSI_ADDR_IR_SHV | | |
1074 | MSI_ADDR_IR_INDEX1(index) | | |
1075 | MSI_ADDR_IR_INDEX2(index); | |
1076 | break; | |
1077 | ||
1078 | default: | |
1079 | BUG_ON(1); | |
1080 | break; | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | static void intel_free_irq_resources(struct irq_domain *domain, | |
1085 | unsigned int virq, unsigned int nr_irqs) | |
1086 | { | |
1087 | struct irq_data *irq_data; | |
1088 | struct intel_ir_data *data; | |
1089 | struct irq_2_iommu *irq_iommu; | |
1090 | unsigned long flags; | |
1091 | int i; | |
1092 | ||
1093 | for (i = 0; i < nr_irqs; i++) { | |
1094 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1095 | if (irq_data && irq_data->chip_data) { | |
1096 | data = irq_data->chip_data; | |
1097 | irq_iommu = &data->irq_2_iommu; | |
1098 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); | |
1099 | clear_entries(irq_iommu); | |
1100 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); | |
1101 | irq_domain_reset_irq_data(irq_data); | |
1102 | kfree(data); | |
1103 | } | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | static int intel_irq_remapping_alloc(struct irq_domain *domain, | |
1108 | unsigned int virq, unsigned int nr_irqs, | |
1109 | void *arg) | |
1110 | { | |
1111 | struct intel_iommu *iommu = domain->host_data; | |
1112 | struct irq_alloc_info *info = arg; | |
9d4c0313 | 1113 | struct intel_ir_data *data, *ird; |
b106ee63 JL |
1114 | struct irq_data *irq_data; |
1115 | struct irq_cfg *irq_cfg; | |
1116 | int i, ret, index; | |
1117 | ||
1118 | if (!info || !iommu) | |
1119 | return -EINVAL; | |
1120 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
1121 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
1122 | return -EINVAL; | |
1123 | ||
1124 | /* | |
1125 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
1126 | * to support multiple MSI interrupts. | |
1127 | */ | |
1128 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
1129 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
1130 | ||
1131 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); | |
1132 | if (ret < 0) | |
1133 | return ret; | |
1134 | ||
1135 | ret = -ENOMEM; | |
1136 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1137 | if (!data) | |
1138 | goto out_free_parent; | |
1139 | ||
1140 | down_read(&dmar_global_lock); | |
1141 | index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs); | |
1142 | up_read(&dmar_global_lock); | |
1143 | if (index < 0) { | |
1144 | pr_warn("Failed to allocate IRTE\n"); | |
1145 | kfree(data); | |
1146 | goto out_free_parent; | |
1147 | } | |
1148 | ||
1149 | for (i = 0; i < nr_irqs; i++) { | |
1150 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1151 | irq_cfg = irqd_cfg(irq_data); | |
1152 | if (!irq_data || !irq_cfg) { | |
1153 | ret = -EINVAL; | |
1154 | goto out_free_data; | |
1155 | } | |
1156 | ||
1157 | if (i > 0) { | |
9d4c0313 TG |
1158 | ird = kzalloc(sizeof(*ird), GFP_KERNEL); |
1159 | if (!ird) | |
b106ee63 | 1160 | goto out_free_data; |
9d4c0313 TG |
1161 | /* Initialize the common data */ |
1162 | ird->irq_2_iommu = data->irq_2_iommu; | |
1163 | ird->irq_2_iommu.sub_handle = i; | |
1164 | } else { | |
1165 | ird = data; | |
b106ee63 | 1166 | } |
9d4c0313 | 1167 | |
b106ee63 | 1168 | irq_data->hwirq = (index << 16) + i; |
9d4c0313 | 1169 | irq_data->chip_data = ird; |
b106ee63 | 1170 | irq_data->chip = &intel_ir_chip; |
9d4c0313 | 1171 | intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i); |
b106ee63 JL |
1172 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); |
1173 | } | |
1174 | return 0; | |
1175 | ||
1176 | out_free_data: | |
1177 | intel_free_irq_resources(domain, virq, i); | |
1178 | out_free_parent: | |
1179 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1180 | return ret; | |
1181 | } | |
1182 | ||
1183 | static void intel_irq_remapping_free(struct irq_domain *domain, | |
1184 | unsigned int virq, unsigned int nr_irqs) | |
1185 | { | |
1186 | intel_free_irq_resources(domain, virq, nr_irqs); | |
1187 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1188 | } | |
1189 | ||
1190 | static void intel_irq_remapping_activate(struct irq_domain *domain, | |
1191 | struct irq_data *irq_data) | |
1192 | { | |
1193 | struct intel_ir_data *data = irq_data->chip_data; | |
1194 | ||
1195 | modify_irte(&data->irq_2_iommu, &data->irte_entry); | |
1196 | } | |
1197 | ||
1198 | static void intel_irq_remapping_deactivate(struct irq_domain *domain, | |
1199 | struct irq_data *irq_data) | |
1200 | { | |
1201 | struct intel_ir_data *data = irq_data->chip_data; | |
1202 | struct irte entry; | |
1203 | ||
1204 | memset(&entry, 0, sizeof(entry)); | |
1205 | modify_irte(&data->irq_2_iommu, &entry); | |
1206 | } | |
1207 | ||
1208 | static struct irq_domain_ops intel_ir_domain_ops = { | |
1209 | .alloc = intel_irq_remapping_alloc, | |
1210 | .free = intel_irq_remapping_free, | |
1211 | .activate = intel_irq_remapping_activate, | |
1212 | .deactivate = intel_irq_remapping_deactivate, | |
736baef4 | 1213 | }; |
6b197249 | 1214 | |
a7a3dad9 JL |
1215 | /* |
1216 | * Support of Interrupt Remapping Unit Hotplug | |
1217 | */ | |
1218 | static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) | |
1219 | { | |
1220 | int ret; | |
1221 | int eim = x2apic_enabled(); | |
1222 | ||
1223 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
1224 | pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", | |
1225 | iommu->reg_phys, iommu->ecap); | |
1226 | return -ENODEV; | |
1227 | } | |
1228 | ||
1229 | if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { | |
1230 | pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", | |
1231 | iommu->reg_phys); | |
1232 | return -ENODEV; | |
1233 | } | |
1234 | ||
1235 | /* TODO: check all IOAPICs are covered by IOMMU */ | |
1236 | ||
1237 | /* Setup Interrupt-remapping now. */ | |
1238 | ret = intel_setup_irq_remapping(iommu); | |
1239 | if (ret) { | |
1240 | pr_err("DRHD %Lx: failed to allocate resource\n", | |
1241 | iommu->reg_phys); | |
1242 | ir_remove_ioapic_hpet_scope(iommu); | |
1243 | return ret; | |
1244 | } | |
1245 | ||
1246 | if (!iommu->qi) { | |
1247 | /* Clear previous faults. */ | |
1248 | dmar_fault(-1, iommu); | |
1249 | iommu_disable_irq_remapping(iommu); | |
1250 | dmar_disable_qi(iommu); | |
1251 | } | |
1252 | ||
1253 | /* Enable queued invalidation */ | |
1254 | ret = dmar_enable_qi(iommu); | |
1255 | if (!ret) { | |
1256 | iommu_set_irq_remapping(iommu, eim); | |
1257 | } else { | |
1258 | pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n", | |
1259 | iommu->reg_phys, iommu->ecap, ret); | |
1260 | intel_teardown_irq_remapping(iommu); | |
1261 | ir_remove_ioapic_hpet_scope(iommu); | |
1262 | } | |
1263 | ||
1264 | return ret; | |
1265 | } | |
1266 | ||
6b197249 JL |
1267 | int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
1268 | { | |
a7a3dad9 JL |
1269 | int ret = 0; |
1270 | struct intel_iommu *iommu = dmaru->iommu; | |
1271 | ||
1272 | if (!irq_remapping_enabled) | |
1273 | return 0; | |
1274 | if (iommu == NULL) | |
1275 | return -EINVAL; | |
1276 | if (!ecap_ir_support(iommu->ecap)) | |
1277 | return 0; | |
1278 | ||
1279 | if (insert) { | |
1280 | if (!iommu->ir_table) | |
1281 | ret = dmar_ir_add(dmaru, iommu); | |
1282 | } else { | |
1283 | if (iommu->ir_table) { | |
1284 | if (!bitmap_empty(iommu->ir_table->bitmap, | |
1285 | INTR_REMAP_TABLE_ENTRIES)) { | |
1286 | ret = -EBUSY; | |
1287 | } else { | |
1288 | iommu_disable_irq_remapping(iommu); | |
1289 | intel_teardown_irq_remapping(iommu); | |
1290 | ir_remove_ioapic_hpet_scope(iommu); | |
1291 | } | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | return ret; | |
6b197249 | 1296 | } |