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e1d3c0fd WD |
1 | /* |
2 | * CPU-agnostic ARM page table allocator. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | * | |
16 | * Copyright (C) 2014 ARM Limited | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt | |
22 | ||
23 | #include <linux/iommu.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/sizes.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/types.h> | |
8f6aff98 | 28 | #include <linux/dma-mapping.h> |
e1d3c0fd | 29 | |
87a91b15 RM |
30 | #include <asm/barrier.h> |
31 | ||
e1d3c0fd WD |
32 | #include "io-pgtable.h" |
33 | ||
34 | #define ARM_LPAE_MAX_ADDR_BITS 48 | |
35 | #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16 | |
36 | #define ARM_LPAE_MAX_LEVELS 4 | |
37 | ||
38 | /* Struct accessors */ | |
39 | #define io_pgtable_to_data(x) \ | |
40 | container_of((x), struct arm_lpae_io_pgtable, iop) | |
41 | ||
e1d3c0fd WD |
42 | #define io_pgtable_ops_to_data(x) \ |
43 | io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) | |
44 | ||
45 | /* | |
46 | * For consistency with the architecture, we always consider | |
47 | * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0 | |
48 | */ | |
49 | #define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels) | |
50 | ||
51 | /* | |
52 | * Calculate the right shift amount to get to the portion describing level l | |
53 | * in a virtual address mapped by the pagetable in d. | |
54 | */ | |
55 | #define ARM_LPAE_LVL_SHIFT(l,d) \ | |
56 | ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \ | |
57 | * (d)->bits_per_level) + (d)->pg_shift) | |
58 | ||
06c610e8 RM |
59 | #define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift) |
60 | ||
367bd978 | 61 | #define ARM_LPAE_PAGES_PER_PGD(d) \ |
06c610e8 | 62 | DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d)) |
e1d3c0fd WD |
63 | |
64 | /* | |
65 | * Calculate the index at level l used to map virtual address a using the | |
66 | * pagetable in d. | |
67 | */ | |
68 | #define ARM_LPAE_PGD_IDX(l,d) \ | |
69 | ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0) | |
70 | ||
71 | #define ARM_LPAE_LVL_IDX(a,l,d) \ | |
367bd978 | 72 | (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \ |
e1d3c0fd WD |
73 | ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1)) |
74 | ||
75 | /* Calculate the block/page mapping size at level l for pagetable in d. */ | |
76 | #define ARM_LPAE_BLOCK_SIZE(l,d) \ | |
77 | (1 << (ilog2(sizeof(arm_lpae_iopte)) + \ | |
78 | ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level))) | |
79 | ||
80 | /* Page table bits */ | |
81 | #define ARM_LPAE_PTE_TYPE_SHIFT 0 | |
82 | #define ARM_LPAE_PTE_TYPE_MASK 0x3 | |
83 | ||
84 | #define ARM_LPAE_PTE_TYPE_BLOCK 1 | |
85 | #define ARM_LPAE_PTE_TYPE_TABLE 3 | |
86 | #define ARM_LPAE_PTE_TYPE_PAGE 3 | |
87 | ||
c896c132 | 88 | #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) |
e1d3c0fd WD |
89 | #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) |
90 | #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) | |
91 | #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8) | |
92 | #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8) | |
93 | #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8) | |
c896c132 | 94 | #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5) |
e1d3c0fd WD |
95 | #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0) |
96 | ||
97 | #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2) | |
98 | /* Ignore the contiguous bit for block splitting */ | |
99 | #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52) | |
100 | #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \ | |
101 | ARM_LPAE_PTE_ATTR_HI_MASK) | |
102 | ||
103 | /* Stage-1 PTE */ | |
104 | #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6) | |
105 | #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6) | |
106 | #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2 | |
107 | #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11) | |
108 | ||
109 | /* Stage-2 PTE */ | |
110 | #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6) | |
111 | #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6) | |
112 | #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6) | |
113 | #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2) | |
114 | #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2) | |
115 | #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2) | |
116 | ||
117 | /* Register bits */ | |
118 | #define ARM_32_LPAE_TCR_EAE (1 << 31) | |
119 | #define ARM_64_LPAE_S2_TCR_RES1 (1 << 31) | |
120 | ||
63979b8d WD |
121 | #define ARM_LPAE_TCR_EPD1 (1 << 23) |
122 | ||
e1d3c0fd WD |
123 | #define ARM_LPAE_TCR_TG0_4K (0 << 14) |
124 | #define ARM_LPAE_TCR_TG0_64K (1 << 14) | |
125 | #define ARM_LPAE_TCR_TG0_16K (2 << 14) | |
126 | ||
127 | #define ARM_LPAE_TCR_SH0_SHIFT 12 | |
128 | #define ARM_LPAE_TCR_SH0_MASK 0x3 | |
129 | #define ARM_LPAE_TCR_SH_NS 0 | |
130 | #define ARM_LPAE_TCR_SH_OS 2 | |
131 | #define ARM_LPAE_TCR_SH_IS 3 | |
132 | ||
133 | #define ARM_LPAE_TCR_ORGN0_SHIFT 10 | |
134 | #define ARM_LPAE_TCR_IRGN0_SHIFT 8 | |
135 | #define ARM_LPAE_TCR_RGN_MASK 0x3 | |
136 | #define ARM_LPAE_TCR_RGN_NC 0 | |
137 | #define ARM_LPAE_TCR_RGN_WBWA 1 | |
138 | #define ARM_LPAE_TCR_RGN_WT 2 | |
139 | #define ARM_LPAE_TCR_RGN_WB 3 | |
140 | ||
141 | #define ARM_LPAE_TCR_SL0_SHIFT 6 | |
142 | #define ARM_LPAE_TCR_SL0_MASK 0x3 | |
143 | ||
144 | #define ARM_LPAE_TCR_T0SZ_SHIFT 0 | |
145 | #define ARM_LPAE_TCR_SZ_MASK 0xf | |
146 | ||
147 | #define ARM_LPAE_TCR_PS_SHIFT 16 | |
148 | #define ARM_LPAE_TCR_PS_MASK 0x7 | |
149 | ||
150 | #define ARM_LPAE_TCR_IPS_SHIFT 32 | |
151 | #define ARM_LPAE_TCR_IPS_MASK 0x7 | |
152 | ||
153 | #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL | |
154 | #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL | |
155 | #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL | |
156 | #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL | |
157 | #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL | |
158 | #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL | |
159 | ||
160 | #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3) | |
161 | #define ARM_LPAE_MAIR_ATTR_MASK 0xff | |
162 | #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04 | |
163 | #define ARM_LPAE_MAIR_ATTR_NC 0x44 | |
164 | #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff | |
165 | #define ARM_LPAE_MAIR_ATTR_IDX_NC 0 | |
166 | #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1 | |
167 | #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2 | |
168 | ||
169 | /* IOPTE accessors */ | |
170 | #define iopte_deref(pte,d) \ | |
171 | (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \ | |
06c610e8 | 172 | & ~(ARM_LPAE_GRANULE(d) - 1ULL))) |
e1d3c0fd WD |
173 | |
174 | #define iopte_type(pte,l) \ | |
175 | (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK) | |
176 | ||
177 | #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK) | |
178 | ||
179 | #define iopte_leaf(pte,l) \ | |
180 | (l == (ARM_LPAE_MAX_LEVELS - 1) ? \ | |
181 | (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \ | |
182 | (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK)) | |
183 | ||
184 | #define iopte_to_pfn(pte,d) \ | |
185 | (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift) | |
186 | ||
187 | #define pfn_to_iopte(pfn,d) \ | |
188 | (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) | |
189 | ||
190 | struct arm_lpae_io_pgtable { | |
191 | struct io_pgtable iop; | |
192 | ||
193 | int levels; | |
194 | size_t pgd_size; | |
195 | unsigned long pg_shift; | |
196 | unsigned long bits_per_level; | |
197 | ||
198 | void *pgd; | |
199 | }; | |
200 | ||
201 | typedef u64 arm_lpae_iopte; | |
202 | ||
fe4b991d WD |
203 | static bool selftest_running = false; |
204 | ||
ffcb6d16 | 205 | static dma_addr_t __arm_lpae_dma_addr(void *pages) |
f8d54961 | 206 | { |
ffcb6d16 | 207 | return (dma_addr_t)virt_to_phys(pages); |
f8d54961 RM |
208 | } |
209 | ||
210 | static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, | |
211 | struct io_pgtable_cfg *cfg) | |
212 | { | |
213 | struct device *dev = cfg->iommu_dev; | |
214 | dma_addr_t dma; | |
215 | void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO); | |
216 | ||
217 | if (!pages) | |
218 | return NULL; | |
219 | ||
87a91b15 | 220 | if (!selftest_running) { |
f8d54961 RM |
221 | dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE); |
222 | if (dma_mapping_error(dev, dma)) | |
223 | goto out_free; | |
224 | /* | |
225 | * We depend on the IOMMU being able to work with any physical | |
ffcb6d16 RM |
226 | * address directly, so if the DMA layer suggests otherwise by |
227 | * translating or truncating them, that bodes very badly... | |
f8d54961 | 228 | */ |
ffcb6d16 | 229 | if (dma != virt_to_phys(pages)) |
f8d54961 RM |
230 | goto out_unmap; |
231 | } | |
232 | ||
233 | return pages; | |
234 | ||
235 | out_unmap: | |
236 | dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); | |
237 | dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); | |
238 | out_free: | |
239 | free_pages_exact(pages, size); | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | static void __arm_lpae_free_pages(void *pages, size_t size, | |
244 | struct io_pgtable_cfg *cfg) | |
245 | { | |
87a91b15 | 246 | if (!selftest_running) |
ffcb6d16 | 247 | dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), |
f8d54961 RM |
248 | size, DMA_TO_DEVICE); |
249 | free_pages_exact(pages, size); | |
250 | } | |
251 | ||
252 | static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte, | |
87a91b15 | 253 | struct io_pgtable_cfg *cfg) |
f8d54961 | 254 | { |
f8d54961 RM |
255 | *ptep = pte; |
256 | ||
87a91b15 | 257 | if (!selftest_running) |
ffcb6d16 RM |
258 | dma_sync_single_for_device(cfg->iommu_dev, |
259 | __arm_lpae_dma_addr(ptep), | |
f8d54961 | 260 | sizeof(pte), DMA_TO_DEVICE); |
f8d54961 RM |
261 | } |
262 | ||
cf27ec93 WD |
263 | static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, |
264 | unsigned long iova, size_t size, int lvl, | |
265 | arm_lpae_iopte *ptep); | |
266 | ||
e1d3c0fd WD |
267 | static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, |
268 | unsigned long iova, phys_addr_t paddr, | |
269 | arm_lpae_iopte prot, int lvl, | |
270 | arm_lpae_iopte *ptep) | |
271 | { | |
272 | arm_lpae_iopte pte = prot; | |
f8d54961 | 273 | struct io_pgtable_cfg *cfg = &data->iop.cfg; |
e1d3c0fd | 274 | |
fe4b991d | 275 | if (iopte_leaf(*ptep, lvl)) { |
cf27ec93 | 276 | /* We require an unmap first */ |
fe4b991d | 277 | WARN_ON(!selftest_running); |
e1d3c0fd | 278 | return -EEXIST; |
cf27ec93 WD |
279 | } else if (iopte_type(*ptep, lvl) == ARM_LPAE_PTE_TYPE_TABLE) { |
280 | /* | |
281 | * We need to unmap and free the old table before | |
282 | * overwriting it with a block entry. | |
283 | */ | |
284 | arm_lpae_iopte *tblp; | |
285 | size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data); | |
286 | ||
287 | tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data); | |
288 | if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz)) | |
289 | return -EINVAL; | |
fe4b991d | 290 | } |
e1d3c0fd | 291 | |
f8d54961 | 292 | if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) |
c896c132 LP |
293 | pte |= ARM_LPAE_PTE_NS; |
294 | ||
e1d3c0fd WD |
295 | if (lvl == ARM_LPAE_MAX_LEVELS - 1) |
296 | pte |= ARM_LPAE_PTE_TYPE_PAGE; | |
297 | else | |
298 | pte |= ARM_LPAE_PTE_TYPE_BLOCK; | |
299 | ||
300 | pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS; | |
301 | pte |= pfn_to_iopte(paddr >> data->pg_shift, data); | |
302 | ||
87a91b15 | 303 | __arm_lpae_set_pte(ptep, pte, cfg); |
e1d3c0fd WD |
304 | return 0; |
305 | } | |
306 | ||
307 | static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, | |
308 | phys_addr_t paddr, size_t size, arm_lpae_iopte prot, | |
309 | int lvl, arm_lpae_iopte *ptep) | |
310 | { | |
311 | arm_lpae_iopte *cptep, pte; | |
e1d3c0fd | 312 | size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data); |
f8d54961 | 313 | struct io_pgtable_cfg *cfg = &data->iop.cfg; |
e1d3c0fd WD |
314 | |
315 | /* Find our entry at the current level */ | |
316 | ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); | |
317 | ||
318 | /* If we can install a leaf entry at this level, then do so */ | |
f8d54961 | 319 | if (size == block_size && (size & cfg->pgsize_bitmap)) |
e1d3c0fd WD |
320 | return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep); |
321 | ||
322 | /* We can't allocate tables at the final level */ | |
323 | if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1)) | |
324 | return -EINVAL; | |
325 | ||
326 | /* Grab a pointer to the next level */ | |
327 | pte = *ptep; | |
328 | if (!pte) { | |
06c610e8 | 329 | cptep = __arm_lpae_alloc_pages(ARM_LPAE_GRANULE(data), |
f8d54961 | 330 | GFP_ATOMIC, cfg); |
e1d3c0fd WD |
331 | if (!cptep) |
332 | return -ENOMEM; | |
333 | ||
e1d3c0fd | 334 | pte = __pa(cptep) | ARM_LPAE_PTE_TYPE_TABLE; |
f8d54961 | 335 | if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) |
c896c132 | 336 | pte |= ARM_LPAE_PTE_NSTABLE; |
87a91b15 | 337 | __arm_lpae_set_pte(ptep, pte, cfg); |
e1d3c0fd WD |
338 | } else { |
339 | cptep = iopte_deref(pte, data); | |
340 | } | |
341 | ||
342 | /* Rinse, repeat */ | |
343 | return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep); | |
344 | } | |
345 | ||
346 | static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, | |
347 | int prot) | |
348 | { | |
349 | arm_lpae_iopte pte; | |
350 | ||
351 | if (data->iop.fmt == ARM_64_LPAE_S1 || | |
352 | data->iop.fmt == ARM_32_LPAE_S1) { | |
353 | pte = ARM_LPAE_PTE_AP_UNPRIV | ARM_LPAE_PTE_nG; | |
354 | ||
355 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) | |
356 | pte |= ARM_LPAE_PTE_AP_RDONLY; | |
357 | ||
358 | if (prot & IOMMU_CACHE) | |
359 | pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE | |
360 | << ARM_LPAE_PTE_ATTRINDX_SHIFT); | |
361 | } else { | |
362 | pte = ARM_LPAE_PTE_HAP_FAULT; | |
363 | if (prot & IOMMU_READ) | |
364 | pte |= ARM_LPAE_PTE_HAP_READ; | |
365 | if (prot & IOMMU_WRITE) | |
366 | pte |= ARM_LPAE_PTE_HAP_WRITE; | |
367 | if (prot & IOMMU_CACHE) | |
368 | pte |= ARM_LPAE_PTE_MEMATTR_OIWB; | |
369 | else | |
370 | pte |= ARM_LPAE_PTE_MEMATTR_NC; | |
371 | } | |
372 | ||
373 | if (prot & IOMMU_NOEXEC) | |
374 | pte |= ARM_LPAE_PTE_XN; | |
375 | ||
376 | return pte; | |
377 | } | |
378 | ||
379 | static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, | |
380 | phys_addr_t paddr, size_t size, int iommu_prot) | |
381 | { | |
382 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
383 | arm_lpae_iopte *ptep = data->pgd; | |
87a91b15 | 384 | int ret, lvl = ARM_LPAE_START_LVL(data); |
e1d3c0fd WD |
385 | arm_lpae_iopte prot; |
386 | ||
387 | /* If no access, then nothing to do */ | |
388 | if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) | |
389 | return 0; | |
390 | ||
391 | prot = arm_lpae_prot_to_pte(data, iommu_prot); | |
87a91b15 RM |
392 | ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep); |
393 | /* | |
394 | * Synchronise all PTE updates for the new mapping before there's | |
395 | * a chance for anything to kick off a table walk for the new iova. | |
396 | */ | |
397 | wmb(); | |
398 | ||
399 | return ret; | |
e1d3c0fd WD |
400 | } |
401 | ||
402 | static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl, | |
403 | arm_lpae_iopte *ptep) | |
404 | { | |
405 | arm_lpae_iopte *start, *end; | |
406 | unsigned long table_size; | |
407 | ||
e1d3c0fd WD |
408 | if (lvl == ARM_LPAE_START_LVL(data)) |
409 | table_size = data->pgd_size; | |
410 | else | |
06c610e8 | 411 | table_size = ARM_LPAE_GRANULE(data); |
e1d3c0fd WD |
412 | |
413 | start = ptep; | |
12c2ab09 WD |
414 | |
415 | /* Only leaf entries at the last level */ | |
416 | if (lvl == ARM_LPAE_MAX_LEVELS - 1) | |
417 | end = ptep; | |
418 | else | |
419 | end = (void *)ptep + table_size; | |
e1d3c0fd WD |
420 | |
421 | while (ptep != end) { | |
422 | arm_lpae_iopte pte = *ptep++; | |
423 | ||
424 | if (!pte || iopte_leaf(pte, lvl)) | |
425 | continue; | |
426 | ||
427 | __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data)); | |
428 | } | |
429 | ||
f8d54961 | 430 | __arm_lpae_free_pages(start, table_size, &data->iop.cfg); |
e1d3c0fd WD |
431 | } |
432 | ||
433 | static void arm_lpae_free_pgtable(struct io_pgtable *iop) | |
434 | { | |
435 | struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop); | |
436 | ||
437 | __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd); | |
438 | kfree(data); | |
439 | } | |
440 | ||
441 | static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, | |
442 | unsigned long iova, size_t size, | |
443 | arm_lpae_iopte prot, int lvl, | |
444 | arm_lpae_iopte *ptep, size_t blk_size) | |
445 | { | |
446 | unsigned long blk_start, blk_end; | |
447 | phys_addr_t blk_paddr; | |
448 | arm_lpae_iopte table = 0; | |
e1d3c0fd WD |
449 | |
450 | blk_start = iova & ~(blk_size - 1); | |
451 | blk_end = blk_start + blk_size; | |
452 | blk_paddr = iopte_to_pfn(*ptep, data) << data->pg_shift; | |
453 | ||
454 | for (; blk_start < blk_end; blk_start += size, blk_paddr += size) { | |
455 | arm_lpae_iopte *tablep; | |
456 | ||
457 | /* Unmap! */ | |
458 | if (blk_start == iova) | |
459 | continue; | |
460 | ||
461 | /* __arm_lpae_map expects a pointer to the start of the table */ | |
462 | tablep = &table - ARM_LPAE_LVL_IDX(blk_start, lvl, data); | |
463 | if (__arm_lpae_map(data, blk_start, blk_paddr, size, prot, lvl, | |
464 | tablep) < 0) { | |
465 | if (table) { | |
466 | /* Free the table we allocated */ | |
467 | tablep = iopte_deref(table, data); | |
468 | __arm_lpae_free_pgtable(data, lvl + 1, tablep); | |
469 | } | |
470 | return 0; /* Bytes unmapped */ | |
471 | } | |
472 | } | |
473 | ||
507e4c9d | 474 | __arm_lpae_set_pte(ptep, table, &data->iop.cfg); |
e1d3c0fd | 475 | iova &= ~(blk_size - 1); |
507e4c9d | 476 | io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true); |
e1d3c0fd WD |
477 | return size; |
478 | } | |
479 | ||
480 | static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, | |
481 | unsigned long iova, size_t size, int lvl, | |
482 | arm_lpae_iopte *ptep) | |
483 | { | |
484 | arm_lpae_iopte pte; | |
507e4c9d | 485 | struct io_pgtable *iop = &data->iop; |
e1d3c0fd WD |
486 | size_t blk_size = ARM_LPAE_BLOCK_SIZE(lvl, data); |
487 | ||
2eb97c78 RM |
488 | /* Something went horribly wrong and we ran out of page table */ |
489 | if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) | |
490 | return 0; | |
491 | ||
e1d3c0fd WD |
492 | ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); |
493 | pte = *ptep; | |
2eb97c78 | 494 | if (WARN_ON(!pte)) |
e1d3c0fd WD |
495 | return 0; |
496 | ||
497 | /* If the size matches this level, we're in the right place */ | |
498 | if (size == blk_size) { | |
507e4c9d | 499 | __arm_lpae_set_pte(ptep, 0, &iop->cfg); |
e1d3c0fd WD |
500 | |
501 | if (!iopte_leaf(pte, lvl)) { | |
502 | /* Also flush any partial walks */ | |
507e4c9d RM |
503 | io_pgtable_tlb_add_flush(iop, iova, size, |
504 | ARM_LPAE_GRANULE(data), false); | |
505 | io_pgtable_tlb_sync(iop); | |
e1d3c0fd WD |
506 | ptep = iopte_deref(pte, data); |
507 | __arm_lpae_free_pgtable(data, lvl + 1, ptep); | |
508 | } else { | |
507e4c9d | 509 | io_pgtable_tlb_add_flush(iop, iova, size, size, true); |
e1d3c0fd WD |
510 | } |
511 | ||
512 | return size; | |
513 | } else if (iopte_leaf(pte, lvl)) { | |
514 | /* | |
515 | * Insert a table at the next level to map the old region, | |
516 | * minus the part we want to unmap | |
517 | */ | |
518 | return arm_lpae_split_blk_unmap(data, iova, size, | |
519 | iopte_prot(pte), lvl, ptep, | |
520 | blk_size); | |
521 | } | |
522 | ||
523 | /* Keep on walkin' */ | |
524 | ptep = iopte_deref(pte, data); | |
525 | return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep); | |
526 | } | |
527 | ||
528 | static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova, | |
529 | size_t size) | |
530 | { | |
531 | size_t unmapped; | |
532 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
e1d3c0fd WD |
533 | arm_lpae_iopte *ptep = data->pgd; |
534 | int lvl = ARM_LPAE_START_LVL(data); | |
535 | ||
536 | unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep); | |
537 | if (unmapped) | |
507e4c9d | 538 | io_pgtable_tlb_sync(&data->iop); |
e1d3c0fd WD |
539 | |
540 | return unmapped; | |
541 | } | |
542 | ||
543 | static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops, | |
544 | unsigned long iova) | |
545 | { | |
546 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
547 | arm_lpae_iopte pte, *ptep = data->pgd; | |
548 | int lvl = ARM_LPAE_START_LVL(data); | |
549 | ||
550 | do { | |
551 | /* Valid IOPTE pointer? */ | |
552 | if (!ptep) | |
553 | return 0; | |
554 | ||
555 | /* Grab the IOPTE we're interested in */ | |
556 | pte = *(ptep + ARM_LPAE_LVL_IDX(iova, lvl, data)); | |
557 | ||
558 | /* Valid entry? */ | |
559 | if (!pte) | |
560 | return 0; | |
561 | ||
562 | /* Leaf entry? */ | |
563 | if (iopte_leaf(pte,lvl)) | |
564 | goto found_translation; | |
565 | ||
566 | /* Take it to the next level */ | |
567 | ptep = iopte_deref(pte, data); | |
568 | } while (++lvl < ARM_LPAE_MAX_LEVELS); | |
569 | ||
570 | /* Ran out of page tables to walk */ | |
571 | return 0; | |
572 | ||
573 | found_translation: | |
06c610e8 | 574 | iova &= (ARM_LPAE_GRANULE(data) - 1); |
e1d3c0fd WD |
575 | return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova; |
576 | } | |
577 | ||
578 | static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) | |
579 | { | |
580 | unsigned long granule; | |
581 | ||
582 | /* | |
583 | * We need to restrict the supported page sizes to match the | |
584 | * translation regime for a particular granule. Aim to match | |
585 | * the CPU page size if possible, otherwise prefer smaller sizes. | |
586 | * While we're at it, restrict the block sizes to match the | |
587 | * chosen granule. | |
588 | */ | |
589 | if (cfg->pgsize_bitmap & PAGE_SIZE) | |
590 | granule = PAGE_SIZE; | |
591 | else if (cfg->pgsize_bitmap & ~PAGE_MASK) | |
592 | granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK); | |
593 | else if (cfg->pgsize_bitmap & PAGE_MASK) | |
594 | granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK); | |
595 | else | |
596 | granule = 0; | |
597 | ||
598 | switch (granule) { | |
599 | case SZ_4K: | |
600 | cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); | |
601 | break; | |
602 | case SZ_16K: | |
603 | cfg->pgsize_bitmap &= (SZ_16K | SZ_32M); | |
604 | break; | |
605 | case SZ_64K: | |
606 | cfg->pgsize_bitmap &= (SZ_64K | SZ_512M); | |
607 | break; | |
608 | default: | |
609 | cfg->pgsize_bitmap = 0; | |
610 | } | |
611 | } | |
612 | ||
613 | static struct arm_lpae_io_pgtable * | |
614 | arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) | |
615 | { | |
616 | unsigned long va_bits, pgd_bits; | |
617 | struct arm_lpae_io_pgtable *data; | |
618 | ||
619 | arm_lpae_restrict_pgsizes(cfg); | |
620 | ||
621 | if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K))) | |
622 | return NULL; | |
623 | ||
624 | if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS) | |
625 | return NULL; | |
626 | ||
627 | if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS) | |
628 | return NULL; | |
629 | ||
ffcb6d16 RM |
630 | if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) { |
631 | dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n"); | |
632 | return NULL; | |
633 | } | |
634 | ||
e1d3c0fd WD |
635 | data = kmalloc(sizeof(*data), GFP_KERNEL); |
636 | if (!data) | |
637 | return NULL; | |
638 | ||
639 | data->pg_shift = __ffs(cfg->pgsize_bitmap); | |
640 | data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte)); | |
641 | ||
642 | va_bits = cfg->ias - data->pg_shift; | |
643 | data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level); | |
644 | ||
645 | /* Calculate the actual size of our pgd (without concatenation) */ | |
646 | pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1)); | |
647 | data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte))); | |
648 | ||
649 | data->iop.ops = (struct io_pgtable_ops) { | |
650 | .map = arm_lpae_map, | |
651 | .unmap = arm_lpae_unmap, | |
652 | .iova_to_phys = arm_lpae_iova_to_phys, | |
653 | }; | |
654 | ||
655 | return data; | |
656 | } | |
657 | ||
658 | static struct io_pgtable * | |
659 | arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) | |
660 | { | |
661 | u64 reg; | |
3850db49 RM |
662 | struct arm_lpae_io_pgtable *data; |
663 | ||
664 | if (cfg->quirks & ~IO_PGTABLE_QUIRK_ARM_NS) | |
665 | return NULL; | |
e1d3c0fd | 666 | |
3850db49 | 667 | data = arm_lpae_alloc_pgtable(cfg); |
e1d3c0fd WD |
668 | if (!data) |
669 | return NULL; | |
670 | ||
671 | /* TCR */ | |
672 | reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | | |
673 | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | | |
674 | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); | |
675 | ||
06c610e8 | 676 | switch (ARM_LPAE_GRANULE(data)) { |
e1d3c0fd WD |
677 | case SZ_4K: |
678 | reg |= ARM_LPAE_TCR_TG0_4K; | |
679 | break; | |
680 | case SZ_16K: | |
681 | reg |= ARM_LPAE_TCR_TG0_16K; | |
682 | break; | |
683 | case SZ_64K: | |
684 | reg |= ARM_LPAE_TCR_TG0_64K; | |
685 | break; | |
686 | } | |
687 | ||
688 | switch (cfg->oas) { | |
689 | case 32: | |
690 | reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT); | |
691 | break; | |
692 | case 36: | |
693 | reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT); | |
694 | break; | |
695 | case 40: | |
696 | reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT); | |
697 | break; | |
698 | case 42: | |
699 | reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT); | |
700 | break; | |
701 | case 44: | |
702 | reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT); | |
703 | break; | |
704 | case 48: | |
705 | reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT); | |
706 | break; | |
707 | default: | |
708 | goto out_free_data; | |
709 | } | |
710 | ||
711 | reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT; | |
63979b8d WD |
712 | |
713 | /* Disable speculative walks through TTBR1 */ | |
714 | reg |= ARM_LPAE_TCR_EPD1; | |
e1d3c0fd WD |
715 | cfg->arm_lpae_s1_cfg.tcr = reg; |
716 | ||
717 | /* MAIRs */ | |
718 | reg = (ARM_LPAE_MAIR_ATTR_NC | |
719 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) | | |
720 | (ARM_LPAE_MAIR_ATTR_WBRWA | |
721 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) | | |
722 | (ARM_LPAE_MAIR_ATTR_DEVICE | |
723 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)); | |
724 | ||
725 | cfg->arm_lpae_s1_cfg.mair[0] = reg; | |
726 | cfg->arm_lpae_s1_cfg.mair[1] = 0; | |
727 | ||
728 | /* Looking good; allocate a pgd */ | |
f8d54961 | 729 | data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg); |
e1d3c0fd WD |
730 | if (!data->pgd) |
731 | goto out_free_data; | |
732 | ||
87a91b15 RM |
733 | /* Ensure the empty pgd is visible before any actual TTBR write */ |
734 | wmb(); | |
e1d3c0fd WD |
735 | |
736 | /* TTBRs */ | |
737 | cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); | |
738 | cfg->arm_lpae_s1_cfg.ttbr[1] = 0; | |
739 | return &data->iop; | |
740 | ||
741 | out_free_data: | |
742 | kfree(data); | |
743 | return NULL; | |
744 | } | |
745 | ||
746 | static struct io_pgtable * | |
747 | arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) | |
748 | { | |
749 | u64 reg, sl; | |
3850db49 RM |
750 | struct arm_lpae_io_pgtable *data; |
751 | ||
752 | /* The NS quirk doesn't apply at stage 2 */ | |
753 | if (cfg->quirks) | |
754 | return NULL; | |
e1d3c0fd | 755 | |
3850db49 | 756 | data = arm_lpae_alloc_pgtable(cfg); |
e1d3c0fd WD |
757 | if (!data) |
758 | return NULL; | |
759 | ||
760 | /* | |
761 | * Concatenate PGDs at level 1 if possible in order to reduce | |
762 | * the depth of the stage-2 walk. | |
763 | */ | |
764 | if (data->levels == ARM_LPAE_MAX_LEVELS) { | |
765 | unsigned long pgd_pages; | |
766 | ||
767 | pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte)); | |
768 | if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) { | |
769 | data->pgd_size = pgd_pages << data->pg_shift; | |
770 | data->levels--; | |
771 | } | |
772 | } | |
773 | ||
774 | /* VTCR */ | |
775 | reg = ARM_64_LPAE_S2_TCR_RES1 | | |
776 | (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | | |
777 | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | | |
778 | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); | |
779 | ||
780 | sl = ARM_LPAE_START_LVL(data); | |
781 | ||
06c610e8 | 782 | switch (ARM_LPAE_GRANULE(data)) { |
e1d3c0fd WD |
783 | case SZ_4K: |
784 | reg |= ARM_LPAE_TCR_TG0_4K; | |
785 | sl++; /* SL0 format is different for 4K granule size */ | |
786 | break; | |
787 | case SZ_16K: | |
788 | reg |= ARM_LPAE_TCR_TG0_16K; | |
789 | break; | |
790 | case SZ_64K: | |
791 | reg |= ARM_LPAE_TCR_TG0_64K; | |
792 | break; | |
793 | } | |
794 | ||
795 | switch (cfg->oas) { | |
796 | case 32: | |
797 | reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT); | |
798 | break; | |
799 | case 36: | |
800 | reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT); | |
801 | break; | |
802 | case 40: | |
803 | reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT); | |
804 | break; | |
805 | case 42: | |
806 | reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT); | |
807 | break; | |
808 | case 44: | |
809 | reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT); | |
810 | break; | |
811 | case 48: | |
812 | reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT); | |
813 | break; | |
814 | default: | |
815 | goto out_free_data; | |
816 | } | |
817 | ||
818 | reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT; | |
819 | reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT; | |
820 | cfg->arm_lpae_s2_cfg.vtcr = reg; | |
821 | ||
822 | /* Allocate pgd pages */ | |
f8d54961 | 823 | data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg); |
e1d3c0fd WD |
824 | if (!data->pgd) |
825 | goto out_free_data; | |
826 | ||
87a91b15 RM |
827 | /* Ensure the empty pgd is visible before any actual TTBR write */ |
828 | wmb(); | |
e1d3c0fd WD |
829 | |
830 | /* VTTBR */ | |
831 | cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd); | |
832 | return &data->iop; | |
833 | ||
834 | out_free_data: | |
835 | kfree(data); | |
836 | return NULL; | |
837 | } | |
838 | ||
839 | static struct io_pgtable * | |
840 | arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) | |
841 | { | |
842 | struct io_pgtable *iop; | |
843 | ||
844 | if (cfg->ias > 32 || cfg->oas > 40) | |
845 | return NULL; | |
846 | ||
847 | cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); | |
848 | iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie); | |
849 | if (iop) { | |
850 | cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE; | |
851 | cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff; | |
852 | } | |
853 | ||
854 | return iop; | |
855 | } | |
856 | ||
857 | static struct io_pgtable * | |
858 | arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) | |
859 | { | |
860 | struct io_pgtable *iop; | |
861 | ||
862 | if (cfg->ias > 40 || cfg->oas > 40) | |
863 | return NULL; | |
864 | ||
865 | cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); | |
866 | iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie); | |
867 | if (iop) | |
868 | cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff; | |
869 | ||
870 | return iop; | |
871 | } | |
872 | ||
873 | struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = { | |
874 | .alloc = arm_64_lpae_alloc_pgtable_s1, | |
875 | .free = arm_lpae_free_pgtable, | |
876 | }; | |
877 | ||
878 | struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = { | |
879 | .alloc = arm_64_lpae_alloc_pgtable_s2, | |
880 | .free = arm_lpae_free_pgtable, | |
881 | }; | |
882 | ||
883 | struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = { | |
884 | .alloc = arm_32_lpae_alloc_pgtable_s1, | |
885 | .free = arm_lpae_free_pgtable, | |
886 | }; | |
887 | ||
888 | struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = { | |
889 | .alloc = arm_32_lpae_alloc_pgtable_s2, | |
890 | .free = arm_lpae_free_pgtable, | |
891 | }; | |
fe4b991d WD |
892 | |
893 | #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST | |
894 | ||
895 | static struct io_pgtable_cfg *cfg_cookie; | |
896 | ||
897 | static void dummy_tlb_flush_all(void *cookie) | |
898 | { | |
899 | WARN_ON(cookie != cfg_cookie); | |
900 | } | |
901 | ||
06c610e8 RM |
902 | static void dummy_tlb_add_flush(unsigned long iova, size_t size, |
903 | size_t granule, bool leaf, void *cookie) | |
fe4b991d WD |
904 | { |
905 | WARN_ON(cookie != cfg_cookie); | |
906 | WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); | |
907 | } | |
908 | ||
909 | static void dummy_tlb_sync(void *cookie) | |
910 | { | |
911 | WARN_ON(cookie != cfg_cookie); | |
912 | } | |
913 | ||
fe4b991d WD |
914 | static struct iommu_gather_ops dummy_tlb_ops __initdata = { |
915 | .tlb_flush_all = dummy_tlb_flush_all, | |
916 | .tlb_add_flush = dummy_tlb_add_flush, | |
917 | .tlb_sync = dummy_tlb_sync, | |
fe4b991d WD |
918 | }; |
919 | ||
920 | static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops) | |
921 | { | |
922 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
923 | struct io_pgtable_cfg *cfg = &data->iop.cfg; | |
924 | ||
925 | pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n", | |
926 | cfg->pgsize_bitmap, cfg->ias); | |
927 | pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n", | |
928 | data->levels, data->pgd_size, data->pg_shift, | |
929 | data->bits_per_level, data->pgd); | |
930 | } | |
931 | ||
932 | #define __FAIL(ops, i) ({ \ | |
933 | WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \ | |
934 | arm_lpae_dump_ops(ops); \ | |
935 | selftest_running = false; \ | |
936 | -EFAULT; \ | |
937 | }) | |
938 | ||
939 | static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg) | |
940 | { | |
941 | static const enum io_pgtable_fmt fmts[] = { | |
942 | ARM_64_LPAE_S1, | |
943 | ARM_64_LPAE_S2, | |
944 | }; | |
945 | ||
946 | int i, j; | |
947 | unsigned long iova; | |
948 | size_t size; | |
949 | struct io_pgtable_ops *ops; | |
950 | ||
951 | selftest_running = true; | |
952 | ||
953 | for (i = 0; i < ARRAY_SIZE(fmts); ++i) { | |
954 | cfg_cookie = cfg; | |
955 | ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg); | |
956 | if (!ops) { | |
957 | pr_err("selftest: failed to allocate io pgtable ops\n"); | |
958 | return -ENOMEM; | |
959 | } | |
960 | ||
961 | /* | |
962 | * Initial sanity checks. | |
963 | * Empty page tables shouldn't provide any translations. | |
964 | */ | |
965 | if (ops->iova_to_phys(ops, 42)) | |
966 | return __FAIL(ops, i); | |
967 | ||
968 | if (ops->iova_to_phys(ops, SZ_1G + 42)) | |
969 | return __FAIL(ops, i); | |
970 | ||
971 | if (ops->iova_to_phys(ops, SZ_2G + 42)) | |
972 | return __FAIL(ops, i); | |
973 | ||
974 | /* | |
975 | * Distinct mappings of different granule sizes. | |
976 | */ | |
977 | iova = 0; | |
978 | j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG); | |
979 | while (j != BITS_PER_LONG) { | |
980 | size = 1UL << j; | |
981 | ||
982 | if (ops->map(ops, iova, iova, size, IOMMU_READ | | |
983 | IOMMU_WRITE | | |
984 | IOMMU_NOEXEC | | |
985 | IOMMU_CACHE)) | |
986 | return __FAIL(ops, i); | |
987 | ||
988 | /* Overlapping mappings */ | |
989 | if (!ops->map(ops, iova, iova + size, size, | |
990 | IOMMU_READ | IOMMU_NOEXEC)) | |
991 | return __FAIL(ops, i); | |
992 | ||
993 | if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) | |
994 | return __FAIL(ops, i); | |
995 | ||
996 | iova += SZ_1G; | |
997 | j++; | |
998 | j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j); | |
999 | } | |
1000 | ||
1001 | /* Partial unmap */ | |
1002 | size = 1UL << __ffs(cfg->pgsize_bitmap); | |
1003 | if (ops->unmap(ops, SZ_1G + size, size) != size) | |
1004 | return __FAIL(ops, i); | |
1005 | ||
1006 | /* Remap of partial unmap */ | |
1007 | if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ)) | |
1008 | return __FAIL(ops, i); | |
1009 | ||
1010 | if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42)) | |
1011 | return __FAIL(ops, i); | |
1012 | ||
1013 | /* Full unmap */ | |
1014 | iova = 0; | |
1015 | j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG); | |
1016 | while (j != BITS_PER_LONG) { | |
1017 | size = 1UL << j; | |
1018 | ||
1019 | if (ops->unmap(ops, iova, size) != size) | |
1020 | return __FAIL(ops, i); | |
1021 | ||
1022 | if (ops->iova_to_phys(ops, iova + 42)) | |
1023 | return __FAIL(ops, i); | |
1024 | ||
1025 | /* Remap full block */ | |
1026 | if (ops->map(ops, iova, iova, size, IOMMU_WRITE)) | |
1027 | return __FAIL(ops, i); | |
1028 | ||
1029 | if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) | |
1030 | return __FAIL(ops, i); | |
1031 | ||
1032 | iova += SZ_1G; | |
1033 | j++; | |
1034 | j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j); | |
1035 | } | |
1036 | ||
1037 | free_io_pgtable_ops(ops); | |
1038 | } | |
1039 | ||
1040 | selftest_running = false; | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static int __init arm_lpae_do_selftests(void) | |
1045 | { | |
1046 | static const unsigned long pgsize[] = { | |
1047 | SZ_4K | SZ_2M | SZ_1G, | |
1048 | SZ_16K | SZ_32M, | |
1049 | SZ_64K | SZ_512M, | |
1050 | }; | |
1051 | ||
1052 | static const unsigned int ias[] = { | |
1053 | 32, 36, 40, 42, 44, 48, | |
1054 | }; | |
1055 | ||
1056 | int i, j, pass = 0, fail = 0; | |
1057 | struct io_pgtable_cfg cfg = { | |
1058 | .tlb = &dummy_tlb_ops, | |
1059 | .oas = 48, | |
1060 | }; | |
1061 | ||
1062 | for (i = 0; i < ARRAY_SIZE(pgsize); ++i) { | |
1063 | for (j = 0; j < ARRAY_SIZE(ias); ++j) { | |
1064 | cfg.pgsize_bitmap = pgsize[i]; | |
1065 | cfg.ias = ias[j]; | |
1066 | pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n", | |
1067 | pgsize[i], ias[j]); | |
1068 | if (arm_lpae_run_tests(&cfg)) | |
1069 | fail++; | |
1070 | else | |
1071 | pass++; | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail); | |
1076 | return fail ? -EFAULT : 0; | |
1077 | } | |
1078 | subsys_initcall(arm_lpae_do_selftests); | |
1079 | #endif |