Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
f626b52d | 21 | #include <linux/iommu.h> |
c8d35c84 | 22 | #include <linux/omap-iommu.h> |
f626b52d OBC |
23 | #include <linux/mutex.h> |
24 | #include <linux/spinlock.h> | |
ed1c7de2 | 25 | #include <linux/io.h> |
a9dcad5e HD |
26 | |
27 | #include <asm/cacheflush.h> | |
28 | ||
2ab7c848 | 29 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 30 | |
2f7702af | 31 | #include "omap-iopgtable.h" |
ed1c7de2 | 32 | #include "omap-iommu.h" |
a9dcad5e | 33 | |
37c2836c HD |
34 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
35 | for (__i = 0; \ | |
36 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
37 | __i++) | |
38 | ||
66bc8cf3 OBC |
39 | /* bitmap of the page sizes currently supported */ |
40 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
41 | ||
f626b52d OBC |
42 | /** |
43 | * struct omap_iommu_domain - omap iommu domain | |
44 | * @pgtable: the page table | |
45 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
46 | * iommu device can be attached for now. | |
803b5277 | 47 | * @dev: Device using this domain. |
f626b52d OBC |
48 | * @lock: domain lock, should be taken when attaching/detaching |
49 | */ | |
50 | struct omap_iommu_domain { | |
51 | u32 *pgtable; | |
6c32df43 | 52 | struct omap_iommu *iommu_dev; |
803b5277 | 53 | struct device *dev; |
f626b52d OBC |
54 | spinlock_t lock; |
55 | }; | |
56 | ||
7bd9e25f IY |
57 | #define MMU_LOCK_BASE_SHIFT 10 |
58 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
59 | #define MMU_LOCK_BASE(x) \ | |
60 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
61 | ||
62 | #define MMU_LOCK_VICT_SHIFT 4 | |
63 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
64 | #define MMU_LOCK_VICT(x) \ | |
65 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
66 | ||
67 | struct iotlb_lock { | |
68 | short base; | |
69 | short vict; | |
70 | }; | |
71 | ||
a9dcad5e HD |
72 | /* accommodate the difference between omap1 and omap2/3 */ |
73 | static const struct iommu_functions *arch_iommu; | |
74 | ||
75 | static struct platform_driver omap_iommu_driver; | |
76 | static struct kmem_cache *iopte_cachep; | |
77 | ||
78 | /** | |
6c32df43 | 79 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
80 | * @ops: a pointer to architecture specific iommu functions |
81 | * | |
82 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
83 | * omap series. This interface installs such an iommu algorighm. | |
84 | **/ | |
6c32df43 | 85 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
86 | { |
87 | if (arch_iommu) | |
88 | return -EBUSY; | |
89 | ||
90 | arch_iommu = ops; | |
91 | return 0; | |
92 | } | |
6c32df43 | 93 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
94 | |
95 | /** | |
6c32df43 | 96 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
97 | * @ops: a pointer to architecture specific iommu functions |
98 | * | |
99 | * This interface uninstalls the iommu algorighm installed previously. | |
100 | **/ | |
6c32df43 | 101 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
102 | { |
103 | if (arch_iommu != ops) | |
104 | pr_err("%s: not your arch\n", __func__); | |
105 | ||
106 | arch_iommu = NULL; | |
107 | } | |
6c32df43 | 108 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
109 | |
110 | /** | |
6c32df43 | 111 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 112 | * @dev: client device |
a9dcad5e | 113 | **/ |
fabdbca8 | 114 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 115 | { |
fabdbca8 OBC |
116 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
117 | ||
a9dcad5e HD |
118 | arch_iommu->save_ctx(obj); |
119 | } | |
6c32df43 | 120 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
121 | |
122 | /** | |
6c32df43 | 123 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 124 | * @dev: client device |
a9dcad5e | 125 | **/ |
fabdbca8 | 126 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 127 | { |
fabdbca8 OBC |
128 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
129 | ||
a9dcad5e HD |
130 | arch_iommu->restore_ctx(obj); |
131 | } | |
6c32df43 | 132 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
133 | |
134 | /** | |
6c32df43 | 135 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 136 | **/ |
6c32df43 | 137 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
138 | { |
139 | return arch_iommu->version; | |
140 | } | |
6c32df43 | 141 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 142 | |
6c32df43 | 143 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
144 | { |
145 | int err; | |
146 | ||
147 | if (!obj) | |
148 | return -EINVAL; | |
149 | ||
ef4815ab MH |
150 | if (!arch_iommu) |
151 | return -ENODEV; | |
152 | ||
a9dcad5e HD |
153 | clk_enable(obj->clk); |
154 | ||
155 | err = arch_iommu->enable(obj); | |
156 | ||
a9dcad5e HD |
157 | return err; |
158 | } | |
159 | ||
6c32df43 | 160 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e HD |
161 | { |
162 | if (!obj) | |
163 | return; | |
164 | ||
a9dcad5e HD |
165 | arch_iommu->disable(obj); |
166 | ||
167 | clk_disable(obj->clk); | |
168 | } | |
169 | ||
170 | /* | |
171 | * TLB operations | |
172 | */ | |
6c32df43 | 173 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
174 | { |
175 | BUG_ON(!cr || !e); | |
176 | ||
177 | arch_iommu->cr_to_e(cr, e); | |
178 | } | |
6c32df43 | 179 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
180 | |
181 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
182 | { | |
183 | if (!cr) | |
184 | return -EINVAL; | |
185 | ||
186 | return arch_iommu->cr_valid(cr); | |
187 | } | |
188 | ||
6c32df43 | 189 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
190 | struct iotlb_entry *e) |
191 | { | |
192 | if (!e) | |
193 | return NULL; | |
194 | ||
195 | return arch_iommu->alloc_cr(obj, e); | |
196 | } | |
197 | ||
e1f23813 | 198 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
199 | { |
200 | return arch_iommu->cr_to_virt(cr); | |
201 | } | |
a9dcad5e HD |
202 | |
203 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
204 | { | |
205 | return arch_iommu->get_pte_attr(e); | |
206 | } | |
207 | ||
6c32df43 | 208 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
209 | { |
210 | return arch_iommu->fault_isr(obj, da); | |
211 | } | |
212 | ||
6c32df43 | 213 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
214 | { |
215 | u32 val; | |
216 | ||
217 | val = iommu_read_reg(obj, MMU_LOCK); | |
218 | ||
219 | l->base = MMU_LOCK_BASE(val); | |
220 | l->vict = MMU_LOCK_VICT(val); | |
221 | ||
a9dcad5e HD |
222 | } |
223 | ||
6c32df43 | 224 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
225 | { |
226 | u32 val; | |
227 | ||
a9dcad5e HD |
228 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
229 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
230 | ||
231 | iommu_write_reg(obj, val, MMU_LOCK); | |
232 | } | |
233 | ||
6c32df43 | 234 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
235 | { |
236 | arch_iommu->tlb_read_cr(obj, cr); | |
237 | } | |
238 | ||
6c32df43 | 239 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
240 | { |
241 | arch_iommu->tlb_load_cr(obj, cr); | |
242 | ||
243 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
244 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
245 | } | |
246 | ||
247 | /** | |
248 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
249 | * @obj: target iommu | |
250 | * @cr: contents of cam and ram register | |
251 | * @buf: output buffer | |
252 | **/ | |
6c32df43 | 253 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
254 | char *buf) |
255 | { | |
256 | BUG_ON(!cr || !buf); | |
257 | ||
258 | return arch_iommu->dump_cr(obj, cr, buf); | |
259 | } | |
260 | ||
37c2836c | 261 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 262 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
263 | { |
264 | struct cr_regs cr; | |
265 | struct iotlb_lock l; | |
266 | ||
267 | iotlb_lock_get(obj, &l); | |
268 | l.vict = n; | |
269 | iotlb_lock_set(obj, &l); | |
270 | iotlb_read_cr(obj, &cr); | |
271 | ||
272 | return cr; | |
273 | } | |
274 | ||
a9dcad5e HD |
275 | /** |
276 | * load_iotlb_entry - Set an iommu tlb entry | |
277 | * @obj: target iommu | |
278 | * @e: an iommu tlb entry info | |
279 | **/ | |
5da14a47 | 280 | #ifdef PREFETCH_IOTLB |
6c32df43 | 281 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 282 | { |
a9dcad5e HD |
283 | int err = 0; |
284 | struct iotlb_lock l; | |
285 | struct cr_regs *cr; | |
286 | ||
287 | if (!obj || !obj->nr_tlb_entries || !e) | |
288 | return -EINVAL; | |
289 | ||
290 | clk_enable(obj->clk); | |
291 | ||
be6d8026 KH |
292 | iotlb_lock_get(obj, &l); |
293 | if (l.base == obj->nr_tlb_entries) { | |
294 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
295 | err = -EBUSY; |
296 | goto out; | |
297 | } | |
be6d8026 | 298 | if (!e->prsvd) { |
37c2836c HD |
299 | int i; |
300 | struct cr_regs tmp; | |
be6d8026 | 301 | |
37c2836c | 302 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
303 | if (!iotlb_cr_valid(&tmp)) |
304 | break; | |
37c2836c | 305 | |
be6d8026 KH |
306 | if (i == obj->nr_tlb_entries) { |
307 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
308 | err = -EBUSY; | |
309 | goto out; | |
310 | } | |
37c2836c HD |
311 | |
312 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
313 | } else { |
314 | l.vict = l.base; | |
315 | iotlb_lock_set(obj, &l); | |
316 | } | |
a9dcad5e HD |
317 | |
318 | cr = iotlb_alloc_cr(obj, e); | |
319 | if (IS_ERR(cr)) { | |
320 | clk_disable(obj->clk); | |
321 | return PTR_ERR(cr); | |
322 | } | |
323 | ||
324 | iotlb_load_cr(obj, cr); | |
325 | kfree(cr); | |
326 | ||
be6d8026 KH |
327 | if (e->prsvd) |
328 | l.base++; | |
a9dcad5e HD |
329 | /* increment victim for next tlb load */ |
330 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 331 | l.vict = l.base; |
a9dcad5e HD |
332 | iotlb_lock_set(obj, &l); |
333 | out: | |
334 | clk_disable(obj->clk); | |
335 | return err; | |
336 | } | |
a9dcad5e | 337 | |
5da14a47 OBC |
338 | #else /* !PREFETCH_IOTLB */ |
339 | ||
6c32df43 | 340 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
341 | { |
342 | return 0; | |
343 | } | |
344 | ||
345 | #endif /* !PREFETCH_IOTLB */ | |
346 | ||
6c32df43 | 347 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
348 | { |
349 | return load_iotlb_entry(obj, e); | |
350 | } | |
a9dcad5e HD |
351 | |
352 | /** | |
353 | * flush_iotlb_page - Clear an iommu tlb entry | |
354 | * @obj: target iommu | |
355 | * @da: iommu device virtual address | |
356 | * | |
357 | * Clear an iommu tlb entry which includes 'da' address. | |
358 | **/ | |
6c32df43 | 359 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 360 | { |
a9dcad5e | 361 | int i; |
37c2836c | 362 | struct cr_regs cr; |
a9dcad5e HD |
363 | |
364 | clk_enable(obj->clk); | |
365 | ||
37c2836c | 366 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
367 | u32 start; |
368 | size_t bytes; | |
369 | ||
a9dcad5e HD |
370 | if (!iotlb_cr_valid(&cr)) |
371 | continue; | |
372 | ||
373 | start = iotlb_cr_to_virt(&cr); | |
374 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
375 | ||
376 | if ((start <= da) && (da < start + bytes)) { | |
377 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
378 | __func__, start, da, bytes); | |
0fa035e5 | 379 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
380 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
381 | } | |
382 | } | |
383 | clk_disable(obj->clk); | |
384 | ||
385 | if (i == obj->nr_tlb_entries) | |
386 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
387 | } | |
a9dcad5e HD |
388 | |
389 | /** | |
390 | * flush_iotlb_all - Clear all iommu tlb entries | |
391 | * @obj: target iommu | |
392 | **/ | |
6c32df43 | 393 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
394 | { |
395 | struct iotlb_lock l; | |
396 | ||
397 | clk_enable(obj->clk); | |
398 | ||
399 | l.base = 0; | |
400 | l.vict = 0; | |
401 | iotlb_lock_set(obj, &l); | |
402 | ||
403 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
404 | ||
405 | clk_disable(obj->clk); | |
406 | } | |
ddfa975a | 407 | |
e4efd94b | 408 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 409 | |
6c32df43 | 410 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 411 | { |
a9dcad5e HD |
412 | if (!obj || !buf) |
413 | return -EINVAL; | |
414 | ||
415 | clk_enable(obj->clk); | |
416 | ||
14e0e679 | 417 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e HD |
418 | |
419 | clk_disable(obj->clk); | |
420 | ||
421 | return bytes; | |
422 | } | |
6c32df43 | 423 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 424 | |
6c32df43 OBC |
425 | static int |
426 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
427 | { |
428 | int i; | |
37c2836c HD |
429 | struct iotlb_lock saved; |
430 | struct cr_regs tmp; | |
a9dcad5e HD |
431 | struct cr_regs *p = crs; |
432 | ||
433 | clk_enable(obj->clk); | |
a9dcad5e | 434 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 435 | |
37c2836c | 436 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
437 | if (!iotlb_cr_valid(&tmp)) |
438 | continue; | |
a9dcad5e HD |
439 | *p++ = tmp; |
440 | } | |
37c2836c | 441 | |
a9dcad5e HD |
442 | iotlb_lock_set(obj, &saved); |
443 | clk_disable(obj->clk); | |
444 | ||
445 | return p - crs; | |
446 | } | |
447 | ||
448 | /** | |
6c32df43 | 449 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
450 | * @obj: target iommu |
451 | * @buf: output buffer | |
452 | **/ | |
6c32df43 | 453 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 454 | { |
14e0e679 | 455 | int i, num; |
a9dcad5e HD |
456 | struct cr_regs *cr; |
457 | char *p = buf; | |
458 | ||
14e0e679 HD |
459 | num = bytes / sizeof(*cr); |
460 | num = min(obj->nr_tlb_entries, num); | |
461 | ||
462 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
463 | if (!cr) |
464 | return 0; | |
465 | ||
14e0e679 HD |
466 | num = __dump_tlb_entries(obj, cr, num); |
467 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
468 | p += iotlb_dump_cr(obj, cr + i, p); |
469 | kfree(cr); | |
470 | ||
471 | return p - buf; | |
472 | } | |
6c32df43 | 473 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 474 | |
6c32df43 | 475 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
476 | { |
477 | return driver_for_each_device(&omap_iommu_driver.driver, | |
478 | NULL, data, fn); | |
479 | } | |
6c32df43 | 480 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
481 | |
482 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
483 | ||
484 | /* | |
485 | * H/W pagetable operations | |
486 | */ | |
487 | static void flush_iopgd_range(u32 *first, u32 *last) | |
488 | { | |
489 | /* FIXME: L2 cache should be taken care of if it exists */ | |
490 | do { | |
491 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
492 | : : "r" (first)); | |
493 | first += L1_CACHE_BYTES / sizeof(*first); | |
494 | } while (first <= last); | |
495 | } | |
496 | ||
497 | static void flush_iopte_range(u32 *first, u32 *last) | |
498 | { | |
499 | /* FIXME: L2 cache should be taken care of if it exists */ | |
500 | do { | |
501 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
502 | : : "r" (first)); | |
503 | first += L1_CACHE_BYTES / sizeof(*first); | |
504 | } while (first <= last); | |
505 | } | |
506 | ||
507 | static void iopte_free(u32 *iopte) | |
508 | { | |
509 | /* Note: freed iopte's must be clean ready for re-use */ | |
510 | kmem_cache_free(iopte_cachep, iopte); | |
511 | } | |
512 | ||
6c32df43 | 513 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
514 | { |
515 | u32 *iopte; | |
516 | ||
517 | /* a table has already existed */ | |
518 | if (*iopgd) | |
519 | goto pte_ready; | |
520 | ||
521 | /* | |
522 | * do the allocation outside the page table lock | |
523 | */ | |
524 | spin_unlock(&obj->page_table_lock); | |
525 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
526 | spin_lock(&obj->page_table_lock); | |
527 | ||
528 | if (!*iopgd) { | |
529 | if (!iopte) | |
530 | return ERR_PTR(-ENOMEM); | |
531 | ||
532 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
533 | flush_iopgd_range(iopgd, iopgd); | |
534 | ||
535 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
536 | } else { | |
537 | /* We raced, free the reduniovant table */ | |
538 | iopte_free(iopte); | |
539 | } | |
540 | ||
541 | pte_ready: | |
542 | iopte = iopte_offset(iopgd, da); | |
543 | ||
544 | dev_vdbg(obj->dev, | |
545 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
546 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
547 | ||
548 | return iopte; | |
549 | } | |
550 | ||
6c32df43 | 551 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
552 | { |
553 | u32 *iopgd = iopgd_offset(obj, da); | |
554 | ||
4abb7617 HD |
555 | if ((da | pa) & ~IOSECTION_MASK) { |
556 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
557 | __func__, da, pa, IOSECTION_SIZE); | |
558 | return -EINVAL; | |
559 | } | |
560 | ||
a9dcad5e HD |
561 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
562 | flush_iopgd_range(iopgd, iopgd); | |
563 | return 0; | |
564 | } | |
565 | ||
6c32df43 | 566 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
567 | { |
568 | u32 *iopgd = iopgd_offset(obj, da); | |
569 | int i; | |
570 | ||
4abb7617 HD |
571 | if ((da | pa) & ~IOSUPER_MASK) { |
572 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
573 | __func__, da, pa, IOSUPER_SIZE); | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
a9dcad5e HD |
577 | for (i = 0; i < 16; i++) |
578 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
579 | flush_iopgd_range(iopgd, iopgd + 15); | |
580 | return 0; | |
581 | } | |
582 | ||
6c32df43 | 583 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
584 | { |
585 | u32 *iopgd = iopgd_offset(obj, da); | |
586 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
587 | ||
588 | if (IS_ERR(iopte)) | |
589 | return PTR_ERR(iopte); | |
590 | ||
591 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
592 | flush_iopte_range(iopte, iopte); | |
593 | ||
594 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
595 | __func__, da, pa, iopte, *iopte); | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
6c32df43 | 600 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
601 | { |
602 | u32 *iopgd = iopgd_offset(obj, da); | |
603 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
604 | int i; | |
605 | ||
4abb7617 HD |
606 | if ((da | pa) & ~IOLARGE_MASK) { |
607 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
608 | __func__, da, pa, IOLARGE_SIZE); | |
609 | return -EINVAL; | |
610 | } | |
611 | ||
a9dcad5e HD |
612 | if (IS_ERR(iopte)) |
613 | return PTR_ERR(iopte); | |
614 | ||
615 | for (i = 0; i < 16; i++) | |
616 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
617 | flush_iopte_range(iopte, iopte + 15); | |
618 | return 0; | |
619 | } | |
620 | ||
6c32df43 OBC |
621 | static int |
622 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 623 | { |
6c32df43 | 624 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
625 | u32 prot; |
626 | int err; | |
627 | ||
628 | if (!obj || !e) | |
629 | return -EINVAL; | |
630 | ||
631 | switch (e->pgsz) { | |
632 | case MMU_CAM_PGSZ_16M: | |
633 | fn = iopgd_alloc_super; | |
634 | break; | |
635 | case MMU_CAM_PGSZ_1M: | |
636 | fn = iopgd_alloc_section; | |
637 | break; | |
638 | case MMU_CAM_PGSZ_64K: | |
639 | fn = iopte_alloc_large; | |
640 | break; | |
641 | case MMU_CAM_PGSZ_4K: | |
642 | fn = iopte_alloc_page; | |
643 | break; | |
644 | default: | |
645 | fn = NULL; | |
646 | BUG(); | |
647 | break; | |
648 | } | |
649 | ||
650 | prot = get_iopte_attr(e); | |
651 | ||
652 | spin_lock(&obj->page_table_lock); | |
653 | err = fn(obj, e->da, e->pa, prot); | |
654 | spin_unlock(&obj->page_table_lock); | |
655 | ||
656 | return err; | |
657 | } | |
658 | ||
659 | /** | |
6c32df43 | 660 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
661 | * @obj: target iommu |
662 | * @e: an iommu tlb entry info | |
663 | **/ | |
6c32df43 | 664 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
665 | { |
666 | int err; | |
667 | ||
668 | flush_iotlb_page(obj, e->da); | |
669 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 670 | if (!err) |
5da14a47 | 671 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
672 | return err; |
673 | } | |
6c32df43 | 674 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
675 | |
676 | /** | |
677 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
678 | * @obj: target iommu | |
679 | * @da: iommu device virtual address | |
680 | * @ppgd: iommu pgd entry pointer to be returned | |
681 | * @ppte: iommu pte entry pointer to be returned | |
682 | **/ | |
e1f23813 OBC |
683 | static void |
684 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
685 | { |
686 | u32 *iopgd, *iopte = NULL; | |
687 | ||
688 | iopgd = iopgd_offset(obj, da); | |
689 | if (!*iopgd) | |
690 | goto out; | |
691 | ||
a1a54456 | 692 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
693 | iopte = iopte_offset(iopgd, da); |
694 | out: | |
695 | *ppgd = iopgd; | |
696 | *ppte = iopte; | |
697 | } | |
a9dcad5e | 698 | |
6c32df43 | 699 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
700 | { |
701 | size_t bytes; | |
702 | u32 *iopgd = iopgd_offset(obj, da); | |
703 | int nent = 1; | |
704 | ||
705 | if (!*iopgd) | |
706 | return 0; | |
707 | ||
a1a54456 | 708 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
709 | int i; |
710 | u32 *iopte = iopte_offset(iopgd, da); | |
711 | ||
712 | bytes = IOPTE_SIZE; | |
713 | if (*iopte & IOPTE_LARGE) { | |
714 | nent *= 16; | |
715 | /* rewind to the 1st entry */ | |
c127c7dc | 716 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
717 | } |
718 | bytes *= nent; | |
719 | memset(iopte, 0, nent * sizeof(*iopte)); | |
720 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
721 | ||
722 | /* | |
723 | * do table walk to check if this table is necessary or not | |
724 | */ | |
725 | iopte = iopte_offset(iopgd, 0); | |
726 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
727 | if (iopte[i]) | |
728 | goto out; | |
729 | ||
730 | iopte_free(iopte); | |
731 | nent = 1; /* for the next L1 entry */ | |
732 | } else { | |
733 | bytes = IOPGD_SIZE; | |
dcc730dc | 734 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
735 | nent *= 16; |
736 | /* rewind to the 1st entry */ | |
8d33ea58 | 737 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
738 | } |
739 | bytes *= nent; | |
740 | } | |
741 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
742 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
743 | out: | |
744 | return bytes; | |
745 | } | |
746 | ||
747 | /** | |
748 | * iopgtable_clear_entry - Remove an iommu pte entry | |
749 | * @obj: target iommu | |
750 | * @da: iommu device virtual address | |
751 | **/ | |
6c32df43 | 752 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
753 | { |
754 | size_t bytes; | |
755 | ||
756 | spin_lock(&obj->page_table_lock); | |
757 | ||
758 | bytes = iopgtable_clear_entry_core(obj, da); | |
759 | flush_iotlb_page(obj, da); | |
760 | ||
761 | spin_unlock(&obj->page_table_lock); | |
762 | ||
763 | return bytes; | |
764 | } | |
a9dcad5e | 765 | |
6c32df43 | 766 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
767 | { |
768 | int i; | |
769 | ||
770 | spin_lock(&obj->page_table_lock); | |
771 | ||
772 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
773 | u32 da; | |
774 | u32 *iopgd; | |
775 | ||
776 | da = i << IOPGD_SHIFT; | |
777 | iopgd = iopgd_offset(obj, da); | |
778 | ||
779 | if (!*iopgd) | |
780 | continue; | |
781 | ||
a1a54456 | 782 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
783 | iopte_free(iopte_offset(iopgd, 0)); |
784 | ||
785 | *iopgd = 0; | |
786 | flush_iopgd_range(iopgd, iopgd); | |
787 | } | |
788 | ||
789 | flush_iotlb_all(obj); | |
790 | ||
791 | spin_unlock(&obj->page_table_lock); | |
792 | } | |
793 | ||
794 | /* | |
795 | * Device IOMMU generic operations | |
796 | */ | |
797 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
798 | { | |
d594f1f3 | 799 | u32 da, errs; |
a9dcad5e | 800 | u32 *iopgd, *iopte; |
6c32df43 | 801 | struct omap_iommu *obj = data; |
e7f10f02 | 802 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
803 | |
804 | if (!obj->refcount) | |
805 | return IRQ_NONE; | |
806 | ||
d594f1f3 | 807 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
808 | if (errs == 0) |
809 | return IRQ_HANDLED; | |
d594f1f3 DC |
810 | |
811 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 812 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
813 | return IRQ_HANDLED; |
814 | ||
37b29810 HD |
815 | iommu_disable(obj); |
816 | ||
a9dcad5e HD |
817 | iopgd = iopgd_offset(obj, da); |
818 | ||
a1a54456 | 819 | if (!iopgd_is_table(*iopgd)) { |
d594f1f3 DC |
820 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
821 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
822 | return IRQ_NONE; |
823 | } | |
824 | ||
825 | iopte = iopte_offset(iopgd, da); | |
826 | ||
d594f1f3 DC |
827 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
828 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, | |
829 | iopte, *iopte); | |
a9dcad5e HD |
830 | |
831 | return IRQ_NONE; | |
832 | } | |
833 | ||
834 | static int device_match_by_alias(struct device *dev, void *data) | |
835 | { | |
6c32df43 | 836 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
837 | const char *name = data; |
838 | ||
839 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
840 | ||
841 | return strcmp(obj->name, name) == 0; | |
842 | } | |
843 | ||
844 | /** | |
f626b52d | 845 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 846 | * @name: name of target omap iommu device |
f626b52d | 847 | * @iopgd: page table |
a9dcad5e | 848 | **/ |
fabdbca8 | 849 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e HD |
850 | { |
851 | int err = -ENOMEM; | |
fabdbca8 OBC |
852 | struct device *dev; |
853 | struct omap_iommu *obj; | |
854 | ||
855 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
856 | (void *)name, | |
857 | device_match_by_alias); | |
858 | if (!dev) | |
859 | return NULL; | |
860 | ||
861 | obj = to_iommu(dev); | |
a9dcad5e | 862 | |
f626b52d | 863 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 864 | |
f626b52d OBC |
865 | /* an iommu device can only be attached once */ |
866 | if (++obj->refcount > 1) { | |
867 | dev_err(dev, "%s: already attached!\n", obj->name); | |
868 | err = -EBUSY; | |
869 | goto err_enable; | |
a9dcad5e HD |
870 | } |
871 | ||
f626b52d OBC |
872 | obj->iopgd = iopgd; |
873 | err = iommu_enable(obj); | |
874 | if (err) | |
875 | goto err_enable; | |
876 | flush_iotlb_all(obj); | |
877 | ||
a9dcad5e HD |
878 | if (!try_module_get(obj->owner)) |
879 | goto err_module; | |
880 | ||
f626b52d | 881 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
882 | |
883 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
884 | return obj; | |
885 | ||
886 | err_module: | |
887 | if (obj->refcount == 1) | |
888 | iommu_disable(obj); | |
889 | err_enable: | |
890 | obj->refcount--; | |
f626b52d | 891 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
892 | return ERR_PTR(err); |
893 | } | |
a9dcad5e HD |
894 | |
895 | /** | |
f626b52d | 896 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
897 | * @obj: target iommu |
898 | **/ | |
6c32df43 | 899 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 900 | { |
acf9d467 | 901 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
902 | return; |
903 | ||
f626b52d | 904 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
905 | |
906 | if (--obj->refcount == 0) | |
907 | iommu_disable(obj); | |
908 | ||
909 | module_put(obj->owner); | |
910 | ||
f626b52d | 911 | obj->iopgd = NULL; |
d594f1f3 | 912 | |
f626b52d | 913 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 914 | |
a9dcad5e | 915 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 916 | } |
d594f1f3 | 917 | |
a9dcad5e HD |
918 | /* |
919 | * OMAP Device MMU(IOMMU) detection | |
920 | */ | |
921 | static int __devinit omap_iommu_probe(struct platform_device *pdev) | |
922 | { | |
923 | int err = -ENODEV; | |
a9dcad5e | 924 | int irq; |
6c32df43 | 925 | struct omap_iommu *obj; |
a9dcad5e HD |
926 | struct resource *res; |
927 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
928 | ||
929 | if (pdev->num_resources != 2) | |
930 | return -EINVAL; | |
931 | ||
932 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | |
933 | if (!obj) | |
934 | return -ENOMEM; | |
935 | ||
936 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); | |
937 | if (IS_ERR(obj->clk)) | |
938 | goto err_clk; | |
939 | ||
940 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
941 | obj->name = pdata->name; | |
942 | obj->dev = &pdev->dev; | |
943 | obj->ctx = (void *)obj + sizeof(*obj); | |
c7f4ab26 GLF |
944 | obj->da_start = pdata->da_start; |
945 | obj->da_end = pdata->da_end; | |
a9dcad5e | 946 | |
f626b52d | 947 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
948 | mutex_init(&obj->mmap_lock); |
949 | spin_lock_init(&obj->page_table_lock); | |
950 | INIT_LIST_HEAD(&obj->mmap); | |
951 | ||
952 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
953 | if (!res) { | |
954 | err = -ENODEV; | |
955 | goto err_mem; | |
956 | } | |
a9dcad5e HD |
957 | |
958 | res = request_mem_region(res->start, resource_size(res), | |
959 | dev_name(&pdev->dev)); | |
960 | if (!res) { | |
961 | err = -EIO; | |
962 | goto err_mem; | |
963 | } | |
964 | ||
da4a0f76 AK |
965 | obj->regbase = ioremap(res->start, resource_size(res)); |
966 | if (!obj->regbase) { | |
967 | err = -ENOMEM; | |
968 | goto err_ioremap; | |
969 | } | |
970 | ||
a9dcad5e HD |
971 | irq = platform_get_irq(pdev, 0); |
972 | if (irq < 0) { | |
973 | err = -ENODEV; | |
974 | goto err_irq; | |
975 | } | |
976 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
977 | dev_name(&pdev->dev), obj); | |
978 | if (err < 0) | |
979 | goto err_irq; | |
980 | platform_set_drvdata(pdev, obj); | |
981 | ||
a9dcad5e HD |
982 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
983 | return 0; | |
984 | ||
a9dcad5e | 985 | err_irq: |
a9dcad5e | 986 | iounmap(obj->regbase); |
da4a0f76 AK |
987 | err_ioremap: |
988 | release_mem_region(res->start, resource_size(res)); | |
a9dcad5e HD |
989 | err_mem: |
990 | clk_put(obj->clk); | |
991 | err_clk: | |
992 | kfree(obj); | |
993 | return err; | |
994 | } | |
995 | ||
996 | static int __devexit omap_iommu_remove(struct platform_device *pdev) | |
997 | { | |
998 | int irq; | |
999 | struct resource *res; | |
6c32df43 | 1000 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e HD |
1001 | |
1002 | platform_set_drvdata(pdev, NULL); | |
1003 | ||
1004 | iopgtable_clear_entry_all(obj); | |
a9dcad5e HD |
1005 | |
1006 | irq = platform_get_irq(pdev, 0); | |
1007 | free_irq(irq, obj); | |
1008 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1009 | release_mem_region(res->start, resource_size(res)); | |
1010 | iounmap(obj->regbase); | |
1011 | ||
1012 | clk_put(obj->clk); | |
1013 | dev_info(&pdev->dev, "%s removed\n", obj->name); | |
1014 | kfree(obj); | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static struct platform_driver omap_iommu_driver = { | |
1019 | .probe = omap_iommu_probe, | |
1020 | .remove = __devexit_p(omap_iommu_remove), | |
1021 | .driver = { | |
1022 | .name = "omap-iommu", | |
1023 | }, | |
1024 | }; | |
1025 | ||
1026 | static void iopte_cachep_ctor(void *iopte) | |
1027 | { | |
1028 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1029 | } | |
1030 | ||
ed1c7de2 TL |
1031 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, |
1032 | u32 flags) | |
1033 | { | |
1034 | memset(e, 0, sizeof(*e)); | |
1035 | ||
1036 | e->da = da; | |
1037 | e->pa = pa; | |
1038 | e->valid = 1; | |
1039 | /* FIXME: add OMAP1 support */ | |
1040 | e->pgsz = flags & MMU_CAM_PGSZ_MASK; | |
1041 | e->endian = flags & MMU_RAM_ENDIAN_MASK; | |
1042 | e->elsz = flags & MMU_RAM_ELSZ_MASK; | |
1043 | e->mixed = flags & MMU_RAM_MIXED_MASK; | |
1044 | ||
1045 | return iopgsz_to_bytes(e->pgsz); | |
1046 | } | |
1047 | ||
f626b52d | 1048 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1049 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1050 | { |
1051 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1052 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1053 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1054 | struct iotlb_entry e; |
1055 | int omap_pgsz; | |
1056 | u32 ret, flags; | |
1057 | ||
1058 | /* we only support mapping a single iommu page for now */ | |
1059 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1060 | if (omap_pgsz < 0) { | |
1061 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1062 | return -EINVAL; | |
1063 | } | |
1064 | ||
1065 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1066 | ||
1067 | flags = omap_pgsz | prot; | |
1068 | ||
1069 | iotlb_init_entry(&e, da, pa, flags); | |
1070 | ||
6c32df43 | 1071 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1072 | if (ret) |
6c32df43 | 1073 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1074 | |
b4550d41 | 1075 | return ret; |
f626b52d OBC |
1076 | } |
1077 | ||
5009065d OBC |
1078 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1079 | size_t size) | |
f626b52d OBC |
1080 | { |
1081 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1082 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1083 | struct device *dev = oiommu->dev; |
f626b52d | 1084 | |
5009065d | 1085 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1086 | |
5009065d | 1087 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1088 | } |
1089 | ||
1090 | static int | |
1091 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1092 | { | |
1093 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1094 | struct omap_iommu *oiommu; |
fabdbca8 | 1095 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1096 | int ret = 0; |
1097 | ||
1098 | spin_lock(&omap_domain->lock); | |
1099 | ||
1100 | /* only a single device is supported per domain for now */ | |
1101 | if (omap_domain->iommu_dev) { | |
1102 | dev_err(dev, "iommu domain is already attached\n"); | |
1103 | ret = -EBUSY; | |
1104 | goto out; | |
1105 | } | |
1106 | ||
1107 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1108 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1109 | if (IS_ERR(oiommu)) { |
1110 | ret = PTR_ERR(oiommu); | |
1111 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1112 | goto out; | |
1113 | } | |
1114 | ||
fabdbca8 | 1115 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1116 | omap_domain->dev = dev; |
e7f10f02 | 1117 | oiommu->domain = domain; |
f626b52d OBC |
1118 | |
1119 | out: | |
1120 | spin_unlock(&omap_domain->lock); | |
1121 | return ret; | |
1122 | } | |
1123 | ||
803b5277 ORL |
1124 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1125 | struct device *dev) | |
f626b52d | 1126 | { |
fabdbca8 | 1127 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1128 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1129 | |
1130 | /* only a single device is supported per domain for now */ | |
1131 | if (omap_domain->iommu_dev != oiommu) { | |
1132 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1133 | return; |
f626b52d OBC |
1134 | } |
1135 | ||
1136 | iopgtable_clear_entry_all(oiommu); | |
1137 | ||
1138 | omap_iommu_detach(oiommu); | |
1139 | ||
fabdbca8 | 1140 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1141 | omap_domain->dev = NULL; |
1142 | } | |
f626b52d | 1143 | |
803b5277 ORL |
1144 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1145 | struct device *dev) | |
1146 | { | |
1147 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1148 | ||
1149 | spin_lock(&omap_domain->lock); | |
1150 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1151 | spin_unlock(&omap_domain->lock); |
1152 | } | |
1153 | ||
1154 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1155 | { | |
1156 | struct omap_iommu_domain *omap_domain; | |
1157 | ||
1158 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1159 | if (!omap_domain) { | |
1160 | pr_err("kzalloc failed\n"); | |
1161 | goto out; | |
1162 | } | |
1163 | ||
1164 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1165 | if (!omap_domain->pgtable) { | |
1166 | pr_err("kzalloc failed\n"); | |
1167 | goto fail_nomem; | |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * should never fail, but please keep this around to ensure | |
1172 | * we keep the hardware happy | |
1173 | */ | |
1174 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1175 | ||
1176 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1177 | spin_lock_init(&omap_domain->lock); | |
1178 | ||
1179 | domain->priv = omap_domain; | |
1180 | ||
2c6edb0c JR |
1181 | domain->geometry.aperture_start = 0; |
1182 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1183 | domain->geometry.force_aperture = true; | |
1184 | ||
f626b52d OBC |
1185 | return 0; |
1186 | ||
1187 | fail_nomem: | |
1188 | kfree(omap_domain); | |
1189 | out: | |
1190 | return -ENOMEM; | |
1191 | } | |
1192 | ||
f626b52d OBC |
1193 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1194 | { | |
1195 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1196 | ||
1197 | domain->priv = NULL; | |
1198 | ||
803b5277 ORL |
1199 | /* |
1200 | * An iommu device is still attached | |
1201 | * (currently, only one device can be attached) ? | |
1202 | */ | |
1203 | if (omap_domain->iommu_dev) | |
1204 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1205 | ||
f626b52d OBC |
1206 | kfree(omap_domain->pgtable); |
1207 | kfree(omap_domain); | |
1208 | } | |
1209 | ||
1210 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
1211 | unsigned long da) | |
1212 | { | |
1213 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1214 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1215 | struct device *dev = oiommu->dev; |
1216 | u32 *pgd, *pte; | |
1217 | phys_addr_t ret = 0; | |
1218 | ||
1219 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1220 | ||
1221 | if (pte) { | |
1222 | if (iopte_is_small(*pte)) | |
1223 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1224 | else if (iopte_is_large(*pte)) | |
1225 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1226 | else | |
1a36ea81 | 1227 | dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da); |
f626b52d OBC |
1228 | } else { |
1229 | if (iopgd_is_section(*pgd)) | |
1230 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1231 | else if (iopgd_is_super(*pgd)) | |
1232 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1233 | else | |
1a36ea81 | 1234 | dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da); |
f626b52d OBC |
1235 | } |
1236 | ||
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1241 | unsigned long cap) | |
1242 | { | |
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | static struct iommu_ops omap_iommu_ops = { | |
1247 | .domain_init = omap_iommu_domain_init, | |
1248 | .domain_destroy = omap_iommu_domain_destroy, | |
1249 | .attach_dev = omap_iommu_attach_dev, | |
1250 | .detach_dev = omap_iommu_detach_dev, | |
1251 | .map = omap_iommu_map, | |
1252 | .unmap = omap_iommu_unmap, | |
1253 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1254 | .domain_has_cap = omap_iommu_domain_has_cap, | |
66bc8cf3 | 1255 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1256 | }; |
1257 | ||
a9dcad5e HD |
1258 | static int __init omap_iommu_init(void) |
1259 | { | |
1260 | struct kmem_cache *p; | |
1261 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1262 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1263 | ||
1264 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1265 | iopte_cachep_ctor); | |
1266 | if (!p) | |
1267 | return -ENOMEM; | |
1268 | iopte_cachep = p; | |
1269 | ||
a65bc64f | 1270 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1271 | |
a9dcad5e HD |
1272 | return platform_driver_register(&omap_iommu_driver); |
1273 | } | |
435792d9 OBC |
1274 | /* must be ready before omap3isp is probed */ |
1275 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1276 | |
1277 | static void __exit omap_iommu_exit(void) | |
1278 | { | |
1279 | kmem_cache_destroy(iopte_cachep); | |
1280 | ||
1281 | platform_driver_unregister(&omap_iommu_driver); | |
1282 | } | |
1283 | module_exit(omap_iommu_exit); | |
1284 | ||
1285 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1286 | MODULE_ALIAS("platform:omap-iommu"); | |
1287 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1288 | MODULE_LICENSE("GPL v2"); |