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ed1c7de2 TL |
1 | /* |
2 | * omap iommu: main structures | |
3 | * | |
4 | * Copyright (C) 2008-2009 Nokia Corporation | |
5 | * | |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #if defined(CONFIG_ARCH_OMAP1) | |
14 | #error "iommu for this processor not implemented yet" | |
15 | #endif | |
16 | ||
17 | struct iotlb_entry { | |
18 | u32 da; | |
19 | u32 pa; | |
20 | u32 pgsz, prsvd, valid; | |
21 | union { | |
22 | u16 ap; | |
23 | struct { | |
24 | u32 endian, elsz, mixed; | |
25 | }; | |
26 | }; | |
27 | }; | |
28 | ||
29 | struct omap_iommu { | |
30 | const char *name; | |
ed1c7de2 TL |
31 | void __iomem *regbase; |
32 | struct device *dev; | |
33 | void *isr_priv; | |
34 | struct iommu_domain *domain; | |
35 | ||
36 | unsigned int refcount; | |
37 | spinlock_t iommu_lock; /* global for this whole object */ | |
38 | ||
39 | /* | |
40 | * We don't change iopgd for a situation like pgd for a task, | |
41 | * but share it globally for each iommu. | |
42 | */ | |
43 | u32 *iopgd; | |
44 | spinlock_t page_table_lock; /* protect iopgd */ | |
45 | ||
46 | int nr_tlb_entries; | |
47 | ||
ed1c7de2 | 48 | void *ctx; /* iommu context: registres saved area */ |
b148d5fb SA |
49 | |
50 | int has_bus_err_back; | |
ed1c7de2 TL |
51 | }; |
52 | ||
53 | struct cr_regs { | |
54 | union { | |
55 | struct { | |
56 | u16 cam_l; | |
57 | u16 cam_h; | |
58 | }; | |
59 | u32 cam; | |
60 | }; | |
61 | union { | |
62 | struct { | |
63 | u16 ram_l; | |
64 | u16 ram_h; | |
65 | }; | |
66 | u32 ram; | |
67 | }; | |
68 | }; | |
69 | ||
ed1c7de2 TL |
70 | /* architecture specific functions */ |
71 | struct iommu_functions { | |
72 | unsigned long version; | |
73 | ||
74 | int (*enable)(struct omap_iommu *obj); | |
75 | void (*disable)(struct omap_iommu *obj); | |
76 | void (*set_twl)(struct omap_iommu *obj, bool on); | |
77 | u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra); | |
78 | ||
79 | void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr); | |
80 | void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr); | |
81 | ||
82 | struct cr_regs *(*alloc_cr)(struct omap_iommu *obj, | |
83 | struct iotlb_entry *e); | |
84 | int (*cr_valid)(struct cr_regs *cr); | |
85 | u32 (*cr_to_virt)(struct cr_regs *cr); | |
86 | void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); | |
87 | ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr, | |
88 | char *buf); | |
89 | ||
90 | u32 (*get_pte_attr)(struct iotlb_entry *e); | |
91 | ||
92 | void (*save_ctx)(struct omap_iommu *obj); | |
93 | void (*restore_ctx)(struct omap_iommu *obj); | |
94 | ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len); | |
95 | }; | |
96 | ||
97 | #ifdef CONFIG_IOMMU_API | |
98 | /** | |
99 | * dev_to_omap_iommu() - retrieves an omap iommu object from a user device | |
100 | * @dev: iommu client device | |
101 | */ | |
102 | static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) | |
103 | { | |
104 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
105 | ||
106 | return arch_data->iommu_dev; | |
107 | } | |
108 | #endif | |
109 | ||
ed1c7de2 TL |
110 | /* |
111 | * MMU Register offsets | |
112 | */ | |
113 | #define MMU_REVISION 0x00 | |
ed1c7de2 TL |
114 | #define MMU_IRQSTATUS 0x18 |
115 | #define MMU_IRQENABLE 0x1c | |
116 | #define MMU_WALKING_ST 0x40 | |
117 | #define MMU_CNTL 0x44 | |
118 | #define MMU_FAULT_AD 0x48 | |
119 | #define MMU_TTB 0x4c | |
120 | #define MMU_LOCK 0x50 | |
121 | #define MMU_LD_TLB 0x54 | |
122 | #define MMU_CAM 0x58 | |
123 | #define MMU_RAM 0x5c | |
124 | #define MMU_GFLUSH 0x60 | |
125 | #define MMU_FLUSH_ENTRY 0x64 | |
126 | #define MMU_READ_CAM 0x68 | |
127 | #define MMU_READ_RAM 0x6c | |
128 | #define MMU_EMU_FAULT_AD 0x70 | |
b148d5fb | 129 | #define MMU_GP_REG 0x88 |
ed1c7de2 TL |
130 | |
131 | #define MMU_REG_SIZE 256 | |
132 | ||
133 | /* | |
134 | * MMU Register bit definitions | |
135 | */ | |
ed1c7de2 TL |
136 | #define MMU_CAM_VATAG_SHIFT 12 |
137 | #define MMU_CAM_VATAG_MASK \ | |
138 | ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) | |
139 | #define MMU_CAM_P (1 << 3) | |
140 | #define MMU_CAM_V (1 << 2) | |
141 | #define MMU_CAM_PGSZ_MASK 3 | |
142 | #define MMU_CAM_PGSZ_1M (0 << 0) | |
143 | #define MMU_CAM_PGSZ_64K (1 << 0) | |
144 | #define MMU_CAM_PGSZ_4K (2 << 0) | |
145 | #define MMU_CAM_PGSZ_16M (3 << 0) | |
146 | ||
147 | #define MMU_RAM_PADDR_SHIFT 12 | |
148 | #define MMU_RAM_PADDR_MASK \ | |
149 | ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) | |
150 | ||
baaa7b5d | 151 | #define MMU_RAM_ENDIAN_SHIFT 9 |
ed1c7de2 | 152 | #define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) |
baaa7b5d | 153 | #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) |
ed1c7de2 TL |
154 | #define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) |
155 | ||
baaa7b5d | 156 | #define MMU_RAM_ELSZ_SHIFT 7 |
ed1c7de2 TL |
157 | #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) |
158 | #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) | |
159 | #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) | |
160 | #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) | |
161 | #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) | |
162 | #define MMU_RAM_MIXED_SHIFT 6 | |
163 | #define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) | |
164 | #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK | |
165 | ||
b148d5fb SA |
166 | #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1 |
167 | ||
ed1c7de2 TL |
168 | /* |
169 | * utilities for super page(16MB, 1MB, 64KB and 4KB) | |
170 | */ | |
171 | ||
172 | #define iopgsz_max(bytes) \ | |
173 | (((bytes) >= SZ_16M) ? SZ_16M : \ | |
174 | ((bytes) >= SZ_1M) ? SZ_1M : \ | |
175 | ((bytes) >= SZ_64K) ? SZ_64K : \ | |
176 | ((bytes) >= SZ_4K) ? SZ_4K : 0) | |
177 | ||
178 | #define bytes_to_iopgsz(bytes) \ | |
179 | (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ | |
180 | ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ | |
181 | ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ | |
182 | ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) | |
183 | ||
184 | #define iopgsz_to_bytes(iopgsz) \ | |
185 | (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ | |
186 | ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ | |
187 | ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ | |
188 | ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) | |
189 | ||
190 | #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) | |
191 | ||
192 | /* | |
193 | * global functions | |
194 | */ | |
195 | extern u32 omap_iommu_arch_version(void); | |
196 | ||
197 | extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); | |
198 | ||
199 | extern int | |
200 | omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e); | |
201 | ||
ed1c7de2 TL |
202 | extern void omap_iommu_save_ctx(struct device *dev); |
203 | extern void omap_iommu_restore_ctx(struct device *dev); | |
204 | ||
ed1c7de2 TL |
205 | extern int omap_foreach_iommu_device(void *data, |
206 | int (*fn)(struct device *, void *)); | |
207 | ||
7bd9e25f IY |
208 | extern int omap_install_iommu_arch(const struct iommu_functions *ops); |
209 | extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops); | |
210 | ||
ed1c7de2 TL |
211 | extern ssize_t |
212 | omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len); | |
213 | extern size_t | |
214 | omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len); | |
215 | ||
216 | /* | |
217 | * register accessors | |
218 | */ | |
219 | static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) | |
220 | { | |
221 | return __raw_readl(obj->regbase + offs); | |
222 | } | |
223 | ||
224 | static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) | |
225 | { | |
226 | __raw_writel(val, obj->regbase + offs); | |
227 | } |