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ed1c7de2 TL |
1 | /* |
2 | * omap iommu: main structures | |
3 | * | |
4 | * Copyright (C) 2008-2009 Nokia Corporation | |
5 | * | |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
533b40cc SA |
13 | #ifndef _OMAP_IOMMU_H |
14 | #define _OMAP_IOMMU_H | |
15 | ||
69c2c196 SA |
16 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
17 | for (__i = 0; \ | |
18 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
19 | __i++) | |
20 | ||
ed1c7de2 TL |
21 | struct iotlb_entry { |
22 | u32 da; | |
23 | u32 pa; | |
24 | u32 pgsz, prsvd, valid; | |
dc308f9f | 25 | u32 endian, elsz, mixed; |
ed1c7de2 TL |
26 | }; |
27 | ||
28 | struct omap_iommu { | |
29 | const char *name; | |
ed1c7de2 TL |
30 | void __iomem *regbase; |
31 | struct device *dev; | |
ed1c7de2 | 32 | struct iommu_domain *domain; |
61c75352 | 33 | struct dentry *debug_dir; |
ed1c7de2 | 34 | |
ed1c7de2 TL |
35 | spinlock_t iommu_lock; /* global for this whole object */ |
36 | ||
37 | /* | |
38 | * We don't change iopgd for a situation like pgd for a task, | |
39 | * but share it globally for each iommu. | |
40 | */ | |
41 | u32 *iopgd; | |
42 | spinlock_t page_table_lock; /* protect iopgd */ | |
43 | ||
44 | int nr_tlb_entries; | |
45 | ||
ed1c7de2 | 46 | void *ctx; /* iommu context: registres saved area */ |
b148d5fb SA |
47 | |
48 | int has_bus_err_back; | |
ed1c7de2 TL |
49 | }; |
50 | ||
51 | struct cr_regs { | |
dc308f9f SA |
52 | u32 cam; |
53 | u32 ram; | |
ed1c7de2 TL |
54 | }; |
55 | ||
69c2c196 SA |
56 | struct iotlb_lock { |
57 | short base; | |
58 | short vict; | |
59 | }; | |
60 | ||
ed1c7de2 TL |
61 | /** |
62 | * dev_to_omap_iommu() - retrieves an omap iommu object from a user device | |
63 | * @dev: iommu client device | |
64 | */ | |
65 | static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) | |
66 | { | |
67 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
68 | ||
69 | return arch_data->iommu_dev; | |
70 | } | |
ed1c7de2 | 71 | |
ed1c7de2 TL |
72 | /* |
73 | * MMU Register offsets | |
74 | */ | |
75 | #define MMU_REVISION 0x00 | |
ed1c7de2 TL |
76 | #define MMU_IRQSTATUS 0x18 |
77 | #define MMU_IRQENABLE 0x1c | |
78 | #define MMU_WALKING_ST 0x40 | |
79 | #define MMU_CNTL 0x44 | |
80 | #define MMU_FAULT_AD 0x48 | |
81 | #define MMU_TTB 0x4c | |
82 | #define MMU_LOCK 0x50 | |
83 | #define MMU_LD_TLB 0x54 | |
84 | #define MMU_CAM 0x58 | |
85 | #define MMU_RAM 0x5c | |
86 | #define MMU_GFLUSH 0x60 | |
87 | #define MMU_FLUSH_ENTRY 0x64 | |
88 | #define MMU_READ_CAM 0x68 | |
89 | #define MMU_READ_RAM 0x6c | |
90 | #define MMU_EMU_FAULT_AD 0x70 | |
b148d5fb | 91 | #define MMU_GP_REG 0x88 |
ed1c7de2 TL |
92 | |
93 | #define MMU_REG_SIZE 256 | |
94 | ||
95 | /* | |
96 | * MMU Register bit definitions | |
97 | */ | |
bd4396f0 SA |
98 | /* IRQSTATUS & IRQENABLE */ |
99 | #define MMU_IRQ_MULTIHITFAULT (1 << 4) | |
100 | #define MMU_IRQ_TABLEWALKFAULT (1 << 3) | |
101 | #define MMU_IRQ_EMUMISS (1 << 2) | |
102 | #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) | |
103 | #define MMU_IRQ_TLBMISS (1 << 0) | |
104 | ||
105 | #define __MMU_IRQ_FAULT \ | |
106 | (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) | |
107 | #define MMU_IRQ_MASK \ | |
108 | (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) | |
109 | #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) | |
110 | #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) | |
111 | ||
112 | /* MMU_CNTL */ | |
113 | #define MMU_CNTL_SHIFT 1 | |
114 | #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) | |
115 | #define MMU_CNTL_EML_TLB (1 << 3) | |
116 | #define MMU_CNTL_TWL_EN (1 << 2) | |
117 | #define MMU_CNTL_MMU_EN (1 << 1) | |
118 | ||
119 | /* CAM */ | |
ed1c7de2 TL |
120 | #define MMU_CAM_VATAG_SHIFT 12 |
121 | #define MMU_CAM_VATAG_MASK \ | |
122 | ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) | |
123 | #define MMU_CAM_P (1 << 3) | |
124 | #define MMU_CAM_V (1 << 2) | |
125 | #define MMU_CAM_PGSZ_MASK 3 | |
126 | #define MMU_CAM_PGSZ_1M (0 << 0) | |
127 | #define MMU_CAM_PGSZ_64K (1 << 0) | |
128 | #define MMU_CAM_PGSZ_4K (2 << 0) | |
129 | #define MMU_CAM_PGSZ_16M (3 << 0) | |
130 | ||
bd4396f0 | 131 | /* RAM */ |
ed1c7de2 TL |
132 | #define MMU_RAM_PADDR_SHIFT 12 |
133 | #define MMU_RAM_PADDR_MASK \ | |
134 | ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) | |
135 | ||
baaa7b5d | 136 | #define MMU_RAM_ENDIAN_SHIFT 9 |
ed1c7de2 | 137 | #define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) |
baaa7b5d | 138 | #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) |
ed1c7de2 TL |
139 | #define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) |
140 | ||
baaa7b5d | 141 | #define MMU_RAM_ELSZ_SHIFT 7 |
ed1c7de2 TL |
142 | #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) |
143 | #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) | |
144 | #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) | |
145 | #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) | |
146 | #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) | |
147 | #define MMU_RAM_MIXED_SHIFT 6 | |
148 | #define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) | |
149 | #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK | |
150 | ||
b148d5fb SA |
151 | #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1 |
152 | ||
bd4396f0 SA |
153 | #define get_cam_va_mask(pgsz) \ |
154 | (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ | |
155 | ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ | |
156 | ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ | |
157 | ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) | |
158 | ||
ed1c7de2 TL |
159 | /* |
160 | * utilities for super page(16MB, 1MB, 64KB and 4KB) | |
161 | */ | |
162 | ||
163 | #define iopgsz_max(bytes) \ | |
164 | (((bytes) >= SZ_16M) ? SZ_16M : \ | |
165 | ((bytes) >= SZ_1M) ? SZ_1M : \ | |
166 | ((bytes) >= SZ_64K) ? SZ_64K : \ | |
167 | ((bytes) >= SZ_4K) ? SZ_4K : 0) | |
168 | ||
169 | #define bytes_to_iopgsz(bytes) \ | |
170 | (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ | |
171 | ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ | |
172 | ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ | |
173 | ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) | |
174 | ||
175 | #define iopgsz_to_bytes(iopgsz) \ | |
176 | (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ | |
177 | ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ | |
178 | ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ | |
179 | ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) | |
180 | ||
181 | #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) | |
182 | ||
183 | /* | |
184 | * global functions | |
185 | */ | |
ed1c7de2 | 186 | |
69c2c196 SA |
187 | struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n); |
188 | void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l); | |
189 | void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l); | |
190 | ||
191 | #ifdef CONFIG_OMAP_IOMMU_DEBUG | |
61c75352 SA |
192 | void omap_iommu_debugfs_init(void); |
193 | void omap_iommu_debugfs_exit(void); | |
194 | ||
195 | void omap_iommu_debugfs_add(struct omap_iommu *obj); | |
196 | void omap_iommu_debugfs_remove(struct omap_iommu *obj); | |
197 | #else | |
198 | static inline void omap_iommu_debugfs_init(void) { } | |
199 | static inline void omap_iommu_debugfs_exit(void) { } | |
200 | ||
201 | static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { } | |
202 | static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { } | |
203 | #endif | |
204 | ||
ed1c7de2 TL |
205 | /* |
206 | * register accessors | |
207 | */ | |
208 | static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) | |
209 | { | |
210 | return __raw_readl(obj->regbase + offs); | |
211 | } | |
212 | ||
213 | static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) | |
214 | { | |
215 | __raw_writel(val, obj->regbase + offs); | |
216 | } | |
533b40cc | 217 | |
69c2c196 SA |
218 | static inline int iotlb_cr_valid(struct cr_regs *cr) |
219 | { | |
220 | if (!cr) | |
221 | return -EINVAL; | |
222 | ||
223 | return cr->cam & MMU_CAM_V; | |
224 | } | |
225 | ||
533b40cc | 226 | #endif /* _OMAP_IOMMU_H */ |