[deliverable/linux.git] / drivers / irqchip / exynos-combiner.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Combiner irqchip for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/mach/irq.h>

#include <plat/cpu.h>

#include "irqchip.h"

#define COMBINER_ENABLE_SET	0x0
#define COMBINER_ENABLE_CLEAR	0x4
#define COMBINER_INT_STATUS	0xC

static DEFINE_SPINLOCK(irq_controller_lock);

struct combiner_chip_data {
	unsigned int irq_offset;
	unsigned int irq_mask;
	void __iomem *base;
	unsigned int parent_irq;
};

static struct irq_domain *combiner_irq_domain;
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];

static inline void __iomem *combiner_base(struct irq_data *data)
{
	struct combiner_chip_data *combiner_data =
		irq_data_get_irq_chip_data(data);

	return combiner_data->base;
}

static void combiner_mask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->hwirq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}

static void combiner_unmask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->hwirq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}

static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned int cascade_irq, combiner_irq;
	unsigned long status;

	chained_irq_enter(chip, desc);

	spin_lock(&irq_controller_lock);
	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	spin_unlock(&irq_controller_lock);
	status &= chip_data->irq_mask;

	if (status == 0)
		goto out;

	combiner_irq = __ffs(status);

	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
	if (unlikely(cascade_irq >= NR_IRQS))
		do_bad_IRQ(cascade_irq, desc);
	else
		generic_handle_irq(cascade_irq);

 out:
	chained_irq_exit(chip, desc);
}

#ifdef CONFIG_SMP
static int combiner_set_affinity(struct irq_data *d,
				 const struct cpumask *mask_val, bool force)
{
	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);

	if (chip && chip->irq_set_affinity)
		return chip->irq_set_affinity(data, mask_val, force);
	else
		return -EINVAL;
}
#endif

static struct irq_chip combiner_chip = {
	.name			= "COMBINER",
	.irq_mask		= combiner_mask_irq,
	.irq_unmask		= combiner_unmask_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	= combiner_set_affinity,
#endif
};

static unsigned int max_combiner_nr(void)
{
	if (soc_is_exynos5250())
		return EXYNOS5_MAX_COMBINER_NR;
	else if (soc_is_exynos4412())
		return EXYNOS4412_MAX_COMBINER_NR;
	else if (soc_is_exynos4212())
		return EXYNOS4212_MAX_COMBINER_NR;
	else
		return EXYNOS4210_MAX_COMBINER_NR;
}

static void __init combiner_cascade_irq(unsigned int combiner_nr,
					unsigned int irq)
{
	if (combiner_nr >= max_combiner_nr())
		BUG();
	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
		BUG();
	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}

static void __init combiner_init_one(unsigned int combiner_nr,
				     void __iomem *base, unsigned int irq)
{
	combiner_data[combiner_nr].base = base;
	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
	combiner_data[combiner_nr].parent_irq = irq;

	/* Disable all interrupts */
	__raw_writel(combiner_data[combiner_nr].irq_mask,
		     base + COMBINER_ENABLE_CLEAR);
}

#ifdef CONFIG_OF
static int combiner_irq_domain_xlate(struct irq_domain *d,
				     struct device_node *controller,
				     const u32 *intspec, unsigned int intsize,
				     unsigned long *out_hwirq,
				     unsigned int *out_type)
{
	if (d->of_node != controller)
		return -EINVAL;

	if (intsize < 2)
		return -EINVAL;

	*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
	*out_type = 0;

	return 0;
}
#else
static int combiner_irq_domain_xlate(struct irq_domain *d,
				     struct device_node *controller,
				     const u32 *intspec, unsigned int intsize,
				     unsigned long *out_hwirq,
				     unsigned int *out_type)
{
	return -EINVAL;
}
#endif

static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
				   irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

	return 0;
}

static struct irq_domain_ops combiner_irq_domain_ops = {
	.xlate	= combiner_irq_domain_xlate,
	.map	= combiner_irq_domain_map,
};

static unsigned int exynos4x12_combiner_extra_irq(int group)
{
	switch (group) {
	case 16:
		return IRQ_SPI(107);
	case 17:
		return IRQ_SPI(108);
	case 18:
		return IRQ_SPI(48);
	case 19:
		return IRQ_SPI(42);
	default:
		return 0;
	}
}

void __init combiner_init(void __iomem *combiner_base,
			  struct device_node *np)
{
	int i, irq, irq_base;
	unsigned int max_nr, nr_irq;

	max_nr = max_combiner_nr();

	if (np) {
		if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
			pr_info("%s: number of combiners not specified, "
				"setting default as %d.\n",
				__func__, max_nr);
		}
	}

	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;

	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
	if (IS_ERR_VALUE(irq_base)) {
		irq_base = COMBINER_IRQ(0, 0);
		pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
	}

	combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
				&combiner_irq_domain_ops, &combiner_data);
	if (WARN_ON(!combiner_irq_domain)) {
		pr_warning("%s: irq domain init failed\n", __func__);
		return;
	}

	for (i = 0; i < max_nr; i++) {
		if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
			irq = IRQ_SPI(i);
		else
			irq = exynos4x12_combiner_extra_irq(i);
#ifdef CONFIG_OF
		if (np)
			irq = irq_of_parse_and_map(np, i);
#endif
		combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
		combiner_cascade_irq(i, irq);
	}
}

#ifdef CONFIG_OF
static int __init combiner_of_init(struct device_node *np,
				   struct device_node *parent)
{
	void __iomem *combiner_base;

	combiner_base = of_iomap(np, 0);
	if (!combiner_base) {
		pr_err("%s: failed to map combiner registers\n", __func__);
		return -ENXIO;
	}

	combiner_init(combiner_base, np);

	return 0;
}
IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
		combiner_of_init);
#endif
Commit	Line	Data
a900e5d9 RH	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Combiner irqchip for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/err.h>
	12	#include <linux/export.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
	15	#include <linux/irqdomain.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <asm/mach/irq.h>
	19
	20	#include <plat/cpu.h>
	21
	22	#include "irqchip.h"
	23
	24	#define COMBINER_ENABLE_SET 0x0
	25	#define COMBINER_ENABLE_CLEAR 0x4
	26	#define COMBINER_INT_STATUS 0xC
	27
	28	static DEFINE_SPINLOCK(irq_controller_lock);
	29
	30	struct combiner_chip_data {
	31	unsigned int irq_offset;
	32	unsigned int irq_mask;
	33	void __iomem *base;
df7ef462	34	unsigned int parent_irq;
a900e5d9 RH	35	};
	36
	37	static struct irq_domain *combiner_irq_domain;
	38	static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
	39
	40	static inline void __iomem combiner_base(struct irq_data data)
	41	{
	42	struct combiner_chip_data *combiner_data =
	43	irq_data_get_irq_chip_data(data);
	44
	45	return combiner_data->base;
	46	}
	47
	48	static void combiner_mask_irq(struct irq_data *data)
	49	{
	50	u32 mask = 1 << (data->hwirq % 32);
	51
	52	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
	53	}
	54
	55	static void combiner_unmask_irq(struct irq_data *data)
	56	{
	57	u32 mask = 1 << (data->hwirq % 32);
	58
	59	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
	60	}
	61
	62	static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
	63	{
	64	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	65	struct irq_chip *chip = irq_get_chip(irq);
	66	unsigned int cascade_irq, combiner_irq;
	67	unsigned long status;
	68
	69	chained_irq_enter(chip, desc);
	70
	71	spin_lock(&irq_controller_lock);
	72	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	73	spin_unlock(&irq_controller_lock);
	74	status &= chip_data->irq_mask;
	75
	76	if (status == 0)
	77	goto out;
	78
	79	combiner_irq = __ffs(status);
	80
	81	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
	82	if (unlikely(cascade_irq >= NR_IRQS))
	83	do_bad_IRQ(cascade_irq, desc);
	84	else
	85	generic_handle_irq(cascade_irq);
	86
	87	out:
	88	chained_irq_exit(chip, desc);
	89	}
	90
df7ef462 CP	91	#ifdef CONFIG_SMP
	92	static int combiner_set_affinity(struct irq_data *d,
	93	const struct cpumask *mask_val, bool force)
	94	{
	95	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
	96	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
	97	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
	98
	99	if (chip && chip->irq_set_affinity)
	100	return chip->irq_set_affinity(data, mask_val, force);
	101	else
	102	return -EINVAL;
	103	}
	104	#endif
	105
a900e5d9	106	static struct irq_chip combiner_chip = {
df7ef462 CP	107	.name = "COMBINER",
	108	.irq_mask = combiner_mask_irq,
	109	.irq_unmask = combiner_unmask_irq,
	110	#ifdef CONFIG_SMP
	111	.irq_set_affinity = combiner_set_affinity,
	112	#endif
a900e5d9 RH	113	};
a900e5d9 RH	114
4e164dc5	115	static unsigned int max_combiner_nr(void)
a900e5d9	116	{
a900e5d9	117	if (soc_is_exynos5250())
4e164dc5 CP	118	return EXYNOS5_MAX_COMBINER_NR;
	119	else if (soc_is_exynos4412())
	120	return EXYNOS4412_MAX_COMBINER_NR;
	121	else if (soc_is_exynos4212())
	122	return EXYNOS4212_MAX_COMBINER_NR;
a900e5d9	123	else
4e164dc5 CP	124	return EXYNOS4210_MAX_COMBINER_NR;
4e164dc5 CP	125	}
a900e5d9	126
4e164dc5 CP	127	static void __init combiner_cascade_irq(unsigned int combiner_nr,
	128	unsigned int irq)
	129	{
	130	if (combiner_nr >= max_combiner_nr())
a900e5d9 RH	131	BUG();
	132	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
	133	BUG();
	134	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
	135	}
	136
	137	static void __init combiner_init_one(unsigned int combiner_nr,
df7ef462	138	void __iomem *base, unsigned int irq)
a900e5d9 RH	139	{
	140	combiner_data[combiner_nr].base = base;
	141	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
	142	combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
	143	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
df7ef462	144	combiner_data[combiner_nr].parent_irq = irq;
a900e5d9 RH	145
	146	/* Disable all interrupts */
	147	__raw_writel(combiner_data[combiner_nr].irq_mask,
	148	base + COMBINER_ENABLE_CLEAR);
	149	}
	150
	151	#ifdef CONFIG_OF
	152	static int combiner_irq_domain_xlate(struct irq_domain *d,
	153	struct device_node *controller,
	154	const u32 *intspec, unsigned int intsize,
	155	unsigned long *out_hwirq,
	156	unsigned int *out_type)
	157	{
	158	if (d->of_node != controller)
	159	return -EINVAL;
	160
	161	if (intsize < 2)
	162	return -EINVAL;
	163
	164	out_hwirq = intspec[0] MAX_IRQ_IN_COMBINER + intspec[1];
	165	*out_type = 0;
	166
	167	return 0;
	168	}
	169	#else
	170	static int combiner_irq_domain_xlate(struct irq_domain *d,
	171	struct device_node *controller,
	172	const u32 *intspec, unsigned int intsize,
	173	unsigned long *out_hwirq,
	174	unsigned int *out_type)
	175	{
	176	return -EINVAL;
	177	}
	178	#endif
	179
	180	static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
	181	irq_hw_number_t hw)
	182	{
	183	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
	184	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
	185	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	186
	187	return 0;
	188	}
	189
	190	static struct irq_domain_ops combiner_irq_domain_ops = {
	191	.xlate = combiner_irq_domain_xlate,
	192	.map = combiner_irq_domain_map,
	193	};
	194
4e164dc5 CP	195	static unsigned int exynos4x12_combiner_extra_irq(int group)
	196	{
	197	switch (group) {
	198	case 16:
	199	return IRQ_SPI(107);
	200	case 17:
	201	return IRQ_SPI(108);
	202	case 18:
	203	return IRQ_SPI(48);
	204	case 19:
	205	return IRQ_SPI(42);
	206	default:
	207	return 0;
	208	}
	209	}
	210
a900e5d9 RH	211	void __init combiner_init(void __iomem *combiner_base,
	212	struct device_node *np)
	213	{
	214	int i, irq, irq_base;
	215	unsigned int max_nr, nr_irq;
	216
4e164dc5 CP	217	max_nr = max_combiner_nr();
4e164dc5 CP	218
a900e5d9 RH	219	if (np) {
a900e5d9 RH	220	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
4e164dc5	221	pr_info("%s: number of combiners not specified, "
a900e5d9	222	"setting default as %d.\n",
4e164dc5	223	__func__, max_nr);
a900e5d9	224	}
a900e5d9	225	}
4e164dc5	226
a900e5d9 RH	227	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
	228
	229	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
	230	if (IS_ERR_VALUE(irq_base)) {
	231	irq_base = COMBINER_IRQ(0, 0);
	232	pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
	233	}
	234
	235	combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
	236	&combiner_irq_domain_ops, &combiner_data);
	237	if (WARN_ON(!combiner_irq_domain)) {
	238	pr_warning("%s: irq domain init failed\n", __func__);
	239	return;
	240	}
	241
	242	for (i = 0; i < max_nr; i++) {
4e164dc5 CP	243	if (i < EXYNOS4210_MAX_COMBINER_NR \|\| soc_is_exynos5250())
	244	irq = IRQ_SPI(i);
	245	else
	246	irq = exynos4x12_combiner_extra_irq(i);
a900e5d9 RH	247	#ifdef CONFIG_OF
	248	if (np)
	249	irq = irq_of_parse_and_map(np, i);
	250	#endif
df7ef462	251	combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
a900e5d9 RH	252	combiner_cascade_irq(i, irq);
	253	}
	254	}
	255
	256	#ifdef CONFIG_OF
	257	static int __init combiner_of_init(struct device_node *np,
	258	struct device_node *parent)
	259	{
	260	void __iomem *combiner_base;
	261
	262	combiner_base = of_iomap(np, 0);
	263	if (!combiner_base) {
	264	pr_err("%s: failed to map combiner registers\n", __func__);
	265	return -ENXIO;
	266	}
	267
	268	combiner_init(combiner_base, np);
	269
	270	return 0;
	271	}
	272	IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
	273	combiner_of_init);
	274	#endif