[deliverable/linux.git] / drivers / irqchip / irq-armada-370-xp.c

/*
 * Marvell Armada 370 and Armada XP SoC IRQ handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/cpu.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/msi.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>

/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)

#define ARMADA_370_XP_INT_CONTROL		(0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)

#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
#define ARMADA_375_PPI_CAUSE			(0x10)

#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)

#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ	(5)
#define ARMADA_370_XP_FABRIC_IRQ		(3)

#define IPI_DOORBELL_START                      (0)
#define IPI_DOORBELL_END                        (8)
#define IPI_DOORBELL_MASK                       0xFF
#define PCI_MSI_DOORBELL_START                  (16)
#define PCI_MSI_DOORBELL_NR                     (16)
#define PCI_MSI_DOORBELL_END                    (32)
#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000

static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
static u32 doorbell_mask_reg;
static int parent_irq;
#ifdef CONFIG_PCI_MSI
static struct irq_domain *armada_370_xp_msi_domain;
static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

static inline bool is_percpu_irq(irq_hw_number_t irq)
{
	switch (irq) {
	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
	case ARMADA_370_XP_FABRIC_IRQ:
		return true;
	default:
		return false;
	}
}

/*
 * In SMP mode:
 * For shared global interrupts, mask/unmask global enable bit
 * For CPU interrupts, mask/unmask the calling CPU's bit
 */
static void armada_370_xp_irq_mask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_SET_MASK_OFFS);
}

static void armada_370_xp_irq_unmask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

#ifdef CONFIG_PCI_MSI

static int armada_370_xp_alloc_msi(void)
{
	int hwirq;

	mutex_lock(&msi_used_lock);
	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	if (hwirq >= PCI_MSI_DOORBELL_NR)
		hwirq = -ENOSPC;
	else
		set_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);

	return hwirq;
}

static void armada_370_xp_free_msi(int hwirq)
{
	mutex_lock(&msi_used_lock);
	if (!test_bit(hwirq, msi_used))
		pr_err("trying to free unused MSI#%d\n", hwirq);
	else
		clear_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);
}

static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
				       struct pci_dev *pdev,
				       struct msi_desc *desc)
{
	struct msi_msg msg;
	int virq, hwirq;

	/* We support MSI, but not MSI-X */
	if (desc->msi_attrib.is_msix)
		return -EINVAL;

	hwirq = armada_370_xp_alloc_msi();
	if (hwirq < 0)
		return hwirq;

	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	if (!virq) {
		armada_370_xp_free_msi(hwirq);
		return -EINVAL;
	}

	irq_set_msi_desc(virq, desc);

	msg.address_lo = msi_doorbell_addr;
	msg.address_hi = 0;
	msg.data = 0xf00 | (hwirq + 16);

	pci_write_msi_msg(virq, &msg);
	return 0;
}

static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
					   unsigned int irq)
{
	struct irq_data *d = irq_get_irq_data(irq);
	unsigned long hwirq = d->hwirq;

	irq_dispose_mapping(irq);
	armada_370_xp_free_msi(hwirq);
}

static struct irq_chip armada_370_xp_msi_irq_chip = {
	.name = "armada_370_xp_msi_irq",
	.irq_enable = pci_msi_unmask_irq,
	.irq_disable = pci_msi_mask_irq,
	.irq_mask = pci_msi_mask_irq,
	.irq_unmask = pci_msi_unmask_irq,
};

static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
				 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
				 handle_simple_irq);

	return 0;
}

static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	.map = armada_370_xp_msi_map,
};

static int armada_370_xp_msi_init(struct device_node *node,
				  phys_addr_t main_int_phys_base)
{
	struct msi_controller *msi_chip;
	u32 reg;
	int ret;

	msi_doorbell_addr = main_int_phys_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS;

	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	if (!msi_chip)
		return -ENOMEM;

	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	msi_chip->of_node = node;

	armada_370_xp_msi_domain =
		irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
				      &armada_370_xp_msi_irq_ops,
				      NULL);
	if (!armada_370_xp_msi_domain) {
		kfree(msi_chip);
		return -ENOMEM;
	}

	ret = of_pci_msi_chip_add(msi_chip);
	if (ret < 0) {
		irq_domain_remove(armada_370_xp_msi_domain);
		kfree(msi_chip);
		return ret;
	}

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	return 0;
}
#else
static inline int armada_370_xp_msi_init(struct device_node *node,
					 phys_addr_t main_int_phys_base)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
static DEFINE_RAW_SPINLOCK(irq_controller_lock);

static int armada_xp_set_affinity(struct irq_data *d,
				  const struct cpumask *mask_val, bool force)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	unsigned long reg, mask;
	int cpu;

	/* Select a single core from the affinity mask which is online */
	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	mask = 1UL << cpu_logical_map(cpu);

	raw_spin_lock(&irq_controller_lock);
	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	raw_spin_unlock(&irq_controller_lock);

	return IRQ_SET_MASK_OK;
}
#endif

static struct irq_chip armada_370_xp_irq_chip = {
	.name		= "armada_370_xp_irq",
	.irq_mask       = armada_370_xp_irq_mask,
	.irq_mask_ack   = armada_370_xp_irq_mask,
	.irq_unmask     = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = armada_xp_set_affinity,
#endif
	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
};

static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
				      unsigned int virq, irq_hw_number_t hw)
{
	armada_370_xp_irq_mask(irq_get_irq_data(virq));
	if (!is_percpu_irq(hw))
		writel(hw, per_cpu_int_base +
			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	else
		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	irq_set_status_flags(virq, IRQ_LEVEL);

	if (is_percpu_irq(hw)) {
		irq_set_percpu_devid(virq);
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_percpu_devid_irq);

	} else {
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_level_irq);
	}
	irq_set_probe(virq);

	return 0;
}

static void armada_xp_mpic_smp_cpu_init(void)
{
	u32 control;
	int nr_irqs, i;

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);

	/* Clear pending IPIs */
	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	/* Enable first 8 IPIs */
	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

static void armada_xp_mpic_perf_init(void)
{
	unsigned long cpuid = cpu_logical_map(smp_processor_id());

	/* Enable Performance Counter Overflow interrupts */
	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
}

#ifdef CONFIG_SMP
static void armada_mpic_send_doorbell(const struct cpumask *mask,
				      unsigned int irq)
{
	int cpu;
	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */
	for_each_cpu(cpu, mask)
		map |= 1 << cpu_logical_map(cpu);

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	dsb();

	/* submit softirq */
	writel((map << 8) | irq, main_int_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS);
}

static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
					 unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		armada_xp_mpic_smp_cpu_init();
	}

	return NOTIFY_OK;
}

static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	.notifier_call = armada_xp_mpic_secondary_init,
	.priority = 100,
};

static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
					unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
	}

	return NOTIFY_OK;
}

static struct notifier_block mpic_cascaded_cpu_notifier = {
	.notifier_call = mpic_cascaded_secondary_init,
	.priority = 100,
};
#endif /* CONFIG_SMP */

static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	.map = armada_370_xp_mpic_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

#ifdef CONFIG_PCI_MSI
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
{
	u32 msimask, msinr;

	msimask = readl_relaxed(per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
		& PCI_MSI_DOORBELL_MASK;

	writel(~msimask, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	for (msinr = PCI_MSI_DOORBELL_START;
	     msinr < PCI_MSI_DOORBELL_END; msinr++) {
		int irq;

		if (!(msimask & BIT(msinr)))
			continue;

		if (is_chained) {
			irq = irq_find_mapping(armada_370_xp_msi_domain,
					       msinr - 16);
			generic_handle_irq(irq);
		} else {
			irq = msinr - 16;
			handle_domain_irq(armada_370_xp_msi_domain,
					  irq, regs);
		}
	}
}
#else
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
#endif

static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned long irqmap, irqn, irqsrc, cpuid;
	unsigned int cascade_irq;

	chained_irq_enter(chip, desc);

	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
	cpuid = cpu_logical_map(smp_processor_id());

	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
		irqsrc = readl_relaxed(main_int_base +
				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));

		/* Check if the interrupt is not masked on current CPU.
		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
		 */
		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
			continue;

		if (irqn == 1) {
			armada_370_xp_handle_msi_irq(NULL, true);
			continue;
		}

		cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
		generic_handle_irq(cascade_irq);
	}

	chained_irq_exit(chip, desc);
}

static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs *regs)
{
	u32 irqstat, irqnr;

	do {
		irqstat = readl_relaxed(per_cpu_int_base +
					ARMADA_370_XP_CPU_INTACK_OFFS);
		irqnr = irqstat & 0x3FF;

		if (irqnr > 1022)
			break;

		if (irqnr > 1) {
			handle_domain_irq(armada_370_xp_mpic_domain,
					  irqnr, regs);
			continue;
		}

		/* MSI handling */
		if (irqnr == 1)
			armada_370_xp_handle_msi_irq(regs, false);

#ifdef CONFIG_SMP
		/* IPI Handling */
		if (irqnr == 0) {
			u32 ipimask, ipinr;

			ipimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& IPI_DOORBELL_MASK;

			writel(~ipimask, per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			/* Handle all pending doorbells */
			for (ipinr = IPI_DOORBELL_START;
			     ipinr < IPI_DOORBELL_END; ipinr++) {
				if (ipimask & (0x1 << ipinr))
					handle_IPI(ipinr, regs);
			}
			continue;
		}
#endif

	} while (1);
}

static int armada_370_xp_mpic_suspend(void)
{
	doorbell_mask_reg = readl(per_cpu_int_base +
				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	return 0;
}

static void armada_370_xp_mpic_resume(void)
{
	int nirqs;
	irq_hw_number_t irq;

	/* Re-enable interrupts */
	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	for (irq = 0; irq < nirqs; irq++) {
		struct irq_data *data;
		int virq;

		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
		if (virq == 0)
			continue;

		if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
			writel(irq, per_cpu_int_base +
			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
		else
			writel(irq, main_int_base +
			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);

		data = irq_get_irq_data(virq);
		if (!irqd_irq_disabled(data))
			armada_370_xp_irq_unmask(data);
	}

	/* Reconfigure doorbells for IPIs and MSIs */
	writel(doorbell_mask_reg,
	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	.suspend	= armada_370_xp_mpic_suspend,
	.resume		= armada_370_xp_mpic_resume,
};

static int __init armada_370_xp_mpic_of_init(struct device_node *node,
					     struct device_node *parent)
{
	struct resource main_int_res, per_cpu_int_res;
	int nr_irqs, i;
	u32 control;

	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

	BUG_ON(!request_mem_region(main_int_res.start,
				   resource_size(&main_int_res),
				   node->full_name));
	BUG_ON(!request_mem_region(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res),
				   node->full_name));

	main_int_base = ioremap(main_int_res.start,
				resource_size(&main_int_res));
	BUG_ON(!main_int_base);

	per_cpu_int_base = ioremap(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res));
	BUG_ON(!per_cpu_int_base);

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);

	armada_370_xp_mpic_domain =
		irq_domain_add_linear(node, nr_irqs,
				&armada_370_xp_mpic_irq_ops, NULL);

	BUG_ON(!armada_370_xp_mpic_domain);

	/* Setup for the boot CPU */
	armada_xp_mpic_perf_init();
	armada_xp_mpic_smp_cpu_init();

	armada_370_xp_msi_init(node, main_int_res.start);

	parent_irq = irq_of_parse_and_map(node, 0);
	if (parent_irq <= 0) {
		irq_set_default_host(armada_370_xp_mpic_domain);
		set_handle_irq(armada_370_xp_handle_irq);
#ifdef CONFIG_SMP
		set_smp_cross_call(armada_mpic_send_doorbell);
		register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
#endif
	} else {
#ifdef CONFIG_SMP
		register_cpu_notifier(&mpic_cascaded_cpu_notifier);
#endif
		irq_set_chained_handler(parent_irq,
					armada_370_xp_mpic_handle_cascade_irq);
	}

	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);

	return 0;
}

IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Marvell Armada 370 and Armada XP SoC IRQ handling
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
41a83e06	21	#include <linux/irqchip.h>
bc69b8ad	22	#include <linux/irqchip/chained_irq.h>
d7df84b3	23	#include <linux/cpu.h>
9ae6f740 TP	24	#include <linux/io.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_irq.h>
31f614ed	27	#include <linux/of_pci.h>
9ae6f740	28	#include <linux/irqdomain.h>
31f614ed	29	#include <linux/slab.h>
0f077eb5	30	#include <linux/syscore_ops.h>
31f614ed	31	#include <linux/msi.h>
9ae6f740 TP	32	#include <asm/mach/arch.h>
9ae6f740 TP	33	#include <asm/exception.h>
344e873e	34	#include <asm/smp_plat.h>
9339d432 TP	35	#include <asm/mach/irq.h>
9339d432 TP	36
9ae6f740 TP	37	/* Interrupt Controller Registers Map */
	38	#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
	39	#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
28da06df MR	40	#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
28da06df MR	41	#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
9ae6f740	42
f3e16ccd	43	#define ARMADA_370_XP_INT_CONTROL (0x00)
9ae6f740 TP	44	#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
9ae6f740 TP	45	#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
3202bf01	46	#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
8cc3cfc5	47	#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
758e8366	48	#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) \| BIT(8)) << cpuid)
9ae6f740 TP	49
9ae6f740 TP	50	#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
bc69b8ad	51	#define ARMADA_375_PPI_CAUSE (0x10)
9ae6f740	52
344e873e GC	53	#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
	54	#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
	55	#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
	56
3202bf01 GC	57	#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
3202bf01 GC	58
7f23f62f	59	#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
28da06df	60	#define ARMADA_370_XP_FABRIC_IRQ (3)
7f23f62f	61
5ec69017 TP	62	#define IPI_DOORBELL_START (0)
	63	#define IPI_DOORBELL_END (8)
	64	#define IPI_DOORBELL_MASK 0xFF
31f614ed TP	65	#define PCI_MSI_DOORBELL_START (16)
	66	#define PCI_MSI_DOORBELL_NR (16)
	67	#define PCI_MSI_DOORBELL_END (32)
	68	#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
344e873e	69
9ae6f740 TP	70	static void __iomem *per_cpu_int_base;
	71	static void __iomem *main_int_base;
	72	static struct irq_domain *armada_370_xp_mpic_domain;
0f077eb5	73	static u32 doorbell_mask_reg;
5724be84	74	static int parent_irq;
31f614ed TP	75	#ifdef CONFIG_PCI_MSI
	76	static struct irq_domain *armada_370_xp_msi_domain;
	77	static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
	78	static DEFINE_MUTEX(msi_used_lock);
	79	static phys_addr_t msi_doorbell_addr;
	80	#endif
9ae6f740	81
2c299de5 EG	82	static inline bool is_percpu_irq(irq_hw_number_t irq)
	83	{
	84	switch (irq) {
	85	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
28da06df	86	case ARMADA_370_XP_FABRIC_IRQ:
2c299de5 EG	87	return true;
	88	default:
	89	return false;
	90	}
	91	}
	92
3202bf01 GC	93	/*
	94	* In SMP mode:
	95	* For shared global interrupts, mask/unmask global enable bit
097ef18d	96	* For CPU interrupts, mask/unmask the calling CPU's bit
3202bf01	97	*/
9ae6f740 TP	98	static void armada_370_xp_irq_mask(struct irq_data *d)
9ae6f740 TP	99	{
3202bf01 GC	100	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	101
2c299de5	102	if (!is_percpu_irq(hwirq))
3202bf01 GC	103	writel(hwirq, main_int_base +
	104	ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	105	else
	106	writel(hwirq, per_cpu_int_base +
	107	ARMADA_370_XP_INT_SET_MASK_OFFS);
9ae6f740 TP	108	}
	109
	110	static void armada_370_xp_irq_unmask(struct irq_data *d)
	111	{
3202bf01 GC	112	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	113
2c299de5	114	if (!is_percpu_irq(hwirq))
3202bf01 GC	115	writel(hwirq, main_int_base +
	116	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	117	else
	118	writel(hwirq, per_cpu_int_base +
	119	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
9ae6f740 TP	120	}
9ae6f740 TP	121
31f614ed TP	122	#ifdef CONFIG_PCI_MSI
	123
	124	static int armada_370_xp_alloc_msi(void)
	125	{
	126	int hwirq;
	127
	128	mutex_lock(&msi_used_lock);
	129	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	130	if (hwirq >= PCI_MSI_DOORBELL_NR)
	131	hwirq = -ENOSPC;
	132	else
	133	set_bit(hwirq, msi_used);
	134	mutex_unlock(&msi_used_lock);
	135
	136	return hwirq;
	137	}
	138
	139	static void armada_370_xp_free_msi(int hwirq)
	140	{
	141	mutex_lock(&msi_used_lock);
	142	if (!test_bit(hwirq, msi_used))
	143	pr_err("trying to free unused MSI#%d\n", hwirq);
	144	else
	145	clear_bit(hwirq, msi_used);
	146	mutex_unlock(&msi_used_lock);
	147	}
	148
c2791b80	149	static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
31f614ed TP	150	struct pci_dev *pdev,
	151	struct msi_desc *desc)
	152	{
	153	struct msi_msg msg;
da343fc7	154	int virq, hwirq;
31f614ed	155
3930115e AG	156	/* We support MSI, but not MSI-X */
	157	if (desc->msi_attrib.is_msix)
	158	return -EINVAL;
	159
31f614ed TP	160	hwirq = armada_370_xp_alloc_msi();
	161	if (hwirq < 0)
	162	return hwirq;
	163
	164	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	165	if (!virq) {
	166	armada_370_xp_free_msi(hwirq);
	167	return -EINVAL;
	168	}
	169
	170	irq_set_msi_desc(virq, desc);
	171
	172	msg.address_lo = msi_doorbell_addr;
	173	msg.address_hi = 0;
	174	msg.data = 0xf00 \| (hwirq + 16);
	175
83a18912	176	pci_write_msi_msg(virq, &msg);
31f614ed TP	177	return 0;
	178	}
	179
c2791b80	180	static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
31f614ed TP	181	unsigned int irq)
	182	{
	183	struct irq_data *d = irq_get_irq_data(irq);
ff3c6645 NG	184	unsigned long hwirq = d->hwirq;
ff3c6645 NG	185
31f614ed	186	irq_dispose_mapping(irq);
ff3c6645	187	armada_370_xp_free_msi(hwirq);
31f614ed TP	188	}
	189
	190	static struct irq_chip armada_370_xp_msi_irq_chip = {
	191	.name = "armada_370_xp_msi_irq",
280510f1 TG	192	.irq_enable = pci_msi_unmask_irq,
	193	.irq_disable = pci_msi_mask_irq,
	194	.irq_mask = pci_msi_mask_irq,
	195	.irq_unmask = pci_msi_unmask_irq,
31f614ed TP	196	};
	197
	198	static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
	199	irq_hw_number_t hw)
	200	{
	201	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
	202	handle_simple_irq);
31f614ed TP	203
	204	return 0;
	205	}
	206
	207	static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	208	.map = armada_370_xp_msi_map,
	209	};
	210
	211	static int armada_370_xp_msi_init(struct device_node *node,
	212	phys_addr_t main_int_phys_base)
	213	{
c2791b80	214	struct msi_controller *msi_chip;
31f614ed TP	215	u32 reg;
	216	int ret;
	217
	218	msi_doorbell_addr = main_int_phys_base +
	219	ARMADA_370_XP_SW_TRIG_INT_OFFS;
	220
	221	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	222	if (!msi_chip)
	223	return -ENOMEM;
	224
	225	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	226	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	227	msi_chip->of_node = node;
	228
	229	armada_370_xp_msi_domain =
	230	irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
	231	&armada_370_xp_msi_irq_ops,
	232	NULL);
	233	if (!armada_370_xp_msi_domain) {
	234	kfree(msi_chip);
	235	return -ENOMEM;
	236	}
	237
	238	ret = of_pci_msi_chip_add(msi_chip);
	239	if (ret < 0) {
	240	irq_domain_remove(armada_370_xp_msi_domain);
	241	kfree(msi_chip);
	242	return ret;
	243	}
	244
	245	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
	246	\| PCI_MSI_DOORBELL_MASK;
	247
	248	writel(reg, per_cpu_int_base +
	249	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	250
	251	/* Unmask IPI interrupt */
	252	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	253
	254	return 0;
	255	}
	256	#else
	257	static inline int armada_370_xp_msi_init(struct device_node *node,
	258	phys_addr_t main_int_phys_base)
	259	{
	260	return 0;
	261	}
	262	#endif
	263
344e873e	264	#ifdef CONFIG_SMP
19e61d41 AE	265	static DEFINE_RAW_SPINLOCK(irq_controller_lock);
19e61d41 AE	266
344e873e GC	267	static int armada_xp_set_affinity(struct irq_data *d,
	268	const struct cpumask *mask_val, bool force)
	269	{
3202bf01	270	irq_hw_number_t hwirq = irqd_to_hwirq(d);
8cc3cfc5	271	unsigned long reg, mask;
3202bf01 GC	272	int cpu;
3202bf01 GC	273
8cc3cfc5 TG	274	/* Select a single core from the affinity mask which is online */
	275	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	276	mask = 1UL << cpu_logical_map(cpu);
3202bf01 GC	277
3202bf01 GC	278	raw_spin_lock(&irq_controller_lock);
3202bf01	279	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
8cc3cfc5	280	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) \| mask;
3202bf01	281	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
3202bf01 GC	282	raw_spin_unlock(&irq_controller_lock);
3202bf01 GC	283
1dacf194	284	return IRQ_SET_MASK_OK;
344e873e GC	285	}
	286	#endif
	287
9ae6f740 TP	288	static struct irq_chip armada_370_xp_irq_chip = {
	289	.name = "armada_370_xp_irq",
	290	.irq_mask = armada_370_xp_irq_mask,
	291	.irq_mask_ack = armada_370_xp_irq_mask,
	292	.irq_unmask = armada_370_xp_irq_unmask,
344e873e GC	293	#ifdef CONFIG_SMP
	294	.irq_set_affinity = armada_xp_set_affinity,
	295	#endif
0d8e1d80	296	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
9ae6f740 TP	297	};
	298
	299	static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
	300	unsigned int virq, irq_hw_number_t hw)
	301	{
	302	armada_370_xp_irq_mask(irq_get_irq_data(virq));
2c299de5	303	if (!is_percpu_irq(hw))
600468d0 GC	304	writel(hw, per_cpu_int_base +
	305	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	306	else
	307	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
9ae6f740	308	irq_set_status_flags(virq, IRQ_LEVEL);
3a6f08a3	309
2c299de5	310	if (is_percpu_irq(hw)) {
3a6f08a3 GC	311	irq_set_percpu_devid(virq);
	312	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	313	handle_percpu_devid_irq);
	314
	315	} else {
	316	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	317	handle_level_irq);
	318	}
d17cab44	319	irq_set_probe(virq);
9ae6f740 TP	320
	321	return 0;
	322	}
	323
d7df84b3	324	static void armada_xp_mpic_smp_cpu_init(void)
344e873e	325	{
b73842b7 TP	326	u32 control;
	327	int nr_irqs, i;
	328
	329	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	330	nr_irqs = (control >> 2) & 0x3ff;
	331
	332	for (i = 0; i < nr_irqs; i++)
	333	writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
	334
344e873e GC	335	/* Clear pending IPIs */
	336	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	337
	338	/* Enable first 8 IPIs */
5ec69017	339	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	340	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	341
	342	/* Unmask IPI interrupt */
	343	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	344	}
d7df84b3	345
28da06df MR	346	static void armada_xp_mpic_perf_init(void)
	347	{
	348	unsigned long cpuid = cpu_logical_map(smp_processor_id());
	349
	350	/* Enable Performance Counter Overflow interrupts */
	351	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	352	per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
	353	}
	354
933a24b0 EG	355	#ifdef CONFIG_SMP
	356	static void armada_mpic_send_doorbell(const struct cpumask *mask,
	357	unsigned int irq)
	358	{
	359	int cpu;
	360	unsigned long map = 0;
	361
	362	/* Convert our logical CPU mask into a physical one. */
	363	for_each_cpu(cpu, mask)
	364	map \|= 1 << cpu_logical_map(cpu);
	365
	366	/*
	367	* Ensure that stores to Normal memory are visible to the
	368	* other CPUs before issuing the IPI.
	369	*/
	370	dsb();
	371
	372	/* submit softirq */
	373	writel((map << 8) \| irq, main_int_base +
	374	ARMADA_370_XP_SW_TRIG_INT_OFFS);
	375	}
	376
d7df84b3 TP	377	static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
	378	unsigned long action, void *hcpu)
	379	{
28da06df MR	380	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	381	armada_xp_mpic_perf_init();
d7df84b3	382	armada_xp_mpic_smp_cpu_init();
28da06df	383	}
5724be84	384
d7df84b3 TP	385	return NOTIFY_OK;
	386	}
	387
	388	static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	389	.notifier_call = armada_xp_mpic_secondary_init,
	390	.priority = 100,
	391	};
	392
5724be84 MR	393	static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
	394	unsigned long action, void *hcpu)
	395	{
28da06df MR	396	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	397	armada_xp_mpic_perf_init();
5724be84	398	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
28da06df	399	}
5724be84 MR	400
	401	return NOTIFY_OK;
	402	}
	403
	404	static struct notifier_block mpic_cascaded_cpu_notifier = {
	405	.notifier_call = mpic_cascaded_secondary_init,
	406	.priority = 100,
	407	};
344e873e GC	408	#endif /* CONFIG_SMP */
344e873e GC	409
96009736	410	static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
9ae6f740 TP	411	.map = armada_370_xp_mpic_irq_map,
	412	.xlate = irq_domain_xlate_onecell,
	413	};
	414
9b8cf779	415	#ifdef CONFIG_PCI_MSI
bc69b8ad	416	static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
9b8cf779 EG	417	{
	418	u32 msimask, msinr;
	419
	420	msimask = readl_relaxed(per_cpu_int_base +
	421	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
	422	& PCI_MSI_DOORBELL_MASK;
	423
	424	writel(~msimask, per_cpu_int_base +
	425	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	426
	427	for (msinr = PCI_MSI_DOORBELL_START;
	428	msinr < PCI_MSI_DOORBELL_END; msinr++) {
	429	int irq;
	430
	431	if (!(msimask & BIT(msinr)))
	432	continue;
	433
e89c6a06 MZ	434	if (is_chained) {
	435	irq = irq_find_mapping(armada_370_xp_msi_domain,
	436	msinr - 16);
bc69b8ad	437	generic_handle_irq(irq);
e89c6a06 MZ	438	} else {
	439	irq = msinr - 16;
	440	handle_domain_irq(armada_370_xp_msi_domain,
	441	irq, regs);
	442	}
9b8cf779 EG	443	}
	444	}
	445	#else
bc69b8ad	446	static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
9b8cf779 EG	447	#endif
9b8cf779 EG	448
bd0b9ac4	449	static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
bc69b8ad	450	{
5b29264c	451	struct irq_chip *chip = irq_desc_get_chip(desc);
758e8366	452	unsigned long irqmap, irqn, irqsrc, cpuid;
bc69b8ad EG	453	unsigned int cascade_irq;
	454
	455	chained_irq_enter(chip, desc);
	456
	457	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
758e8366	458	cpuid = cpu_logical_map(smp_processor_id());
bc69b8ad EG	459
bc69b8ad EG	460	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
758e8366 GJ	461	irqsrc = readl_relaxed(main_int_base +
	462	ARMADA_370_XP_INT_SOURCE_CTL(irqn));
	463
	464	/* Check if the interrupt is not masked on current CPU.
	465	* Test IRQ (0-1) and FIQ (8-9) mask bits.
	466	*/
	467	if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
	468	continue;
	469
	470	if (irqn == 1) {
	471	armada_370_xp_handle_msi_irq(NULL, true);
	472	continue;
	473	}
	474
bc69b8ad EG	475	cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
	476	generic_handle_irq(cascade_irq);
	477	}
	478
	479	chained_irq_exit(chip, desc);
	480	}
	481
8783dd3a	482	static void __exception_irq_entry
9339d432	483	armada_370_xp_handle_irq(struct pt_regs *regs)
9ae6f740 TP	484	{
	485	u32 irqstat, irqnr;
	486
	487	do {
	488	irqstat = readl_relaxed(per_cpu_int_base +
	489	ARMADA_370_XP_CPU_INTACK_OFFS);
	490	irqnr = irqstat & 0x3FF;
	491
344e873e GC	492	if (irqnr > 1022)
	493	break;
	494
31f614ed	495	if (irqnr > 1) {
e89c6a06 MZ	496	handle_domain_irq(armada_370_xp_mpic_domain,
e89c6a06 MZ	497	irqnr, regs);
9ae6f740 TP	498	continue;
9ae6f740 TP	499	}
31f614ed	500
31f614ed	501	/* MSI handling */
9b8cf779	502	if (irqnr == 1)
bc69b8ad	503	armada_370_xp_handle_msi_irq(regs, false);
31f614ed	504
344e873e GC	505	#ifdef CONFIG_SMP
	506	/* IPI Handling */
	507	if (irqnr == 0) {
	508	u32 ipimask, ipinr;
	509
	510	ipimask = readl_relaxed(per_cpu_int_base +
	511	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
5ec69017	512	& IPI_DOORBELL_MASK;
344e873e	513
a6f089e9	514	writel(~ipimask, per_cpu_int_base +
344e873e GC	515	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	516
	517	/* Handle all pending doorbells */
5ec69017 TP	518	for (ipinr = IPI_DOORBELL_START;
5ec69017 TP	519	ipinr < IPI_DOORBELL_END; ipinr++) {
344e873e GC	520	if (ipimask & (0x1 << ipinr))
	521	handle_IPI(ipinr, regs);
	522	}
	523	continue;
	524	}
	525	#endif
9ae6f740	526
9ae6f740 TP	527	} while (1);
	528	}
	529
0f077eb5 TP	530	static int armada_370_xp_mpic_suspend(void)
	531	{
	532	doorbell_mask_reg = readl(per_cpu_int_base +
	533	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	534	return 0;
	535	}
	536
	537	static void armada_370_xp_mpic_resume(void)
	538	{
	539	int nirqs;
	540	irq_hw_number_t irq;
	541
	542	/* Re-enable interrupts */
	543	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	544	for (irq = 0; irq < nirqs; irq++) {
	545	struct irq_data *data;
	546	int virq;
	547
	548	virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
	549	if (virq == 0)
	550	continue;
	551
	552	if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
	553	writel(irq, per_cpu_int_base +
	554	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	555	else
	556	writel(irq, main_int_base +
	557	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	558
	559	data = irq_get_irq_data(virq);
	560	if (!irqd_irq_disabled(data))
	561	armada_370_xp_irq_unmask(data);
	562	}
	563
	564	/* Reconfigure doorbells for IPIs and MSIs */
	565	writel(doorbell_mask_reg,
	566	per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	567	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
	568	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	569	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
	570	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	571	}
	572
	573	struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	574	.suspend = armada_370_xp_mpic_suspend,
	575	.resume = armada_370_xp_mpic_resume,
	576	};
	577
b313ada8 TP	578	static int __init armada_370_xp_mpic_of_init(struct device_node *node,
b313ada8 TP	579	struct device_node *parent)
9ae6f740	580	{
627dfcc2	581	struct resource main_int_res, per_cpu_int_res;
5724be84	582	int nr_irqs, i;
b313ada8 TP	583	u32 control;
b313ada8 TP	584
627dfcc2 TP	585	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
627dfcc2 TP	586	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
b313ada8	587
627dfcc2 TP	588	BUG_ON(!request_mem_region(main_int_res.start,
	589	resource_size(&main_int_res),
	590	node->full_name));
	591	BUG_ON(!request_mem_region(per_cpu_int_res.start,
	592	resource_size(&per_cpu_int_res),
	593	node->full_name));
	594
	595	main_int_base = ioremap(main_int_res.start,
	596	resource_size(&main_int_res));
b313ada8	597	BUG_ON(!main_int_base);
627dfcc2 TP	598
	599	per_cpu_int_base = ioremap(per_cpu_int_res.start,
	600	resource_size(&per_cpu_int_res));
b313ada8 TP	601	BUG_ON(!per_cpu_int_base);
	602
	603	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
b73842b7 TP	604	nr_irqs = (control >> 2) & 0x3ff;
	605
	606	for (i = 0; i < nr_irqs; i++)
	607	writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
b313ada8 TP	608
b313ada8 TP	609	armada_370_xp_mpic_domain =
b73842b7	610	irq_domain_add_linear(node, nr_irqs,
b313ada8 TP	611	&armada_370_xp_mpic_irq_ops, NULL);
b313ada8 TP	612
627dfcc2	613	BUG_ON(!armada_370_xp_mpic_domain);
b313ada8	614
933a24b0	615	/* Setup for the boot CPU */
28da06df	616	armada_xp_mpic_perf_init();
b313ada8	617	armada_xp_mpic_smp_cpu_init();
b313ada8	618
31f614ed TP	619	armada_370_xp_msi_init(node, main_int_res.start);
31f614ed TP	620
bc69b8ad EG	621	parent_irq = irq_of_parse_and_map(node, 0);
	622	if (parent_irq <= 0) {
	623	irq_set_default_host(armada_370_xp_mpic_domain);
	624	set_handle_irq(armada_370_xp_handle_irq);
ef37d337 TP	625	#ifdef CONFIG_SMP
ef37d337 TP	626	set_smp_cross_call(armada_mpic_send_doorbell);
d7df84b3	627	register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
ef37d337	628	#endif
bc69b8ad	629	} else {
5724be84 MR	630	#ifdef CONFIG_SMP
	631	register_cpu_notifier(&mpic_cascaded_cpu_notifier);
	632	#endif
bc69b8ad EG	633	irq_set_chained_handler(parent_irq,
	634	armada_370_xp_mpic_handle_cascade_irq);
	635	}
b313ada8	636
0f077eb5 TP	637	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
0f077eb5 TP	638
b313ada8	639	return 0;
9ae6f740	640	}
b313ada8	641
9339d432	642	IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);