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9ae6f740 TP |
1 | /* |
2 | * Marvell Armada 370 and Armada XP SoC IRQ handling | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/interrupt.h> | |
bc69b8ad | 21 | #include <linux/irqchip/chained_irq.h> |
d7df84b3 | 22 | #include <linux/cpu.h> |
9ae6f740 TP |
23 | #include <linux/io.h> |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
31f614ed | 26 | #include <linux/of_pci.h> |
9ae6f740 | 27 | #include <linux/irqdomain.h> |
31f614ed TP |
28 | #include <linux/slab.h> |
29 | #include <linux/msi.h> | |
9ae6f740 TP |
30 | #include <asm/mach/arch.h> |
31 | #include <asm/exception.h> | |
344e873e | 32 | #include <asm/smp_plat.h> |
9339d432 TP |
33 | #include <asm/mach/irq.h> |
34 | ||
35 | #include "irqchip.h" | |
9ae6f740 TP |
36 | |
37 | /* Interrupt Controller Registers Map */ | |
38 | #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) | |
39 | #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) | |
40 | ||
f3e16ccd | 41 | #define ARMADA_370_XP_INT_CONTROL (0x00) |
9ae6f740 TP |
42 | #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) |
43 | #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) | |
3202bf01 | 44 | #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) |
8cc3cfc5 | 45 | #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF |
9ae6f740 TP |
46 | |
47 | #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) | |
bc69b8ad | 48 | #define ARMADA_375_PPI_CAUSE (0x10) |
9ae6f740 | 49 | |
344e873e GC |
50 | #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) |
51 | #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) | |
52 | #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) | |
53 | ||
3202bf01 GC |
54 | #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) |
55 | ||
7f23f62f GC |
56 | #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) |
57 | ||
5ec69017 TP |
58 | #define IPI_DOORBELL_START (0) |
59 | #define IPI_DOORBELL_END (8) | |
60 | #define IPI_DOORBELL_MASK 0xFF | |
31f614ed TP |
61 | #define PCI_MSI_DOORBELL_START (16) |
62 | #define PCI_MSI_DOORBELL_NR (16) | |
63 | #define PCI_MSI_DOORBELL_END (32) | |
64 | #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 | |
344e873e | 65 | |
9ae6f740 TP |
66 | static void __iomem *per_cpu_int_base; |
67 | static void __iomem *main_int_base; | |
68 | static struct irq_domain *armada_370_xp_mpic_domain; | |
31f614ed TP |
69 | #ifdef CONFIG_PCI_MSI |
70 | static struct irq_domain *armada_370_xp_msi_domain; | |
71 | static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); | |
72 | static DEFINE_MUTEX(msi_used_lock); | |
73 | static phys_addr_t msi_doorbell_addr; | |
74 | #endif | |
9ae6f740 | 75 | |
3202bf01 GC |
76 | /* |
77 | * In SMP mode: | |
78 | * For shared global interrupts, mask/unmask global enable bit | |
097ef18d | 79 | * For CPU interrupts, mask/unmask the calling CPU's bit |
3202bf01 | 80 | */ |
9ae6f740 TP |
81 | static void armada_370_xp_irq_mask(struct irq_data *d) |
82 | { | |
3202bf01 GC |
83 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
84 | ||
7f23f62f | 85 | if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) |
3202bf01 GC |
86 | writel(hwirq, main_int_base + |
87 | ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); | |
88 | else | |
89 | writel(hwirq, per_cpu_int_base + | |
90 | ARMADA_370_XP_INT_SET_MASK_OFFS); | |
9ae6f740 TP |
91 | } |
92 | ||
93 | static void armada_370_xp_irq_unmask(struct irq_data *d) | |
94 | { | |
3202bf01 GC |
95 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
96 | ||
7f23f62f | 97 | if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) |
3202bf01 GC |
98 | writel(hwirq, main_int_base + |
99 | ARMADA_370_XP_INT_SET_ENABLE_OFFS); | |
100 | else | |
101 | writel(hwirq, per_cpu_int_base + | |
102 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
9ae6f740 TP |
103 | } |
104 | ||
31f614ed TP |
105 | #ifdef CONFIG_PCI_MSI |
106 | ||
107 | static int armada_370_xp_alloc_msi(void) | |
108 | { | |
109 | int hwirq; | |
110 | ||
111 | mutex_lock(&msi_used_lock); | |
112 | hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR); | |
113 | if (hwirq >= PCI_MSI_DOORBELL_NR) | |
114 | hwirq = -ENOSPC; | |
115 | else | |
116 | set_bit(hwirq, msi_used); | |
117 | mutex_unlock(&msi_used_lock); | |
118 | ||
119 | return hwirq; | |
120 | } | |
121 | ||
122 | static void armada_370_xp_free_msi(int hwirq) | |
123 | { | |
124 | mutex_lock(&msi_used_lock); | |
125 | if (!test_bit(hwirq, msi_used)) | |
126 | pr_err("trying to free unused MSI#%d\n", hwirq); | |
127 | else | |
128 | clear_bit(hwirq, msi_used); | |
129 | mutex_unlock(&msi_used_lock); | |
130 | } | |
131 | ||
c2791b80 | 132 | static int armada_370_xp_setup_msi_irq(struct msi_controller *chip, |
31f614ed TP |
133 | struct pci_dev *pdev, |
134 | struct msi_desc *desc) | |
135 | { | |
136 | struct msi_msg msg; | |
da343fc7 | 137 | int virq, hwirq; |
31f614ed | 138 | |
3930115e AG |
139 | /* We support MSI, but not MSI-X */ |
140 | if (desc->msi_attrib.is_msix) | |
141 | return -EINVAL; | |
142 | ||
31f614ed TP |
143 | hwirq = armada_370_xp_alloc_msi(); |
144 | if (hwirq < 0) | |
145 | return hwirq; | |
146 | ||
147 | virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq); | |
148 | if (!virq) { | |
149 | armada_370_xp_free_msi(hwirq); | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
153 | irq_set_msi_desc(virq, desc); | |
154 | ||
155 | msg.address_lo = msi_doorbell_addr; | |
156 | msg.address_hi = 0; | |
157 | msg.data = 0xf00 | (hwirq + 16); | |
158 | ||
159 | write_msi_msg(virq, &msg); | |
160 | return 0; | |
161 | } | |
162 | ||
c2791b80 | 163 | static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip, |
31f614ed TP |
164 | unsigned int irq) |
165 | { | |
166 | struct irq_data *d = irq_get_irq_data(irq); | |
ff3c6645 NG |
167 | unsigned long hwirq = d->hwirq; |
168 | ||
31f614ed | 169 | irq_dispose_mapping(irq); |
ff3c6645 | 170 | armada_370_xp_free_msi(hwirq); |
31f614ed TP |
171 | } |
172 | ||
173 | static struct irq_chip armada_370_xp_msi_irq_chip = { | |
174 | .name = "armada_370_xp_msi_irq", | |
175 | .irq_enable = unmask_msi_irq, | |
176 | .irq_disable = mask_msi_irq, | |
177 | .irq_mask = mask_msi_irq, | |
178 | .irq_unmask = unmask_msi_irq, | |
179 | }; | |
180 | ||
181 | static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq, | |
182 | irq_hw_number_t hw) | |
183 | { | |
184 | irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip, | |
185 | handle_simple_irq); | |
186 | set_irq_flags(virq, IRQF_VALID); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static const struct irq_domain_ops armada_370_xp_msi_irq_ops = { | |
192 | .map = armada_370_xp_msi_map, | |
193 | }; | |
194 | ||
195 | static int armada_370_xp_msi_init(struct device_node *node, | |
196 | phys_addr_t main_int_phys_base) | |
197 | { | |
c2791b80 | 198 | struct msi_controller *msi_chip; |
31f614ed TP |
199 | u32 reg; |
200 | int ret; | |
201 | ||
202 | msi_doorbell_addr = main_int_phys_base + | |
203 | ARMADA_370_XP_SW_TRIG_INT_OFFS; | |
204 | ||
205 | msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL); | |
206 | if (!msi_chip) | |
207 | return -ENOMEM; | |
208 | ||
209 | msi_chip->setup_irq = armada_370_xp_setup_msi_irq; | |
210 | msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; | |
211 | msi_chip->of_node = node; | |
212 | ||
213 | armada_370_xp_msi_domain = | |
214 | irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, | |
215 | &armada_370_xp_msi_irq_ops, | |
216 | NULL); | |
217 | if (!armada_370_xp_msi_domain) { | |
218 | kfree(msi_chip); | |
219 | return -ENOMEM; | |
220 | } | |
221 | ||
222 | ret = of_pci_msi_chip_add(msi_chip); | |
223 | if (ret < 0) { | |
224 | irq_domain_remove(armada_370_xp_msi_domain); | |
225 | kfree(msi_chip); | |
226 | return ret; | |
227 | } | |
228 | ||
229 | reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) | |
230 | | PCI_MSI_DOORBELL_MASK; | |
231 | ||
232 | writel(reg, per_cpu_int_base + | |
233 | ARMADA_370_XP_IN_DRBEL_MSK_OFFS); | |
234 | ||
235 | /* Unmask IPI interrupt */ | |
236 | writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
237 | ||
238 | return 0; | |
239 | } | |
240 | #else | |
241 | static inline int armada_370_xp_msi_init(struct device_node *node, | |
242 | phys_addr_t main_int_phys_base) | |
243 | { | |
244 | return 0; | |
245 | } | |
246 | #endif | |
247 | ||
344e873e | 248 | #ifdef CONFIG_SMP |
19e61d41 AE |
249 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
250 | ||
344e873e GC |
251 | static int armada_xp_set_affinity(struct irq_data *d, |
252 | const struct cpumask *mask_val, bool force) | |
253 | { | |
3202bf01 | 254 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
8cc3cfc5 | 255 | unsigned long reg, mask; |
3202bf01 GC |
256 | int cpu; |
257 | ||
8cc3cfc5 TG |
258 | /* Select a single core from the affinity mask which is online */ |
259 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
260 | mask = 1UL << cpu_logical_map(cpu); | |
3202bf01 GC |
261 | |
262 | raw_spin_lock(&irq_controller_lock); | |
3202bf01 | 263 | reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); |
8cc3cfc5 | 264 | reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; |
3202bf01 | 265 | writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); |
3202bf01 GC |
266 | raw_spin_unlock(&irq_controller_lock); |
267 | ||
344e873e GC |
268 | return 0; |
269 | } | |
270 | #endif | |
271 | ||
9ae6f740 TP |
272 | static struct irq_chip armada_370_xp_irq_chip = { |
273 | .name = "armada_370_xp_irq", | |
274 | .irq_mask = armada_370_xp_irq_mask, | |
275 | .irq_mask_ack = armada_370_xp_irq_mask, | |
276 | .irq_unmask = armada_370_xp_irq_unmask, | |
344e873e GC |
277 | #ifdef CONFIG_SMP |
278 | .irq_set_affinity = armada_xp_set_affinity, | |
279 | #endif | |
9ae6f740 TP |
280 | }; |
281 | ||
282 | static int armada_370_xp_mpic_irq_map(struct irq_domain *h, | |
283 | unsigned int virq, irq_hw_number_t hw) | |
284 | { | |
285 | armada_370_xp_irq_mask(irq_get_irq_data(virq)); | |
600468d0 GC |
286 | if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) |
287 | writel(hw, per_cpu_int_base + | |
288 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
289 | else | |
290 | writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); | |
9ae6f740 | 291 | irq_set_status_flags(virq, IRQ_LEVEL); |
3a6f08a3 | 292 | |
7f23f62f | 293 | if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { |
3a6f08a3 GC |
294 | irq_set_percpu_devid(virq); |
295 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | |
296 | handle_percpu_devid_irq); | |
297 | ||
298 | } else { | |
299 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | |
300 | handle_level_irq); | |
301 | } | |
9ae6f740 TP |
302 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
344e873e | 307 | #ifdef CONFIG_SMP |
ef37d337 TP |
308 | static void armada_mpic_send_doorbell(const struct cpumask *mask, |
309 | unsigned int irq) | |
344e873e GC |
310 | { |
311 | int cpu; | |
312 | unsigned long map = 0; | |
313 | ||
314 | /* Convert our logical CPU mask into a physical one. */ | |
315 | for_each_cpu(cpu, mask) | |
316 | map |= 1 << cpu_logical_map(cpu); | |
317 | ||
318 | /* | |
319 | * Ensure that stores to Normal memory are visible to the | |
320 | * other CPUs before issuing the IPI. | |
321 | */ | |
322 | dsb(); | |
323 | ||
324 | /* submit softirq */ | |
325 | writel((map << 8) | irq, main_int_base + | |
326 | ARMADA_370_XP_SW_TRIG_INT_OFFS); | |
327 | } | |
328 | ||
d7df84b3 | 329 | static void armada_xp_mpic_smp_cpu_init(void) |
344e873e | 330 | { |
b73842b7 TP |
331 | u32 control; |
332 | int nr_irqs, i; | |
333 | ||
334 | control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); | |
335 | nr_irqs = (control >> 2) & 0x3ff; | |
336 | ||
337 | for (i = 0; i < nr_irqs; i++) | |
338 | writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); | |
339 | ||
344e873e GC |
340 | /* Clear pending IPIs */ |
341 | writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); | |
342 | ||
343 | /* Enable first 8 IPIs */ | |
5ec69017 | 344 | writel(IPI_DOORBELL_MASK, per_cpu_int_base + |
344e873e GC |
345 | ARMADA_370_XP_IN_DRBEL_MSK_OFFS); |
346 | ||
347 | /* Unmask IPI interrupt */ | |
348 | writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
349 | } | |
d7df84b3 TP |
350 | |
351 | static int armada_xp_mpic_secondary_init(struct notifier_block *nfb, | |
352 | unsigned long action, void *hcpu) | |
353 | { | |
354 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
355 | armada_xp_mpic_smp_cpu_init(); | |
356 | return NOTIFY_OK; | |
357 | } | |
358 | ||
359 | static struct notifier_block armada_370_xp_mpic_cpu_notifier = { | |
360 | .notifier_call = armada_xp_mpic_secondary_init, | |
361 | .priority = 100, | |
362 | }; | |
363 | ||
344e873e GC |
364 | #endif /* CONFIG_SMP */ |
365 | ||
9ae6f740 TP |
366 | static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { |
367 | .map = armada_370_xp_mpic_irq_map, | |
368 | .xlate = irq_domain_xlate_onecell, | |
369 | }; | |
370 | ||
9b8cf779 | 371 | #ifdef CONFIG_PCI_MSI |
bc69b8ad | 372 | static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) |
9b8cf779 EG |
373 | { |
374 | u32 msimask, msinr; | |
375 | ||
376 | msimask = readl_relaxed(per_cpu_int_base + | |
377 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) | |
378 | & PCI_MSI_DOORBELL_MASK; | |
379 | ||
380 | writel(~msimask, per_cpu_int_base + | |
381 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); | |
382 | ||
383 | for (msinr = PCI_MSI_DOORBELL_START; | |
384 | msinr < PCI_MSI_DOORBELL_END; msinr++) { | |
385 | int irq; | |
386 | ||
387 | if (!(msimask & BIT(msinr))) | |
388 | continue; | |
389 | ||
e89c6a06 MZ |
390 | if (is_chained) { |
391 | irq = irq_find_mapping(armada_370_xp_msi_domain, | |
392 | msinr - 16); | |
bc69b8ad | 393 | generic_handle_irq(irq); |
e89c6a06 MZ |
394 | } else { |
395 | irq = msinr - 16; | |
396 | handle_domain_irq(armada_370_xp_msi_domain, | |
397 | irq, regs); | |
398 | } | |
9b8cf779 EG |
399 | } |
400 | } | |
401 | #else | |
bc69b8ad | 402 | static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} |
9b8cf779 EG |
403 | #endif |
404 | ||
bc69b8ad EG |
405 | static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq, |
406 | struct irq_desc *desc) | |
407 | { | |
408 | struct irq_chip *chip = irq_get_chip(irq); | |
409 | unsigned long irqmap, irqn; | |
410 | unsigned int cascade_irq; | |
411 | ||
412 | chained_irq_enter(chip, desc); | |
413 | ||
414 | irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); | |
415 | ||
416 | if (irqmap & BIT(0)) { | |
417 | armada_370_xp_handle_msi_irq(NULL, true); | |
418 | irqmap &= ~BIT(0); | |
419 | } | |
420 | ||
421 | for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { | |
422 | cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn); | |
423 | generic_handle_irq(cascade_irq); | |
424 | } | |
425 | ||
426 | chained_irq_exit(chip, desc); | |
427 | } | |
428 | ||
8783dd3a | 429 | static void __exception_irq_entry |
9339d432 | 430 | armada_370_xp_handle_irq(struct pt_regs *regs) |
9ae6f740 TP |
431 | { |
432 | u32 irqstat, irqnr; | |
433 | ||
434 | do { | |
435 | irqstat = readl_relaxed(per_cpu_int_base + | |
436 | ARMADA_370_XP_CPU_INTACK_OFFS); | |
437 | irqnr = irqstat & 0x3FF; | |
438 | ||
344e873e GC |
439 | if (irqnr > 1022) |
440 | break; | |
441 | ||
31f614ed | 442 | if (irqnr > 1) { |
e89c6a06 MZ |
443 | handle_domain_irq(armada_370_xp_mpic_domain, |
444 | irqnr, regs); | |
9ae6f740 TP |
445 | continue; |
446 | } | |
31f614ed | 447 | |
31f614ed | 448 | /* MSI handling */ |
9b8cf779 | 449 | if (irqnr == 1) |
bc69b8ad | 450 | armada_370_xp_handle_msi_irq(regs, false); |
31f614ed | 451 | |
344e873e GC |
452 | #ifdef CONFIG_SMP |
453 | /* IPI Handling */ | |
454 | if (irqnr == 0) { | |
455 | u32 ipimask, ipinr; | |
456 | ||
457 | ipimask = readl_relaxed(per_cpu_int_base + | |
458 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) | |
5ec69017 | 459 | & IPI_DOORBELL_MASK; |
344e873e | 460 | |
a6f089e9 | 461 | writel(~ipimask, per_cpu_int_base + |
344e873e GC |
462 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); |
463 | ||
464 | /* Handle all pending doorbells */ | |
5ec69017 TP |
465 | for (ipinr = IPI_DOORBELL_START; |
466 | ipinr < IPI_DOORBELL_END; ipinr++) { | |
344e873e GC |
467 | if (ipimask & (0x1 << ipinr)) |
468 | handle_IPI(ipinr, regs); | |
469 | } | |
470 | continue; | |
471 | } | |
472 | #endif | |
9ae6f740 | 473 | |
9ae6f740 TP |
474 | } while (1); |
475 | } | |
476 | ||
b313ada8 TP |
477 | static int __init armada_370_xp_mpic_of_init(struct device_node *node, |
478 | struct device_node *parent) | |
9ae6f740 | 479 | { |
627dfcc2 | 480 | struct resource main_int_res, per_cpu_int_res; |
b73842b7 | 481 | int parent_irq, nr_irqs, i; |
b313ada8 TP |
482 | u32 control; |
483 | ||
627dfcc2 TP |
484 | BUG_ON(of_address_to_resource(node, 0, &main_int_res)); |
485 | BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res)); | |
b313ada8 | 486 | |
627dfcc2 TP |
487 | BUG_ON(!request_mem_region(main_int_res.start, |
488 | resource_size(&main_int_res), | |
489 | node->full_name)); | |
490 | BUG_ON(!request_mem_region(per_cpu_int_res.start, | |
491 | resource_size(&per_cpu_int_res), | |
492 | node->full_name)); | |
493 | ||
494 | main_int_base = ioremap(main_int_res.start, | |
495 | resource_size(&main_int_res)); | |
b313ada8 | 496 | BUG_ON(!main_int_base); |
627dfcc2 TP |
497 | |
498 | per_cpu_int_base = ioremap(per_cpu_int_res.start, | |
499 | resource_size(&per_cpu_int_res)); | |
b313ada8 TP |
500 | BUG_ON(!per_cpu_int_base); |
501 | ||
502 | control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); | |
b73842b7 TP |
503 | nr_irqs = (control >> 2) & 0x3ff; |
504 | ||
505 | for (i = 0; i < nr_irqs; i++) | |
506 | writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); | |
b313ada8 TP |
507 | |
508 | armada_370_xp_mpic_domain = | |
b73842b7 | 509 | irq_domain_add_linear(node, nr_irqs, |
b313ada8 TP |
510 | &armada_370_xp_mpic_irq_ops, NULL); |
511 | ||
627dfcc2 | 512 | BUG_ON(!armada_370_xp_mpic_domain); |
b313ada8 | 513 | |
b313ada8 TP |
514 | #ifdef CONFIG_SMP |
515 | armada_xp_mpic_smp_cpu_init(); | |
d792b1e9 | 516 | #endif |
b313ada8 | 517 | |
31f614ed TP |
518 | armada_370_xp_msi_init(node, main_int_res.start); |
519 | ||
bc69b8ad EG |
520 | parent_irq = irq_of_parse_and_map(node, 0); |
521 | if (parent_irq <= 0) { | |
522 | irq_set_default_host(armada_370_xp_mpic_domain); | |
523 | set_handle_irq(armada_370_xp_handle_irq); | |
ef37d337 TP |
524 | #ifdef CONFIG_SMP |
525 | set_smp_cross_call(armada_mpic_send_doorbell); | |
d7df84b3 | 526 | register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier); |
ef37d337 | 527 | #endif |
bc69b8ad EG |
528 | } else { |
529 | irq_set_chained_handler(parent_irq, | |
530 | armada_370_xp_mpic_handle_cascade_irq); | |
531 | } | |
b313ada8 TP |
532 | |
533 | return 0; | |
9ae6f740 | 534 | } |
b313ada8 | 535 | |
9339d432 | 536 | IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); |