[deliverable/linux.git] / drivers / irqchip / irq-atmel-aic.c

/*
 * Atmel AT91 AIC (Advanced Interrupt Controller) driver
 *
 *  Copyright (C) 2004 SAN People
 *  Copyright (C) 2004 ATMEL
 *  Copyright (C) Rick Bronson
 *  Copyright (C) 2014 Free Electrons
 *
 *  Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/bitmap.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>

#include "irq-atmel-aic-common.h"
#include "irqchip.h"

/* Number of irq lines managed by AIC */
#define NR_AIC_IRQS	32

#define AT91_AIC_SMR(n)			((n) * 4)

#define AT91_AIC_SVR(n)			(0x80 + ((n) * 4))
#define AT91_AIC_IVR			0x100
#define AT91_AIC_FVR			0x104
#define AT91_AIC_ISR			0x108

#define AT91_AIC_IPR			0x10c
#define AT91_AIC_IMR			0x110
#define AT91_AIC_CISR			0x114

#define AT91_AIC_IECR			0x120
#define AT91_AIC_IDCR			0x124
#define AT91_AIC_ICCR			0x128
#define AT91_AIC_ISCR			0x12c
#define AT91_AIC_EOICR			0x130
#define AT91_AIC_SPU			0x134
#define AT91_AIC_DCR			0x138

static struct irq_domain *aic_domain;

static asmlinkage void __exception_irq_entry
aic_handle(struct pt_regs *regs)
{
	struct irq_domain_chip_generic *dgc = aic_domain->gc;
	struct irq_chip_generic *gc = dgc->gc[0];
	u32 irqnr;
	u32 irqstat;

	irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR);
	irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR);

	if (!irqstat)
		irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
	else
		handle_domain_irq(aic_domain, irqnr, regs);
}

static int aic_retrigger(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	/* Enable interrupt on AIC5 */
	irq_gc_lock(gc);
	irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR);
	irq_gc_unlock(gc);

	return 0;
}

static int aic_set_type(struct irq_data *d, unsigned type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	unsigned int smr;
	int ret;

	smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq));
	ret = aic_common_set_type(d, type, &smr);
	if (ret)
		return ret;

	irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq));

	return 0;
}

#ifdef CONFIG_PM
static void aic_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	irq_gc_lock(gc);
	irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR);
	irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR);
	irq_gc_unlock(gc);
}

static void aic_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	irq_gc_lock(gc);
	irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR);
	irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR);
	irq_gc_unlock(gc);
}

static void aic_pm_shutdown(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	irq_gc_lock(gc);
	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
	irq_gc_unlock(gc);
}
#else
#define aic_suspend		NULL
#define aic_resume		NULL
#define aic_pm_shutdown		NULL
#endif /* CONFIG_PM */

static void __init aic_hw_init(struct irq_domain *domain)
{
	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
	int i;

	/*
	 * Perform 8 End Of Interrupt Command to make sure AIC
	 * will not Lock out nIRQ
	 */
	for (i = 0; i < 8; i++)
		irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);

	/*
	 * Spurious Interrupt ID in Spurious Vector Register.
	 * When there is no current interrupt, the IRQ Vector Register
	 * reads the value stored in AIC_SPU
	 */
	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU);

	/* No debugging in AIC: Debug (Protect) Control Register */
	irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR);

	/* Disable and clear all interrupts initially */
	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);

	for (i = 0; i < 32; i++)
		irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i));
}

static int aic_irq_domain_xlate(struct irq_domain *d,
				struct device_node *ctrlr,
				const u32 *intspec, unsigned int intsize,
				irq_hw_number_t *out_hwirq,
				unsigned int *out_type)
{
	struct irq_domain_chip_generic *dgc = d->gc;
	struct irq_chip_generic *gc;
	unsigned smr;
	int idx;
	int ret;

	if (!dgc)
		return -EINVAL;

	ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
					  out_hwirq, out_type);
	if (ret)
		return ret;

	idx = intspec[0] / dgc->irqs_per_chip;
	if (idx >= dgc->num_chips)
		return -EINVAL;

	gc = dgc->gc[idx];

	irq_gc_lock(gc);
	smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(*out_hwirq));
	ret = aic_common_set_priority(intspec[2], &smr);
	if (!ret)
		irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(*out_hwirq));
	irq_gc_unlock(gc);

	return ret;
}

static const struct irq_domain_ops aic_irq_ops = {
	.map	= irq_map_generic_chip,
	.xlate	= aic_irq_domain_xlate,
};

static void __init at91sam9_aic_irq_fixup(struct device_node *root)
{
	aic_common_rtc_irq_fixup(root);
}

static const struct of_device_id __initdata aic_irq_fixups[] = {
	{ .compatible = "atmel,at91sam9g45", .data = at91sam9_aic_irq_fixup },
	{ .compatible = "atmel,at91sam9n12", .data = at91sam9_aic_irq_fixup },
	{ .compatible = "atmel,at91sam9rl", .data = at91sam9_aic_irq_fixup },
	{ .compatible = "atmel,at91sam9x5", .data = at91sam9_aic_irq_fixup },
	{ /* sentinel */ },
};

static int __init aic_of_init(struct device_node *node,
			      struct device_node *parent)
{
	struct irq_chip_generic *gc;
	struct irq_domain *domain;

	if (aic_domain)
		return -EEXIST;

	domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
				    NR_AIC_IRQS);
	if (IS_ERR(domain))
		return PTR_ERR(domain);

	aic_common_irq_fixup(aic_irq_fixups);

	aic_domain = domain;
	gc = irq_get_domain_generic_chip(domain, 0);

	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
	gc->chip_types[0].regs.enable = AT91_AIC_IECR;
	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
	gc->chip_types[0].chip.irq_set_type = aic_set_type;
	gc->chip_types[0].chip.irq_suspend = aic_suspend;
	gc->chip_types[0].chip.irq_resume = aic_resume;
	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;

	aic_hw_init(domain);
	set_handle_irq(aic_handle);

	return 0;
}
IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);
Commit	Line	Data
b1479ebb BB	1	/*
	2	* Atmel AT91 AIC (Advanced Interrupt Controller) driver
	3	*
	4	* Copyright (C) 2004 SAN People
	5	* Copyright (C) 2004 ATMEL
	6	* Copyright (C) Rick Bronson
	7	* Copyright (C) 2014 Free Electrons
	8	*
	9	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/module.h>
	18	#include <linux/mm.h>
	19	#include <linux/bitmap.h>
	20	#include <linux/types.h>
	21	#include <linux/irq.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/irqdomain.h>
	26	#include <linux/err.h>
	27	#include <linux/slab.h>
	28	#include <linux/io.h>
	29
	30	#include <asm/exception.h>
	31	#include <asm/mach/irq.h>
	32
	33	#include "irq-atmel-aic-common.h"
	34	#include "irqchip.h"
	35
	36	/* Number of irq lines managed by AIC */
	37	#define NR_AIC_IRQS 32
	38
	39	#define AT91_AIC_SMR(n) ((n) * 4)
	40
	41	#define AT91_AIC_SVR(n) (0x80 + ((n) * 4))
	42	#define AT91_AIC_IVR 0x100
	43	#define AT91_AIC_FVR 0x104
	44	#define AT91_AIC_ISR 0x108
	45
	46	#define AT91_AIC_IPR 0x10c
	47	#define AT91_AIC_IMR 0x110
	48	#define AT91_AIC_CISR 0x114
	49
	50	#define AT91_AIC_IECR 0x120
	51	#define AT91_AIC_IDCR 0x124
	52	#define AT91_AIC_ICCR 0x128
	53	#define AT91_AIC_ISCR 0x12c
	54	#define AT91_AIC_EOICR 0x130
	55	#define AT91_AIC_SPU 0x134
	56	#define AT91_AIC_DCR 0x138
	57
	58	static struct irq_domain *aic_domain;
	59
	60	static asmlinkage void __exception_irq_entry
	61	aic_handle(struct pt_regs *regs)
	62	{
	63	struct irq_domain_chip_generic *dgc = aic_domain->gc;
	64	struct irq_chip_generic *gc = dgc->gc[0];
65	u32 irqnr;
66	u32 irqstat;
67
68	irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR);
69	irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR);
70
b1479ebb BB	71	if (!irqstat)
	72	irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
	73	else
841f2aa4	74	handle_domain_irq(aic_domain, irqnr, regs);
b1479ebb BB	75	}
	76
	77	static int aic_retrigger(struct irq_data *d)
	78	{
	79	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	80
	81	/* Enable interrupt on AIC5 */
	82	irq_gc_lock(gc);
	83	irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR);
	84	irq_gc_unlock(gc);
	85
	86	return 0;
	87	}
	88
	89	static int aic_set_type(struct irq_data *d, unsigned type)
	90	{
	91	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	92	unsigned int smr;
	93	int ret;
	94
	95	smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq));
	96	ret = aic_common_set_type(d, type, &smr);
	97	if (ret)
	98	return ret;
	99
	100	irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq));
	101
	102	return 0;
	103	}
	104
	105	#ifdef CONFIG_PM
	106	static void aic_suspend(struct irq_data *d)
	107	{
	108	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	109
	110	irq_gc_lock(gc);
	111	irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR);
	112	irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR);
	113	irq_gc_unlock(gc);
	114	}
	115
	116	static void aic_resume(struct irq_data *d)
	117	{
	118	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	119
	120	irq_gc_lock(gc);
	121	irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR);
	122	irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR);
	123	irq_gc_unlock(gc);
	124	}
	125
	126	static void aic_pm_shutdown(struct irq_data *d)
	127	{
	128	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	129
	130	irq_gc_lock(gc);
	131	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
	132	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
	133	irq_gc_unlock(gc);
	134	}
	135	#else
	136	#define aic_suspend NULL
	137	#define aic_resume NULL
	138	#define aic_pm_shutdown NULL
139	#endif /* CONFIG_PM */
140
141	static void __init aic_hw_init(struct irq_domain *domain)
142	{
143	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
144	int i;
145
146	/*
147	* Perform 8 End Of Interrupt Command to make sure AIC
148	* will not Lock out nIRQ
149	*/
150	for (i = 0; i < 8; i++)
151	irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
152
153	/*
154	* Spurious Interrupt ID in Spurious Vector Register.
155	* When there is no current interrupt, the IRQ Vector Register
156	* reads the value stored in AIC_SPU
157	*/
158	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU);
159
160	/* No debugging in AIC: Debug (Protect) Control Register */
161	irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR);
162
163	/* Disable and clear all interrupts initially */
164	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
165	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
166
167	for (i = 0; i < 32; i++)
168	irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i));
169	}
170
171	static int aic_irq_domain_xlate(struct irq_domain *d,
172	struct device_node *ctrlr,
173	const u32 *intspec, unsigned int intsize,
174	irq_hw_number_t *out_hwirq,
175	unsigned int *out_type)
176	{
177	struct irq_domain_chip_generic *dgc = d->gc;
178	struct irq_chip_generic *gc;
179	unsigned smr;
180	int idx;
181	int ret;
182
183	if (!dgc)
184	return -EINVAL;
185
186	ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
187	out_hwirq, out_type);
188	if (ret)
189	return ret;
190
191	idx = intspec[0] / dgc->irqs_per_chip;
192	if (idx >= dgc->num_chips)
193	return -EINVAL;
194
195	gc = dgc->gc[idx];
196
197	irq_gc_lock(gc);
198	smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(*out_hwirq));
199	ret = aic_common_set_priority(intspec[2], &smr);
200	if (!ret)
201	irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(*out_hwirq));
202	irq_gc_unlock(gc);
203
204	return ret;
205	}
206
207	static const struct irq_domain_ops aic_irq_ops = {
208	.map = irq_map_generic_chip,
209	.xlate = aic_irq_domain_xlate,
210	};
211
6704d12d BB	212	static void __init at91sam9_aic_irq_fixup(struct device_node *root)
	213	{
	214	aic_common_rtc_irq_fixup(root);
	215	}
	216
	217	static const struct of_device_id __initdata aic_irq_fixups[] = {
	218	{ .compatible = "atmel,at91sam9g45", .data = at91sam9_aic_irq_fixup },
	219	{ .compatible = "atmel,at91sam9n12", .data = at91sam9_aic_irq_fixup },
	220	{ .compatible = "atmel,at91sam9rl", .data = at91sam9_aic_irq_fixup },
	221	{ .compatible = "atmel,at91sam9x5", .data = at91sam9_aic_irq_fixup },
	222	{ /* sentinel */ },
	223	};
	224
b1479ebb BB	225	static int __init aic_of_init(struct device_node *node,
	226	struct device_node *parent)
	227	{
	228	struct irq_chip_generic *gc;
	229	struct irq_domain *domain;
	230
	231	if (aic_domain)
	232	return -EEXIST;
	233
	234	domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
	235	NR_AIC_IRQS);
	236	if (IS_ERR(domain))
	237	return PTR_ERR(domain);
	238
6704d12d BB	239	aic_common_irq_fixup(aic_irq_fixups);
6704d12d BB	240
b1479ebb BB	241	aic_domain = domain;
	242	gc = irq_get_domain_generic_chip(domain, 0);
	243
	244	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
	245	gc->chip_types[0].regs.enable = AT91_AIC_IECR;
	246	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
	247	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
	248	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
	249	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
	250	gc->chip_types[0].chip.irq_set_type = aic_set_type;
	251	gc->chip_types[0].chip.irq_suspend = aic_suspend;
	252	gc->chip_types[0].chip.irq_resume = aic_resume;
	253	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
	254
	255	aic_hw_init(domain);
	256	set_handle_irq(aic_handle);
	257
	258	return 0;
	259	}
	260	IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);