[deliverable/linux.git] / drivers / irqchip / irq-bcm7120-l2.c

/*
 * Broadcom BCM7120 style Level 2 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip/chained_irq.h>

#include "irqchip.h"

/* Register offset in the L2 interrupt controller */
#define IRQEN		0x00
#define IRQSTAT		0x04

#define MAX_WORDS	4
#define IRQS_PER_WORD	32

struct bcm7120_l2_intc_data {
	unsigned int n_words;
	void __iomem *base[MAX_WORDS];
	struct irq_domain *domain;
	bool can_wake;
	u32 irq_fwd_mask[MAX_WORDS];
	u32 irq_map_mask[MAX_WORDS];
};

static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
{
	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < b->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		struct irq_chip_generic *gc =
			irq_get_domain_generic_chip(b->domain, base);
		unsigned long pending;
		int hwirq;

		irq_gc_lock(gc);
		pending = __raw_readl(b->base[idx] + IRQSTAT) &
			  gc->mask_cache;
		irq_gc_unlock(gc);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			generic_handle_irq(irq_find_mapping(b->domain,
					   base + hwirq));
		}
	}

	chained_irq_exit(chip, desc);
}

static void bcm7120_l2_intc_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct bcm7120_l2_intc_data *b = gc->private;

	irq_gc_lock(gc);
	if (b->can_wake) {
		__raw_writel(gc->mask_cache | gc->wake_active,
			     gc->reg_base + IRQEN);
	}
	irq_gc_unlock(gc);
}

static void bcm7120_l2_intc_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	/* Restore the saved mask */
	irq_gc_lock(gc);
	__raw_writel(gc->mask_cache, gc->reg_base + IRQEN);
	irq_gc_unlock(gc);
}

static int bcm7120_l2_intc_init_one(struct device_node *dn,
					struct bcm7120_l2_intc_data *data,
					int irq, const __be32 *map_mask)
{
	int parent_irq;
	unsigned int idx;

	parent_irq = irq_of_parse_and_map(dn, irq);
	if (parent_irq < 0) {
		pr_err("failed to map interrupt %d\n", irq);
		return parent_irq;
	}

	/* For multiple parent IRQs with multiple words, this looks like:
	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	 */
	for (idx = 0; idx < data->n_words; idx++)
		data->irq_map_mask[idx] |=
			be32_to_cpup(map_mask + irq * data->n_words + idx);

	irq_set_handler_data(parent_irq, data);
	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);

	return 0;
}

int __init bcm7120_l2_intc_of_init(struct device_node *dn,
					struct device_node *parent)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct bcm7120_l2_intc_data *data;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	const __be32 *map_mask;
	int num_parent_irqs;
	int ret = 0, len;
	unsigned int idx, irq;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	for (idx = 0; idx < MAX_WORDS; idx++) {
		data->base[idx] = of_iomap(dn, idx);
		if (!data->base[idx])
			break;
		data->n_words = idx + 1;
	}
	if (!data->n_words) {
		pr_err("failed to remap intc L2 registers\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	/* Enable all interrupts specified in the interrupt forward mask;
	 * disable all others.  If the property doesn't exist (-EINVAL),
	 * assume all zeroes.
	 */
	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
					 data->irq_fwd_mask, data->n_words);
	if (ret == 0 || ret == -EINVAL) {
		for (idx = 0; idx < data->n_words; idx++)
			__raw_writel(data->irq_fwd_mask[idx],
				     data->base[idx] + IRQEN);
	} else {
		/* property exists but has the wrong number of words */
		pr_err("invalid int-fwd-mask property\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	num_parent_irqs = of_irq_count(dn);
	if (num_parent_irqs <= 0) {
		pr_err("invalid number of parent interrupts\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	map_mask = of_get_property(dn, "brcm,int-map-mask", &len);
	if (!map_mask ||
	    (len != (sizeof(*map_mask) * num_parent_irqs * data->n_words))) {
		pr_err("invalid brcm,int-map-mask property\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	for (irq = 0; irq < num_parent_irqs; irq++) {
		ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask);
		if (ret)
			goto out_unmap;
	}

	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
					     &irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
				dn->full_name, handle_level_irq, clr, 0,
				IRQ_GC_INIT_MASK_CACHE);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		data->can_wake = true;

	for (idx = 0; idx < data->n_words; idx++) {
		irq = idx * IRQS_PER_WORD;
		gc = irq_get_domain_generic_chip(data->domain, irq);

		gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
		gc->reg_base = data->base[idx];
		gc->private = data;
		ct = gc->chip_types;

		ct->regs.mask = IRQEN;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->chip.irq_ack = irq_gc_noop;
		ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
		ct->chip.irq_resume = bcm7120_l2_intc_resume;

		if (data->can_wake) {
			/* This IRQ chip can wake the system, set all
			 * relevant child interupts in wake_enabled mask
			 */
			gc->wake_enabled = 0xffffffff;
			gc->wake_enabled &= ~gc->unused;
			ct->chip.irq_set_wake = irq_gc_set_wake;
		}
	}

	pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n",
			data->base[0], num_parent_irqs);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_unmap:
	for (idx = 0; idx < MAX_WORDS; idx++) {
		if (data->base[idx])
			iounmap(data->base[idx]);
	}
	kfree(data);
	return ret;
}
IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,bcm7120-l2-intc",
		bcm7120_l2_intc_of_init);
Commit	Line	Data
a5042de2 FF	1	/*
	2	* Broadcom BCM7120 style Level 2 interrupt controller driver
	3	*
	4	* Copyright (C) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/of.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_platform.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/irq.h>
	23	#include <linux/io.h>
	24	#include <linux/irqdomain.h>
	25	#include <linux/reboot.h>
c76acf4d	26	#include <linux/bitops.h>
a5042de2 FF	27	#include <linux/irqchip/chained_irq.h>
	28
	29	#include "irqchip.h"
	30
a5042de2 FF	31	/* Register offset in the L2 interrupt controller */
	32	#define IRQEN 0x00
	33	#define IRQSTAT 0x04
	34
c76acf4d KC	35	#define MAX_WORDS 4
	36	#define IRQS_PER_WORD 32
	37
a5042de2	38	struct bcm7120_l2_intc_data {
c76acf4d KC	39	unsigned int n_words;
c76acf4d KC	40	void __iomem *base[MAX_WORDS];
a5042de2 FF	41	struct irq_domain *domain;
a5042de2 FF	42	bool can_wake;
c76acf4d KC	43	u32 irq_fwd_mask[MAX_WORDS];
c76acf4d KC	44	u32 irq_map_mask[MAX_WORDS];
a5042de2 FF	45	};
	46
	47	static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
	48	{
	49	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
	50	struct irq_chip *chip = irq_desc_get_chip(desc);
c76acf4d	51	unsigned int idx;
a5042de2 FF	52
	53	chained_irq_enter(chip, desc);
	54
c76acf4d KC	55	for (idx = 0; idx < b->n_words; idx++) {
	56	int base = idx * IRQS_PER_WORD;
	57	struct irq_chip_generic *gc =
	58	irq_get_domain_generic_chip(b->domain, base);
	59	unsigned long pending;
	60	int hwirq;
	61
	62	irq_gc_lock(gc);
	63	pending = __raw_readl(b->base[idx] + IRQSTAT) &
	64	gc->mask_cache;
	65	irq_gc_unlock(gc);
	66
	67	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
	68	generic_handle_irq(irq_find_mapping(b->domain,
	69	base + hwirq));
	70	}
f668f074	71	}
a5042de2	72
a5042de2 FF	73	chained_irq_exit(chip, desc);
	74	}
	75
	76	static void bcm7120_l2_intc_suspend(struct irq_data *d)
	77	{
	78	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	79	struct bcm7120_l2_intc_data *b = gc->private;
a5042de2 FF	80
a5042de2 FF	81	irq_gc_lock(gc);
a5042de2	82	if (b->can_wake) {
05b8ce82	83	__raw_writel(gc->mask_cache \| gc->wake_active,
c76acf4d	84	gc->reg_base + IRQEN);
a5042de2 FF	85	}
	86	irq_gc_unlock(gc);
	87	}
	88
	89	static void bcm7120_l2_intc_resume(struct irq_data *d)
	90	{
	91	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
a5042de2 FF	92
	93	/* Restore the saved mask */
	94	irq_gc_lock(gc);
c76acf4d	95	__raw_writel(gc->mask_cache, gc->reg_base + IRQEN);
a5042de2 FF	96	irq_gc_unlock(gc);
	97	}
	98
	99	static int bcm7120_l2_intc_init_one(struct device_node *dn,
	100	struct bcm7120_l2_intc_data *data,
	101	int irq, const __be32 *map_mask)
	102	{
	103	int parent_irq;
c76acf4d	104	unsigned int idx;
a5042de2 FF	105
	106	parent_irq = irq_of_parse_and_map(dn, irq);
	107	if (parent_irq < 0) {
	108	pr_err("failed to map interrupt %d\n", irq);
	109	return parent_irq;
	110	}
	111
c76acf4d KC	112	/* For multiple parent IRQs with multiple words, this looks like:
	113	* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	114	*/
	115	for (idx = 0; idx < data->n_words; idx++)
	116	data->irq_map_mask[idx] \|=
	117	be32_to_cpup(map_mask + irq * data->n_words + idx);
a5042de2 FF	118
	119	irq_set_handler_data(parent_irq, data);
	120	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
	121
	122	return 0;
	123	}
	124
	125	int __init bcm7120_l2_intc_of_init(struct device_node *dn,
	126	struct device_node *parent)
	127	{
	128	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	129	struct bcm7120_l2_intc_data *data;
	130	struct irq_chip_generic *gc;
	131	struct irq_chip_type *ct;
	132	const __be32 *map_mask;
	133	int num_parent_irqs;
c76acf4d KC	134	int ret = 0, len;
c76acf4d KC	135	unsigned int idx, irq;
a5042de2 FF	136
	137	data = kzalloc(sizeof(*data), GFP_KERNEL);
	138	if (!data)
	139	return -ENOMEM;
	140
c76acf4d KC	141	for (idx = 0; idx < MAX_WORDS; idx++) {
	142	data->base[idx] = of_iomap(dn, idx);
	143	if (!data->base[idx])
	144	break;
	145	data->n_words = idx + 1;
	146	}
	147	if (!data->n_words) {
a5042de2 FF	148	pr_err("failed to remap intc L2 registers\n");
a5042de2 FF	149	ret = -ENOMEM;
c76acf4d	150	goto out_unmap;
a5042de2 FF	151	}
a5042de2 FF	152
c76acf4d KC	153	/* Enable all interrupts specified in the interrupt forward mask;
	154	* disable all others. If the property doesn't exist (-EINVAL),
	155	* assume all zeroes.
a5042de2	156	*/
c76acf4d KC	157	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
	158	data->irq_fwd_mask, data->n_words);
	159	if (ret == 0 \|\| ret == -EINVAL) {
	160	for (idx = 0; idx < data->n_words; idx++)
	161	__raw_writel(data->irq_fwd_mask[idx],
	162	data->base[idx] + IRQEN);
	163	} else {
	164	/* property exists but has the wrong number of words */
	165	pr_err("invalid int-fwd-mask property\n");
	166	ret = -EINVAL;
	167	goto out_unmap;
	168	}
a5042de2 FF	169
	170	num_parent_irqs = of_irq_count(dn);
	171	if (num_parent_irqs <= 0) {
	172	pr_err("invalid number of parent interrupts\n");
	173	ret = -ENOMEM;
	174	goto out_unmap;
	175	}
	176
	177	map_mask = of_get_property(dn, "brcm,int-map-mask", &len);
c76acf4d KC	178	if (!map_mask \|\|
c76acf4d KC	179	(len != (sizeof(map_mask) num_parent_irqs * data->n_words))) {
a5042de2 FF	180	pr_err("invalid brcm,int-map-mask property\n");
	181	ret = -EINVAL;
	182	goto out_unmap;
	183	}
	184
	185	for (irq = 0; irq < num_parent_irqs; irq++) {
	186	ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask);
	187	if (ret)
	188	goto out_unmap;
	189	}
	190
c76acf4d KC	191	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
c76acf4d KC	192	&irq_generic_chip_ops, NULL);
a5042de2 FF	193	if (!data->domain) {
	194	ret = -ENOMEM;
	195	goto out_unmap;
	196	}
	197
c76acf4d	198	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
a5042de2 FF	199	dn->full_name, handle_level_irq, clr, 0,
	200	IRQ_GC_INIT_MASK_CACHE);
	201	if (ret) {
	202	pr_err("failed to allocate generic irq chip\n");
	203	goto out_free_domain;
	204	}
	205
c76acf4d	206	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
a5042de2	207	data->can_wake = true;
c76acf4d KC	208
	209	for (idx = 0; idx < data->n_words; idx++) {
	210	irq = idx * IRQS_PER_WORD;
	211	gc = irq_get_domain_generic_chip(data->domain, irq);
	212
	213	gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
	214	gc->reg_base = data->base[idx];
	215	gc->private = data;
	216	ct = gc->chip_types;
	217
	218	ct->regs.mask = IRQEN;
	219	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	220	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	221	ct->chip.irq_ack = irq_gc_noop;
	222	ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
	223	ct->chip.irq_resume = bcm7120_l2_intc_resume;
	224
	225	if (data->can_wake) {
	226	/* This IRQ chip can wake the system, set all
	227	* relevant child interupts in wake_enabled mask
	228	*/
	229	gc->wake_enabled = 0xffffffff;
	230	gc->wake_enabled &= ~gc->unused;
	231	ct->chip.irq_set_wake = irq_gc_set_wake;
	232	}
a5042de2 FF	233	}
	234
	235	pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n",
c76acf4d	236	data->base[0], num_parent_irqs);
a5042de2 FF	237
	238	return 0;
	239
	240	out_free_domain:
	241	irq_domain_remove(data->domain);
	242	out_unmap:
c76acf4d KC	243	for (idx = 0; idx < MAX_WORDS; idx++) {
	244	if (data->base[idx])
	245	iounmap(data->base[idx]);
	246	}
a5042de2 FF	247	kfree(data);
	248	return ret;
	249	}
	250	IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,bcm7120-l2-intc",
	251	bcm7120_l2_intc_of_init);