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d51d0af4 MZ |
1 | /* |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqchip/arm-gic.h> | |
21 | ||
22 | #include "irq-gic-common.h" | |
23 | ||
fb7e7deb | 24 | int gic_configure_irq(unsigned int irq, unsigned int type, |
d51d0af4 MZ |
25 | void __iomem *base, void (*sync_access)(void)) |
26 | { | |
d51d0af4 MZ |
27 | u32 confmask = 0x2 << ((irq % 16) * 2); |
28 | u32 confoff = (irq / 16) * 4; | |
fb7e7deb LD |
29 | u32 val, oldval; |
30 | int ret = 0; | |
d51d0af4 MZ |
31 | |
32 | /* | |
33 | * Read current configuration register, and insert the config | |
34 | * for "irq", depending on "type". | |
35 | */ | |
fb7e7deb LD |
36 | val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
37 | if (type & IRQ_TYPE_LEVEL_MASK) | |
d51d0af4 | 38 | val &= ~confmask; |
fb7e7deb | 39 | else if (type & IRQ_TYPE_EDGE_BOTH) |
d51d0af4 MZ |
40 | val |= confmask; |
41 | ||
d51d0af4 MZ |
42 | /* |
43 | * Write back the new configuration, and possibly re-enable | |
fb7e7deb LD |
44 | * the interrupt. If we tried to write a new configuration and failed, |
45 | * return an error. | |
d51d0af4 MZ |
46 | */ |
47 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); | |
fb7e7deb LD |
48 | if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval) |
49 | ret = -EINVAL; | |
d51d0af4 | 50 | |
d51d0af4 MZ |
51 | if (sync_access) |
52 | sync_access(); | |
fb7e7deb LD |
53 | |
54 | return ret; | |
d51d0af4 MZ |
55 | } |
56 | ||
57 | void __init gic_dist_config(void __iomem *base, int gic_irqs, | |
58 | void (*sync_access)(void)) | |
59 | { | |
60 | unsigned int i; | |
61 | ||
62 | /* | |
63 | * Set all global interrupts to be level triggered, active low. | |
64 | */ | |
65 | for (i = 32; i < gic_irqs; i += 16) | |
e5f81539 FK |
66 | writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, |
67 | base + GIC_DIST_CONFIG + i / 4); | |
d51d0af4 MZ |
68 | |
69 | /* | |
70 | * Set priority on all global interrupts. | |
71 | */ | |
72 | for (i = 32; i < gic_irqs; i += 4) | |
e5f81539 | 73 | writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); |
d51d0af4 MZ |
74 | |
75 | /* | |
76 | * Disable all interrupts. Leave the PPI and SGIs alone | |
77 | * as they are enabled by redistributor registers. | |
78 | */ | |
79 | for (i = 32; i < gic_irqs; i += 32) | |
e5f81539 FK |
80 | writel_relaxed(GICD_INT_EN_CLR_X32, |
81 | base + GIC_DIST_ENABLE_CLEAR + i / 8); | |
d51d0af4 MZ |
82 | |
83 | if (sync_access) | |
84 | sync_access(); | |
85 | } | |
86 | ||
87 | void gic_cpu_config(void __iomem *base, void (*sync_access)(void)) | |
88 | { | |
89 | int i; | |
90 | ||
91 | /* | |
92 | * Deal with the banked PPI and SGI interrupts - disable all | |
93 | * PPI interrupts, ensure all SGI interrupts are enabled. | |
94 | */ | |
e5f81539 FK |
95 | writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); |
96 | writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); | |
d51d0af4 MZ |
97 | |
98 | /* | |
99 | * Set priority on PPI and SGI interrupts | |
100 | */ | |
101 | for (i = 0; i < 32; i += 4) | |
e5f81539 FK |
102 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
103 | base + GIC_DIST_PRI + i * 4 / 4); | |
d51d0af4 MZ |
104 | |
105 | if (sync_access) | |
106 | sync_access(); | |
107 | } |