Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 44 | |
29e697b1 | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
0b996fd3 | 49 | #include <asm/virt.h> |
f27ecacc | 50 | |
d51d0af4 | 51 | #include "irq-gic-common.h" |
f27ecacc | 52 | |
76e52dd0 MZ |
53 | #ifdef CONFIG_ARM64 |
54 | #include <asm/cpufeature.h> | |
55 | ||
56 | static void gic_check_cpu_features(void) | |
57 | { | |
25fc11ae | 58 | WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), |
76e52dd0 MZ |
59 | TAINT_CPU_OUT_OF_SPEC, |
60 | "GICv3 system registers enabled, broken firmware!\n"); | |
61 | } | |
62 | #else | |
63 | #define gic_check_cpu_features() do { } while(0) | |
64 | #endif | |
65 | ||
db0d4db2 MZ |
66 | union gic_base { |
67 | void __iomem *common_base; | |
6859358e | 68 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
69 | }; |
70 | ||
71 | struct gic_chip_data { | |
58b89649 | 72 | struct irq_chip chip; |
db0d4db2 MZ |
73 | union gic_base dist_base; |
74 | union gic_base cpu_base; | |
f673b9b5 JH |
75 | void __iomem *raw_dist_base; |
76 | void __iomem *raw_cpu_base; | |
77 | u32 percpu_offset; | |
db0d4db2 MZ |
78 | #ifdef CONFIG_CPU_PM |
79 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
1c7d4dd4 | 80 | u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; |
db0d4db2 MZ |
81 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
82 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
83 | u32 __percpu *saved_ppi_enable; | |
1c7d4dd4 | 84 | u32 __percpu *saved_ppi_active; |
db0d4db2 MZ |
85 | u32 __percpu *saved_ppi_conf; |
86 | #endif | |
75294957 | 87 | struct irq_domain *domain; |
db0d4db2 MZ |
88 | unsigned int gic_irqs; |
89 | #ifdef CONFIG_GIC_NON_BANKED | |
90 | void __iomem *(*get_base)(union gic_base *); | |
91 | #endif | |
92 | }; | |
93 | ||
bd31b859 | 94 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 95 | |
384a2902 NP |
96 | /* |
97 | * The GIC mapping of CPU interfaces does not necessarily match | |
98 | * the logical CPU numbering. Let's use a mapping as returned | |
99 | * by the GIC itself. | |
100 | */ | |
101 | #define NR_GIC_CPU_IF 8 | |
102 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
103 | ||
0b996fd3 MZ |
104 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
105 | ||
a27d21e0 | 106 | static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; |
b3a1bde4 | 107 | |
db0d4db2 MZ |
108 | #ifdef CONFIG_GIC_NON_BANKED |
109 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
110 | { | |
513d1a28 | 111 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
112 | } |
113 | ||
114 | static void __iomem *gic_get_common_base(union gic_base *base) | |
115 | { | |
116 | return base->common_base; | |
117 | } | |
118 | ||
119 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
120 | { | |
121 | return data->get_base(&data->dist_base); | |
122 | } | |
123 | ||
124 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
125 | { | |
126 | return data->get_base(&data->cpu_base); | |
127 | } | |
128 | ||
129 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
130 | void __iomem *(*f)(union gic_base *)) | |
131 | { | |
132 | data->get_base = f; | |
133 | } | |
134 | #else | |
135 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
136 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 137 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
138 | #endif |
139 | ||
7d1f4288 | 140 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 141 | { |
7d1f4288 | 142 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 143 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
144 | } |
145 | ||
7d1f4288 | 146 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 147 | { |
7d1f4288 | 148 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 149 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
150 | } |
151 | ||
7d1f4288 | 152 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 153 | { |
4294f8ba | 154 | return d->hwirq; |
b3a1bde4 CM |
155 | } |
156 | ||
01f779f4 MZ |
157 | static inline bool cascading_gic_irq(struct irq_data *d) |
158 | { | |
159 | void *data = irq_data_get_irq_handler_data(d); | |
160 | ||
161 | /* | |
71466535 TG |
162 | * If handler_data is set, this is a cascading interrupt, and |
163 | * it cannot possibly be forwarded. | |
01f779f4 | 164 | */ |
71466535 | 165 | return data != NULL; |
01f779f4 MZ |
166 | } |
167 | ||
f27ecacc RK |
168 | /* |
169 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 170 | */ |
56717807 MZ |
171 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
172 | { | |
173 | u32 mask = 1 << (gic_irq(d) % 32); | |
174 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
175 | } | |
176 | ||
177 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 178 | { |
4294f8ba | 179 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
180 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
181 | } | |
182 | ||
183 | static void gic_mask_irq(struct irq_data *d) | |
184 | { | |
56717807 | 185 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
186 | } |
187 | ||
0b996fd3 MZ |
188 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
189 | { | |
190 | gic_mask_irq(d); | |
01f779f4 MZ |
191 | /* |
192 | * When masking a forwarded interrupt, make sure it is | |
193 | * deactivated as well. | |
194 | * | |
195 | * This ensures that an interrupt that is getting | |
196 | * disabled/masked will not get "stuck", because there is | |
197 | * noone to deactivate it (guest is being terminated). | |
198 | */ | |
71466535 | 199 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 200 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
201 | } |
202 | ||
7d1f4288 | 203 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 204 | { |
56717807 | 205 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
206 | } |
207 | ||
1a01753e WD |
208 | static void gic_eoi_irq(struct irq_data *d) |
209 | { | |
6ac77e46 | 210 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
211 | } |
212 | ||
0b996fd3 MZ |
213 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
214 | { | |
01f779f4 | 215 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 216 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
217 | return; |
218 | ||
0b996fd3 MZ |
219 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
220 | } | |
221 | ||
56717807 MZ |
222 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
223 | enum irqchip_irq_state which, bool val) | |
224 | { | |
225 | u32 reg; | |
226 | ||
227 | switch (which) { | |
228 | case IRQCHIP_STATE_PENDING: | |
229 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
230 | break; | |
231 | ||
232 | case IRQCHIP_STATE_ACTIVE: | |
233 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
234 | break; | |
235 | ||
236 | case IRQCHIP_STATE_MASKED: | |
237 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
238 | break; | |
239 | ||
240 | default: | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
244 | gic_poke_irq(d, reg); | |
245 | return 0; | |
246 | } | |
247 | ||
248 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
249 | enum irqchip_irq_state which, bool *val) | |
250 | { | |
251 | switch (which) { | |
252 | case IRQCHIP_STATE_PENDING: | |
253 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
254 | break; | |
255 | ||
256 | case IRQCHIP_STATE_ACTIVE: | |
257 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
258 | break; | |
259 | ||
260 | case IRQCHIP_STATE_MASKED: | |
261 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
262 | break; | |
263 | ||
264 | default: | |
265 | return -EINVAL; | |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
7d1f4288 | 271 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 272 | { |
7d1f4288 LB |
273 | void __iomem *base = gic_dist_base(d); |
274 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
275 | |
276 | /* Interrupt configuration for SGIs can't be changed */ | |
277 | if (gicirq < 16) | |
278 | return -EINVAL; | |
279 | ||
fb7e7deb LD |
280 | /* SPIs have restrictions on the supported types */ |
281 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
282 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
283 | return -EINVAL; |
284 | ||
1dcc73d7 | 285 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
286 | } |
287 | ||
01f779f4 MZ |
288 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
289 | { | |
290 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
291 | if (cascading_gic_irq(d)) | |
292 | return -EINVAL; | |
293 | ||
71466535 TG |
294 | if (vcpu) |
295 | irqd_set_forwarded_to_vcpu(d); | |
296 | else | |
297 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
298 | return 0; |
299 | } | |
300 | ||
a06f5466 | 301 | #ifdef CONFIG_SMP |
c191789c RK |
302 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
303 | bool force) | |
f27ecacc | 304 | { |
7d1f4288 | 305 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 306 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 307 | u32 val, mask, bit; |
cf613871 | 308 | unsigned long flags; |
f27ecacc | 309 | |
ffde1de6 TG |
310 | if (!force) |
311 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
312 | else | |
313 | cpu = cpumask_first(mask_val); | |
314 | ||
384a2902 | 315 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 316 | return -EINVAL; |
c191789c | 317 | |
cf613871 | 318 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 319 | mask = 0xff << shift; |
384a2902 | 320 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
321 | val = readl_relaxed(reg) & ~mask; |
322 | writel_relaxed(val | bit, reg); | |
cf613871 | 323 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 324 | |
0407dace | 325 | return IRQ_SET_MASK_OK_DONE; |
f27ecacc | 326 | } |
a06f5466 | 327 | #endif |
f27ecacc | 328 | |
8783dd3a | 329 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
330 | { |
331 | u32 irqstat, irqnr; | |
332 | struct gic_chip_data *gic = &gic_data[0]; | |
333 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
334 | ||
335 | do { | |
336 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 337 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 | 338 | |
327ebe1f | 339 | if (likely(irqnr > 15 && irqnr < 1020)) { |
0b996fd3 MZ |
340 | if (static_key_true(&supports_deactivate)) |
341 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
60031b4e | 342 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
343 | continue; |
344 | } | |
345 | if (irqnr < 16) { | |
346 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
0b996fd3 MZ |
347 | if (static_key_true(&supports_deactivate)) |
348 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); | |
562e0027 | 349 | #ifdef CONFIG_SMP |
f86c4fbd WD |
350 | /* |
351 | * Ensure any shared data written by the CPU sending | |
352 | * the IPI is read after we've read the ACK register | |
353 | * on the GIC. | |
354 | * | |
355 | * Pairs with the write barrier in gic_raise_softirq | |
356 | */ | |
357 | smp_rmb(); | |
562e0027 MZ |
358 | handle_IPI(irqnr, regs); |
359 | #endif | |
360 | continue; | |
361 | } | |
362 | break; | |
363 | } while (1); | |
364 | } | |
365 | ||
bd0b9ac4 | 366 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 367 | { |
5b29264c JL |
368 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
369 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 370 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
371 | unsigned long status; |
372 | ||
1a01753e | 373 | chained_irq_enter(chip, desc); |
b3a1bde4 | 374 | |
bd31b859 | 375 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 376 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 377 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 378 | |
e5f81539 FK |
379 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
380 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 381 | goto out; |
b3a1bde4 | 382 | |
75294957 GL |
383 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
384 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
bd0b9ac4 | 385 | handle_bad_irq(desc); |
0f347bb9 RK |
386 | else |
387 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
388 | |
389 | out: | |
1a01753e | 390 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
391 | } |
392 | ||
38c677cb | 393 | static struct irq_chip gic_chip = { |
7d1f4288 LB |
394 | .irq_mask = gic_mask_irq, |
395 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 396 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 397 | .irq_set_type = gic_set_type, |
56717807 MZ |
398 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
399 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
400 | .flags = IRQCHIP_SET_TYPE_MASKED | |
401 | IRQCHIP_SKIP_SET_WAKE | | |
402 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
403 | }; |
404 | ||
b3a1bde4 CM |
405 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
406 | { | |
a27d21e0 | 407 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
4d83fcf8 TG |
408 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
409 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
410 | } |
411 | ||
2bb31351 RK |
412 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
413 | { | |
414 | void __iomem *base = gic_data_dist_base(gic); | |
415 | u32 mask, i; | |
416 | ||
417 | for (i = mask = 0; i < 32; i += 4) { | |
418 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
419 | mask |= mask >> 16; | |
420 | mask |= mask >> 8; | |
421 | if (mask) | |
422 | break; | |
423 | } | |
424 | ||
6e3aca44 | 425 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
426 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
427 | ||
428 | return mask; | |
429 | } | |
430 | ||
4c2880b3 | 431 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 432 | { |
4c2880b3 | 433 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 434 | u32 bypass = 0; |
0b996fd3 MZ |
435 | u32 mode = 0; |
436 | ||
389a00d3 | 437 | if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) |
0b996fd3 | 438 | mode = GIC_CPU_CTRL_EOImodeNS; |
32289506 FK |
439 | |
440 | /* | |
441 | * Preserve bypass disable bits to be written back later | |
442 | */ | |
443 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
444 | bypass &= GICC_DIS_BYPASS_MASK; | |
445 | ||
0b996fd3 | 446 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
447 | } |
448 | ||
449 | ||
4294f8ba | 450 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 451 | { |
75294957 | 452 | unsigned int i; |
267840f3 | 453 | u32 cpumask; |
4294f8ba | 454 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 455 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 456 | |
e5f81539 | 457 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 458 | |
f27ecacc RK |
459 | /* |
460 | * Set all global interrupts to this CPU only. | |
461 | */ | |
2bb31351 RK |
462 | cpumask = gic_get_cpumask(gic); |
463 | cpumask |= cpumask << 8; | |
464 | cpumask |= cpumask << 16; | |
e6afec9b | 465 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 466 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 467 | |
d51d0af4 | 468 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 469 | |
e5f81539 | 470 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
471 | } |
472 | ||
dc9722cc | 473 | static int gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 474 | { |
db0d4db2 MZ |
475 | void __iomem *dist_base = gic_data_dist_base(gic); |
476 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 477 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
478 | int i; |
479 | ||
384a2902 | 480 | /* |
567e5a01 JH |
481 | * Setting up the CPU map is only relevant for the primary GIC |
482 | * because any nested/secondary GICs do not directly interface | |
483 | * with the CPU(s). | |
384a2902 | 484 | */ |
567e5a01 JH |
485 | if (gic == &gic_data[0]) { |
486 | /* | |
487 | * Get what the GIC says our CPU mask is. | |
488 | */ | |
dc9722cc JH |
489 | if (WARN_ON(cpu >= NR_GIC_CPU_IF)) |
490 | return -EINVAL; | |
491 | ||
25fc11ae | 492 | gic_check_cpu_features(); |
567e5a01 JH |
493 | cpu_mask = gic_get_cpumask(gic); |
494 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 495 | |
567e5a01 JH |
496 | /* |
497 | * Clear our mask from the other map entries in case they're | |
498 | * still undefined. | |
499 | */ | |
500 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
501 | if (i != cpu) | |
502 | gic_cpu_map[i] &= ~cpu_mask; | |
503 | } | |
384a2902 | 504 | |
d51d0af4 | 505 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 506 | |
e5f81539 | 507 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 508 | gic_cpu_if_up(gic); |
dc9722cc JH |
509 | |
510 | return 0; | |
f27ecacc RK |
511 | } |
512 | ||
4c2880b3 | 513 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 514 | { |
4c2880b3 | 515 | void __iomem *cpu_base; |
32289506 FK |
516 | u32 val = 0; |
517 | ||
a27d21e0 | 518 | if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) |
4c2880b3 JH |
519 | return -EINVAL; |
520 | ||
521 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
522 | val = readl(cpu_base + GIC_CPU_CTRL); |
523 | val &= ~GICC_ENABLE; | |
524 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
525 | |
526 | return 0; | |
10d9eb8a NP |
527 | } |
528 | ||
254056f3 CC |
529 | #ifdef CONFIG_CPU_PM |
530 | /* | |
531 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
532 | * with interrupts disabled but before powering down the GIC. After calling | |
533 | * this function, no interrupts will be delivered by the GIC, and another | |
534 | * platform-specific wakeup source must be enabled. | |
535 | */ | |
6e5b5924 | 536 | static void gic_dist_save(struct gic_chip_data *gic) |
254056f3 CC |
537 | { |
538 | unsigned int gic_irqs; | |
539 | void __iomem *dist_base; | |
540 | int i; | |
541 | ||
6e5b5924 JH |
542 | if (WARN_ON(!gic)) |
543 | return; | |
254056f3 | 544 | |
6e5b5924 JH |
545 | gic_irqs = gic->gic_irqs; |
546 | dist_base = gic_data_dist_base(gic); | |
254056f3 CC |
547 | |
548 | if (!dist_base) | |
549 | return; | |
550 | ||
551 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
6e5b5924 | 552 | gic->saved_spi_conf[i] = |
254056f3 CC |
553 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
554 | ||
555 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
6e5b5924 | 556 | gic->saved_spi_target[i] = |
254056f3 CC |
557 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
558 | ||
559 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
6e5b5924 | 560 | gic->saved_spi_enable[i] = |
254056f3 | 561 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
1c7d4dd4 MZ |
562 | |
563 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
6e5b5924 | 564 | gic->saved_spi_active[i] = |
1c7d4dd4 | 565 | readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
254056f3 CC |
566 | } |
567 | ||
568 | /* | |
569 | * Restores the GIC distributor registers during resume or when coming out of | |
570 | * idle. Must be called before enabling interrupts. If a level interrupt | |
571 | * that occured while the GIC was suspended is still present, it will be | |
572 | * handled normally, but any edge interrupts that occured will not be seen by | |
573 | * the GIC and need to be handled by the platform-specific wakeup source. | |
574 | */ | |
6e5b5924 | 575 | static void gic_dist_restore(struct gic_chip_data *gic) |
254056f3 CC |
576 | { |
577 | unsigned int gic_irqs; | |
578 | unsigned int i; | |
579 | void __iomem *dist_base; | |
580 | ||
6e5b5924 JH |
581 | if (WARN_ON(!gic)) |
582 | return; | |
254056f3 | 583 | |
6e5b5924 JH |
584 | gic_irqs = gic->gic_irqs; |
585 | dist_base = gic_data_dist_base(gic); | |
254056f3 CC |
586 | |
587 | if (!dist_base) | |
588 | return; | |
589 | ||
e5f81539 | 590 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
591 | |
592 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
6e5b5924 | 593 | writel_relaxed(gic->saved_spi_conf[i], |
254056f3 CC |
594 | dist_base + GIC_DIST_CONFIG + i * 4); |
595 | ||
596 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 597 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
598 | dist_base + GIC_DIST_PRI + i * 4); |
599 | ||
600 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
6e5b5924 | 601 | writel_relaxed(gic->saved_spi_target[i], |
254056f3 CC |
602 | dist_base + GIC_DIST_TARGET + i * 4); |
603 | ||
92eda4ad MZ |
604 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
605 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
606 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
6e5b5924 | 607 | writel_relaxed(gic->saved_spi_enable[i], |
254056f3 | 608 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 609 | } |
254056f3 | 610 | |
1c7d4dd4 MZ |
611 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
612 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
613 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
6e5b5924 | 614 | writel_relaxed(gic->saved_spi_active[i], |
1c7d4dd4 MZ |
615 | dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
616 | } | |
617 | ||
e5f81539 | 618 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
619 | } |
620 | ||
6e5b5924 | 621 | static void gic_cpu_save(struct gic_chip_data *gic) |
254056f3 CC |
622 | { |
623 | int i; | |
624 | u32 *ptr; | |
625 | void __iomem *dist_base; | |
626 | void __iomem *cpu_base; | |
627 | ||
6e5b5924 JH |
628 | if (WARN_ON(!gic)) |
629 | return; | |
254056f3 | 630 | |
6e5b5924 JH |
631 | dist_base = gic_data_dist_base(gic); |
632 | cpu_base = gic_data_cpu_base(gic); | |
254056f3 CC |
633 | |
634 | if (!dist_base || !cpu_base) | |
635 | return; | |
636 | ||
6e5b5924 | 637 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
254056f3 CC |
638 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
639 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
640 | ||
6e5b5924 | 641 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
1c7d4dd4 MZ |
642 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
643 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
644 | ||
6e5b5924 | 645 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
254056f3 CC |
646 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
647 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
648 | ||
649 | } | |
650 | ||
6e5b5924 | 651 | static void gic_cpu_restore(struct gic_chip_data *gic) |
254056f3 CC |
652 | { |
653 | int i; | |
654 | u32 *ptr; | |
655 | void __iomem *dist_base; | |
656 | void __iomem *cpu_base; | |
657 | ||
6e5b5924 JH |
658 | if (WARN_ON(!gic)) |
659 | return; | |
254056f3 | 660 | |
6e5b5924 JH |
661 | dist_base = gic_data_dist_base(gic); |
662 | cpu_base = gic_data_cpu_base(gic); | |
254056f3 CC |
663 | |
664 | if (!dist_base || !cpu_base) | |
665 | return; | |
666 | ||
6e5b5924 | 667 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
92eda4ad MZ |
668 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
669 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
670 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 | 671 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 672 | } |
254056f3 | 673 | |
6e5b5924 | 674 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
1c7d4dd4 MZ |
675 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
676 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
677 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
678 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
679 | } | |
680 | ||
6e5b5924 | 681 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
254056f3 CC |
682 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
683 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
684 | ||
685 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
686 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
687 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 688 | |
e5f81539 | 689 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
6e5b5924 | 690 | gic_cpu_if_up(gic); |
254056f3 CC |
691 | } |
692 | ||
693 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
694 | { | |
695 | int i; | |
696 | ||
a27d21e0 | 697 | for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { |
db0d4db2 MZ |
698 | #ifdef CONFIG_GIC_NON_BANKED |
699 | /* Skip over unused GICs */ | |
700 | if (!gic_data[i].get_base) | |
701 | continue; | |
702 | #endif | |
254056f3 CC |
703 | switch (cmd) { |
704 | case CPU_PM_ENTER: | |
6e5b5924 | 705 | gic_cpu_save(&gic_data[i]); |
254056f3 CC |
706 | break; |
707 | case CPU_PM_ENTER_FAILED: | |
708 | case CPU_PM_EXIT: | |
6e5b5924 | 709 | gic_cpu_restore(&gic_data[i]); |
254056f3 CC |
710 | break; |
711 | case CPU_CLUSTER_PM_ENTER: | |
6e5b5924 | 712 | gic_dist_save(&gic_data[i]); |
254056f3 CC |
713 | break; |
714 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
715 | case CPU_CLUSTER_PM_EXIT: | |
6e5b5924 | 716 | gic_dist_restore(&gic_data[i]); |
254056f3 CC |
717 | break; |
718 | } | |
719 | } | |
720 | ||
721 | return NOTIFY_OK; | |
722 | } | |
723 | ||
724 | static struct notifier_block gic_notifier_block = { | |
725 | .notifier_call = gic_notifier, | |
726 | }; | |
727 | ||
dc9722cc | 728 | static int __init gic_pm_init(struct gic_chip_data *gic) |
254056f3 CC |
729 | { |
730 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
731 | sizeof(u32)); | |
dc9722cc JH |
732 | if (WARN_ON(!gic->saved_ppi_enable)) |
733 | return -ENOMEM; | |
254056f3 | 734 | |
1c7d4dd4 MZ |
735 | gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
736 | sizeof(u32)); | |
dc9722cc JH |
737 | if (WARN_ON(!gic->saved_ppi_active)) |
738 | goto free_ppi_enable; | |
1c7d4dd4 | 739 | |
254056f3 CC |
740 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
741 | sizeof(u32)); | |
dc9722cc JH |
742 | if (WARN_ON(!gic->saved_ppi_conf)) |
743 | goto free_ppi_active; | |
254056f3 | 744 | |
abdd7b91 MZ |
745 | if (gic == &gic_data[0]) |
746 | cpu_pm_register_notifier(&gic_notifier_block); | |
dc9722cc JH |
747 | |
748 | return 0; | |
749 | ||
750 | free_ppi_active: | |
751 | free_percpu(gic->saved_ppi_active); | |
752 | free_ppi_enable: | |
753 | free_percpu(gic->saved_ppi_enable); | |
754 | ||
755 | return -ENOMEM; | |
254056f3 CC |
756 | } |
757 | #else | |
dc9722cc | 758 | static int __init gic_pm_init(struct gic_chip_data *gic) |
254056f3 | 759 | { |
dc9722cc | 760 | return 0; |
254056f3 CC |
761 | } |
762 | #endif | |
763 | ||
b1cffebf | 764 | #ifdef CONFIG_SMP |
6859358e | 765 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
766 | { |
767 | int cpu; | |
1a6b69b6 NP |
768 | unsigned long flags, map = 0; |
769 | ||
770 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
771 | |
772 | /* Convert our logical CPU mask into a physical one. */ | |
773 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 774 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
775 | |
776 | /* | |
777 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 778 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 779 | */ |
8adbf57f | 780 | dmb(ishst); |
b1cffebf RH |
781 | |
782 | /* this always happens on GIC0 */ | |
783 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
784 | |
785 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
786 | } | |
787 | #endif | |
788 | ||
789 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
790 | /* |
791 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
792 | * | |
793 | * cpu_id: the ID for the destination CPU interface | |
794 | * irq: the IPI number to send a SGI for | |
795 | */ | |
796 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
797 | { | |
798 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
799 | cpu_id = 1 << cpu_id; | |
800 | /* this always happens on GIC0 */ | |
801 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
802 | } | |
803 | ||
ed96762e NP |
804 | /* |
805 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
806 | * | |
807 | * @cpu: the logical CPU number to get the GIC ID for. | |
808 | * | |
809 | * Return the CPU interface ID for the given logical CPU number, | |
810 | * or -1 if the CPU number is too large or the interface ID is | |
811 | * unknown (more than one bit set). | |
812 | */ | |
813 | int gic_get_cpu_id(unsigned int cpu) | |
814 | { | |
815 | unsigned int cpu_bit; | |
816 | ||
817 | if (cpu >= NR_GIC_CPU_IF) | |
818 | return -1; | |
819 | cpu_bit = gic_cpu_map[cpu]; | |
820 | if (cpu_bit & (cpu_bit - 1)) | |
821 | return -1; | |
822 | return __ffs(cpu_bit); | |
823 | } | |
824 | ||
1a6b69b6 NP |
825 | /* |
826 | * gic_migrate_target - migrate IRQs to another CPU interface | |
827 | * | |
828 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
829 | * | |
830 | * Migrate all peripheral interrupts with a target matching the current CPU | |
831 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
832 | * is also updated. Targets to other CPU interfaces are unchanged. | |
833 | * This must be called with IRQs locally disabled. | |
834 | */ | |
835 | void gic_migrate_target(unsigned int new_cpu_id) | |
836 | { | |
837 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
838 | void __iomem *dist_base; | |
839 | int i, ror_val, cpu = smp_processor_id(); | |
840 | u32 val, cur_target_mask, active_mask; | |
841 | ||
a27d21e0 | 842 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
1a6b69b6 NP |
843 | |
844 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
845 | if (!dist_base) | |
846 | return; | |
847 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
848 | ||
849 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
850 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
851 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
852 | ||
853 | raw_spin_lock(&irq_controller_lock); | |
854 | ||
855 | /* Update the target interface for this logical CPU */ | |
856 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
857 | ||
858 | /* | |
859 | * Find all the peripheral interrupts targetting the current | |
860 | * CPU interface and migrate them to the new CPU interface. | |
861 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
862 | */ | |
863 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
864 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
865 | active_mask = val & cur_target_mask; | |
866 | if (active_mask) { | |
867 | val &= ~active_mask; | |
868 | val |= ror32(active_mask, ror_val); | |
869 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
870 | } | |
871 | } | |
872 | ||
873 | raw_spin_unlock(&irq_controller_lock); | |
874 | ||
875 | /* | |
876 | * Now let's migrate and clear any potential SGIs that might be | |
877 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
878 | * is a banked register, we can only forward the SGI using | |
879 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
880 | * doesn't use that information anyway. | |
881 | * | |
882 | * For the same reason we do not adjust SGI source information | |
883 | * for previously sent SGIs by us to other CPUs either. | |
884 | */ | |
885 | for (i = 0; i < 16; i += 4) { | |
886 | int j; | |
887 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
888 | if (!val) | |
889 | continue; | |
890 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
891 | for (j = i; j < i + 4; j++) { | |
892 | if (val & 0xff) | |
893 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
894 | dist_base + GIC_DIST_SOFTINT); | |
895 | val >>= 8; | |
896 | } | |
897 | } | |
b1cffebf | 898 | } |
eeb44658 NP |
899 | |
900 | /* | |
901 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
902 | * | |
903 | * REturn the physical address of the SGI register to be used | |
904 | * by some early assembly code when the kernel is not yet available. | |
905 | */ | |
906 | static unsigned long gic_dist_physaddr; | |
907 | ||
908 | unsigned long gic_get_sgir_physaddr(void) | |
909 | { | |
910 | if (!gic_dist_physaddr) | |
911 | return 0; | |
912 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
913 | } | |
914 | ||
915 | void __init gic_init_physaddr(struct device_node *node) | |
916 | { | |
917 | struct resource res; | |
918 | if (of_address_to_resource(node, 0, &res) == 0) { | |
919 | gic_dist_physaddr = res.start; | |
920 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
921 | } | |
922 | } | |
923 | ||
924 | #else | |
925 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
926 | #endif |
927 | ||
75294957 GL |
928 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
929 | irq_hw_number_t hw) | |
930 | { | |
58b89649 | 931 | struct gic_chip_data *gic = d->host_data; |
0b996fd3 | 932 | |
75294957 GL |
933 | if (hw < 32) { |
934 | irq_set_percpu_devid(irq); | |
58b89649 | 935 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 936 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 937 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 938 | } else { |
58b89649 | 939 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 940 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 941 | irq_set_probe(irq); |
75294957 | 942 | } |
75294957 GL |
943 | return 0; |
944 | } | |
945 | ||
006e983b S |
946 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
947 | { | |
006e983b S |
948 | } |
949 | ||
f833f57f MZ |
950 | static int gic_irq_domain_translate(struct irq_domain *d, |
951 | struct irq_fwspec *fwspec, | |
952 | unsigned long *hwirq, | |
953 | unsigned int *type) | |
954 | { | |
955 | if (is_of_node(fwspec->fwnode)) { | |
956 | if (fwspec->param_count < 3) | |
957 | return -EINVAL; | |
958 | ||
959 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
960 | *hwirq = fwspec->param[1] + 16; | |
961 | ||
962 | /* | |
963 | * For SPIs, we need to add 16 more to get the GIC irq | |
964 | * ID number | |
965 | */ | |
966 | if (!fwspec->param[0]) | |
967 | *hwirq += 16; | |
968 | ||
969 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
970 | return 0; | |
971 | } | |
972 | ||
75aba7b0 | 973 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
891ae769 MZ |
974 | if(fwspec->param_count != 2) |
975 | return -EINVAL; | |
976 | ||
977 | *hwirq = fwspec->param[0]; | |
978 | *type = fwspec->param[1]; | |
979 | return 0; | |
980 | } | |
981 | ||
f833f57f MZ |
982 | return -EINVAL; |
983 | } | |
984 | ||
c0114709 | 985 | #ifdef CONFIG_SMP |
8c37bb3a PG |
986 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
987 | void *hcpu) | |
c0114709 | 988 | { |
8b6fd652 | 989 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
990 | gic_cpu_init(&gic_data[0]); |
991 | return NOTIFY_OK; | |
992 | } | |
993 | ||
994 | /* | |
995 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
996 | * priority because the GIC needs to be up before the ARM generic timers. | |
997 | */ | |
8c37bb3a | 998 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
999 | .notifier_call = gic_secondary_init, |
1000 | .priority = 100, | |
1001 | }; | |
1002 | #endif | |
1003 | ||
9a1091ef YC |
1004 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1005 | unsigned int nr_irqs, void *arg) | |
1006 | { | |
1007 | int i, ret; | |
1008 | irq_hw_number_t hwirq; | |
1009 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1010 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 1011 | |
f833f57f | 1012 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
1013 | if (ret) |
1014 | return ret; | |
1015 | ||
1016 | for (i = 0; i < nr_irqs; i++) | |
1017 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 1023 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
1024 | .alloc = gic_irq_domain_alloc, |
1025 | .free = irq_domain_free_irqs_top, | |
1026 | }; | |
1027 | ||
6859358e | 1028 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 1029 | .map = gic_irq_domain_map, |
006e983b | 1030 | .unmap = gic_irq_domain_unmap, |
4294f8ba RH |
1031 | }; |
1032 | ||
f673b9b5 JH |
1033 | static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start, |
1034 | struct fwnode_handle *handle) | |
b580b899 | 1035 | { |
75294957 | 1036 | irq_hw_number_t hwirq_base; |
dc9722cc | 1037 | int gic_irqs, irq_base, i, ret; |
bef8f9ee | 1038 | |
f673b9b5 JH |
1039 | if (WARN_ON(!gic || gic->domain)) |
1040 | return -EINVAL; | |
58b89649 LW |
1041 | |
1042 | /* Initialize irq_chip */ | |
c2baa2f3 JH |
1043 | gic->chip = gic_chip; |
1044 | ||
f673b9b5 | 1045 | if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { |
c2baa2f3 JH |
1046 | gic->chip.irq_mask = gic_eoimode1_mask_irq; |
1047 | gic->chip.irq_eoi = gic_eoimode1_eoi_irq; | |
1048 | gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; | |
dc9722cc | 1049 | gic->chip.name = kasprintf(GFP_KERNEL, "GICv2"); |
58b89649 | 1050 | } else { |
f673b9b5 JH |
1051 | gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", |
1052 | (int)(gic - &gic_data[0])); | |
58b89649 LW |
1053 | } |
1054 | ||
7bf29d3a | 1055 | #ifdef CONFIG_SMP |
f673b9b5 | 1056 | if (gic == &gic_data[0]) |
7bf29d3a JH |
1057 | gic->chip.irq_set_affinity = gic_set_affinity; |
1058 | #endif | |
1059 | ||
f673b9b5 | 1060 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
dc9722cc | 1061 | /* Frankein-GIC without banked registers... */ |
db0d4db2 MZ |
1062 | unsigned int cpu; |
1063 | ||
1064 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1065 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1066 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1067 | !gic->cpu_base.percpu_base)) { | |
dc9722cc JH |
1068 | ret = -ENOMEM; |
1069 | goto error; | |
db0d4db2 MZ |
1070 | } |
1071 | ||
1072 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1073 | u32 mpidr = cpu_logical_map(cpu); |
1074 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
f673b9b5 JH |
1075 | unsigned long offset = gic->percpu_offset * core_id; |
1076 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = | |
1077 | gic->raw_dist_base + offset; | |
1078 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = | |
1079 | gic->raw_cpu_base + offset; | |
db0d4db2 MZ |
1080 | } |
1081 | ||
1082 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
dc9722cc JH |
1083 | } else { |
1084 | /* Normal, sane GIC... */ | |
f673b9b5 | 1085 | WARN(gic->percpu_offset, |
db0d4db2 | 1086 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
f673b9b5 JH |
1087 | gic->percpu_offset); |
1088 | gic->dist_base.common_base = gic->raw_dist_base; | |
1089 | gic->cpu_base.common_base = gic->raw_cpu_base; | |
db0d4db2 MZ |
1090 | gic_set_base_accessor(gic, gic_get_common_base); |
1091 | } | |
bef8f9ee | 1092 | |
4294f8ba RH |
1093 | /* |
1094 | * Find out how many interrupts are supported. | |
1095 | * The GIC only supports up to 1020 interrupt sources. | |
1096 | */ | |
db0d4db2 | 1097 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1098 | gic_irqs = (gic_irqs + 1) * 32; |
1099 | if (gic_irqs > 1020) | |
1100 | gic_irqs = 1020; | |
1101 | gic->gic_irqs = gic_irqs; | |
1102 | ||
891ae769 MZ |
1103 | if (handle) { /* DT/ACPI */ |
1104 | gic->domain = irq_domain_create_linear(handle, gic_irqs, | |
1105 | &gic_irq_domain_hierarchy_ops, | |
1106 | gic); | |
1107 | } else { /* Legacy support */ | |
9a1091ef YC |
1108 | /* |
1109 | * For primary GICs, skip over SGIs. | |
1110 | * For secondary GICs, skip over PPIs, too. | |
1111 | */ | |
f673b9b5 | 1112 | if (gic == &gic_data[0] && (irq_start & 31) > 0) { |
9a1091ef YC |
1113 | hwirq_base = 16; |
1114 | if (irq_start != -1) | |
1115 | irq_start = (irq_start & ~31) + 16; | |
1116 | } else { | |
1117 | hwirq_base = 32; | |
1118 | } | |
1119 | ||
1120 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1121 | |
006e983b S |
1122 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1123 | numa_node_id()); | |
1124 | if (IS_ERR_VALUE(irq_base)) { | |
1125 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
1126 | irq_start); | |
1127 | irq_base = irq_start; | |
1128 | } | |
1129 | ||
891ae769 | 1130 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
006e983b | 1131 | hwirq_base, &gic_irq_domain_ops, gic); |
f37a53cc | 1132 | } |
006e983b | 1133 | |
dc9722cc JH |
1134 | if (WARN_ON(!gic->domain)) { |
1135 | ret = -ENODEV; | |
1136 | goto error; | |
1137 | } | |
bef8f9ee | 1138 | |
f673b9b5 | 1139 | if (gic == &gic_data[0]) { |
567e5a01 JH |
1140 | /* |
1141 | * Initialize the CPU interface map to all CPUs. | |
1142 | * It will be refined as each CPU probes its ID. | |
1143 | * This is only necessary for the primary GIC. | |
1144 | */ | |
1145 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1146 | gic_cpu_map[i] = 0xff; | |
b1cffebf | 1147 | #ifdef CONFIG_SMP |
08332dff MR |
1148 | set_smp_cross_call(gic_raise_softirq); |
1149 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 1150 | #endif |
08332dff | 1151 | set_handle_irq(gic_handle_irq); |
0b996fd3 MZ |
1152 | if (static_key_true(&supports_deactivate)) |
1153 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
08332dff | 1154 | } |
cfed7d60 | 1155 | |
4294f8ba | 1156 | gic_dist_init(gic); |
dc9722cc JH |
1157 | ret = gic_cpu_init(gic); |
1158 | if (ret) | |
1159 | goto error; | |
1160 | ||
1161 | ret = gic_pm_init(gic); | |
1162 | if (ret) | |
1163 | goto error; | |
1164 | ||
1165 | return 0; | |
1166 | ||
1167 | error: | |
f673b9b5 | 1168 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
dc9722cc JH |
1169 | free_percpu(gic->dist_base.percpu_base); |
1170 | free_percpu(gic->cpu_base.percpu_base); | |
1171 | } | |
1172 | ||
1173 | kfree(gic->chip.name); | |
1174 | ||
1175 | return ret; | |
b580b899 RK |
1176 | } |
1177 | ||
e81a7cd9 MZ |
1178 | void __init gic_init(unsigned int gic_nr, int irq_start, |
1179 | void __iomem *dist_base, void __iomem *cpu_base) | |
4a6ac304 | 1180 | { |
f673b9b5 JH |
1181 | struct gic_chip_data *gic; |
1182 | ||
1183 | if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR)) | |
1184 | return; | |
1185 | ||
4a6ac304 MZ |
1186 | /* |
1187 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1188 | * bother with these... | |
1189 | */ | |
1190 | static_key_slow_dec(&supports_deactivate); | |
f673b9b5 JH |
1191 | |
1192 | gic = &gic_data[gic_nr]; | |
1193 | gic->raw_dist_base = dist_base; | |
1194 | gic->raw_cpu_base = cpu_base; | |
1195 | ||
1196 | __gic_init_bases(gic, irq_start, NULL); | |
4a6ac304 MZ |
1197 | } |
1198 | ||
d6490461 JH |
1199 | static void gic_teardown(struct gic_chip_data *gic) |
1200 | { | |
1201 | if (WARN_ON(!gic)) | |
1202 | return; | |
1203 | ||
1204 | if (gic->raw_dist_base) | |
1205 | iounmap(gic->raw_dist_base); | |
1206 | if (gic->raw_cpu_base) | |
1207 | iounmap(gic->raw_cpu_base); | |
4a6ac304 MZ |
1208 | } |
1209 | ||
b3f7ed03 | 1210 | #ifdef CONFIG_OF |
46f101df | 1211 | static int gic_cnt __initdata; |
b3f7ed03 | 1212 | |
12e14066 MZ |
1213 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1214 | { | |
1215 | struct resource cpuif_res; | |
1216 | ||
1217 | of_address_to_resource(node, 1, &cpuif_res); | |
1218 | ||
1219 | if (!is_hyp_mode_available()) | |
1220 | return false; | |
1221 | if (resource_size(&cpuif_res) < SZ_8K) | |
1222 | return false; | |
1223 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1224 | u32 val_low, val_high; | |
1225 | ||
1226 | /* | |
1227 | * Verify that we have the first 4kB of a GIC400 | |
1228 | * aliased over the first 64kB by checking the | |
1229 | * GICC_IIDR register on both ends. | |
1230 | */ | |
1231 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); | |
1232 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); | |
1233 | if ((val_low & 0xffff0fff) != 0x0202043B || | |
1234 | val_low != val_high) | |
1235 | return false; | |
1236 | ||
1237 | /* | |
1238 | * Move the base up by 60kB, so that we have a 8kB | |
1239 | * contiguous region, which allows us to use GICC_DIR | |
1240 | * at its normal offset. Please pass me that bucket. | |
1241 | */ | |
1242 | *base += 0xf000; | |
1243 | cpuif_res.start += 0xf000; | |
1244 | pr_warn("GIC: Adjusting CPU interface base to %pa", | |
1245 | &cpuif_res.start); | |
1246 | } | |
1247 | ||
1248 | return true; | |
1249 | } | |
1250 | ||
d6490461 JH |
1251 | static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) |
1252 | { | |
1253 | if (!gic || !node) | |
1254 | return -EINVAL; | |
1255 | ||
1256 | gic->raw_dist_base = of_iomap(node, 0); | |
1257 | if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) | |
1258 | goto error; | |
1259 | ||
1260 | gic->raw_cpu_base = of_iomap(node, 1); | |
1261 | if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) | |
1262 | goto error; | |
1263 | ||
1264 | if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) | |
1265 | gic->percpu_offset = 0; | |
1266 | ||
1267 | return 0; | |
1268 | ||
1269 | error: | |
1270 | gic_teardown(gic); | |
1271 | ||
1272 | return -ENOMEM; | |
1273 | } | |
1274 | ||
8673c1d7 | 1275 | int __init |
6859358e | 1276 | gic_of_init(struct device_node *node, struct device_node *parent) |
b3f7ed03 | 1277 | { |
f673b9b5 | 1278 | struct gic_chip_data *gic; |
dc9722cc | 1279 | int irq, ret; |
b3f7ed03 RH |
1280 | |
1281 | if (WARN_ON(!node)) | |
1282 | return -ENODEV; | |
1283 | ||
f673b9b5 JH |
1284 | if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) |
1285 | return -EINVAL; | |
1286 | ||
1287 | gic = &gic_data[gic_cnt]; | |
b3f7ed03 | 1288 | |
d6490461 JH |
1289 | ret = gic_of_setup(gic, node); |
1290 | if (ret) | |
1291 | return ret; | |
b3f7ed03 | 1292 | |
0b996fd3 MZ |
1293 | /* |
1294 | * Disable split EOI/Deactivate if either HYP is not available | |
1295 | * or the CPU interface is too small. | |
1296 | */ | |
f673b9b5 | 1297 | if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) |
0b996fd3 MZ |
1298 | static_key_slow_dec(&supports_deactivate); |
1299 | ||
f673b9b5 | 1300 | ret = __gic_init_bases(gic, -1, &node->fwnode); |
dc9722cc | 1301 | if (ret) { |
d6490461 | 1302 | gic_teardown(gic); |
dc9722cc JH |
1303 | return ret; |
1304 | } | |
db0d4db2 | 1305 | |
eeb44658 NP |
1306 | if (!gic_cnt) |
1307 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1308 | |
1309 | if (parent) { | |
1310 | irq = irq_of_parse_and_map(node, 0); | |
1311 | gic_cascade_irq(gic_cnt, irq); | |
1312 | } | |
853a33ce SS |
1313 | |
1314 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
0644b3da | 1315 | gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); |
853a33ce | 1316 | |
b3f7ed03 RH |
1317 | gic_cnt++; |
1318 | return 0; | |
1319 | } | |
144cb088 | 1320 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1321 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1322 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1323 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1324 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1325 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1326 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1327 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1328 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
81243e44 | 1329 | |
b3f7ed03 | 1330 | #endif |
d60fc389 TN |
1331 | |
1332 | #ifdef CONFIG_ACPI | |
f26527b1 | 1333 | static phys_addr_t cpu_phy_base __initdata; |
d60fc389 TN |
1334 | |
1335 | static int __init | |
1336 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1337 | const unsigned long end) | |
1338 | { | |
1339 | struct acpi_madt_generic_interrupt *processor; | |
1340 | phys_addr_t gic_cpu_base; | |
1341 | static int cpu_base_assigned; | |
1342 | ||
1343 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1344 | ||
99e3e3ae | 1345 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1346 | return -EINVAL; |
1347 | ||
1348 | /* | |
1349 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1350 | * All CPU interface addresses have to be the same. | |
1351 | */ | |
1352 | gic_cpu_base = processor->base_address; | |
1353 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1354 | return -EINVAL; | |
1355 | ||
1356 | cpu_phy_base = gic_cpu_base; | |
1357 | cpu_base_assigned = 1; | |
1358 | return 0; | |
1359 | } | |
1360 | ||
f26527b1 MZ |
1361 | /* The things you have to do to just *count* something... */ |
1362 | static int __init acpi_dummy_func(struct acpi_subtable_header *header, | |
1363 | const unsigned long end) | |
d60fc389 | 1364 | { |
f26527b1 MZ |
1365 | return 0; |
1366 | } | |
d60fc389 | 1367 | |
f26527b1 MZ |
1368 | static bool __init acpi_gic_redist_is_present(void) |
1369 | { | |
1370 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1371 | acpi_dummy_func, 0) > 0; | |
1372 | } | |
d60fc389 | 1373 | |
f26527b1 MZ |
1374 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
1375 | struct acpi_probe_entry *ape) | |
1376 | { | |
1377 | struct acpi_madt_generic_distributor *dist; | |
1378 | dist = (struct acpi_madt_generic_distributor *)header; | |
d60fc389 | 1379 | |
f26527b1 MZ |
1380 | return (dist->version == ape->driver_data && |
1381 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || | |
1382 | !acpi_gic_redist_is_present())); | |
d60fc389 TN |
1383 | } |
1384 | ||
f26527b1 MZ |
1385 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
1386 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) | |
1387 | ||
1388 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, | |
1389 | const unsigned long end) | |
d60fc389 | 1390 | { |
f26527b1 | 1391 | struct acpi_madt_generic_distributor *dist; |
891ae769 | 1392 | struct fwnode_handle *domain_handle; |
f673b9b5 | 1393 | struct gic_chip_data *gic = &gic_data[0]; |
dc9722cc | 1394 | int count, ret; |
d60fc389 TN |
1395 | |
1396 | /* Collect CPU base addresses */ | |
f26527b1 MZ |
1397 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
1398 | gic_acpi_parse_madt_cpu, 0); | |
d60fc389 TN |
1399 | if (count <= 0) { |
1400 | pr_err("No valid GICC entries exist\n"); | |
1401 | return -EINVAL; | |
1402 | } | |
1403 | ||
f673b9b5 JH |
1404 | gic->raw_cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
1405 | if (!gic->raw_cpu_base) { | |
d60fc389 TN |
1406 | pr_err("Unable to map GICC registers\n"); |
1407 | return -ENOMEM; | |
1408 | } | |
1409 | ||
f26527b1 | 1410 | dist = (struct acpi_madt_generic_distributor *)header; |
f673b9b5 JH |
1411 | gic->raw_dist_base = ioremap(dist->base_address, |
1412 | ACPI_GICV2_DIST_MEM_SIZE); | |
1413 | if (!gic->raw_dist_base) { | |
d60fc389 | 1414 | pr_err("Unable to map GICD registers\n"); |
d6490461 | 1415 | gic_teardown(gic); |
d60fc389 TN |
1416 | return -ENOMEM; |
1417 | } | |
1418 | ||
0b996fd3 MZ |
1419 | /* |
1420 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1421 | * guarantees that we'll always have a GICv2, so the CPU | |
1422 | * interface will always be the right size. | |
1423 | */ | |
1424 | if (!is_hyp_mode_available()) | |
1425 | static_key_slow_dec(&supports_deactivate); | |
1426 | ||
d60fc389 | 1427 | /* |
891ae769 | 1428 | * Initialize GIC instance zero (no multi-GIC support). |
d60fc389 | 1429 | */ |
f673b9b5 | 1430 | domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); |
891ae769 MZ |
1431 | if (!domain_handle) { |
1432 | pr_err("Unable to allocate domain handle\n"); | |
d6490461 | 1433 | gic_teardown(gic); |
891ae769 MZ |
1434 | return -ENOMEM; |
1435 | } | |
1436 | ||
f673b9b5 | 1437 | ret = __gic_init_bases(gic, -1, domain_handle); |
dc9722cc JH |
1438 | if (ret) { |
1439 | pr_err("Failed to initialise GIC\n"); | |
1440 | irq_domain_free_fwnode(domain_handle); | |
d6490461 | 1441 | gic_teardown(gic); |
dc9722cc JH |
1442 | return ret; |
1443 | } | |
d8f4f161 | 1444 | |
891ae769 | 1445 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
0644b3da SS |
1446 | |
1447 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1448 | gicv2m_init(NULL, gic_data[0].domain); | |
1449 | ||
d60fc389 TN |
1450 | return 0; |
1451 | } | |
f26527b1 MZ |
1452 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
1453 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, | |
1454 | gic_v2_acpi_init); | |
1455 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1456 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, | |
1457 | gic_v2_acpi_init); | |
d60fc389 | 1458 | #endif |