[deliverable/linux.git] / drivers / irqchip / irq-mbigen.c

/*
 * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
 * Author: Jun Ma <majun258@huawei.com>
 * Author: Yun Wu <wuyun.wu@huawei.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/module.h>
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

/* Interrupt numbers per mbigen node supported */
#define IRQS_PER_MBIGEN_NODE		128

/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
#define RESERVED_IRQ_PER_MBIGEN_CHIP	64

/* The maximum IRQ pin number of mbigen chip(start from 0) */
#define MAXIMUM_IRQ_PIN_NUM		1407

/**
 * In mbigen vector register
 * bit[21:12]:	event id value
 * bit[11:0]:	device id
 */
#define IRQ_EVENT_ID_SHIFT		12
#define IRQ_EVENT_ID_MASK		0x3ff

/* register range of each mbigen node */
#define MBIGEN_NODE_OFFSET		0x1000

/* offset of vector register in mbigen node */
#define REG_MBIGEN_VEC_OFFSET		0x200

/**
 * struct mbigen_device - holds the information of mbigen device.
 *
 * @pdev:		pointer to the platform device structure of mbigen chip.
 * @base:		mapped address of this mbigen chip.
 */
struct mbigen_device {
	struct platform_device	*pdev;
	void __iomem		*base;
};

static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
{
	unsigned int nid, pin;

	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
	pin = hwirq % IRQS_PER_MBIGEN_NODE;

	return pin * 4 + nid * MBIGEN_NODE_OFFSET
			+ REG_MBIGEN_VEC_OFFSET;
}

static struct irq_chip mbigen_irq_chip = {
	.name =			"mbigen-v2",
};

static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
{
	struct irq_data *d = irq_get_irq_data(desc->irq);
	void __iomem *base = d->chip_data;
	u32 val;

	base += get_mbigen_vec_reg(d->hwirq);
	val = readl_relaxed(base);

	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
	val |= (msg->data << IRQ_EVENT_ID_SHIFT);

	/* The address of doorbell is encoded in mbigen register by default
	 * So,we don't need to program the doorbell address at here
	 */
	writel_relaxed(val, base);
}

static int mbigen_domain_translate(struct irq_domain *d,
				    struct irq_fwspec *fwspec,
				    unsigned long *hwirq,
				    unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 2)
			return -EINVAL;

		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
			(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
			return -EINVAL;
		else
			*hwirq = fwspec->param[0];

		/* If there is no valid irq type, just use the default type */
		if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
			(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
			*type = fwspec->param[1];
		else
			return -EINVAL;

		return 0;
	}
	return -EINVAL;
}

static int mbigen_irq_domain_alloc(struct irq_domain *domain,
					unsigned int virq,
					unsigned int nr_irqs,
					void *args)
{
	struct irq_fwspec *fwspec = args;
	irq_hw_number_t hwirq;
	unsigned int type;
	struct mbigen_device *mgn_chip;
	int i, err;

	err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
	if (err)
		return err;

	err = platform_msi_domain_alloc(domain, virq, nr_irqs);
	if (err)
		return err;

	mgn_chip = platform_msi_get_host_data(domain);

	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
				      &mbigen_irq_chip, mgn_chip->base);

	return 0;
}

static struct irq_domain_ops mbigen_domain_ops = {
	.translate	= mbigen_domain_translate,
	.alloc		= mbigen_irq_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

static int mbigen_device_probe(struct platform_device *pdev)
{
	struct mbigen_device *mgn_chip;
	struct resource *res;
	struct irq_domain *domain;
	u32 num_pins;

	mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
	if (!mgn_chip)
		return -ENOMEM;

	mgn_chip->pdev = pdev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mgn_chip->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mgn_chip->base))
		return PTR_ERR(mgn_chip->base);

	if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) {
		dev_err(&pdev->dev, "No num-pins property\n");
		return -EINVAL;
	}

	domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
							mbigen_write_msg,
							&mbigen_domain_ops,
							mgn_chip);

	if (!domain)
		return -ENOMEM;

	platform_set_drvdata(pdev, mgn_chip);

	dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins);

	return 0;
}

static const struct of_device_id mbigen_of_match[] = {
	{ .compatible = "hisilicon,mbigen-v2" },
	{ /* END */ }
};
MODULE_DEVICE_TABLE(of, mbigen_of_match);

static struct platform_driver mbigen_platform_driver = {
	.driver = {
		.name		= "Hisilicon MBIGEN-V2",
		.owner		= THIS_MODULE,
		.of_match_table	= mbigen_of_match,
	},
	.probe			= mbigen_device_probe,
};

module_platform_driver(mbigen_platform_driver);

MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
Commit	Line	Data
717c3dbc MJ	1	/*
	2	* Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
	3	* Author: Jun Ma <majun258@huawei.com>
	4	* Author: Yun Wu <wuyun.wu@huawei.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
9650c60e MJ	19	#include <linux/interrupt.h>
9650c60e MJ	20	#include <linux/irqchip.h>
717c3dbc	21	#include <linux/module.h>
9650c60e	22	#include <linux/msi.h>
717c3dbc MJ	23	#include <linux/of_address.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/of_platform.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/slab.h>
	28
9650c60e MJ	29	/* Interrupt numbers per mbigen node supported */
	30	#define IRQS_PER_MBIGEN_NODE 128
	31
	32	/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
	33	#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
	34
	35	/* The maximum IRQ pin number of mbigen chip(start from 0) */
	36	#define MAXIMUM_IRQ_PIN_NUM 1407
	37
	38	/**
	39	* In mbigen vector register
	40	* bit[21:12]: event id value
	41	* bit[11:0]: device id
	42	*/
	43	#define IRQ_EVENT_ID_SHIFT 12
	44	#define IRQ_EVENT_ID_MASK 0x3ff
	45
	46	/* register range of each mbigen node */
	47	#define MBIGEN_NODE_OFFSET 0x1000
	48
	49	/* offset of vector register in mbigen node */
	50	#define REG_MBIGEN_VEC_OFFSET 0x200
	51
717c3dbc MJ	52	/**
	53	* struct mbigen_device - holds the information of mbigen device.
	54	*
	55	* @pdev: pointer to the platform device structure of mbigen chip.
	56	* @base: mapped address of this mbigen chip.
	57	*/
	58	struct mbigen_device {
	59	struct platform_device *pdev;
	60	void __iomem *base;
	61	};
	62
9650c60e MJ	63	static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
	64	{
	65	unsigned int nid, pin;
	66
	67	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
	68	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
	69	pin = hwirq % IRQS_PER_MBIGEN_NODE;
	70
	71	return pin * 4 + nid * MBIGEN_NODE_OFFSET
	72	+ REG_MBIGEN_VEC_OFFSET;
	73	}
	74
	75	static struct irq_chip mbigen_irq_chip = {
	76	.name = "mbigen-v2",
	77	};
	78
	79	static void mbigen_write_msg(struct msi_desc desc, struct msi_msg msg)
	80	{
	81	struct irq_data *d = irq_get_irq_data(desc->irq);
	82	void __iomem *base = d->chip_data;
	83	u32 val;
	84
	85	base += get_mbigen_vec_reg(d->hwirq);
	86	val = readl_relaxed(base);
	87
	88	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
	89	val \|= (msg->data << IRQ_EVENT_ID_SHIFT);
	90
	91	/* The address of doorbell is encoded in mbigen register by default
	92	* So,we don't need to program the doorbell address at here
	93	*/
	94	writel_relaxed(val, base);
	95	}
	96
	97	static int mbigen_domain_translate(struct irq_domain *d,
	98	struct irq_fwspec *fwspec,
	99	unsigned long *hwirq,
	100	unsigned int *type)
	101	{
	102	if (is_of_node(fwspec->fwnode)) {
	103	if (fwspec->param_count != 2)
	104	return -EINVAL;
	105
	106	if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) \|\|
	107	(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
	108	return -EINVAL;
	109	else
	110	*hwirq = fwspec->param[0];
	111
	112	/* If there is no valid irq type, just use the default type */
	113	if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) \|\|
	114	(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
	115	*type = fwspec->param[1];
	116	else
	117	return -EINVAL;
	118
	119	return 0;
	120	}
	121	return -EINVAL;
	122	}
	123
	124	static int mbigen_irq_domain_alloc(struct irq_domain *domain,
	125	unsigned int virq,
	126	unsigned int nr_irqs,
127	void *args)
128	{
129	struct irq_fwspec *fwspec = args;
130	irq_hw_number_t hwirq;
131	unsigned int type;
132	struct mbigen_device *mgn_chip;
133	int i, err;
134
135	err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
136	if (err)
137	return err;
138
139	err = platform_msi_domain_alloc(domain, virq, nr_irqs);
140	if (err)
141	return err;
142
143	mgn_chip = platform_msi_get_host_data(domain);
144
145	for (i = 0; i < nr_irqs; i++)
146	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
147	&mbigen_irq_chip, mgn_chip->base);
148
149	return 0;
150	}
151
152	static struct irq_domain_ops mbigen_domain_ops = {
153	.translate = mbigen_domain_translate,
154	.alloc = mbigen_irq_domain_alloc,
155	.free = irq_domain_free_irqs_common,
156	};
157
717c3dbc MJ	158	static int mbigen_device_probe(struct platform_device *pdev)
	159	{
	160	struct mbigen_device *mgn_chip;
	161	struct resource *res;
9650c60e MJ	162	struct irq_domain *domain;
9650c60e MJ	163	u32 num_pins;
717c3dbc MJ	164
	165	mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
	166	if (!mgn_chip)
	167	return -ENOMEM;
	168
	169	mgn_chip->pdev = pdev;
	170
	171	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	172	mgn_chip->base = devm_ioremap_resource(&pdev->dev, res);
	173	if (IS_ERR(mgn_chip->base))
	174	return PTR_ERR(mgn_chip->base);
	175
9650c60e MJ	176	if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) {
	177	dev_err(&pdev->dev, "No num-pins property\n");
	178	return -EINVAL;
	179	}
	180
	181	domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
	182	mbigen_write_msg,
	183	&mbigen_domain_ops,
	184	mgn_chip);
	185
	186	if (!domain)
	187	return -ENOMEM;
	188
717c3dbc MJ	189	platform_set_drvdata(pdev, mgn_chip);
717c3dbc MJ	190
9650c60e MJ	191	dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins);
9650c60e MJ	192
717c3dbc MJ	193	return 0;
	194	}
	195
	196	static const struct of_device_id mbigen_of_match[] = {
	197	{ .compatible = "hisilicon,mbigen-v2" },
	198	{ /* END */ }
	199	};
	200	MODULE_DEVICE_TABLE(of, mbigen_of_match);
	201
	202	static struct platform_driver mbigen_platform_driver = {
	203	.driver = {
	204	.name = "Hisilicon MBIGEN-V2",
	205	.owner = THIS_MODULE,
	206	.of_match_table = mbigen_of_match,
	207	},
	208	.probe = mbigen_device_probe,
	209	};
	210
	211	module_platform_driver(mbigen_platform_driver);
	212
	213	MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
	214	MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
	215	MODULE_LICENSE("GPL");
	216	MODULE_DESCRIPTION("Hisilicon MBI Generator driver");