[deliverable/linux.git] / drivers / irqchip / irq-mmp.c

/*
 *  linux/arch/arm/mach-mmp/irq.c
 *
 *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
 *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
 *
 *  Author:	Bin Yang <bin.yang@marvell.com>
 *              Haojian Zhuang <haojian.zhuang@gmail.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>

#include <mach/irqs.h>

#include "irqchip.h"

#define MAX_ICU_NR		16

#define PJ1_INT_SEL		0x10c
#define PJ4_INT_SEL		0x104

/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
#define SEL_INT_PENDING		(1 << 6)
#define SEL_INT_NUM_MASK	0x3f

struct icu_chip_data {
	int			nr_irqs;
	unsigned int		virq_base;
	unsigned int		cascade_irq;
	void __iomem		*reg_status;
	void __iomem		*reg_mask;
	unsigned int		conf_enable;
	unsigned int		conf_disable;
	unsigned int		conf_mask;
	unsigned int		clr_mfp_irq_base;
	unsigned int		clr_mfp_hwirq;
	struct irq_domain	*domain;
};

struct mmp_intc_conf {
	unsigned int	conf_enable;
	unsigned int	conf_disable;
	unsigned int	conf_mask;
};

static void __iomem *mmp_icu_base;
static struct icu_chip_data icu_data[MAX_ICU_NR];
static int max_icu_nr;

extern void mmp2_clear_pmic_int(void);

static void icu_mask_ack_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_disable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
#ifdef CONFIG_CPU_MMP2
		if ((data->virq_base == data->clr_mfp_irq_base)
			&& (hwirq == data->clr_mfp_hwirq))
			mmp2_clear_pmic_int();
#endif
		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

static void icu_mask_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_disable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

static void icu_unmask_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_enable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
		r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

struct irq_chip icu_irq_chip = {
	.name		= "icu_irq",
	.irq_mask	= icu_mask_irq,
	.irq_mask_ack	= icu_mask_ack_irq,
	.irq_unmask	= icu_unmask_irq,
};

static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	struct irq_domain *domain;
	struct icu_chip_data *data;
	int i;
	unsigned long mask, status, n;

	for (i = 1; i < max_icu_nr; i++) {
		if (irq == icu_data[i].cascade_irq) {
			domain = icu_data[i].domain;
			data = (struct icu_chip_data *)domain->host_data;
			break;
		}
	}
	if (i >= max_icu_nr) {
		pr_err("Spurious irq %d in MMP INTC\n", irq);
		return;
	}

	mask = readl_relaxed(data->reg_mask);
	while (1) {
		status = readl_relaxed(data->reg_status) & ~mask;
		if (status == 0)
			break;
		for_each_set_bit(n, &status, BITS_PER_LONG) {
			generic_handle_irq(icu_data[i].virq_base + n);
		}
	}
}

static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	set_irq_flags(irq, IRQF_VALID);
	return 0;
}

static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
				const u32 *intspec, unsigned int intsize,
				unsigned long *out_hwirq,
				unsigned int *out_type)
{
	*out_hwirq = intspec[0];
	return 0;
}

const struct irq_domain_ops mmp_irq_domain_ops = {
	.map		= mmp_irq_domain_map,
	.xlate		= mmp_irq_domain_xlate,
};

static struct mmp_intc_conf mmp_conf = {
	.conf_enable	= 0x51,
	.conf_disable	= 0x0,
	.conf_mask	= 0x7f,
};

static struct mmp_intc_conf mmp2_conf = {
	.conf_enable	= 0x20,
	.conf_disable	= 0x0,
	.conf_mask	= 0x7f,
};

static asmlinkage void __exception_irq_entry
mmp_handle_irq(struct pt_regs *regs)
{
	int irq, hwirq;

	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
	if (!(hwirq & SEL_INT_PENDING))
		return;
	hwirq &= SEL_INT_NUM_MASK;
	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	handle_IRQ(irq, regs);
}

static asmlinkage void __exception_irq_entry
mmp2_handle_irq(struct pt_regs *regs)
{
	int irq, hwirq;

	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
	if (!(hwirq & SEL_INT_PENDING))
		return;
	hwirq &= SEL_INT_NUM_MASK;
	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	handle_IRQ(irq, regs);
}

/* MMP (ARMv5) */
void __init icu_init_irq(void)
{
	int irq;

	max_icu_nr = 1;
	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	icu_data[0].conf_enable = mmp_conf.conf_enable;
	icu_data[0].conf_disable = mmp_conf.conf_disable;
	icu_data[0].conf_mask = mmp_conf.conf_mask;
	icu_data[0].nr_irqs = 64;
	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
						   &irq_domain_simple_ops,
						   &icu_data[0]);
	for (irq = 0; irq < 64; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp_handle_irq);
}

/* MMP2 (ARMv7) */
void __init mmp2_init_icu(void)
{
	int irq;

	max_icu_nr = 8;
	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	icu_data[0].nr_irqs = 64;
	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
						   &irq_domain_simple_ops,
						   &icu_data[0]);
	icu_data[1].reg_status = mmp_icu_base + 0x150;
	icu_data[1].reg_mask = mmp_icu_base + 0x168;
	icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
	icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
	icu_data[1].nr_irqs = 2;
	icu_data[1].cascade_irq = 4;
	icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
						   icu_data[1].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[1]);
	icu_data[2].reg_status = mmp_icu_base + 0x154;
	icu_data[2].reg_mask = mmp_icu_base + 0x16c;
	icu_data[2].nr_irqs = 2;
	icu_data[2].cascade_irq = 5;
	icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
						   icu_data[2].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[2]);
	icu_data[3].reg_status = mmp_icu_base + 0x180;
	icu_data[3].reg_mask = mmp_icu_base + 0x17c;
	icu_data[3].nr_irqs = 3;
	icu_data[3].cascade_irq = 9;
	icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
						   icu_data[3].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[3]);
	icu_data[4].reg_status = mmp_icu_base + 0x158;
	icu_data[4].reg_mask = mmp_icu_base + 0x170;
	icu_data[4].nr_irqs = 5;
	icu_data[4].cascade_irq = 17;
	icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
						   icu_data[4].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[4]);
	icu_data[5].reg_status = mmp_icu_base + 0x15c;
	icu_data[5].reg_mask = mmp_icu_base + 0x174;
	icu_data[5].nr_irqs = 15;
	icu_data[5].cascade_irq = 35;
	icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
						   icu_data[5].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[5]);
	icu_data[6].reg_status = mmp_icu_base + 0x160;
	icu_data[6].reg_mask = mmp_icu_base + 0x178;
	icu_data[6].nr_irqs = 2;
	icu_data[6].cascade_irq = 51;
	icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
						   icu_data[6].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[6]);
	icu_data[7].reg_status = mmp_icu_base + 0x188;
	icu_data[7].reg_mask = mmp_icu_base + 0x184;
	icu_data[7].nr_irqs = 2;
	icu_data[7].cascade_irq = 55;
	icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
						   icu_data[7].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[7]);
	for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		switch (irq) {
		case IRQ_MMP2_PMIC_MUX:
		case IRQ_MMP2_RTC_MUX:
		case IRQ_MMP2_KEYPAD_MUX:
		case IRQ_MMP2_TWSI_MUX:
		case IRQ_MMP2_MISC_MUX:
		case IRQ_MMP2_MIPI_HSI1_MUX:
		case IRQ_MMP2_MIPI_HSI0_MUX:
			irq_set_chip(irq, &icu_irq_chip);
			irq_set_chained_handler(irq, icu_mux_irq_demux);
			break;
		default:
			irq_set_chip_and_handler(irq, &icu_irq_chip,
						 handle_level_irq);
			break;
		}
		set_irq_flags(irq, IRQF_VALID);
	}
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp2_handle_irq);
}

#ifdef CONFIG_OF
static int __init mmp_init_bases(struct device_node *node)
{
	int ret, nr_irqs, irq, i = 0;

	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
	if (ret) {
		pr_err("Not found mrvl,intc-nr-irqs property\n");
		return ret;
	}

	mmp_icu_base = of_iomap(node, 0);
	if (!mmp_icu_base) {
		pr_err("Failed to get interrupt controller register\n");
		return -ENOMEM;
	}

	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
						   &mmp_irq_domain_ops,
						   &icu_data[0]);
	for (irq = 0; irq < nr_irqs; irq++) {
		ret = irq_create_mapping(icu_data[0].domain, irq);
		if (!ret) {
			pr_err("Failed to mapping hwirq\n");
			goto err;
		}
		if (!irq)
			icu_data[0].virq_base = ret;
	}
	icu_data[0].nr_irqs = nr_irqs;
	return 0;
err:
	if (icu_data[0].virq_base) {
		for (i = 0; i < irq; i++)
			irq_dispose_mapping(icu_data[0].virq_base + i);
	}
	irq_domain_remove(icu_data[0].domain);
	iounmap(mmp_icu_base);
	return -EINVAL;
}

static int __init mmp_of_init(struct device_node *node,
			      struct device_node *parent)
{
	int ret;

	ret = mmp_init_bases(node);
	if (ret < 0)
		return ret;

	icu_data[0].conf_enable = mmp_conf.conf_enable;
	icu_data[0].conf_disable = mmp_conf.conf_disable;
	icu_data[0].conf_mask = mmp_conf.conf_mask;
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp_handle_irq);
	max_icu_nr = 1;
	return 0;
}
IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);

static int __init mmp2_of_init(struct device_node *node,
			       struct device_node *parent)
{
	int ret;

	ret = mmp_init_bases(node);
	if (ret < 0)
		return ret;

	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp2_handle_irq);
	max_icu_nr = 1;
	return 0;
}
IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);

static int __init mmp2_mux_of_init(struct device_node *node,
				   struct device_node *parent)
{
	struct resource res;
	int i, ret, irq, j = 0;
	u32 nr_irqs, mfp_irq;

	if (!parent)
		return -ENODEV;

	i = max_icu_nr;
	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
				   &nr_irqs);
	if (ret) {
		pr_err("Not found mrvl,intc-nr-irqs property\n");
		return -EINVAL;
	}
	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("Not found reg property\n");
		return -EINVAL;
	}
	icu_data[i].reg_status = mmp_icu_base + res.start;
	ret = of_address_to_resource(node, 1, &res);
	if (ret < 0) {
		pr_err("Not found reg property\n");
		return -EINVAL;
	}
	icu_data[i].reg_mask = mmp_icu_base + res.start;
	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
	if (!icu_data[i].cascade_irq)
		return -EINVAL;

	icu_data[i].virq_base = 0;
	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
						   &mmp_irq_domain_ops,
						   &icu_data[i]);
	for (irq = 0; irq < nr_irqs; irq++) {
		ret = irq_create_mapping(icu_data[i].domain, irq);
		if (!ret) {
			pr_err("Failed to mapping hwirq\n");
			goto err;
		}
		if (!irq)
			icu_data[i].virq_base = ret;
	}
	icu_data[i].nr_irqs = nr_irqs;
	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
				  &mfp_irq)) {
		icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
		icu_data[i].clr_mfp_hwirq = mfp_irq;
	}
	irq_set_chained_handler(icu_data[i].cascade_irq,
				icu_mux_irq_demux);
	max_icu_nr++;
	return 0;
err:
	if (icu_data[i].virq_base) {
		for (j = 0; j < irq; j++)
			irq_dispose_mapping(icu_data[i].virq_base + j);
	}
	irq_domain_remove(icu_data[i].domain);
	return -EINVAL;
}
IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
#endif
Commit	Line	Data
c24b3114 HZ	1	/*
	2	* linux/arch/arm/mach-mmp/irq.c
	3	*
	4	* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
	5	* Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
	6	*
	7	* Author: Bin Yang <bin.yang@marvell.com>
	8	* Haojian Zhuang <haojian.zhuang@gmail.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/init.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqdomain.h>
	19	#include <linux/io.h>
	20	#include <linux/ioport.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23
0f374561 HZ	24	#include <asm/exception.h>
	25	#include <asm/mach/irq.h>
	26
c24b3114 HZ	27	#include <mach/irqs.h>
c24b3114 HZ	28
0f374561 HZ	29	#include "irqchip.h"
0f374561 HZ	30
c24b3114 HZ	31	#define MAX_ICU_NR 16
c24b3114 HZ	32
0f374561 HZ	33	#define PJ1_INT_SEL 0x10c
	34	#define PJ4_INT_SEL 0x104
	35
	36	/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
	37	#define SEL_INT_PENDING (1 << 6)
	38	#define SEL_INT_NUM_MASK 0x3f
	39
c24b3114 HZ	40	struct icu_chip_data {
	41	int nr_irqs;
	42	unsigned int virq_base;
	43	unsigned int cascade_irq;
	44	void __iomem *reg_status;
	45	void __iomem *reg_mask;
	46	unsigned int conf_enable;
	47	unsigned int conf_disable;
	48	unsigned int conf_mask;
	49	unsigned int clr_mfp_irq_base;
	50	unsigned int clr_mfp_hwirq;
	51	struct irq_domain *domain;
	52	};
	53
	54	struct mmp_intc_conf {
	55	unsigned int conf_enable;
	56	unsigned int conf_disable;
	57	unsigned int conf_mask;
	58	};
	59
0f374561	60	static void __iomem *mmp_icu_base;
c24b3114 HZ	61	static struct icu_chip_data icu_data[MAX_ICU_NR];
	62	static int max_icu_nr;
	63
	64	extern void mmp2_clear_pmic_int(void);
	65
	66	static void icu_mask_ack_irq(struct irq_data *d)
	67	{
	68	struct irq_domain *domain = d->domain;
	69	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	70	int hwirq;
	71	u32 r;
	72
	73	hwirq = d->irq - data->virq_base;
	74	if (data == &icu_data[0]) {
	75	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	76	r &= ~data->conf_mask;
	77	r \|= data->conf_disable;
	78	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	79	} else {
	80	#ifdef CONFIG_CPU_MMP2
	81	if ((data->virq_base == data->clr_mfp_irq_base)
	82	&& (hwirq == data->clr_mfp_hwirq))
	83	mmp2_clear_pmic_int();
	84	#endif
	85	r = readl_relaxed(data->reg_mask) \| (1 << hwirq);
	86	writel_relaxed(r, data->reg_mask);
	87	}
	88	}
	89
	90	static void icu_mask_irq(struct irq_data *d)
	91	{
	92	struct irq_domain *domain = d->domain;
	93	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	94	int hwirq;
	95	u32 r;
	96
	97	hwirq = d->irq - data->virq_base;
	98	if (data == &icu_data[0]) {
	99	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	100	r &= ~data->conf_mask;
	101	r \|= data->conf_disable;
	102	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	103	} else {
	104	r = readl_relaxed(data->reg_mask) \| (1 << hwirq);
	105	writel_relaxed(r, data->reg_mask);
	106	}
	107	}
	108
	109	static void icu_unmask_irq(struct irq_data *d)
	110	{
	111	struct irq_domain *domain = d->domain;
	112	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	113	int hwirq;
	114	u32 r;
	115
	116	hwirq = d->irq - data->virq_base;
	117	if (data == &icu_data[0]) {
	118	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	119	r &= ~data->conf_mask;
	120	r \|= data->conf_enable;
	121	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	122	} else {
	123	r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
	124	writel_relaxed(r, data->reg_mask);
125	}
126	}
127
0f102b6c	128	struct irq_chip icu_irq_chip = {
c24b3114 HZ	129	.name = "icu_irq",
	130	.irq_mask = icu_mask_irq,
	131	.irq_mask_ack = icu_mask_ack_irq,
	132	.irq_unmask = icu_unmask_irq,
	133	};
	134
	135	static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
	136	{
	137	struct irq_domain *domain;
	138	struct icu_chip_data *data;
	139	int i;
	140	unsigned long mask, status, n;
	141
	142	for (i = 1; i < max_icu_nr; i++) {
	143	if (irq == icu_data[i].cascade_irq) {
	144	domain = icu_data[i].domain;
	145	data = (struct icu_chip_data *)domain->host_data;
	146	break;
	147	}
	148	}
	149	if (i >= max_icu_nr) {
	150	pr_err("Spurious irq %d in MMP INTC\n", irq);
	151	return;
	152	}
	153
	154	mask = readl_relaxed(data->reg_mask);
	155	while (1) {
	156	status = readl_relaxed(data->reg_status) & ~mask;
	157	if (status == 0)
	158	break;
93d429a7	159	for_each_set_bit(n, &status, BITS_PER_LONG) {
c24b3114	160	generic_handle_irq(icu_data[i].virq_base + n);
c24b3114 HZ	161	}
	162	}
	163	}
	164
	165	static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
	166	irq_hw_number_t hw)
	167	{
	168	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	169	set_irq_flags(irq, IRQF_VALID);
	170	return 0;
	171	}
	172
	173	static int mmp_irq_domain_xlate(struct irq_domain d, struct device_node node,
	174	const u32 *intspec, unsigned int intsize,
	175	unsigned long *out_hwirq,
	176	unsigned int *out_type)
	177	{
	178	*out_hwirq = intspec[0];
	179	return 0;
	180	}
	181
	182	const struct irq_domain_ops mmp_irq_domain_ops = {
	183	.map = mmp_irq_domain_map,
	184	.xlate = mmp_irq_domain_xlate,
	185	};
	186
	187	static struct mmp_intc_conf mmp_conf = {
	188	.conf_enable = 0x51,
	189	.conf_disable = 0x0,
	190	.conf_mask = 0x7f,
	191	};
	192
	193	static struct mmp_intc_conf mmp2_conf = {
	194	.conf_enable = 0x20,
	195	.conf_disable = 0x0,
	196	.conf_mask = 0x7f,
	197	};
	198
0f374561 HZ	199	static asmlinkage void __exception_irq_entry
	200	mmp_handle_irq(struct pt_regs *regs)
	201	{
	202	int irq, hwirq;
	203
	204	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
	205	if (!(hwirq & SEL_INT_PENDING))
	206	return;
	207	hwirq &= SEL_INT_NUM_MASK;
	208	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	209	handle_IRQ(irq, regs);
	210	}
	211
	212	static asmlinkage void __exception_irq_entry
	213	mmp2_handle_irq(struct pt_regs *regs)
	214	{
	215	int irq, hwirq;
	216
	217	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
	218	if (!(hwirq & SEL_INT_PENDING))
	219	return;
	220	hwirq &= SEL_INT_NUM_MASK;
	221	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	222	handle_IRQ(irq, regs);
	223	}
	224
c24b3114 HZ	225	/* MMP (ARMv5) */
	226	void __init icu_init_irq(void)
	227	{
	228	int irq;
	229
	230	max_icu_nr = 1;
	231	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	232	icu_data[0].conf_enable = mmp_conf.conf_enable;
	233	icu_data[0].conf_disable = mmp_conf.conf_disable;
	234	icu_data[0].conf_mask = mmp_conf.conf_mask;
	235	icu_data[0].nr_irqs = 64;
	236	icu_data[0].virq_base = 0;
	237	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
	238	&irq_domain_simple_ops,
	239	&icu_data[0]);
	240	for (irq = 0; irq < 64; irq++) {
	241	icu_mask_irq(irq_get_irq_data(irq));
	242	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	243	set_irq_flags(irq, IRQF_VALID);
	244	}
	245	irq_set_default_host(icu_data[0].domain);
0f374561	246	set_handle_irq(mmp_handle_irq);
c24b3114 HZ	247	}
	248
	249	/* MMP2 (ARMv7) */
	250	void __init mmp2_init_icu(void)
	251	{
	252	int irq;
	253
	254	max_icu_nr = 8;
	255	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	256	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	257	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	258	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	259	icu_data[0].nr_irqs = 64;
	260	icu_data[0].virq_base = 0;
	261	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
	262	&irq_domain_simple_ops,
	263	&icu_data[0]);
	264	icu_data[1].reg_status = mmp_icu_base + 0x150;
	265	icu_data[1].reg_mask = mmp_icu_base + 0x168;
	266	icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
	267	icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
	268	icu_data[1].nr_irqs = 2;
10bd21c0	269	icu_data[1].cascade_irq = 4;
c24b3114 HZ	270	icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
	271	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
	272	icu_data[1].virq_base, 0,
	273	&irq_domain_simple_ops,
	274	&icu_data[1]);
	275	icu_data[2].reg_status = mmp_icu_base + 0x154;
	276	icu_data[2].reg_mask = mmp_icu_base + 0x16c;
	277	icu_data[2].nr_irqs = 2;
10bd21c0	278	icu_data[2].cascade_irq = 5;
c24b3114 HZ	279	icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
	280	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
	281	icu_data[2].virq_base, 0,
	282	&irq_domain_simple_ops,
	283	&icu_data[2]);
	284	icu_data[3].reg_status = mmp_icu_base + 0x180;
	285	icu_data[3].reg_mask = mmp_icu_base + 0x17c;
	286	icu_data[3].nr_irqs = 3;
10bd21c0	287	icu_data[3].cascade_irq = 9;
c24b3114 HZ	288	icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
	289	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
	290	icu_data[3].virq_base, 0,
	291	&irq_domain_simple_ops,
	292	&icu_data[3]);
	293	icu_data[4].reg_status = mmp_icu_base + 0x158;
	294	icu_data[4].reg_mask = mmp_icu_base + 0x170;
	295	icu_data[4].nr_irqs = 5;
10bd21c0	296	icu_data[4].cascade_irq = 17;
c24b3114 HZ	297	icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
	298	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
	299	icu_data[4].virq_base, 0,
	300	&irq_domain_simple_ops,
	301	&icu_data[4]);
	302	icu_data[5].reg_status = mmp_icu_base + 0x15c;
	303	icu_data[5].reg_mask = mmp_icu_base + 0x174;
	304	icu_data[5].nr_irqs = 15;
10bd21c0	305	icu_data[5].cascade_irq = 35;
c24b3114 HZ	306	icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
	307	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
	308	icu_data[5].virq_base, 0,
	309	&irq_domain_simple_ops,
	310	&icu_data[5]);
	311	icu_data[6].reg_status = mmp_icu_base + 0x160;
	312	icu_data[6].reg_mask = mmp_icu_base + 0x178;
	313	icu_data[6].nr_irqs = 2;
10bd21c0	314	icu_data[6].cascade_irq = 51;
c24b3114 HZ	315	icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
	316	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
	317	icu_data[6].virq_base, 0,
	318	&irq_domain_simple_ops,
	319	&icu_data[6]);
	320	icu_data[7].reg_status = mmp_icu_base + 0x188;
	321	icu_data[7].reg_mask = mmp_icu_base + 0x184;
	322	icu_data[7].nr_irqs = 2;
10bd21c0	323	icu_data[7].cascade_irq = 55;
c24b3114 HZ	324	icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
	325	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
	326	icu_data[7].virq_base, 0,
	327	&irq_domain_simple_ops,
	328	&icu_data[7]);
	329	for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
	330	icu_mask_irq(irq_get_irq_data(irq));
	331	switch (irq) {
	332	case IRQ_MMP2_PMIC_MUX:
	333	case IRQ_MMP2_RTC_MUX:
	334	case IRQ_MMP2_KEYPAD_MUX:
	335	case IRQ_MMP2_TWSI_MUX:
	336	case IRQ_MMP2_MISC_MUX:
	337	case IRQ_MMP2_MIPI_HSI1_MUX:
	338	case IRQ_MMP2_MIPI_HSI0_MUX:
	339	irq_set_chip(irq, &icu_irq_chip);
	340	irq_set_chained_handler(irq, icu_mux_irq_demux);
	341	break;
	342	default:
	343	irq_set_chip_and_handler(irq, &icu_irq_chip,
	344	handle_level_irq);
	345	break;
	346	}
	347	set_irq_flags(irq, IRQF_VALID);
	348	}
	349	irq_set_default_host(icu_data[0].domain);
0f374561	350	set_handle_irq(mmp2_handle_irq);
c24b3114 HZ	351	}
	352
	353	#ifdef CONFIG_OF
0f374561	354	static int __init mmp_init_bases(struct device_node *node)
c24b3114	355	{
0f374561	356	int ret, nr_irqs, irq, i = 0;
c24b3114	357
0f374561 HZ	358	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
	359	if (ret) {
	360	pr_err("Not found mrvl,intc-nr-irqs property\n");
	361	return ret;
	362	}
c24b3114	363
0f374561 HZ	364	mmp_icu_base = of_iomap(node, 0);
	365	if (!mmp_icu_base) {
	366	pr_err("Failed to get interrupt controller register\n");
	367	return -ENOMEM;
	368	}
	369
	370	icu_data[0].virq_base = 0;
	371	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
	372	&mmp_irq_domain_ops,
	373	&icu_data[0]);
	374	for (irq = 0; irq < nr_irqs; irq++) {
	375	ret = irq_create_mapping(icu_data[0].domain, irq);
	376	if (!ret) {
	377	pr_err("Failed to mapping hwirq\n");
c24b3114 HZ	378	goto err;
c24b3114 HZ	379	}
0f374561 HZ	380	if (!irq)
0f374561 HZ	381	icu_data[0].virq_base = ret;
c24b3114	382	}
0f374561	383	icu_data[0].nr_irqs = nr_irqs;
c24b3114 HZ	384	return 0;
c24b3114 HZ	385	err:
0f374561 HZ	386	if (icu_data[0].virq_base) {
	387	for (i = 0; i < irq; i++)
	388	irq_dispose_mapping(icu_data[0].virq_base + i);
	389	}
	390	irq_domain_remove(icu_data[0].domain);
	391	iounmap(mmp_icu_base);
	392	return -EINVAL;
c24b3114 HZ	393	}
c24b3114 HZ	394
0f374561 HZ	395	static int __init mmp_of_init(struct device_node *node,
0f374561 HZ	396	struct device_node *parent)
c24b3114	397	{
0f374561	398	int ret;
c24b3114	399
0f374561 HZ	400	ret = mmp_init_bases(node);
	401	if (ret < 0)
	402	return ret;
	403
	404	icu_data[0].conf_enable = mmp_conf.conf_enable;
	405	icu_data[0].conf_disable = mmp_conf.conf_disable;
	406	icu_data[0].conf_mask = mmp_conf.conf_mask;
	407	irq_set_default_host(icu_data[0].domain);
	408	set_handle_irq(mmp_handle_irq);
	409	max_icu_nr = 1;
	410	return 0;
	411	}
	412	IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
	413
	414	static int __init mmp2_of_init(struct device_node *node,
	415	struct device_node *parent)
	416	{
	417	int ret;
	418
	419	ret = mmp_init_bases(node);
	420	if (ret < 0)
	421	return ret;
	422
	423	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	424	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	425	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	426	irq_set_default_host(icu_data[0].domain);
	427	set_handle_irq(mmp2_handle_irq);
	428	max_icu_nr = 1;
	429	return 0;
	430	}
	431	IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
	432
	433	static int __init mmp2_mux_of_init(struct device_node *node,
	434	struct device_node *parent)
	435	{
	436	struct resource res;
	437	int i, ret, irq, j = 0;
	438	u32 nr_irqs, mfp_irq;
	439
	440	if (!parent)
	441	return -ENODEV;
	442
	443	i = max_icu_nr;
	444	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
	445	&nr_irqs);
c24b3114 HZ	446	if (ret) {
c24b3114 HZ	447	pr_err("Not found mrvl,intc-nr-irqs property\n");
0f374561	448	return -EINVAL;
c24b3114	449	}
0f374561 HZ	450	ret = of_address_to_resource(node, 0, &res);
	451	if (ret < 0) {
	452	pr_err("Not found reg property\n");
	453	return -EINVAL;
c24b3114	454	}
0f374561 HZ	455	icu_data[i].reg_status = mmp_icu_base + res.start;
	456	ret = of_address_to_resource(node, 1, &res);
	457	if (ret < 0) {
	458	pr_err("Not found reg property\n");
	459	return -EINVAL;
c24b3114	460	}
0f374561 HZ	461	icu_data[i].reg_mask = mmp_icu_base + res.start;
	462	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
	463	if (!icu_data[i].cascade_irq)
	464	return -EINVAL;
	465
	466	icu_data[i].virq_base = 0;
	467	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
c24b3114	468	&mmp_irq_domain_ops,
0f374561 HZ	469	&icu_data[i]);
	470	for (irq = 0; irq < nr_irqs; irq++) {
	471	ret = irq_create_mapping(icu_data[i].domain, irq);
	472	if (!ret) {
	473	pr_err("Failed to mapping hwirq\n");
	474	goto err;
	475	}
	476	if (!irq)
	477	icu_data[i].virq_base = ret;
	478	}
	479	icu_data[i].nr_irqs = nr_irqs;
	480	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
	481	&mfp_irq)) {
	482	icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
	483	icu_data[i].clr_mfp_hwirq = mfp_irq;
	484	}
	485	irq_set_chained_handler(icu_data[i].cascade_irq,
	486	icu_mux_irq_demux);
	487	max_icu_nr++;
	488	return 0;
c24b3114	489	err:
0f374561 HZ	490	if (icu_data[i].virq_base) {
	491	for (j = 0; j < irq; j++)
	492	irq_dispose_mapping(icu_data[i].virq_base + j);
	493	}
	494	irq_domain_remove(icu_data[i].domain);
	495	return -EINVAL;
c24b3114	496	}
0f374561	497	IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
c24b3114	498	#endif