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289569f9 SG |
1 | /* |
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
41a83e06 | 22 | #include <linux/irqchip.h> |
83a84efc | 23 | #include <linux/irqdomain.h> |
289569f9 | 24 | #include <linux/io.h> |
83a84efc | 25 | #include <linux/of.h> |
8256aa71 | 26 | #include <linux/of_address.h> |
83a84efc | 27 | #include <linux/of_irq.h> |
cec6bae8 | 28 | #include <linux/stmp_device.h> |
4e0a1b8c | 29 | #include <asm/exception.h> |
289569f9 | 30 | |
25e34b44 OR |
31 | /* |
32 | * this device provide 4 offsets for each register: | |
33 | * 0x0 - plain read write mode | |
34 | * 0x4 - set mode, OR logic. | |
35 | * 0x8 - clr mode, XOR logic. | |
36 | * 0xc - togle mode. | |
37 | */ | |
38 | #define SET_REG 4 | |
39 | #define CLR_REG 8 | |
40 | ||
289569f9 SG |
41 | #define HW_ICOLL_VECTOR 0x0000 |
42 | #define HW_ICOLL_LEVELACK 0x0010 | |
43 | #define HW_ICOLL_CTRL 0x0020 | |
4e0a1b8c | 44 | #define HW_ICOLL_STAT_OFFSET 0x0070 |
25e34b44 OR |
45 | #define HW_ICOLL_INTERRUPT0 0x0120 |
46 | #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10) | |
47 | #define BM_ICOLL_INTR_ENABLE BIT(2) | |
289569f9 SG |
48 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 |
49 | ||
83a84efc SG |
50 | #define ICOLL_NUM_IRQS 128 |
51 | ||
25e34b44 OR |
52 | struct icoll_priv { |
53 | void __iomem *vector; | |
54 | void __iomem *levelack; | |
55 | void __iomem *ctrl; | |
56 | void __iomem *stat; | |
57 | void __iomem *intr; | |
58 | }; | |
59 | ||
60 | static struct icoll_priv icoll_priv; | |
83a84efc | 61 | static struct irq_domain *icoll_domain; |
289569f9 | 62 | |
bf0c1118 | 63 | static void icoll_ack_irq(struct irq_data *d) |
289569f9 SG |
64 | { |
65 | /* | |
66 | * The Interrupt Collector is able to prioritize irqs. | |
67 | * Currently only level 0 is used. So acking can use | |
68 | * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. | |
69 | */ | |
70 | __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, | |
25e34b44 | 71 | icoll_priv.levelack); |
289569f9 SG |
72 | } |
73 | ||
bf0c1118 | 74 | static void icoll_mask_irq(struct irq_data *d) |
289569f9 | 75 | { |
25e34b44 OR |
76 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
77 | icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); | |
289569f9 SG |
78 | } |
79 | ||
bf0c1118 | 80 | static void icoll_unmask_irq(struct irq_data *d) |
289569f9 | 81 | { |
25e34b44 OR |
82 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
83 | icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); | |
289569f9 SG |
84 | } |
85 | ||
86 | static struct irq_chip mxs_icoll_chip = { | |
bf0c1118 UKK |
87 | .irq_ack = icoll_ack_irq, |
88 | .irq_mask = icoll_mask_irq, | |
89 | .irq_unmask = icoll_unmask_irq, | |
289569f9 SG |
90 | }; |
91 | ||
4e0a1b8c SG |
92 | asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) |
93 | { | |
94 | u32 irqnr; | |
95 | ||
25e34b44 OR |
96 | irqnr = __raw_readl(icoll_priv.stat); |
97 | __raw_writel(irqnr, icoll_priv.vector); | |
b3410e5f | 98 | handle_domain_irq(icoll_domain, irqnr, regs); |
4e0a1b8c SG |
99 | } |
100 | ||
83a84efc SG |
101 | static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, |
102 | irq_hw_number_t hw) | |
289569f9 | 103 | { |
83a84efc | 104 | irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq); |
83a84efc SG |
105 | |
106 | return 0; | |
107 | } | |
289569f9 | 108 | |
96009736 | 109 | static const struct irq_domain_ops icoll_irq_domain_ops = { |
83a84efc SG |
110 | .map = icoll_irq_domain_map, |
111 | .xlate = irq_domain_xlate_onecell, | |
112 | }; | |
113 | ||
25e34b44 OR |
114 | static void __init icoll_add_domain(struct device_node *np, |
115 | int num) | |
116 | { | |
117 | icoll_domain = irq_domain_add_linear(np, num, | |
118 | &icoll_irq_domain_ops, NULL); | |
119 | ||
120 | if (!icoll_domain) | |
121 | panic("%s: unable to create irq domain", np->full_name); | |
122 | } | |
123 | ||
124 | static void __iomem * __init icoll_init_iobase(struct device_node *np) | |
83a84efc | 125 | { |
25e34b44 OR |
126 | void __iomem *icoll_base; |
127 | ||
128 | icoll_base = of_io_request_and_map(np, 0, np->name); | |
e59a8451 OR |
129 | if (!icoll_base) |
130 | panic("%s: unable to map resource", np->full_name); | |
25e34b44 OR |
131 | return icoll_base; |
132 | } | |
133 | ||
134 | static int __init icoll_of_init(struct device_node *np, | |
135 | struct device_node *interrupt_parent) | |
136 | { | |
137 | void __iomem *icoll_base; | |
138 | ||
139 | icoll_base = icoll_init_iobase(np); | |
140 | icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR; | |
141 | icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK; | |
142 | icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL; | |
143 | icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET; | |
144 | icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; | |
8256aa71 | 145 | |
289569f9 SG |
146 | /* |
147 | * Interrupt Collector reset, which initializes the priority | |
148 | * for each irq to level 0. | |
149 | */ | |
25e34b44 | 150 | stmp_reset_block(icoll_priv.ctrl); |
289569f9 | 151 | |
25e34b44 | 152 | icoll_add_domain(np, ICOLL_NUM_IRQS); |
e59a8451 OR |
153 | |
154 | return 0; | |
83a84efc | 155 | } |
6a8e95b0 | 156 | IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); |