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289569f9 SG |
1 | /* |
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
41a83e06 | 22 | #include <linux/irqchip.h> |
83a84efc | 23 | #include <linux/irqdomain.h> |
289569f9 | 24 | #include <linux/io.h> |
83a84efc | 25 | #include <linux/of.h> |
8256aa71 | 26 | #include <linux/of_address.h> |
83a84efc | 27 | #include <linux/of_irq.h> |
cec6bae8 | 28 | #include <linux/stmp_device.h> |
4e0a1b8c | 29 | #include <asm/exception.h> |
289569f9 SG |
30 | |
31 | #define HW_ICOLL_VECTOR 0x0000 | |
32 | #define HW_ICOLL_LEVELACK 0x0010 | |
33 | #define HW_ICOLL_CTRL 0x0020 | |
4e0a1b8c | 34 | #define HW_ICOLL_STAT_OFFSET 0x0070 |
289569f9 SG |
35 | #define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10) |
36 | #define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10) | |
37 | #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 | |
38 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | |
39 | ||
83a84efc SG |
40 | #define ICOLL_NUM_IRQS 128 |
41 | ||
8256aa71 | 42 | static void __iomem *icoll_base; |
83a84efc | 43 | static struct irq_domain *icoll_domain; |
289569f9 | 44 | |
bf0c1118 | 45 | static void icoll_ack_irq(struct irq_data *d) |
289569f9 SG |
46 | { |
47 | /* | |
48 | * The Interrupt Collector is able to prioritize irqs. | |
49 | * Currently only level 0 is used. So acking can use | |
50 | * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. | |
51 | */ | |
52 | __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, | |
53 | icoll_base + HW_ICOLL_LEVELACK); | |
54 | } | |
55 | ||
bf0c1118 | 56 | static void icoll_mask_irq(struct irq_data *d) |
289569f9 SG |
57 | { |
58 | __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, | |
83a84efc | 59 | icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq)); |
289569f9 SG |
60 | } |
61 | ||
bf0c1118 | 62 | static void icoll_unmask_irq(struct irq_data *d) |
289569f9 SG |
63 | { |
64 | __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, | |
83a84efc | 65 | icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); |
289569f9 SG |
66 | } |
67 | ||
68 | static struct irq_chip mxs_icoll_chip = { | |
bf0c1118 UKK |
69 | .irq_ack = icoll_ack_irq, |
70 | .irq_mask = icoll_mask_irq, | |
71 | .irq_unmask = icoll_unmask_irq, | |
289569f9 SG |
72 | }; |
73 | ||
4e0a1b8c SG |
74 | asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) |
75 | { | |
76 | u32 irqnr; | |
77 | ||
b5f83e9b MP |
78 | irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET); |
79 | __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR); | |
b3410e5f | 80 | handle_domain_irq(icoll_domain, irqnr, regs); |
4e0a1b8c SG |
81 | } |
82 | ||
83a84efc SG |
83 | static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, |
84 | irq_hw_number_t hw) | |
289569f9 | 85 | { |
83a84efc | 86 | irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq); |
83a84efc SG |
87 | |
88 | return 0; | |
89 | } | |
289569f9 | 90 | |
96009736 | 91 | static const struct irq_domain_ops icoll_irq_domain_ops = { |
83a84efc SG |
92 | .map = icoll_irq_domain_map, |
93 | .xlate = irq_domain_xlate_onecell, | |
94 | }; | |
95 | ||
10776b5f | 96 | static int __init icoll_of_init(struct device_node *np, |
83a84efc SG |
97 | struct device_node *interrupt_parent) |
98 | { | |
8256aa71 SG |
99 | icoll_base = of_iomap(np, 0); |
100 | WARN_ON(!icoll_base); | |
101 | ||
289569f9 SG |
102 | /* |
103 | * Interrupt Collector reset, which initializes the priority | |
104 | * for each irq to level 0. | |
105 | */ | |
cec6bae8 | 106 | stmp_reset_block(icoll_base + HW_ICOLL_CTRL); |
289569f9 | 107 | |
83a84efc SG |
108 | icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, |
109 | &icoll_irq_domain_ops, NULL); | |
10776b5f | 110 | return icoll_domain ? 0 : -ENODEV; |
83a84efc | 111 | } |
6a8e95b0 | 112 | IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); |