[deliverable/linux.git] / drivers / irqchip / irq-omap-intc.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

/* Define these here for now until we drop all board-files */
#define OMAP24XX_IC_BASE	0x480fe000
#define OMAP34XX_IC_BASE	0x48200000

/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
#define INTC_PENDING_IRQ1	0x00b8
#define INTC_PENDING_IRQ2	0x00d8
#define INTC_PENDING_IRQ3	0x00f8
#define INTC_ILR0		0x0100

#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
#define INTCPS_NR_ILR_REGS	128
#define INTCPS_NR_MIR_REGS	4

#define INTC_IDLE_FUNCIDLE	(1 << 0)
#define INTC_IDLE_TURBO		(1 << 1)

#define INTC_PROTECTION_ENABLE	(1 << 0)

struct omap_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_ILR_REGS];
	u32 mir[INTCPS_NR_MIR_REGS];
};
static struct omap_intc_regs intc_context;

static struct irq_domain *domain;
static void __iomem *omap_irq_base;
static int omap_nr_pending = 3;
static int omap_nr_irqs = 96;

static void intc_writel(u32 reg, u32 val)
{
	writel_relaxed(val, omap_irq_base + reg);
}

static u32 intc_readl(u32 reg)
{
	return readl_relaxed(omap_irq_base + reg);
}

void omap_intc_save_context(void)
{
	int i;

	intc_context.sysconfig =
		intc_readl(INTC_SYSCONFIG);
	intc_context.protection =
		intc_readl(INTC_PROTECTION);
	intc_context.idle =
		intc_readl(INTC_IDLE);
	intc_context.threshold =
		intc_readl(INTC_THRESHOLD);

	for (i = 0; i < omap_nr_irqs; i++)
		intc_context.ilr[i] =
			intc_readl((INTC_ILR0 + 0x4 * i));
	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_context.mir[i] =
			intc_readl(INTC_MIR0 + (0x20 * i));
}

void omap_intc_restore_context(void)
{
	int i;

	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
	intc_writel(INTC_PROTECTION, intc_context.protection);
	intc_writel(INTC_IDLE, intc_context.idle);
	intc_writel(INTC_THRESHOLD, intc_context.threshold);

	for (i = 0; i < omap_nr_irqs; i++)
		intc_writel(INTC_ILR0 + 0x4 * i,
				intc_context.ilr[i]);

	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_writel(INTC_MIR0 + 0x20 * i,
			intc_context.mir[i]);
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_writel(INTC_SYSCONFIG, 0);
	intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1);
	intc_writel(INTC_IDLE, 0);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_writel(INTC_CONTROL, 0x1);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_soft_reset(void)
{
	unsigned long tmp;

	tmp = intc_readl(INTC_REVISION) & 0xff;

	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
		omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);

	tmp = intc_readl(INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_writel(INTC_SYSCONFIG, tmp);

	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1 << 0);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < omap_nr_pending; i++)
		if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
			return 1;
	return 0;
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(NULL);
}

static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
{
	int ret;
	int i;

	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
			handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
			IRQ_LEVEL, 0);
	if (ret) {
		pr_warn("Failed to allocate irq chips\n");
		return ret;
	}

	for (i = 0; i < omap_nr_pending; i++) {
		struct irq_chip_generic *gc;
		struct irq_chip_type *ct;

		gc = irq_get_domain_generic_chip(d, 32 * i);
		gc->reg_base = base;
		ct = gc->chip_types;

		ct->type = IRQ_TYPE_LEVEL_MASK;
		ct->handler = handle_level_irq;

		ct->chip.irq_ack = omap_mask_ack_irq;
		ct->chip.irq_mask = irq_gc_mask_disable_reg;
		ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

		ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

		ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
		ct->regs.disable = INTC_MIR_SET0 + 32 * i;
	}

	return 0;
}

static void __init omap_alloc_gc_legacy(void __iomem *base,
		unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
			handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int __init omap_init_irq_of(struct device_node *node)
{
	int ret;

	omap_irq_base = of_iomap(node, 0);
	if (WARN_ON(!omap_irq_base))
		return -ENOMEM;

	domain = irq_domain_add_linear(node, omap_nr_irqs,
			&irq_generic_chip_ops, NULL);

	omap_irq_soft_reset();

	ret = omap_alloc_gc_of(domain, omap_irq_base);
	if (ret < 0)
		irq_domain_remove(domain);

	return ret;
}

static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
{
	int j, irq_base;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return -ENOMEM;

	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
			&irq_domain_simple_ops, NULL);

	omap_irq_soft_reset();

	for (j = 0; j < omap_nr_irqs; j += 32)
		omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);

	return 0;
}

static void __init omap_irq_enable_protection(void)
{
	u32 reg;

	reg = intc_readl(INTC_PROTECTION);
	reg |= INTC_PROTECTION_ENABLE;
	intc_writel(INTC_PROTECTION, reg);
}

static int __init omap_init_irq(u32 base, struct device_node *node)
{
	int ret;

	/*
	 * FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
	 * depends is still not ready for linear IRQ domains; because of that
	 * we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
	 * linear IRQ Domain until that driver is finally fixed.
	 */
	if (of_device_is_compatible(node, "ti,omap2-intc") ||
			of_device_is_compatible(node, "ti,omap3-intc")) {
		struct resource res;

		if (of_address_to_resource(node, 0, &res))
			return -ENOMEM;

		base = res.start;
		ret = omap_init_irq_legacy(base, node);
	} else if (node) {
		ret = omap_init_irq_of(node);
	} else {
		ret = omap_init_irq_legacy(base, NULL);
	}

	if (ret == 0)
		omap_irq_enable_protection();

	return ret;
}

static asmlinkage void __exception_irq_entry
omap_intc_handle_irq(struct pt_regs *regs)
{
	u32 irqnr;

	irqnr = intc_readl(INTC_SIR);
	irqnr &= ACTIVEIRQ_MASK;
	WARN_ONCE(!irqnr, "Spurious IRQ ?\n");
	handle_domain_irq(domain, irqnr, regs);
}

void __init omap3_init_irq(void)
{
	omap_nr_irqs = 96;
	omap_nr_pending = 3;
	omap_init_irq(OMAP34XX_IC_BASE, NULL);
	set_handle_irq(omap_intc_handle_irq);
}

static int __init intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	int ret;

	omap_nr_pending = 3;
	omap_nr_irqs = 96;

	if (WARN_ON(!node))
		return -ENODEV;

	if (of_device_is_compatible(node, "ti,dm814-intc") ||
	    of_device_is_compatible(node, "ti,dm816-intc") ||
	    of_device_is_compatible(node, "ti,am33xx-intc")) {
		omap_nr_irqs = 128;
		omap_nr_pending = 4;
	}

	ret = omap_init_irq(-1, of_node_get(node));
	if (ret < 0)
		return ret;

	set_handle_irq(omap_intc_handle_irq);

	return 0;
}

IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
52fa2120	14	#include <linux/module.h>
1dbae815	15	#include <linux/init.h>
1dbae815	16	#include <linux/interrupt.h>
2e7509e5	17	#include <linux/io.h>
ee0839c2	18
2db14997	19	#include <asm/exception.h>
41a83e06	20	#include <linux/irqchip.h>
52fa2120 BC	21	#include <linux/irqdomain.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
c4082d49	24	#include <linux/of_irq.h>
1dbae815	25
8598066c FB	26	/* Define these here for now until we drop all board-files */
	27	#define OMAP24XX_IC_BASE 0x480fe000
	28	#define OMAP34XX_IC_BASE 0x48200000
2e7509e5 PW	29
	30	/* selected INTC register offsets */
	31
	32	#define INTC_REVISION 0x0000
	33	#define INTC_SYSCONFIG 0x0010
	34	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	35	#define INTC_SIR 0x0040
2e7509e5	36	#define INTC_CONTROL 0x0048
0addd61b RN	37	#define INTC_PROTECTION 0x004C
	38	#define INTC_IDLE 0x0050
	39	#define INTC_THRESHOLD 0x0068
	40	#define INTC_MIR0 0x0084
2e7509e5 PW	41	#define INTC_MIR_CLEAR0 0x0088
	42	#define INTC_MIR_SET0 0x008c
	43	#define INTC_PENDING_IRQ0 0x0098
11983656 FB	44	#define INTC_PENDING_IRQ1 0x00b8
	45	#define INTC_PENDING_IRQ2 0x00d8
	46	#define INTC_PENDING_IRQ3 0x00f8
33c7c7b7	47	#define INTC_ILR0 0x0100
1dbae815	48
2db14997	49	#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
a88ab430	50	#define INTCPS_NR_ILR_REGS 128
74b6c8ef	51	#define INTCPS_NR_MIR_REGS 4
2db14997	52
b3079149 FB	53	#define INTC_IDLE_FUNCIDLE (1 << 0)
	54	#define INTC_IDLE_TURBO (1 << 1)
	55
9836ee9f FB	56	#define INTC_PROTECTION_ENABLE (1 << 0)
9836ee9f FB	57
272a8b04	58	struct omap_intc_regs {
0addd61b RN	59	u32 sysconfig;
	60	u32 protection;
	61	u32 idle;
	62	u32 threshold;
a88ab430	63	u32 ilr[INTCPS_NR_ILR_REGS];
0addd61b RN	64	u32 mir[INTCPS_NR_MIR_REGS];
0addd61b RN	65	};
131b48c0 FB	66	static struct omap_intc_regs intc_context;
	67
	68	static struct irq_domain *domain;
	69	static void __iomem *omap_irq_base;
52b1e129	70	static int omap_nr_pending = 3;
131b48c0	71	static int omap_nr_irqs = 96;
0addd61b	72
71be00c9	73	static void intc_writel(u32 reg, u32 val)
2e7509e5	74	{
71be00c9	75	writel_relaxed(val, omap_irq_base + reg);
2e7509e5 PW	76	}
2e7509e5 PW	77
71be00c9	78	static u32 intc_readl(u32 reg)
2e7509e5	79	{
71be00c9	80	return readl_relaxed(omap_irq_base + reg);
2e7509e5 PW	81	}
2e7509e5 PW	82
131b48c0 FB	83	void omap_intc_save_context(void)
	84	{
	85	int i;
	86
	87	intc_context.sysconfig =
	88	intc_readl(INTC_SYSCONFIG);
	89	intc_context.protection =
	90	intc_readl(INTC_PROTECTION);
	91	intc_context.idle =
	92	intc_readl(INTC_IDLE);
	93	intc_context.threshold =
	94	intc_readl(INTC_THRESHOLD);
	95
	96	for (i = 0; i < omap_nr_irqs; i++)
	97	intc_context.ilr[i] =
	98	intc_readl((INTC_ILR0 + 0x4 * i));
	99	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	100	intc_context.mir[i] =
	101	intc_readl(INTC_MIR0 + (0x20 * i));
	102	}
	103
	104	void omap_intc_restore_context(void)
	105	{
	106	int i;
	107
	108	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
	109	intc_writel(INTC_PROTECTION, intc_context.protection);
	110	intc_writel(INTC_IDLE, intc_context.idle);
	111	intc_writel(INTC_THRESHOLD, intc_context.threshold);
	112
	113	for (i = 0; i < omap_nr_irqs; i++)
	114	intc_writel(INTC_ILR0 + 0x4 * i,
	115	intc_context.ilr[i]);
	116
	117	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	118	intc_writel(INTC_MIR0 + 0x20 * i,
	119	intc_context.mir[i]);
	120	/* MIRs are saved and restore with other PRCM registers */
	121	}
	122
	123	void omap3_intc_prepare_idle(void)
	124	{
	125	/*
	126	* Disable autoidle as it can stall interrupt controller,
	127	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	128	*/
	129	intc_writel(INTC_SYSCONFIG, 0);
b3079149	130	intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
131b48c0 FB	131	}
	132
	133	void omap3_intc_resume_idle(void)
	134	{
	135	/* Re-enable autoidle */
	136	intc_writel(INTC_SYSCONFIG, 1);
b3079149	137	intc_writel(INTC_IDLE, 0);
131b48c0 FB	138	}
131b48c0 FB	139
1dbae815	140	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	141	static void omap_ack_irq(struct irq_data *d)
1dbae815	142	{
71be00c9	143	intc_writel(INTC_CONTROL, 0x1);
1dbae815 TL	144	}
1dbae815 TL	145
df303477	146	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	147	{
667a11fa	148	irq_gc_mask_disable_reg(d);
df303477	149	omap_ack_irq(d);
1dbae815 TL	150	}
1dbae815 TL	151
a88ab430	152	static void __init omap_irq_soft_reset(void)
1dbae815 TL	153	{
	154	unsigned long tmp;
	155
71be00c9	156	tmp = intc_readl(INTC_REVISION) & 0xff;
a88ab430	157
7852ec05	158	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
a88ab430	159	omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
1dbae815	160
71be00c9	161	tmp = intc_readl(INTC_SYSCONFIG);
1dbae815	162	tmp \|= 1 << 1; /* soft reset */
71be00c9	163	intc_writel(INTC_SYSCONFIG, tmp);
1dbae815	164
71be00c9	165	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
1dbae815	166	/* Wait for reset to complete */;
375e12ab JY	167
375e12ab JY	168	/* Enable autoidle */
71be00c9	169	intc_writel(INTC_SYSCONFIG, 1 << 0);
1dbae815 TL	170	}
1dbae815 TL	171
94434535 JH	172	int omap_irq_pending(void)
94434535 JH	173	{
6bd0f16e	174	int i;
94434535	175
6bd0f16e FB	176	for (i = 0; i < omap_nr_pending; i++)
6bd0f16e FB	177	if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
a88ab430	178	return 1;
94434535 JH	179	return 0;
	180	}
	181
131b48c0 FB	182	void omap3_intc_suspend(void)
	183	{
	184	/* A pending interrupt would prevent OMAP from entering suspend */
	185	omap_ack_irq(NULL);
	186	}
	187
55601c9f FB	188	static int __init omap_alloc_gc_of(struct irq_domain d, void __iomem base)
	189	{
	190	int ret;
	191	int i;
	192
	193	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
	194	handle_level_irq, IRQ_NOREQUEST \| IRQ_NOPROBE,
	195	IRQ_LEVEL, 0);
	196	if (ret) {
	197	pr_warn("Failed to allocate irq chips\n");
	198	return ret;
	199	}
	200
	201	for (i = 0; i < omap_nr_pending; i++) {
	202	struct irq_chip_generic *gc;
	203	struct irq_chip_type *ct;
	204
	205	gc = irq_get_domain_generic_chip(d, 32 * i);
	206	gc->reg_base = base;
	207	ct = gc->chip_types;
	208
	209	ct->type = IRQ_TYPE_LEVEL_MASK;
	210	ct->handler = handle_level_irq;
	211
	212	ct->chip.irq_ack = omap_mask_ack_irq;
	213	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	214	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	215
	216	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
	217
	218	ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
	219	ct->regs.disable = INTC_MIR_SET0 + 32 * i;
	220	}
	221
	222	return 0;
	223	}
	224
	225	static void __init omap_alloc_gc_legacy(void __iomem *base,
	226	unsigned int irq_start, unsigned int num)
667a11fa TL	227	{
	228	struct irq_chip_generic *gc;
	229	struct irq_chip_type *ct;
	230
	231	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
55601c9f	232	handle_level_irq);
667a11fa TL	233	ct = gc->chip_types;
	234	ct->chip.irq_ack = omap_mask_ack_irq;
	235	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	236	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
e3c83c2d	237	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
667a11fa	238
667a11fa TL	239	ct->regs.enable = INTC_MIR_CLEAR0;
	240	ct->regs.disable = INTC_MIR_SET0;
	241	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
55601c9f	242	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
667a11fa TL	243	}
667a11fa TL	244
55601c9f FB	245	static int __init omap_init_irq_of(struct device_node *node)
	246	{
	247	int ret;
	248
	249	omap_irq_base = of_iomap(node, 0);
	250	if (WARN_ON(!omap_irq_base))
	251	return -ENOMEM;
	252
	253	domain = irq_domain_add_linear(node, omap_nr_irqs,
	254	&irq_generic_chip_ops, NULL);
	255
	256	omap_irq_soft_reset();
	257
	258	ret = omap_alloc_gc_of(domain, omap_irq_base);
	259	if (ret < 0)
	260	irq_domain_remove(domain);
	261
	262	return ret;
	263	}
	264
4b149e41	265	static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
1dbae815	266	{
a88ab430	267	int j, irq_base;
1dbae815	268
741e3a89 TL	269	omap_irq_base = ioremap(base, SZ_4K);
741e3a89 TL	270	if (WARN_ON(!omap_irq_base))
55601c9f	271	return -ENOMEM;
741e3a89	272
a74f0a17	273	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
52fa2120 BC	274	if (irq_base < 0) {
	275	pr_warn("Couldn't allocate IRQ numbers\n");
	276	irq_base = 0;
	277	}
	278
4b149e41	279	domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
a88ab430	280	&irq_domain_simple_ops, NULL);
1dbae815	281
a88ab430	282	omap_irq_soft_reset();
667a11fa	283
a88ab430	284	for (j = 0; j < omap_nr_irqs; j += 32)
55601c9f FB	285	omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
	286
	287	return 0;
	288	}
	289
9836ee9f FB	290	static void __init omap_irq_enable_protection(void)
	291	{
	292	u32 reg;
	293
	294	reg = intc_readl(INTC_PROTECTION);
	295	reg \|= INTC_PROTECTION_ENABLE;
	296	intc_writel(INTC_PROTECTION, reg);
	297	}
	298
55601c9f FB	299	static int __init omap_init_irq(u32 base, struct device_node *node)
55601c9f FB	300	{
9836ee9f FB	301	int ret;
9836ee9f FB	302
4b149e41 FB	303	/*
	304	* FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
	305	* depends is still not ready for linear IRQ domains; because of that
	306	* we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
	307	* linear IRQ Domain until that driver is finally fixed.
	308	*/
	309	if (of_device_is_compatible(node, "ti,omap2-intc") \|\|
	310	of_device_is_compatible(node, "ti,omap3-intc")) {
	311	struct resource res;
	312
	313	if (of_address_to_resource(node, 0, &res))
	314	return -ENOMEM;
	315
	316	base = res.start;
	317	ret = omap_init_irq_legacy(base, node);
	318	} else if (node) {
9836ee9f	319	ret = omap_init_irq_of(node);
4b149e41 FB	320	} else {
	321	ret = omap_init_irq_legacy(base, NULL);
	322	}
9836ee9f FB	323
	324	if (ret == 0)
	325	omap_irq_enable_protection();
	326
	327	return ret;
1dbae815 TL	328	}
1dbae815 TL	329
2aced892 FB	330	static asmlinkage void __exception_irq_entry
2aced892 FB	331	omap_intc_handle_irq(struct pt_regs *regs)
2db14997	332	{
6ed34648	333	u32 irqnr;
2db14997	334
6ed34648 FB	335	irqnr = intc_readl(INTC_SIR);
	336	irqnr &= ACTIVEIRQ_MASK;
	337	WARN_ONCE(!irqnr, "Spurious IRQ ?\n");
	338	handle_domain_irq(domain, irqnr, regs);
2db14997 MZ	339	}
2db14997 MZ	340
a4d3c5d9 FB	341	void __init omap3_init_irq(void)
a4d3c5d9 FB	342	{
a74f0a17	343	omap_nr_irqs = 96;
52b1e129	344	omap_nr_pending = 3;
a74f0a17	345	omap_init_irq(OMAP34XX_IC_BASE, NULL);
2aced892	346	set_handle_irq(omap_intc_handle_irq);
a4d3c5d9 FB	347	}
a4d3c5d9 FB	348
00b6b031	349	static int __init intc_of_init(struct device_node *node,
52fa2120 BC	350	struct device_node *parent)
52fa2120 BC	351	{
55601c9f	352	int ret;
a74f0a17	353
52b1e129	354	omap_nr_pending = 3;
a74f0a17	355	omap_nr_irqs = 96;
52fa2120 BC	356
	357	if (WARN_ON(!node))
	358	return -ENODEV;
	359
19f92b23 TL	360	if (of_device_is_compatible(node, "ti,dm814-intc") \|\|
	361	of_device_is_compatible(node, "ti,dm816-intc") \|\|
	362	of_device_is_compatible(node, "ti,am33xx-intc")) {
a74f0a17	363	omap_nr_irqs = 128;
52b1e129 FB	364	omap_nr_pending = 4;
52b1e129 FB	365	}
470f30de	366
55601c9f FB	367	ret = omap_init_irq(-1, of_node_get(node));
	368	if (ret < 0)
	369	return ret;
52fa2120	370
2aced892	371	set_handle_irq(omap_intc_handle_irq);
b15c76b7	372
52fa2120 BC	373	return 0;
	374	}
	375
a35db9a4 FB	376	IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
a35db9a4 FB	377	IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
19f92b23 TL	378	IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
19f92b23 TL	379	IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
a35db9a4	380	IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);