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fbc83b7f MD |
1 | /* |
2 | * Renesas IRQC Driver | |
3 | * | |
4 | * Copyright (C) 2013 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/irqdomain.h> | |
28 | #include <linux/err.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/platform_data/irq-renesas-irqc.h> | |
32 | ||
33 | #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ | |
34 | ||
35 | #define IRQC_REQ_STS 0x00 | |
36 | #define IRQC_EN_STS 0x04 | |
37 | #define IRQC_EN_SET 0x08 | |
38 | #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) | |
39 | #define DETECT_STATUS 0x100 | |
40 | #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) | |
41 | ||
42 | struct irqc_irq { | |
43 | int hw_irq; | |
44 | int requested_irq; | |
45 | int domain_irq; | |
46 | struct irqc_priv *p; | |
47 | }; | |
48 | ||
49 | struct irqc_priv { | |
50 | void __iomem *iomem; | |
51 | void __iomem *cpu_int_base; | |
52 | struct irqc_irq irq[IRQC_IRQ_MAX]; | |
53 | struct renesas_irqc_config config; | |
54 | unsigned int number_of_irqs; | |
55 | struct platform_device *pdev; | |
56 | struct irq_chip irq_chip; | |
57 | struct irq_domain *irq_domain; | |
58 | }; | |
59 | ||
60 | static void irqc_dbg(struct irqc_irq *i, char *str) | |
61 | { | |
62 | dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", | |
63 | str, i->requested_irq, i->hw_irq, i->domain_irq); | |
64 | } | |
65 | ||
66 | static void irqc_irq_enable(struct irq_data *d) | |
67 | { | |
68 | struct irqc_priv *p = irq_data_get_irq_chip_data(d); | |
69 | int hw_irq = irqd_to_hwirq(d); | |
70 | ||
71 | irqc_dbg(&p->irq[hw_irq], "enable"); | |
72 | iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET); | |
73 | } | |
74 | ||
75 | static void irqc_irq_disable(struct irq_data *d) | |
76 | { | |
77 | struct irqc_priv *p = irq_data_get_irq_chip_data(d); | |
78 | int hw_irq = irqd_to_hwirq(d); | |
79 | ||
80 | irqc_dbg(&p->irq[hw_irq], "disable"); | |
81 | iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); | |
82 | } | |
83 | ||
fbc83b7f | 84 | static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { |
ce70af18 SS |
85 | [IRQ_TYPE_LEVEL_LOW] = 0x01, |
86 | [IRQ_TYPE_LEVEL_HIGH] = 0x02, | |
87 | [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */ | |
88 | [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */ | |
89 | [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */ | |
fbc83b7f MD |
90 | }; |
91 | ||
92 | static int irqc_irq_set_type(struct irq_data *d, unsigned int type) | |
93 | { | |
94 | struct irqc_priv *p = irq_data_get_irq_chip_data(d); | |
95 | int hw_irq = irqd_to_hwirq(d); | |
96 | unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; | |
97 | unsigned long tmp; | |
98 | ||
99 | irqc_dbg(&p->irq[hw_irq], "sense"); | |
100 | ||
ce70af18 | 101 | if (!value) |
fbc83b7f MD |
102 | return -EINVAL; |
103 | ||
104 | tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); | |
105 | tmp &= ~0x3f; | |
ce70af18 | 106 | tmp |= value; |
fbc83b7f MD |
107 | iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); |
108 | return 0; | |
109 | } | |
110 | ||
111 | static irqreturn_t irqc_irq_handler(int irq, void *dev_id) | |
112 | { | |
113 | struct irqc_irq *i = dev_id; | |
114 | struct irqc_priv *p = i->p; | |
115 | unsigned long bit = BIT(i->hw_irq); | |
116 | ||
117 | irqc_dbg(i, "demux1"); | |
118 | ||
119 | if (ioread32(p->iomem + DETECT_STATUS) & bit) { | |
120 | iowrite32(bit, p->iomem + DETECT_STATUS); | |
121 | irqc_dbg(i, "demux2"); | |
122 | generic_handle_irq(i->domain_irq); | |
123 | return IRQ_HANDLED; | |
124 | } | |
125 | return IRQ_NONE; | |
126 | } | |
127 | ||
128 | static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, | |
129 | irq_hw_number_t hw) | |
130 | { | |
131 | struct irqc_priv *p = h->host_data; | |
132 | ||
133 | p->irq[hw].domain_irq = virq; | |
134 | p->irq[hw].hw_irq = hw; | |
135 | ||
136 | irqc_dbg(&p->irq[hw], "map"); | |
137 | irq_set_chip_data(virq, h->host_data); | |
138 | irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); | |
139 | set_irq_flags(virq, IRQF_VALID); /* kill me now */ | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static struct irq_domain_ops irqc_irq_domain_ops = { | |
144 | .map = irqc_irq_domain_map, | |
3b8dfa7c | 145 | .xlate = irq_domain_xlate_twocell, |
fbc83b7f MD |
146 | }; |
147 | ||
148 | static int irqc_probe(struct platform_device *pdev) | |
149 | { | |
150 | struct renesas_irqc_config *pdata = pdev->dev.platform_data; | |
151 | struct irqc_priv *p; | |
152 | struct resource *io; | |
153 | struct resource *irq; | |
154 | struct irq_chip *irq_chip; | |
155 | const char *name = dev_name(&pdev->dev); | |
156 | int ret; | |
157 | int k; | |
158 | ||
159 | p = kzalloc(sizeof(*p), GFP_KERNEL); | |
160 | if (!p) { | |
161 | dev_err(&pdev->dev, "failed to allocate driver data\n"); | |
162 | ret = -ENOMEM; | |
163 | goto err0; | |
164 | } | |
165 | ||
166 | /* deal with driver instance configuration */ | |
167 | if (pdata) | |
168 | memcpy(&p->config, pdata, sizeof(*pdata)); | |
169 | ||
170 | p->pdev = pdev; | |
171 | platform_set_drvdata(pdev, p); | |
172 | ||
173 | /* get hold of manadatory IOMEM */ | |
174 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
175 | if (!io) { | |
176 | dev_err(&pdev->dev, "not enough IOMEM resources\n"); | |
177 | ret = -EINVAL; | |
178 | goto err1; | |
179 | } | |
180 | ||
181 | /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ | |
182 | for (k = 0; k < IRQC_IRQ_MAX; k++) { | |
183 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); | |
184 | if (!irq) | |
185 | break; | |
186 | ||
187 | p->irq[k].p = p; | |
188 | p->irq[k].requested_irq = irq->start; | |
189 | } | |
190 | ||
191 | p->number_of_irqs = k; | |
192 | if (p->number_of_irqs < 1) { | |
193 | dev_err(&pdev->dev, "not enough IRQ resources\n"); | |
194 | ret = -EINVAL; | |
195 | goto err1; | |
196 | } | |
197 | ||
198 | /* ioremap IOMEM and setup read/write callbacks */ | |
199 | p->iomem = ioremap_nocache(io->start, resource_size(io)); | |
200 | if (!p->iomem) { | |
201 | dev_err(&pdev->dev, "failed to remap IOMEM\n"); | |
202 | ret = -ENXIO; | |
203 | goto err2; | |
204 | } | |
205 | ||
206 | p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ | |
207 | ||
208 | irq_chip = &p->irq_chip; | |
209 | irq_chip->name = name; | |
210 | irq_chip->irq_mask = irqc_irq_disable; | |
211 | irq_chip->irq_unmask = irqc_irq_enable; | |
fbc83b7f | 212 | irq_chip->irq_set_type = irqc_irq_set_type; |
6a7e3b30 | 213 | irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; |
fbc83b7f MD |
214 | |
215 | p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, | |
216 | p->number_of_irqs, | |
217 | p->config.irq_base, | |
218 | &irqc_irq_domain_ops, p); | |
219 | if (!p->irq_domain) { | |
220 | ret = -ENXIO; | |
221 | dev_err(&pdev->dev, "cannot initialize irq domain\n"); | |
222 | goto err2; | |
223 | } | |
224 | ||
225 | /* request interrupts one by one */ | |
226 | for (k = 0; k < p->number_of_irqs; k++) { | |
227 | if (request_irq(p->irq[k].requested_irq, irqc_irq_handler, | |
228 | 0, name, &p->irq[k])) { | |
229 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
230 | ret = -ENOENT; | |
231 | goto err3; | |
232 | } | |
233 | } | |
234 | ||
235 | dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); | |
236 | ||
237 | /* warn in case of mismatch if irq base is specified */ | |
238 | if (p->config.irq_base) { | |
239 | if (p->config.irq_base != p->irq[0].domain_irq) | |
240 | dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", | |
241 | p->config.irq_base, p->irq[0].domain_irq); | |
242 | } | |
243 | ||
244 | return 0; | |
245 | err3: | |
dfaf820a AL |
246 | while (--k >= 0) |
247 | free_irq(p->irq[k].requested_irq, &p->irq[k]); | |
fbc83b7f MD |
248 | |
249 | irq_domain_remove(p->irq_domain); | |
250 | err2: | |
251 | iounmap(p->iomem); | |
252 | err1: | |
253 | kfree(p); | |
254 | err0: | |
255 | return ret; | |
256 | } | |
257 | ||
258 | static int irqc_remove(struct platform_device *pdev) | |
259 | { | |
260 | struct irqc_priv *p = platform_get_drvdata(pdev); | |
261 | int k; | |
262 | ||
263 | for (k = 0; k < p->number_of_irqs; k++) | |
264 | free_irq(p->irq[k].requested_irq, &p->irq[k]); | |
265 | ||
266 | irq_domain_remove(p->irq_domain); | |
267 | iounmap(p->iomem); | |
268 | kfree(p); | |
269 | return 0; | |
270 | } | |
271 | ||
3b8dfa7c MD |
272 | static const struct of_device_id irqc_dt_ids[] = { |
273 | { .compatible = "renesas,irqc", }, | |
274 | {}, | |
275 | }; | |
276 | MODULE_DEVICE_TABLE(of, irqc_dt_ids); | |
277 | ||
fbc83b7f MD |
278 | static struct platform_driver irqc_device_driver = { |
279 | .probe = irqc_probe, | |
280 | .remove = irqc_remove, | |
281 | .driver = { | |
282 | .name = "renesas_irqc", | |
3b8dfa7c MD |
283 | .of_match_table = irqc_dt_ids, |
284 | .owner = THIS_MODULE, | |
fbc83b7f MD |
285 | } |
286 | }; | |
287 | ||
288 | static int __init irqc_init(void) | |
289 | { | |
290 | return platform_driver_register(&irqc_device_driver); | |
291 | } | |
292 | postcore_initcall(irqc_init); | |
293 | ||
294 | static void __exit irqc_exit(void) | |
295 | { | |
296 | platform_driver_unregister(&irqc_device_driver); | |
297 | } | |
298 | module_exit(irqc_exit); | |
299 | ||
300 | MODULE_AUTHOR("Magnus Damm"); | |
301 | MODULE_DESCRIPTION("Renesas IRQC Driver"); | |
302 | MODULE_LICENSE("GPL v2"); |