projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
irqchip: s3c24xx: globally keep track of the created intc instances
[deliverable/linux.git] / drivers / irqchip / irq-s3c24xx.c
CommitLineData
1f629b7a
HS		 1/*
2 * S3C24XX IRQ handling
a21765a7 3 *
e02f8664 4 * Copyright (c) 2003-2004 Simtec Electronics
a21765a7 5 * Ben Dooks <ben@simtec.co.uk>
1f629b7a 6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
a21765a7
BD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
a21765a7
BD		 17*/
18
19#include <linux/init.h>
1f629b7a 20#include <linux/slab.h>
a21765a7 21#include <linux/module.h>
1f629b7a
HS		 22#include <linux/io.h>
23#include <linux/err.h>
a21765a7
BD		 24#include <linux/interrupt.h>
25#include <linux/ioport.h>
edbaa603 26#include <linux/device.h>
1f629b7a 27#include <linux/irqdomain.h>
a21765a7 28
17453dd2 29#include <asm/exception.h>
a21765a7
BD		 30#include <asm/mach/irq.h>
31
1f629b7a
HS		 32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
a21765a7 34
a2b7ba9c 35#include <plat/cpu.h>
1f629b7a 36#include <plat/regs-irqtype.h>
a2b7ba9c 37#include <plat/pm.h>
a21765a7 38
1f629b7a
HS		 39#define S3C_IRQTYPE_NONE 0
40#define S3C_IRQTYPE_EINT 1
41#define S3C_IRQTYPE_EDGE 2
42#define S3C_IRQTYPE_LEVEL 3
a21765a7 43
1f629b7a
HS		 44struct s3c_irq_data {
45 unsigned int type;
46 unsigned long parent_irq;
a21765a7 47
1f629b7a
HS		 48 /* data gets filled during init */
49 struct s3c_irq_intc *intc;
50 unsigned long sub_bits;
51 struct s3c_irq_intc *sub_intc;
a21765a7
BD		 52};
53
1f629b7a
HS		 54/*
55 * Sructure holding the controller data
56 * @reg_pending register holding pending irqs
57 * @reg_intpnd special register intpnd in main intc
58 * @reg_mask mask register
59 * @domain irq_domain of the controller
60 * @parent parent controller for ext and sub irqs
61 * @irqs irq-data, always s3c_irq_data[32]
62 */
63struct s3c_irq_intc {
64 void __iomem *reg_pending;
65 void __iomem *reg_intpnd;
66 void __iomem *reg_mask;
67 struct irq_domain *domain;
68 struct s3c_irq_intc *parent;
69 struct s3c_irq_data *irqs;
a21765a7
BD		 70};
71
658dc8fb
HS		 72/*
73 * Array holding pointers to the global controller structs
74 * [0] ... main_intc
75 * [1] ... sub_intc
76 * [2] ... main_intc2 on s3c2416
77 */
78static struct s3c_irq_intc *s3c_intc[3];
79
1f629b7a 80static void s3c_irq_mask(struct irq_data *data)
a21765a7 81{
1f629b7a
HS		 82 struct s3c_irq_intc *intc = data->domain->host_data;
83 struct s3c_irq_intc *parent_intc = intc->parent;
84 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
85 struct s3c_irq_data *parent_data;
a21765a7 86 unsigned long mask;
1f629b7a
HS		 87 unsigned int irqno;
88
89 mask = __raw_readl(intc->reg_mask);
90 mask |= (1UL << data->hwirq);
91 __raw_writel(mask, intc->reg_mask);
92
0fe3cb1e 93 if (parent_intc) {
1f629b7a 94 parent_data = &parent_intc->irqs[irq_data->parent_irq];
a21765a7 95
1f629b7a
HS		 96 /* check to see if we need to mask the parent IRQ */
97 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
98 irqno = irq_find_mapping(parent_intc->domain,
99 irq_data->parent_irq);
100 s3c_irq_mask(irq_get_irq_data(irqno));
101 }
102 }
a21765a7
BD		 103}
104
1f629b7a 105static void s3c_irq_unmask(struct irq_data *data)
a21765a7 106{
1f629b7a
HS		 107 struct s3c_irq_intc *intc = data->domain->host_data;
108 struct s3c_irq_intc *parent_intc = intc->parent;
109 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
a21765a7 110 unsigned long mask;
1f629b7a 111 unsigned int irqno;
a21765a7 112
1f629b7a
HS		 113 mask = __raw_readl(intc->reg_mask);
114 mask &= ~(1UL << data->hwirq);
115 __raw_writel(mask, intc->reg_mask);
a21765a7 116
0fe3cb1e 117 if (parent_intc) {
1f629b7a
HS		 118 irqno = irq_find_mapping(parent_intc->domain,
119 irq_data->parent_irq);
120 s3c_irq_unmask(irq_get_irq_data(irqno));
a21765a7
BD		 121 }
122}
123
1f629b7a 124static inline void s3c_irq_ack(struct irq_data *data)
a21765a7 125{
1f629b7a
HS		 126 struct s3c_irq_intc *intc = data->domain->host_data;
127 unsigned long bitval = 1UL << data->hwirq;
a21765a7 128
1f629b7a
HS		 129 __raw_writel(bitval, intc->reg_pending);
130 if (intc->reg_intpnd)
131 __raw_writel(bitval, intc->reg_intpnd);
a21765a7
BD		 132}
133
bd7c0da2
HS		 134static int s3c_irq_type(struct irq_data *data, unsigned int type)
135{
136 switch (type) {
137 case IRQ_TYPE_NONE:
138 break;
139 case IRQ_TYPE_EDGE_RISING:
140 case IRQ_TYPE_EDGE_FALLING:
141 case IRQ_TYPE_EDGE_BOTH:
142 irq_set_handler(data->irq, handle_edge_irq);
143 break;
144 case IRQ_TYPE_LEVEL_LOW:
145 case IRQ_TYPE_LEVEL_HIGH:
146 irq_set_handler(data->irq, handle_level_irq);
147 break;
148 default:
149 pr_err("No such irq type %d", type);
150 return -EINVAL;
151 }
152
153 return 0;
154}
155
1f629b7a
HS		 156static int s3c_irqext_type_set(void __iomem *gpcon_reg,
157 void __iomem *extint_reg,
158 unsigned long gpcon_offset,
159 unsigned long extint_offset,
160 unsigned int type)
a21765a7 161{
a21765a7
BD		 162 unsigned long newvalue = 0, value;
163
a21765a7
BD		 164 /* Set the GPIO to external interrupt mode */
165 value = __raw_readl(gpcon_reg);
166 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
167 __raw_writel(value, gpcon_reg);
168
169 /* Set the external interrupt to pointed trigger type */
170 switch (type)
171 {
6cab4860 172 case IRQ_TYPE_NONE:
1f629b7a 173 pr_warn("No edge setting!\n");
a21765a7
BD		 174 break;
175
6cab4860 176 case IRQ_TYPE_EDGE_RISING:
a21765a7
BD		 177 newvalue = S3C2410_EXTINT_RISEEDGE;
178 break;
179
6cab4860 180 case IRQ_TYPE_EDGE_FALLING:
a21765a7
BD		 181 newvalue = S3C2410_EXTINT_FALLEDGE;
182 break;
183
6cab4860 184 case IRQ_TYPE_EDGE_BOTH:
a21765a7
BD		 185 newvalue = S3C2410_EXTINT_BOTHEDGE;
186 break;
187
6cab4860 188 case IRQ_TYPE_LEVEL_LOW:
a21765a7
BD		 189 newvalue = S3C2410_EXTINT_LOWLEV;
190 break;
191
6cab4860 192 case IRQ_TYPE_LEVEL_HIGH:
a21765a7
BD		 193 newvalue = S3C2410_EXTINT_HILEV;
194 break;
195
196 default:
1f629b7a
HS		 197 pr_err("No such irq type %d", type);
198 return -EINVAL;
a21765a7
BD		 199 }
200
201 value = __raw_readl(extint_reg);
202 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
203 __raw_writel(value, extint_reg);
204
205 return 0;
206}
207
dc1a3538 208static int s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 209{
1f629b7a
HS		 210 void __iomem *extint_reg;
211 void __iomem *gpcon_reg;
212 unsigned long gpcon_offset, extint_offset;
a21765a7 213
1f629b7a
HS		 214 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
215 gpcon_reg = S3C2410_GPFCON;
216 extint_reg = S3C24XX_EXTINT0;
217 gpcon_offset = (data->hwirq) * 2;
218 extint_offset = (data->hwirq) * 4;
219 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
220 gpcon_reg = S3C2410_GPGCON;
221 extint_reg = S3C24XX_EXTINT1;
222 gpcon_offset = (data->hwirq - 8) * 2;
223 extint_offset = (data->hwirq - 8) * 4;
224 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
225 gpcon_reg = S3C2410_GPGCON;
226 extint_reg = S3C24XX_EXTINT2;
227 gpcon_offset = (data->hwirq - 8) * 2;
228 extint_offset = (data->hwirq - 16) * 4;
229 } else {
230 return -EINVAL;
231 }
a21765a7 232
1f629b7a
HS		 233 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
234 extint_offset, type);
a21765a7
BD		 235}
236
1f629b7a 237static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
a21765a7 238{
1f629b7a
HS		 239 void __iomem *extint_reg;
240 void __iomem *gpcon_reg;
241 unsigned long gpcon_offset, extint_offset;
a21765a7 242
1f629b7a
HS		 243 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
244 gpcon_reg = S3C2410_GPFCON;
245 extint_reg = S3C24XX_EXTINT0;
246 gpcon_offset = (data->hwirq) * 2;
247 extint_offset = (data->hwirq) * 4;
248 } else {
249 return -EINVAL;
250 }
a21765a7 251
1f629b7a
HS		 252 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
253 extint_offset, type);
a21765a7
BD		 254}
255
dc1a3538 256static struct irq_chip s3c_irq_chip = {
1f629b7a
HS		 257 .name = "s3c",
258 .irq_ack = s3c_irq_ack,
259 .irq_mask = s3c_irq_mask,
260 .irq_unmask = s3c_irq_unmask,
bd7c0da2 261 .irq_set_type = s3c_irq_type,
1f629b7a 262 .irq_set_wake = s3c_irq_wake
a21765a7
BD		 263};
264
dc1a3538 265static struct irq_chip s3c_irq_level_chip = {
1f629b7a
HS		 266 .name = "s3c-level",
267 .irq_mask = s3c_irq_mask,
268 .irq_unmask = s3c_irq_unmask,
269 .irq_ack = s3c_irq_ack,
bd7c0da2 270 .irq_set_type = s3c_irq_type,
a21765a7
BD		 271};
272
1f629b7a
HS		 273static struct irq_chip s3c_irqext_chip = {
274 .name = "s3c-ext",
275 .irq_mask = s3c_irq_mask,
276 .irq_unmask = s3c_irq_unmask,
277 .irq_ack = s3c_irq_ack,
278 .irq_set_type = s3c_irqext_type,
279 .irq_set_wake = s3c_irqext_wake
a21765a7
BD		 280};
281
1f629b7a
HS		 282static struct irq_chip s3c_irq_eint0t4 = {
283 .name = "s3c-ext0",
284 .irq_ack = s3c_irq_ack,
285 .irq_mask = s3c_irq_mask,
286 .irq_unmask = s3c_irq_unmask,
287 .irq_set_wake = s3c_irq_wake,
288 .irq_set_type = s3c_irqext0_type,
289};
a21765a7 290
1f629b7a 291static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
a21765a7 292{
1f629b7a
HS		 293 struct irq_chip *chip = irq_desc_get_chip(desc);
294 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
295 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
296 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
297 unsigned long src;
298 unsigned long msk;
299 unsigned int n;
300
301 chained_irq_enter(chip, desc);
302
303 src = __raw_readl(sub_intc->reg_pending);
304 msk = __raw_readl(sub_intc->reg_mask);
305
306 src &= ~msk;
307 src &= irq_data->sub_bits;
308
309 while (src) {
310 n = __ffs(src);
311 src &= ~(1 << n);
312 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
a21765a7
BD		 313 }
314
1f629b7a 315 chained_irq_exit(chip, desc);
a21765a7
BD		 316}
317
17453dd2
HS		 318static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
319 struct pt_regs *regs)
320{
321 int pnd;
322 int offset;
323 int irq;
324
325 pnd = __raw_readl(intc->reg_intpnd);
326 if (!pnd)
327 return false;
328
329 /* We have a problem that the INTOFFSET register does not always
330 * show one interrupt. Occasionally we get two interrupts through
331 * the prioritiser, and this causes the INTOFFSET register to show
332 * what looks like the logical-or of the two interrupt numbers.
333 *
334 * Thanks to Klaus, Shannon, et al for helping to debug this problem
335 */
336 offset = __raw_readl(intc->reg_intpnd + 4);
337
338 /* Find the bit manually, when the offset is wrong.
339 * The pending register only ever contains the one bit of the next
340 * interrupt to handle.
341 */
342 if (!(pnd & (1 << offset)))
343 offset = __ffs(pnd);
344
345 irq = irq_find_mapping(intc->domain, offset);
346 handle_IRQ(irq, regs);
347 return true;
348}
349
350asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
351{
352 do {
658dc8fb
HS		 353 if (likely(s3c_intc[0]))
354 if (s3c24xx_handle_intc(s3c_intc[0], regs))
17453dd2
HS		 355 continue;
356
658dc8fb
HS		 357 if (s3c_intc[2])
358 if (s3c24xx_handle_intc(s3c_intc[2], regs))
17453dd2
HS		 359 continue;
360
361 break;
362 } while (1);
363}
364
229fd8ff
BD		 365#ifdef CONFIG_FIQ
366/**
367 * s3c24xx_set_fiq - set the FIQ routing
368 * @irq: IRQ number to route to FIQ on processor.
369 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
370 *
371 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
372 * @on is true, the @irq is checked to see if it can be routed and the
373 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
374 * routing is cleared, regardless of which @irq is specified.
375 */
376int s3c24xx_set_fiq(unsigned int irq, bool on)
377{
378 u32 intmod;
379 unsigned offs;
380
381 if (on) {
382 offs = irq - FIQ_START;
383 if (offs > 31)
384 return -EINVAL;
385
386 intmod = 1 << offs;
387 } else {
388 intmod = 0;
389 }
390
391 __raw_writel(intmod, S3C2410_INTMOD);
392 return 0;
393}
0f13c824
BD		 394
395EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff
BD		 396#endif
397
1f629b7a
HS		 398static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
399 irq_hw_number_t hw)
a21765a7 400{
1f629b7a
HS		 401 struct s3c_irq_intc *intc = h->host_data;
402 struct s3c_irq_data *irq_data = &intc->irqs[hw];
403 struct s3c_irq_intc *parent_intc;
404 struct s3c_irq_data *parent_irq_data;
405 unsigned int irqno;
406
1f629b7a
HS		 407 /* attach controller pointer to irq_data */
408 irq_data->intc = intc;
a21765a7 409
0fe3cb1e
HS		 410 parent_intc = intc->parent;
411
1f629b7a
HS		 412 /* set handler and flags */
413 switch (irq_data->type) {
414 case S3C_IRQTYPE_NONE:
415 return 0;
416 case S3C_IRQTYPE_EINT:
1c8408e3
HS		 417 /* On the S3C2412, the EINT0to3 have a parent irq
418 * but need the s3c_irq_eint0t4 chip
419 */
0fe3cb1e 420 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
1f629b7a
HS		 421 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
422 handle_edge_irq);
423 else
424 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
425 handle_edge_irq);
426 break;
427 case S3C_IRQTYPE_EDGE:
0fe3cb1e 428 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
1f629b7a
HS		 429 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
430 handle_edge_irq);
431 else
432 irq_set_chip_and_handler(virq, &s3c_irq_chip,
433 handle_edge_irq);
434 break;
435 case S3C_IRQTYPE_LEVEL:
0fe3cb1e 436 if (parent_intc)
1f629b7a
HS		 437 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
438 handle_level_irq);
439 else
440 irq_set_chip_and_handler(virq, &s3c_irq_chip,
441 handle_level_irq);
442 break;
443 default:
444 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
445 return -EINVAL;
a21765a7 446 }
1f629b7a
HS		 447 set_irq_flags(virq, IRQF_VALID);
448
0fe3cb1e 449 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
502a2989
HS		 450 if (irq_data->parent_irq > 31) {
451 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
452 irq_data->parent_irq);
1f629b7a
HS		 453 goto err;
454 }
a21765a7 455
502a2989 456 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1f629b7a
HS		 457 parent_irq_data->sub_intc = intc;
458 parent_irq_data->sub_bits |= (1UL << hw);
a21765a7 459
1f629b7a
HS		 460 /* attach the demuxer to the parent irq */
461 irqno = irq_find_mapping(parent_intc->domain,
462 irq_data->parent_irq);
463 if (!irqno) {
464 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
465 irq_data->parent_irq);
466 goto err;
467 }
468 irq_set_chained_handler(irqno, s3c_irq_demux);
a21765a7
BD		 469 }
470
1f629b7a 471 return 0;
a21765a7 472
1f629b7a
HS		 473err:
474 set_irq_flags(virq, 0);
a21765a7 475
1f629b7a
HS		 476 /* the only error can result from bad mapping data*/
477 return -EINVAL;
478}
a21765a7 479
1f629b7a
HS		 480static struct irq_domain_ops s3c24xx_irq_ops = {
481 .map = s3c24xx_irq_map,
482 .xlate = irq_domain_xlate_twocell,
483};
a21765a7 484
1f629b7a
HS		 485static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
486{
487 void __iomem *reg_source;
488 unsigned long pend;
489 unsigned long last;
490 int i;
a21765a7 491
1f629b7a
HS		 492 /* if intpnd is set, read the next pending irq from there */
493 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
a21765a7 494
1f629b7a
HS		 495 last = 0;
496 for (i = 0; i < 4; i++) {
497 pend = __raw_readl(reg_source);
a21765a7 498
1f629b7a 499 if (pend == 0 || pend == last)
a21765a7
BD		 500 break;
501
1f629b7a
HS		 502 __raw_writel(pend, intc->reg_pending);
503 if (intc->reg_intpnd)
504 __raw_writel(pend, intc->reg_intpnd);
a21765a7 505
1f629b7a
HS		 506 pr_info("irq: clearing pending status %08x\n", (int)pend);
507 last = pend;
a21765a7 508 }
1f629b7a 509}
a21765a7 510
3d3eb5a4 511static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
1f629b7a
HS		 512 struct s3c_irq_data *irq_data,
513 struct s3c_irq_intc *parent,
514 unsigned long address)
515{
516 struct s3c_irq_intc *intc;
517 void __iomem *base = (void *)0xf6000000; /* static mapping */
518 int irq_num;
519 int irq_start;
1f629b7a
HS		 520 int ret;
521
522 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
523 if (!intc)
524 return ERR_PTR(-ENOMEM);
525
526 intc->irqs = irq_data;
527
528 if (parent)
529 intc->parent = parent;
530
531 /* select the correct data for the controller.
532 * Need to hard code the irq num start and offset
533 * to preserve the static mapping for now
534 */
535 switch (address) {
536 case 0x4a000000:
537 pr_debug("irq: found main intc\n");
538 intc->reg_pending = base;
539 intc->reg_mask = base + 0x08;
540 intc->reg_intpnd = base + 0x10;
541 irq_num = 32;
542 irq_start = S3C2410_IRQ(0);
1f629b7a
HS		 543 break;
544 case 0x4a000018:
545 pr_debug("irq: found subintc\n");
546 intc->reg_pending = base + 0x18;
547 intc->reg_mask = base + 0x1c;
548 irq_num = 29;
549 irq_start = S3C2410_IRQSUB(0);
1f629b7a
HS		 550 break;
551 case 0x4a000040:
552 pr_debug("irq: found intc2\n");
553 intc->reg_pending = base + 0x40;
554 intc->reg_mask = base + 0x48;
555 intc->reg_intpnd = base + 0x50;
556 irq_num = 8;
557 irq_start = S3C2416_IRQ(0);
1f629b7a
HS		 558 break;
559 case 0x560000a4:
560 pr_debug("irq: found eintc\n");
561 base = (void *)0xfd000000;
562
563 intc->reg_mask = base + 0xa4;
564 intc->reg_pending = base + 0x08;
5424f218 565 irq_num = 24;
1f629b7a 566 irq_start = S3C2410_IRQ(32);
1f629b7a
HS		 567 break;
568 default:
569 pr_err("irq: unsupported controller address\n");
570 ret = -EINVAL;
571 goto err;
572 }
a21765a7 573
1f629b7a
HS		 574 /* now that all the data is complete, init the irq-domain */
575 s3c24xx_clear_intc(intc);
576 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
5424f218 577 0, &s3c24xx_irq_ops,
1f629b7a
HS		 578 intc);
579 if (!intc->domain) {
580 pr_err("irq: could not create irq-domain\n");
581 ret = -EINVAL;
582 goto err;
583 }
a21765a7 584
17453dd2
HS		 585 set_handle_irq(s3c24xx_handle_irq);
586
1f629b7a 587 return intc;
a21765a7 588
1f629b7a
HS		 589err:
590 kfree(intc);
591 return ERR_PTR(ret);
592}
a21765a7 593
f182aa1d
HS		 594static struct s3c_irq_data init_eint[32] = {
595 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
596 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
597 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
598 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
599 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
600 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
601 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
602 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
603 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
604 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
605 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
606 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
607 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
608 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
609 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
610 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
611 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
612 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
619};
a21765a7 620
f182aa1d
HS		 621#ifdef CONFIG_CPU_S3C2410
622static struct s3c_irq_data init_s3c2410base[32] = {
1f629b7a
HS		 623 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
624 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
625 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
626 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
627 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
628 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
629 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
630 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
631 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
632 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
633 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
634 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
635 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
636 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
637 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
638 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
639 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
640 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
641 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
642 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
643 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
645 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
646 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
647 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
648 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
649 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
650 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
651 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
652 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
654 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
655};
a21765a7 656
f182aa1d 657static struct s3c_irq_data init_s3c2410subint[32] = {
1f629b7a
HS		 658 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
659 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
660 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
661 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
662 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
663 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
664 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
665 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
666 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
667 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
668 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
669};
a21765a7 670
f182aa1d 671void __init s3c2410_init_irq(void)
1f629b7a 672{
1f629b7a
HS		 673#ifdef CONFIG_FIQ
674 init_FIQ(FIQ_START);
675#endif
a21765a7 676
658dc8fb
HS		 677 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
678 0x4a000000);
679 if (IS_ERR(s3c_intc[0])) {
1f629b7a
HS		 680 pr_err("irq: could not create main interrupt controller\n");
681 return;
a21765a7
BD		 682 }
683
658dc8fb
HS		 684 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
685 s3c_intc[0], 0x4a000018);
686 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
a21765a7 687}
f182aa1d 688#endif
ef602eb5 689
d3d5a2c9 690#ifdef CONFIG_CPU_S3C2412
4245944c 691static struct s3c_irq_data init_s3c2412base[32] = {
1c8408e3
HS		 692 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
693 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
694 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
695 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
4245944c
HS		 696 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
697 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
698 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
699 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
700 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
701 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
702 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
703 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
704 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
705 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
706 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
707 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
708 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
709 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
710 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
711 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
712 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
713 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
714 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
715 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
716 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
717 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
718 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
719 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
721 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
722 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
723 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
724};
d3d5a2c9 725
1c8408e3
HS		 726static struct s3c_irq_data init_s3c2412eint[32] = {
727 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
728 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
729 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
730 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
731 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
732 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
733 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
734 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
735 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
736 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
737 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
738 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
739 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
740 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
751};
752
4245944c
HS		 753static struct s3c_irq_data init_s3c2412subint[32] = {
754 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
755 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
756 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
757 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
758 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
759 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
760 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
761 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
762 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
763 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
764 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
765 { .type = S3C_IRQTYPE_NONE, },
766 { .type = S3C_IRQTYPE_NONE, },
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
769};
d3d5a2c9 770
4245944c 771void s3c2412_init_irq(void)
d3d5a2c9 772{
4245944c 773 pr_info("S3C2412: IRQ Support\n");
d3d5a2c9 774
4245944c
HS		 775#ifdef CONFIG_FIQ
776 init_FIQ(FIQ_START);
777#endif
d3d5a2c9 778
658dc8fb
HS		 779 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
780 0x4a000000);
781 if (IS_ERR(s3c_intc[0])) {
4245944c
HS		 782 pr_err("irq: could not create main interrupt controller\n");
783 return;
784 }
d3d5a2c9 785
658dc8fb
HS		 786 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
787 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
788 s3c_intc[0], 0x4a000018);
d3d5a2c9 789}
d3d5a2c9
HS		 790#endif
791
ef602eb5 792#ifdef CONFIG_CPU_S3C2416
20f6c781
HS		 793static struct s3c_irq_data init_s3c2416base[32] = {
794 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
795 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
796 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
797 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
798 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
799 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
800 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
801 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
802 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
803 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
804 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
805 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
806 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
807 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
808 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
809 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
810 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
811 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
812 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
813 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
814 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
815 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
816 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
817 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
818 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
819 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
820 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
821 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
823 { .type = S3C_IRQTYPE_NONE, },
824 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
ef602eb5
HS		 826};
827
20f6c781
HS		 828static struct s3c_irq_data init_s3c2416subint[32] = {
829 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
830 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
831 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
832 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
833 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
834 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
835 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
836 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
837 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
838 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
839 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
840 { .type = S3C_IRQTYPE_NONE }, /* reserved */
841 { .type = S3C_IRQTYPE_NONE }, /* reserved */
842 { .type = S3C_IRQTYPE_NONE }, /* reserved */
843 { .type = S3C_IRQTYPE_NONE }, /* reserved */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
852 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
853 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
ef602eb5
HS		 858};
859
20f6c781
HS		 860static struct s3c_irq_data init_s3c2416_second[32] = {
861 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
1ebc7e83 862 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781
HS		 863 { .type = S3C_IRQTYPE_NONE }, /* reserved */
864 { .type = S3C_IRQTYPE_NONE }, /* reserved */
865 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
1ebc7e83 866 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781 867 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
ef602eb5
HS		 868};
869
4a282dd3 870void __init s3c2416_init_irq(void)
ef602eb5 871{
20f6c781 872 pr_info("S3C2416: IRQ Support\n");
ef602eb5 873
20f6c781
HS		 874#ifdef CONFIG_FIQ
875 init_FIQ(FIQ_START);
876#endif
ef602eb5 877
658dc8fb
HS		 878 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
879 0x4a000000);
880 if (IS_ERR(s3c_intc[0])) {
20f6c781
HS		 881 pr_err("irq: could not create main interrupt controller\n");
882 return;
883 }
ef602eb5 884
658dc8fb
HS		 885 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
886 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
887 s3c_intc[0], 0x4a000018);
ef602eb5 888
658dc8fb
HS		 889 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
890 NULL, 0x4a000040);
ef602eb5
HS		 891}
892
ef602eb5 893#endif
6b628917 894
ce6c164b 895#ifdef CONFIG_CPU_S3C2440
f0301673
HS		 896static struct s3c_irq_data init_s3c2440base[32] = {
897 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
898 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
899 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
900 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
901 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
902 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
903 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
904 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
905 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
906 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
907 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
908 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
909 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
910 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
911 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
912 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
913 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
914 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
915 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
916 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
917 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
918 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
919 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
920 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
921 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
922 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
923 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
924 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
925 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
926 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
927 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
928 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
929};
2286cf46 930
f0301673
HS		 931static struct s3c_irq_data init_s3c2440subint[32] = {
932 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
933 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
934 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
935 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
936 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
937 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
938 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
939 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
940 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
941 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
942 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 943 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
944 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
f0301673
HS		 945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
2286cf46
HS		 947};
948
7cefed5e 949void __init s3c2440_init_irq(void)
2286cf46 950{
f0301673 951 pr_info("S3C2440: IRQ Support\n");
6f8d7ea2 952
f0301673
HS		 953#ifdef CONFIG_FIQ
954 init_FIQ(FIQ_START);
955#endif
6f8d7ea2 956
658dc8fb
HS		 957 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
958 0x4a000000);
959 if (IS_ERR(s3c_intc[0])) {
f0301673
HS		 960 pr_err("irq: could not create main interrupt controller\n");
961 return;
6f8d7ea2 962 }
7cefed5e 963
658dc8fb
HS		 964 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
965 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
966 s3c_intc[0], 0x4a000018);
6f8d7ea2 967}
ce6c164b 968#endif
6f8d7ea2 969
ce6c164b 970#ifdef CONFIG_CPU_S3C2442
70644ade
HS		 971static struct s3c_irq_data init_s3c2442base[32] = {
972 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
973 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
974 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
975 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
976 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
977 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
978 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
979 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
980 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
981 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
982 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
983 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
984 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
985 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
986 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
987 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
988 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
989 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
990 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
991 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
992 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
993 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
994 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
995 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
996 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
997 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
998 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
999 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1000 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1001 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1003 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1004};
6f8d7ea2 1005
70644ade
HS		 1006static struct s3c_irq_data init_s3c2442subint[32] = {
1007 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1008 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1009 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1010 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1011 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1012 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1013 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1014 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1015 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1016 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1017 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 1018 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1019 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
70644ade 1020};
6f8d7ea2 1021
70644ade
HS		 1022void __init s3c2442_init_irq(void)
1023{
70644ade 1024 pr_info("S3C2442: IRQ Support\n");
6f8d7ea2 1025
70644ade
HS		 1026#ifdef CONFIG_FIQ
1027 init_FIQ(FIQ_START);
1028#endif
ce6c164b 1029
658dc8fb
HS		 1030 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1031 0x4a000000);
1032 if (IS_ERR(s3c_intc[0])) {
70644ade
HS		 1033 pr_err("irq: could not create main interrupt controller\n");
1034 return;
ce6c164b 1035 }
70644ade 1036
658dc8fb
HS		 1037 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1038 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1039 s3c_intc[0], 0x4a000018);
6f8d7ea2 1040}
ce6c164b 1041#endif
6f8d7ea2 1042
6b628917 1043#ifdef CONFIG_CPU_S3C2443
f44ddba3
HS		 1044static struct s3c_irq_data init_s3c2443base[32] = {
1045 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1046 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1047 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1048 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1049 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1050 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1051 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1052 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1053 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1054 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1055 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1056 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1057 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1058 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1059 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1060 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1061 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1062 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1063 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1064 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1065 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1066 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1067 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1068 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1072 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1073 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1074 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1075 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
6b628917
HS		 1077};
1078
6b628917 1079
f44ddba3
HS		 1080static struct s3c_irq_data init_s3c2443subint[32] = {
1081 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1082 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1083 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1084 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1085 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1086 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1087 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1088 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1089 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1090 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1091 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1092 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1093 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1094 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1104 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
6b628917
HS		 1110};
1111
b499b7a8 1112void __init s3c2443_init_irq(void)
6b628917 1113{
f44ddba3 1114 pr_info("S3C2443: IRQ Support\n");
6b628917 1115
f44ddba3
HS		 1116#ifdef CONFIG_FIQ
1117 init_FIQ(FIQ_START);
1118#endif
6b628917 1119
658dc8fb
HS		 1120 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1121 0x4a000000);
1122 if (IS_ERR(s3c_intc[0])) {
f44ddba3
HS		 1123 pr_err("irq: could not create main interrupt controller\n");
1124 return;
1125 }
6b628917 1126
658dc8fb
HS		 1127 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1128 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1129 s3c_intc[0], 0x4a000018);
6b628917 1130}
6b628917 1131#endif
Linux kernel - Deliverables
This page took 0.520519 seconds and 5 git commands to generate.