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irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
[deliverable/linux.git] / drivers / irqchip / irq-s3c24xx.c
CommitLineData
1f629b7a
HS		 1/*
2 * S3C24XX IRQ handling
a21765a7 3 *
e02f8664 4 * Copyright (c) 2003-2004 Simtec Electronics
a21765a7 5 * Ben Dooks <ben@simtec.co.uk>
1f629b7a 6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
a21765a7
BD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
a21765a7
BD		 17*/
18
19#include <linux/init.h>
1f629b7a 20#include <linux/slab.h>
a21765a7 21#include <linux/module.h>
1f629b7a
HS		 22#include <linux/io.h>
23#include <linux/err.h>
a21765a7
BD		 24#include <linux/interrupt.h>
25#include <linux/ioport.h>
edbaa603 26#include <linux/device.h>
1f629b7a 27#include <linux/irqdomain.h>
a21765a7 28
17453dd2 29#include <asm/exception.h>
a21765a7
BD		 30#include <asm/mach/irq.h>
31
1f629b7a
HS		 32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
a21765a7 34
a2b7ba9c 35#include <plat/cpu.h>
1f629b7a 36#include <plat/regs-irqtype.h>
a2b7ba9c 37#include <plat/pm.h>
a21765a7 38
1f629b7a
HS		 39#define S3C_IRQTYPE_NONE 0
40#define S3C_IRQTYPE_EINT 1
41#define S3C_IRQTYPE_EDGE 2
42#define S3C_IRQTYPE_LEVEL 3
a21765a7 43
1f629b7a
HS		 44struct s3c_irq_data {
45 unsigned int type;
f5a25524 46 unsigned long offset;
1f629b7a 47 unsigned long parent_irq;
a21765a7 48
1f629b7a
HS		 49 /* data gets filled during init */
50 struct s3c_irq_intc *intc;
51 unsigned long sub_bits;
52 struct s3c_irq_intc *sub_intc;
a21765a7
BD		 53};
54
1f629b7a
HS		 55/*
56 * Sructure holding the controller data
57 * @reg_pending register holding pending irqs
58 * @reg_intpnd special register intpnd in main intc
59 * @reg_mask mask register
60 * @domain irq_domain of the controller
61 * @parent parent controller for ext and sub irqs
62 * @irqs irq-data, always s3c_irq_data[32]
63 */
64struct s3c_irq_intc {
65 void __iomem *reg_pending;
66 void __iomem *reg_intpnd;
67 void __iomem *reg_mask;
68 struct irq_domain *domain;
69 struct s3c_irq_intc *parent;
70 struct s3c_irq_data *irqs;
a21765a7
BD		 71};
72
658dc8fb
HS		 73/*
74 * Array holding pointers to the global controller structs
75 * [0] ... main_intc
76 * [1] ... sub_intc
77 * [2] ... main_intc2 on s3c2416
78 */
79static struct s3c_irq_intc *s3c_intc[3];
80
1f629b7a 81static void s3c_irq_mask(struct irq_data *data)
a21765a7 82{
f5a25524
HS		 83 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
84 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 85 struct s3c_irq_intc *parent_intc = intc->parent;
1f629b7a 86 struct s3c_irq_data *parent_data;
a21765a7 87 unsigned long mask;
1f629b7a
HS		 88 unsigned int irqno;
89
90 mask = __raw_readl(intc->reg_mask);
f5a25524 91 mask |= (1UL << irq_data->offset);
1f629b7a
HS		 92 __raw_writel(mask, intc->reg_mask);
93
0fe3cb1e 94 if (parent_intc) {
1f629b7a 95 parent_data = &parent_intc->irqs[irq_data->parent_irq];
a21765a7 96
1f629b7a
HS		 97 /* check to see if we need to mask the parent IRQ */
98 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
99 irqno = irq_find_mapping(parent_intc->domain,
100 irq_data->parent_irq);
101 s3c_irq_mask(irq_get_irq_data(irqno));
102 }
103 }
a21765a7
BD		 104}
105
1f629b7a 106static void s3c_irq_unmask(struct irq_data *data)
a21765a7 107{
f5a25524
HS		 108 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
109 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 110 struct s3c_irq_intc *parent_intc = intc->parent;
a21765a7 111 unsigned long mask;
1f629b7a 112 unsigned int irqno;
a21765a7 113
1f629b7a 114 mask = __raw_readl(intc->reg_mask);
f5a25524 115 mask &= ~(1UL << irq_data->offset);
1f629b7a 116 __raw_writel(mask, intc->reg_mask);
a21765a7 117
0fe3cb1e 118 if (parent_intc) {
1f629b7a
HS		 119 irqno = irq_find_mapping(parent_intc->domain,
120 irq_data->parent_irq);
121 s3c_irq_unmask(irq_get_irq_data(irqno));
a21765a7
BD		 122 }
123}
124
1f629b7a 125static inline void s3c_irq_ack(struct irq_data *data)
a21765a7 126{
f5a25524
HS		 127 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
128 struct s3c_irq_intc *intc = irq_data->intc;
129 unsigned long bitval = 1UL << irq_data->offset;
a21765a7 130
1f629b7a
HS		 131 __raw_writel(bitval, intc->reg_pending);
132 if (intc->reg_intpnd)
133 __raw_writel(bitval, intc->reg_intpnd);
a21765a7
BD		 134}
135
bd7c0da2
HS		 136static int s3c_irq_type(struct irq_data *data, unsigned int type)
137{
138 switch (type) {
139 case IRQ_TYPE_NONE:
140 break;
141 case IRQ_TYPE_EDGE_RISING:
142 case IRQ_TYPE_EDGE_FALLING:
143 case IRQ_TYPE_EDGE_BOTH:
144 irq_set_handler(data->irq, handle_edge_irq);
145 break;
146 case IRQ_TYPE_LEVEL_LOW:
147 case IRQ_TYPE_LEVEL_HIGH:
148 irq_set_handler(data->irq, handle_level_irq);
149 break;
150 default:
151 pr_err("No such irq type %d", type);
152 return -EINVAL;
153 }
154
155 return 0;
156}
157
1f629b7a
HS		 158static int s3c_irqext_type_set(void __iomem *gpcon_reg,
159 void __iomem *extint_reg,
160 unsigned long gpcon_offset,
161 unsigned long extint_offset,
162 unsigned int type)
a21765a7 163{
a21765a7
BD		 164 unsigned long newvalue = 0, value;
165
a21765a7
BD		 166 /* Set the GPIO to external interrupt mode */
167 value = __raw_readl(gpcon_reg);
168 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
169 __raw_writel(value, gpcon_reg);
170
171 /* Set the external interrupt to pointed trigger type */
172 switch (type)
173 {
6cab4860 174 case IRQ_TYPE_NONE:
1f629b7a 175 pr_warn("No edge setting!\n");
a21765a7
BD		 176 break;
177
6cab4860 178 case IRQ_TYPE_EDGE_RISING:
a21765a7
BD		 179 newvalue = S3C2410_EXTINT_RISEEDGE;
180 break;
181
6cab4860 182 case IRQ_TYPE_EDGE_FALLING:
a21765a7
BD		 183 newvalue = S3C2410_EXTINT_FALLEDGE;
184 break;
185
6cab4860 186 case IRQ_TYPE_EDGE_BOTH:
a21765a7
BD		 187 newvalue = S3C2410_EXTINT_BOTHEDGE;
188 break;
189
6cab4860 190 case IRQ_TYPE_LEVEL_LOW:
a21765a7
BD		 191 newvalue = S3C2410_EXTINT_LOWLEV;
192 break;
193
6cab4860 194 case IRQ_TYPE_LEVEL_HIGH:
a21765a7
BD		 195 newvalue = S3C2410_EXTINT_HILEV;
196 break;
197
198 default:
1f629b7a
HS		 199 pr_err("No such irq type %d", type);
200 return -EINVAL;
a21765a7
BD		 201 }
202
203 value = __raw_readl(extint_reg);
204 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
205 __raw_writel(value, extint_reg);
206
207 return 0;
208}
209
dc1a3538 210static int s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 211{
1f629b7a
HS		 212 void __iomem *extint_reg;
213 void __iomem *gpcon_reg;
214 unsigned long gpcon_offset, extint_offset;
a21765a7 215
1f629b7a
HS		 216 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
217 gpcon_reg = S3C2410_GPFCON;
218 extint_reg = S3C24XX_EXTINT0;
219 gpcon_offset = (data->hwirq) * 2;
220 extint_offset = (data->hwirq) * 4;
221 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
222 gpcon_reg = S3C2410_GPGCON;
223 extint_reg = S3C24XX_EXTINT1;
224 gpcon_offset = (data->hwirq - 8) * 2;
225 extint_offset = (data->hwirq - 8) * 4;
226 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
227 gpcon_reg = S3C2410_GPGCON;
228 extint_reg = S3C24XX_EXTINT2;
229 gpcon_offset = (data->hwirq - 8) * 2;
230 extint_offset = (data->hwirq - 16) * 4;
231 } else {
232 return -EINVAL;
233 }
a21765a7 234
1f629b7a
HS		 235 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
236 extint_offset, type);
a21765a7
BD		 237}
238
1f629b7a 239static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
a21765a7 240{
1f629b7a
HS		 241 void __iomem *extint_reg;
242 void __iomem *gpcon_reg;
243 unsigned long gpcon_offset, extint_offset;
a21765a7 244
1f629b7a
HS		 245 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
246 gpcon_reg = S3C2410_GPFCON;
247 extint_reg = S3C24XX_EXTINT0;
248 gpcon_offset = (data->hwirq) * 2;
249 extint_offset = (data->hwirq) * 4;
250 } else {
251 return -EINVAL;
252 }
a21765a7 253
1f629b7a
HS		 254 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
255 extint_offset, type);
a21765a7
BD		 256}
257
dc1a3538 258static struct irq_chip s3c_irq_chip = {
1f629b7a
HS		 259 .name = "s3c",
260 .irq_ack = s3c_irq_ack,
261 .irq_mask = s3c_irq_mask,
262 .irq_unmask = s3c_irq_unmask,
bd7c0da2 263 .irq_set_type = s3c_irq_type,
1f629b7a 264 .irq_set_wake = s3c_irq_wake
a21765a7
BD		 265};
266
dc1a3538 267static struct irq_chip s3c_irq_level_chip = {
1f629b7a
HS		 268 .name = "s3c-level",
269 .irq_mask = s3c_irq_mask,
270 .irq_unmask = s3c_irq_unmask,
271 .irq_ack = s3c_irq_ack,
bd7c0da2 272 .irq_set_type = s3c_irq_type,
a21765a7
BD		 273};
274
1f629b7a
HS		 275static struct irq_chip s3c_irqext_chip = {
276 .name = "s3c-ext",
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_ack = s3c_irq_ack,
280 .irq_set_type = s3c_irqext_type,
281 .irq_set_wake = s3c_irqext_wake
a21765a7
BD		 282};
283
1f629b7a
HS		 284static struct irq_chip s3c_irq_eint0t4 = {
285 .name = "s3c-ext0",
286 .irq_ack = s3c_irq_ack,
287 .irq_mask = s3c_irq_mask,
288 .irq_unmask = s3c_irq_unmask,
289 .irq_set_wake = s3c_irq_wake,
290 .irq_set_type = s3c_irqext0_type,
291};
a21765a7 292
1f629b7a 293static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
a21765a7 294{
1f629b7a 295 struct irq_chip *chip = irq_desc_get_chip(desc);
f5a25524 296 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
1f629b7a
HS		 297 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
298 unsigned long src;
299 unsigned long msk;
300 unsigned int n;
301
302 chained_irq_enter(chip, desc);
303
304 src = __raw_readl(sub_intc->reg_pending);
305 msk = __raw_readl(sub_intc->reg_mask);
306
307 src &= ~msk;
308 src &= irq_data->sub_bits;
309
310 while (src) {
311 n = __ffs(src);
312 src &= ~(1 << n);
313 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
a21765a7
BD		 314 }
315
1f629b7a 316 chained_irq_exit(chip, desc);
a21765a7
BD		 317}
318
17453dd2
HS		 319static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
320 struct pt_regs *regs)
321{
322 int pnd;
323 int offset;
324 int irq;
325
326 pnd = __raw_readl(intc->reg_intpnd);
327 if (!pnd)
328 return false;
329
330 /* We have a problem that the INTOFFSET register does not always
331 * show one interrupt. Occasionally we get two interrupts through
332 * the prioritiser, and this causes the INTOFFSET register to show
333 * what looks like the logical-or of the two interrupt numbers.
334 *
335 * Thanks to Klaus, Shannon, et al for helping to debug this problem
336 */
337 offset = __raw_readl(intc->reg_intpnd + 4);
338
339 /* Find the bit manually, when the offset is wrong.
340 * The pending register only ever contains the one bit of the next
341 * interrupt to handle.
342 */
343 if (!(pnd & (1 << offset)))
344 offset = __ffs(pnd);
345
346 irq = irq_find_mapping(intc->domain, offset);
347 handle_IRQ(irq, regs);
348 return true;
349}
350
351asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
352{
353 do {
658dc8fb
HS		 354 if (likely(s3c_intc[0]))
355 if (s3c24xx_handle_intc(s3c_intc[0], regs))
17453dd2
HS		 356 continue;
357
658dc8fb
HS		 358 if (s3c_intc[2])
359 if (s3c24xx_handle_intc(s3c_intc[2], regs))
17453dd2
HS		 360 continue;
361
362 break;
363 } while (1);
364}
365
229fd8ff
BD		 366#ifdef CONFIG_FIQ
367/**
368 * s3c24xx_set_fiq - set the FIQ routing
369 * @irq: IRQ number to route to FIQ on processor.
370 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
371 *
372 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
373 * @on is true, the @irq is checked to see if it can be routed and the
374 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
375 * routing is cleared, regardless of which @irq is specified.
376 */
377int s3c24xx_set_fiq(unsigned int irq, bool on)
378{
379 u32 intmod;
380 unsigned offs;
381
382 if (on) {
383 offs = irq - FIQ_START;
384 if (offs > 31)
385 return -EINVAL;
386
387 intmod = 1 << offs;
388 } else {
389 intmod = 0;
390 }
391
392 __raw_writel(intmod, S3C2410_INTMOD);
393 return 0;
394}
0f13c824
BD		 395
396EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff
BD		 397#endif
398
1f629b7a
HS		 399static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
400 irq_hw_number_t hw)
a21765a7 401{
1f629b7a
HS		 402 struct s3c_irq_intc *intc = h->host_data;
403 struct s3c_irq_data *irq_data = &intc->irqs[hw];
404 struct s3c_irq_intc *parent_intc;
405 struct s3c_irq_data *parent_irq_data;
406 unsigned int irqno;
407
1f629b7a
HS		 408 /* attach controller pointer to irq_data */
409 irq_data->intc = intc;
f5a25524 410 irq_data->offset = hw;
a21765a7 411
0fe3cb1e
HS		 412 parent_intc = intc->parent;
413
1f629b7a
HS		 414 /* set handler and flags */
415 switch (irq_data->type) {
416 case S3C_IRQTYPE_NONE:
417 return 0;
418 case S3C_IRQTYPE_EINT:
1c8408e3
HS		 419 /* On the S3C2412, the EINT0to3 have a parent irq
420 * but need the s3c_irq_eint0t4 chip
421 */
0fe3cb1e 422 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
1f629b7a
HS		 423 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
424 handle_edge_irq);
425 else
426 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
427 handle_edge_irq);
428 break;
429 case S3C_IRQTYPE_EDGE:
0fe3cb1e 430 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
1f629b7a
HS		 431 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
432 handle_edge_irq);
433 else
434 irq_set_chip_and_handler(virq, &s3c_irq_chip,
435 handle_edge_irq);
436 break;
437 case S3C_IRQTYPE_LEVEL:
0fe3cb1e 438 if (parent_intc)
1f629b7a
HS		 439 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
440 handle_level_irq);
441 else
442 irq_set_chip_and_handler(virq, &s3c_irq_chip,
443 handle_level_irq);
444 break;
445 default:
446 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
447 return -EINVAL;
a21765a7 448 }
f5a25524
HS		 449
450 irq_set_chip_data(virq, irq_data);
451
1f629b7a
HS		 452 set_irq_flags(virq, IRQF_VALID);
453
0fe3cb1e 454 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
502a2989
HS		 455 if (irq_data->parent_irq > 31) {
456 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
457 irq_data->parent_irq);
1f629b7a
HS		 458 goto err;
459 }
a21765a7 460
502a2989 461 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1f629b7a
HS		 462 parent_irq_data->sub_intc = intc;
463 parent_irq_data->sub_bits |= (1UL << hw);
a21765a7 464
1f629b7a
HS		 465 /* attach the demuxer to the parent irq */
466 irqno = irq_find_mapping(parent_intc->domain,
467 irq_data->parent_irq);
468 if (!irqno) {
469 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
470 irq_data->parent_irq);
471 goto err;
472 }
473 irq_set_chained_handler(irqno, s3c_irq_demux);
a21765a7
BD		 474 }
475
1f629b7a 476 return 0;
a21765a7 477
1f629b7a
HS		 478err:
479 set_irq_flags(virq, 0);
a21765a7 480
1f629b7a
HS		 481 /* the only error can result from bad mapping data*/
482 return -EINVAL;
483}
a21765a7 484
1f629b7a
HS		 485static struct irq_domain_ops s3c24xx_irq_ops = {
486 .map = s3c24xx_irq_map,
487 .xlate = irq_domain_xlate_twocell,
488};
a21765a7 489
1f629b7a
HS		 490static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
491{
492 void __iomem *reg_source;
493 unsigned long pend;
494 unsigned long last;
495 int i;
a21765a7 496
1f629b7a
HS		 497 /* if intpnd is set, read the next pending irq from there */
498 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
a21765a7 499
1f629b7a
HS		 500 last = 0;
501 for (i = 0; i < 4; i++) {
502 pend = __raw_readl(reg_source);
a21765a7 503
1f629b7a 504 if (pend == 0 || pend == last)
a21765a7
BD		 505 break;
506
1f629b7a
HS		 507 __raw_writel(pend, intc->reg_pending);
508 if (intc->reg_intpnd)
509 __raw_writel(pend, intc->reg_intpnd);
a21765a7 510
1f629b7a
HS		 511 pr_info("irq: clearing pending status %08x\n", (int)pend);
512 last = pend;
a21765a7 513 }
1f629b7a 514}
a21765a7 515
3d3eb5a4 516static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
1f629b7a
HS		 517 struct s3c_irq_data *irq_data,
518 struct s3c_irq_intc *parent,
519 unsigned long address)
520{
521 struct s3c_irq_intc *intc;
522 void __iomem *base = (void *)0xf6000000; /* static mapping */
523 int irq_num;
524 int irq_start;
1f629b7a
HS		 525 int ret;
526
527 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
528 if (!intc)
529 return ERR_PTR(-ENOMEM);
530
531 intc->irqs = irq_data;
532
533 if (parent)
534 intc->parent = parent;
535
536 /* select the correct data for the controller.
537 * Need to hard code the irq num start and offset
538 * to preserve the static mapping for now
539 */
540 switch (address) {
541 case 0x4a000000:
542 pr_debug("irq: found main intc\n");
543 intc->reg_pending = base;
544 intc->reg_mask = base + 0x08;
545 intc->reg_intpnd = base + 0x10;
546 irq_num = 32;
547 irq_start = S3C2410_IRQ(0);
1f629b7a
HS		 548 break;
549 case 0x4a000018:
550 pr_debug("irq: found subintc\n");
551 intc->reg_pending = base + 0x18;
552 intc->reg_mask = base + 0x1c;
553 irq_num = 29;
554 irq_start = S3C2410_IRQSUB(0);
1f629b7a
HS		 555 break;
556 case 0x4a000040:
557 pr_debug("irq: found intc2\n");
558 intc->reg_pending = base + 0x40;
559 intc->reg_mask = base + 0x48;
560 intc->reg_intpnd = base + 0x50;
561 irq_num = 8;
562 irq_start = S3C2416_IRQ(0);
1f629b7a
HS		 563 break;
564 case 0x560000a4:
565 pr_debug("irq: found eintc\n");
566 base = (void *)0xfd000000;
567
568 intc->reg_mask = base + 0xa4;
569 intc->reg_pending = base + 0x08;
5424f218 570 irq_num = 24;
1f629b7a 571 irq_start = S3C2410_IRQ(32);
1f629b7a
HS		 572 break;
573 default:
574 pr_err("irq: unsupported controller address\n");
575 ret = -EINVAL;
576 goto err;
577 }
a21765a7 578
1f629b7a
HS		 579 /* now that all the data is complete, init the irq-domain */
580 s3c24xx_clear_intc(intc);
581 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
5424f218 582 0, &s3c24xx_irq_ops,
1f629b7a
HS		 583 intc);
584 if (!intc->domain) {
585 pr_err("irq: could not create irq-domain\n");
586 ret = -EINVAL;
587 goto err;
588 }
a21765a7 589
17453dd2
HS		 590 set_handle_irq(s3c24xx_handle_irq);
591
1f629b7a 592 return intc;
a21765a7 593
1f629b7a
HS		 594err:
595 kfree(intc);
596 return ERR_PTR(ret);
597}
a21765a7 598
f182aa1d
HS		 599static struct s3c_irq_data init_eint[32] = {
600 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
601 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
602 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
603 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
604 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
605 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
606 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
607 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
608 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
609 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
610 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
611 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
612 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
624};
a21765a7 625
f182aa1d
HS		 626#ifdef CONFIG_CPU_S3C2410
627static struct s3c_irq_data init_s3c2410base[32] = {
1f629b7a
HS		 628 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
629 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
630 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
631 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
632 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
633 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
634 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
635 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
636 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
637 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
638 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
639 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
640 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
641 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
642 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
643 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
645 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
646 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
647 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
648 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
649 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
650 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
651 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
652 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
653 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
654 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
655 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
656 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
657 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
658 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
659 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
660};
a21765a7 661
f182aa1d 662static struct s3c_irq_data init_s3c2410subint[32] = {
1f629b7a
HS		 663 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
664 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
665 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
666 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
667 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
668 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
669 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
672 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
673 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
674};
a21765a7 675
f182aa1d 676void __init s3c2410_init_irq(void)
1f629b7a 677{
1f629b7a
HS		 678#ifdef CONFIG_FIQ
679 init_FIQ(FIQ_START);
680#endif
a21765a7 681
658dc8fb
HS		 682 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
683 0x4a000000);
684 if (IS_ERR(s3c_intc[0])) {
1f629b7a
HS		 685 pr_err("irq: could not create main interrupt controller\n");
686 return;
a21765a7
BD		 687 }
688
658dc8fb
HS		 689 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
690 s3c_intc[0], 0x4a000018);
691 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
a21765a7 692}
f182aa1d 693#endif
ef602eb5 694
d3d5a2c9 695#ifdef CONFIG_CPU_S3C2412
4245944c 696static struct s3c_irq_data init_s3c2412base[32] = {
1c8408e3
HS		 697 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
698 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
699 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
700 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
4245944c
HS		 701 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
702 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
703 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
704 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
705 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
706 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
707 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
708 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
709 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
710 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
711 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
712 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
713 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
714 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
715 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
716 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
717 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
718 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
719 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
721 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
722 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
723 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
724 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
725 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
726 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
727 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
728 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
729};
d3d5a2c9 730
1c8408e3
HS		 731static struct s3c_irq_data init_s3c2412eint[32] = {
732 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
733 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
734 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
735 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
736 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
737 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
738 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
739 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
740 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
756};
757
4245944c
HS		 758static struct s3c_irq_data init_s3c2412subint[32] = {
759 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
760 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
761 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
762 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
763 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
764 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
765 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
766 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
768 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
769 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
770 { .type = S3C_IRQTYPE_NONE, },
771 { .type = S3C_IRQTYPE_NONE, },
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
774};
d3d5a2c9 775
4245944c 776void s3c2412_init_irq(void)
d3d5a2c9 777{
4245944c 778 pr_info("S3C2412: IRQ Support\n");
d3d5a2c9 779
4245944c
HS		 780#ifdef CONFIG_FIQ
781 init_FIQ(FIQ_START);
782#endif
d3d5a2c9 783
658dc8fb
HS		 784 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
785 0x4a000000);
786 if (IS_ERR(s3c_intc[0])) {
4245944c
HS		 787 pr_err("irq: could not create main interrupt controller\n");
788 return;
789 }
d3d5a2c9 790
658dc8fb
HS		 791 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
792 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
793 s3c_intc[0], 0x4a000018);
d3d5a2c9 794}
d3d5a2c9
HS		 795#endif
796
ef602eb5 797#ifdef CONFIG_CPU_S3C2416
20f6c781
HS		 798static struct s3c_irq_data init_s3c2416base[32] = {
799 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
800 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
801 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
802 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
803 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
804 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
805 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
806 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
807 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
808 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
809 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
810 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
811 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
812 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
813 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
814 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
815 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
816 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
817 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
818 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
819 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
820 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
821 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
823 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
824 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
825 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
826 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
827 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
828 { .type = S3C_IRQTYPE_NONE, },
829 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
830 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
ef602eb5
HS		 831};
832
20f6c781
HS		 833static struct s3c_irq_data init_s3c2416subint[32] = {
834 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
835 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
836 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
837 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
838 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
839 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
840 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
841 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
842 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
843 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
844 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
845 { .type = S3C_IRQTYPE_NONE }, /* reserved */
846 { .type = S3C_IRQTYPE_NONE }, /* reserved */
847 { .type = S3C_IRQTYPE_NONE }, /* reserved */
848 { .type = S3C_IRQTYPE_NONE }, /* reserved */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
852 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
853 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
ef602eb5
HS		 863};
864
20f6c781
HS		 865static struct s3c_irq_data init_s3c2416_second[32] = {
866 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
1ebc7e83 867 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781
HS		 868 { .type = S3C_IRQTYPE_NONE }, /* reserved */
869 { .type = S3C_IRQTYPE_NONE }, /* reserved */
870 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
1ebc7e83 871 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781 872 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
ef602eb5
HS		 873};
874
4a282dd3 875void __init s3c2416_init_irq(void)
ef602eb5 876{
20f6c781 877 pr_info("S3C2416: IRQ Support\n");
ef602eb5 878
20f6c781
HS		 879#ifdef CONFIG_FIQ
880 init_FIQ(FIQ_START);
881#endif
ef602eb5 882
658dc8fb
HS		 883 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
884 0x4a000000);
885 if (IS_ERR(s3c_intc[0])) {
20f6c781
HS		 886 pr_err("irq: could not create main interrupt controller\n");
887 return;
888 }
ef602eb5 889
658dc8fb
HS		 890 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
891 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
892 s3c_intc[0], 0x4a000018);
ef602eb5 893
658dc8fb
HS		 894 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
895 NULL, 0x4a000040);
ef602eb5
HS		 896}
897
ef602eb5 898#endif
6b628917 899
ce6c164b 900#ifdef CONFIG_CPU_S3C2440
f0301673
HS		 901static struct s3c_irq_data init_s3c2440base[32] = {
902 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
903 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
904 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
905 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
906 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
907 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
908 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
909 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
910 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
911 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
912 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
913 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
914 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
915 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
916 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
917 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
918 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
919 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
920 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
921 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
923 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
924 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
925 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
926 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
927 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
928 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
929 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
930 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
931 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
932 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
933 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
934};
2286cf46 935
f0301673
HS		 936static struct s3c_irq_data init_s3c2440subint[32] = {
937 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
938 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
939 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
940 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
941 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
942 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
943 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
944 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
946 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
947 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
f0301673
HS		 950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
2286cf46
HS		 952};
953
7cefed5e 954void __init s3c2440_init_irq(void)
2286cf46 955{
f0301673 956 pr_info("S3C2440: IRQ Support\n");
6f8d7ea2 957
f0301673
HS		 958#ifdef CONFIG_FIQ
959 init_FIQ(FIQ_START);
960#endif
6f8d7ea2 961
658dc8fb
HS		 962 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
963 0x4a000000);
964 if (IS_ERR(s3c_intc[0])) {
f0301673
HS		 965 pr_err("irq: could not create main interrupt controller\n");
966 return;
6f8d7ea2 967 }
7cefed5e 968
658dc8fb
HS		 969 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
970 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
971 s3c_intc[0], 0x4a000018);
6f8d7ea2 972}
ce6c164b 973#endif
6f8d7ea2 974
ce6c164b 975#ifdef CONFIG_CPU_S3C2442
70644ade
HS		 976static struct s3c_irq_data init_s3c2442base[32] = {
977 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
978 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
979 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
980 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
981 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
982 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
983 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
984 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
985 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
986 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
987 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
988 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
989 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
990 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
991 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
992 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
993 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
994 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
995 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
996 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
997 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
998 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
999 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1000 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1001 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1005 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1008 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1009};
6f8d7ea2 1010
70644ade
HS		 1011static struct s3c_irq_data init_s3c2442subint[32] = {
1012 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1013 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1014 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1015 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1016 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1017 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1018 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1019 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1020 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1021 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1022 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
70644ade 1025};
6f8d7ea2 1026
70644ade
HS		 1027void __init s3c2442_init_irq(void)
1028{
70644ade 1029 pr_info("S3C2442: IRQ Support\n");
6f8d7ea2 1030
70644ade
HS		 1031#ifdef CONFIG_FIQ
1032 init_FIQ(FIQ_START);
1033#endif
ce6c164b 1034
658dc8fb
HS		 1035 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1036 0x4a000000);
1037 if (IS_ERR(s3c_intc[0])) {
70644ade
HS		 1038 pr_err("irq: could not create main interrupt controller\n");
1039 return;
ce6c164b 1040 }
70644ade 1041
658dc8fb
HS		 1042 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1043 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1044 s3c_intc[0], 0x4a000018);
6f8d7ea2 1045}
ce6c164b 1046#endif
6f8d7ea2 1047
6b628917 1048#ifdef CONFIG_CPU_S3C2443
f44ddba3
HS		 1049static struct s3c_irq_data init_s3c2443base[32] = {
1050 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1051 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1052 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1053 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1054 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1055 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1056 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1057 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1058 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1059 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1060 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1061 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1062 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1063 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1064 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1065 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1066 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1067 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1068 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1072 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1073 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1074 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1075 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1076 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1077 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1078 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1081 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
6b628917
HS		 1082};
1083
6b628917 1084
f44ddba3
HS		 1085static struct s3c_irq_data init_s3c2443subint[32] = {
1086 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1087 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1088 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1089 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1090 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1091 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1092 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1093 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1094 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1095 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1096 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1099 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1104 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
6b628917
HS		 1115};
1116
b499b7a8 1117void __init s3c2443_init_irq(void)
6b628917 1118{
f44ddba3 1119 pr_info("S3C2443: IRQ Support\n");
6b628917 1120
f44ddba3
HS		 1121#ifdef CONFIG_FIQ
1122 init_FIQ(FIQ_START);
1123#endif
6b628917 1124
658dc8fb
HS		 1125 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1126 0x4a000000);
1127 if (IS_ERR(s3c_intc[0])) {
f44ddba3
HS		 1128 pr_err("irq: could not create main interrupt controller\n");
1129 return;
1130 }
6b628917 1131
658dc8fb
HS		 1132 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1133 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1134 s3c_intc[0], 0x4a000018);
6b628917 1135}
6b628917 1136#endif
Linux kernel - Deliverables
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