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60dbd768 AB |
1 | /* |
2 | * interrupt controller support for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/init.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/irq.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/irqdomain.h> | |
15 | #include <linux/syscore_ops.h> | |
16 | #include <asm/mach/irq.h> | |
17 | #include <asm/exception.h> | |
18 | #include "irqchip.h" | |
19 | ||
20 | #define SIRFSOC_INT_RISC_MASK0 0x0018 | |
21 | #define SIRFSOC_INT_RISC_MASK1 0x001C | |
22 | #define SIRFSOC_INT_RISC_LEVEL0 0x0020 | |
23 | #define SIRFSOC_INT_RISC_LEVEL1 0x0024 | |
24 | #define SIRFSOC_INIT_IRQ_ID 0x0038 | |
25 | ||
29eb51a7 | 26 | #define SIRFSOC_NUM_IRQS 64 |
60dbd768 AB |
27 | |
28 | static struct irq_domain *sirfsoc_irqdomain; | |
29 | ||
30 | static __init void | |
31 | sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | |
32 | { | |
33 | struct irq_chip_generic *gc; | |
34 | struct irq_chip_type *ct; | |
29eb51a7 BS |
35 | int ret; |
36 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
a87010ef | 37 | unsigned int set = IRQ_LEVEL; |
60dbd768 | 38 | |
29eb51a7 | 39 | ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc", |
a87010ef | 40 | handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE); |
60dbd768 | 41 | |
29eb51a7 BS |
42 | gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start); |
43 | gc->reg_base = base; | |
44 | ct = gc->chip_types; | |
60dbd768 AB |
45 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
46 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
47 | ct->regs.mask = SIRFSOC_INT_RISC_MASK0; | |
60dbd768 AB |
48 | } |
49 | ||
8783dd3a | 50 | static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) |
60dbd768 AB |
51 | { |
52 | void __iomem *base = sirfsoc_irqdomain->host_data; | |
53 | u32 irqstat, irqnr; | |
54 | ||
55 | irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); | |
56 | irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff); | |
57 | ||
58 | handle_IRQ(irqnr, regs); | |
59 | } | |
60 | ||
61 | static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent) | |
62 | { | |
63 | void __iomem *base = of_iomap(np, 0); | |
64 | if (!base) | |
65 | panic("unable to map intc cpu registers\n"); | |
66 | ||
29eb51a7 BS |
67 | sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS, |
68 | &irq_generic_chip_ops, base); | |
60dbd768 AB |
69 | |
70 | sirfsoc_alloc_gc(base, 0, 32); | |
71 | sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); | |
72 | ||
73 | writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); | |
74 | writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); | |
75 | ||
76 | writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); | |
77 | writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); | |
78 | ||
79 | set_handle_irq(sirfsoc_handle_irq); | |
80 | ||
81 | return 0; | |
82 | } | |
83 | IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init); | |
84 | ||
85 | struct sirfsoc_irq_status { | |
86 | u32 mask0; | |
87 | u32 mask1; | |
88 | u32 level0; | |
89 | u32 level1; | |
90 | }; | |
91 | ||
92 | static struct sirfsoc_irq_status sirfsoc_irq_st; | |
93 | ||
94 | static int sirfsoc_irq_suspend(void) | |
95 | { | |
96 | void __iomem *base = sirfsoc_irqdomain->host_data; | |
97 | ||
98 | sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); | |
99 | sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); | |
100 | sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); | |
101 | sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | static void sirfsoc_irq_resume(void) | |
107 | { | |
108 | void __iomem *base = sirfsoc_irqdomain->host_data; | |
109 | ||
110 | writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); | |
111 | writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); | |
112 | writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); | |
113 | writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); | |
114 | } | |
115 | ||
116 | static struct syscore_ops sirfsoc_irq_syscore_ops = { | |
117 | .suspend = sirfsoc_irq_suspend, | |
118 | .resume = sirfsoc_irq_resume, | |
119 | }; | |
120 | ||
121 | static int __init sirfsoc_irq_pm_init(void) | |
122 | { | |
123 | if (!sirfsoc_irqdomain) | |
124 | return 0; | |
125 | ||
126 | register_syscore_ops(&sirfsoc_irq_syscore_ops); | |
127 | return 0; | |
128 | } | |
129 | device_initcall(sirfsoc_irq_pm_init); |