Commit | Line | Data |
---|---|---|
c41b16f8 RK |
1 | /* |
2 | * Support for Versatile FPGA-based IRQ controllers | |
3 | */ | |
3a6ca8c5 | 4 | #include <linux/bitops.h> |
c41b16f8 RK |
5 | #include <linux/irq.h> |
6 | #include <linux/io.h> | |
2389d501 | 7 | #include <linux/irqchip/versatile-fpga.h> |
3108e6ab LW |
8 | #include <linux/irqdomain.h> |
9 | #include <linux/module.h> | |
9bc15031 LW |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | |
bdd272cb | 12 | #include <linux/of_irq.h> |
c41b16f8 | 13 | |
3108e6ab | 14 | #include <asm/exception.h> |
c41b16f8 | 15 | #include <asm/mach/irq.h> |
c41b16f8 RK |
16 | |
17 | #define IRQ_STATUS 0x00 | |
18 | #define IRQ_RAW_STATUS 0x04 | |
19 | #define IRQ_ENABLE_SET 0x08 | |
20 | #define IRQ_ENABLE_CLEAR 0x0c | |
9bc15031 LW |
21 | #define INT_SOFT_SET 0x10 |
22 | #define INT_SOFT_CLEAR 0x14 | |
23 | #define FIQ_STATUS 0x20 | |
24 | #define FIQ_RAW_STATUS 0x24 | |
25 | #define FIQ_ENABLE 0x28 | |
26 | #define FIQ_ENABLE_SET 0x28 | |
27 | #define FIQ_ENABLE_CLEAR 0x2C | |
c41b16f8 | 28 | |
3108e6ab LW |
29 | /** |
30 | * struct fpga_irq_data - irq data container for the FPGA IRQ controller | |
31 | * @base: memory offset in virtual memory | |
3108e6ab LW |
32 | * @chip: chip container for this instance |
33 | * @domain: IRQ domain for this instance | |
34 | * @valid: mask for valid IRQs on this controller | |
35 | * @used_irqs: number of active IRQs on this controller | |
36 | */ | |
37 | struct fpga_irq_data { | |
38 | void __iomem *base; | |
3108e6ab LW |
39 | struct irq_chip chip; |
40 | u32 valid; | |
41 | struct irq_domain *domain; | |
42 | u8 used_irqs; | |
43 | }; | |
44 | ||
45 | /* we cannot allocate memory when the controllers are initially registered */ | |
2389d501 | 46 | static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR]; |
3108e6ab LW |
47 | static int fpga_irq_id; |
48 | ||
c41b16f8 RK |
49 | static void fpga_irq_mask(struct irq_data *d) |
50 | { | |
51 | struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); | |
3108e6ab | 52 | u32 mask = 1 << d->hwirq; |
c41b16f8 RK |
53 | |
54 | writel(mask, f->base + IRQ_ENABLE_CLEAR); | |
55 | } | |
56 | ||
57 | static void fpga_irq_unmask(struct irq_data *d) | |
58 | { | |
59 | struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); | |
3108e6ab | 60 | u32 mask = 1 << d->hwirq; |
c41b16f8 RK |
61 | |
62 | writel(mask, f->base + IRQ_ENABLE_SET); | |
63 | } | |
64 | ||
65 | static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) | |
66 | { | |
6845664a | 67 | struct fpga_irq_data *f = irq_desc_get_handler_data(desc); |
c41b16f8 RK |
68 | u32 status = readl(f->base + IRQ_STATUS); |
69 | ||
70 | if (status == 0) { | |
71 | do_bad_IRQ(irq, desc); | |
72 | return; | |
73 | } | |
74 | ||
75 | do { | |
76 | irq = ffs(status) - 1; | |
77 | status &= ~(1 << irq); | |
3108e6ab | 78 | generic_handle_irq(irq_find_mapping(f->domain, irq)); |
c41b16f8 RK |
79 | } while (status); |
80 | } | |
81 | ||
3108e6ab LW |
82 | /* |
83 | * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero | |
84 | * if we've handled at least one interrupt. This does a single read of the | |
85 | * status register and handles all interrupts in order from LSB first. | |
86 | */ | |
87 | static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs) | |
88 | { | |
89 | int handled = 0; | |
90 | int irq; | |
91 | u32 status; | |
92 | ||
93 | while ((status = readl(f->base + IRQ_STATUS))) { | |
94 | irq = ffs(status) - 1; | |
95 | handle_IRQ(irq_find_mapping(f->domain, irq), regs); | |
96 | handled = 1; | |
97 | } | |
98 | ||
99 | return handled; | |
100 | } | |
101 | ||
102 | /* | |
103 | * Keep iterating over all registered FPGA IRQ controllers until there are | |
104 | * no pending interrupts. | |
105 | */ | |
106 | asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs) | |
c41b16f8 | 107 | { |
3108e6ab | 108 | int i, handled; |
c41b16f8 | 109 | |
3108e6ab LW |
110 | do { |
111 | for (i = 0, handled = 0; i < fpga_irq_id; ++i) | |
112 | handled |= handle_one_fpga(&fpga_irq_devices[i], regs); | |
113 | } while (handled); | |
114 | } | |
115 | ||
116 | static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
117 | irq_hw_number_t hwirq) | |
118 | { | |
119 | struct fpga_irq_data *f = d->host_data; | |
120 | ||
121 | /* Skip invalid IRQs, only register handlers for the real ones */ | |
3a6ca8c5 | 122 | if (!(f->valid & BIT(hwirq))) |
d94ea3f6 | 123 | return -EPERM; |
3108e6ab LW |
124 | irq_set_chip_data(irq, f); |
125 | irq_set_chip_and_handler(irq, &f->chip, | |
126 | handle_level_irq); | |
127 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
3108e6ab LW |
128 | return 0; |
129 | } | |
130 | ||
131 | static struct irq_domain_ops fpga_irqdomain_ops = { | |
132 | .map = fpga_irqdomain_map, | |
133 | .xlate = irq_domain_xlate_onetwocell, | |
134 | }; | |
135 | ||
3a6ca8c5 LW |
136 | void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, |
137 | int parent_irq, u32 valid, struct device_node *node) | |
138 | { | |
3108e6ab | 139 | struct fpga_irq_data *f; |
3a6ca8c5 | 140 | int i; |
3108e6ab LW |
141 | |
142 | if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) { | |
e6423f8b | 143 | pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__); |
3a6ca8c5 | 144 | return; |
3108e6ab | 145 | } |
3108e6ab LW |
146 | f = &fpga_irq_devices[fpga_irq_id]; |
147 | f->base = base; | |
3108e6ab | 148 | f->chip.name = name; |
c41b16f8 RK |
149 | f->chip.irq_ack = fpga_irq_mask; |
150 | f->chip.irq_mask = fpga_irq_mask; | |
151 | f->chip.irq_unmask = fpga_irq_unmask; | |
3108e6ab | 152 | f->valid = valid; |
c41b16f8 RK |
153 | |
154 | if (parent_irq != -1) { | |
6845664a TG |
155 | irq_set_handler_data(parent_irq, f); |
156 | irq_set_chained_handler(parent_irq, fpga_irq_handle); | |
c41b16f8 RK |
157 | } |
158 | ||
3a6ca8c5 LW |
159 | /* This will also allocate irq descriptors */ |
160 | f->domain = irq_domain_add_simple(node, fls(valid), irq_start, | |
3108e6ab | 161 | &fpga_irqdomain_ops, f); |
3a6ca8c5 LW |
162 | |
163 | /* This will allocate all valid descriptors in the linear case */ | |
164 | for (i = 0; i < fls(valid); i++) | |
165 | if (valid & BIT(i)) { | |
166 | if (!irq_start) | |
167 | irq_create_mapping(f->domain, i); | |
168 | f->used_irqs++; | |
169 | } | |
170 | ||
bdd272cb | 171 | pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs", |
3108e6ab | 172 | fpga_irq_id, name, base, f->used_irqs); |
bdd272cb LW |
173 | if (parent_irq != -1) |
174 | pr_cont(", parent IRQ: %d\n", parent_irq); | |
175 | else | |
176 | pr_cont("\n"); | |
3a6ca8c5 LW |
177 | |
178 | fpga_irq_id++; | |
9bc15031 | 179 | } |
c41b16f8 | 180 | |
9bc15031 LW |
181 | #ifdef CONFIG_OF |
182 | int __init fpga_irq_of_init(struct device_node *node, | |
183 | struct device_node *parent) | |
184 | { | |
9bc15031 LW |
185 | void __iomem *base; |
186 | u32 clear_mask; | |
187 | u32 valid_mask; | |
bdd272cb | 188 | int parent_irq; |
9bc15031 LW |
189 | |
190 | if (WARN_ON(!node)) | |
191 | return -ENODEV; | |
192 | ||
193 | base = of_iomap(node, 0); | |
194 | WARN(!base, "unable to map fpga irq registers\n"); | |
195 | ||
196 | if (of_property_read_u32(node, "clear-mask", &clear_mask)) | |
197 | clear_mask = 0; | |
198 | ||
199 | if (of_property_read_u32(node, "valid-mask", &valid_mask)) | |
200 | valid_mask = 0; | |
201 | ||
bdd272cb LW |
202 | /* Some chips are cascaded from a parent IRQ */ |
203 | parent_irq = irq_of_parse_and_map(node, 0); | |
204 | if (!parent_irq) | |
205 | parent_irq = -1; | |
206 | ||
207 | fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); | |
9bc15031 LW |
208 | |
209 | writel(clear_mask, base + IRQ_ENABLE_CLEAR); | |
210 | writel(clear_mask, base + FIQ_ENABLE_CLEAR); | |
211 | ||
9bc15031 | 212 | return 0; |
c41b16f8 | 213 | } |
9bc15031 | 214 | #endif |