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fa0fe48f RK |
1 | /* |
2 | * linux/arch/arm/common/vic.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
bb06b737 | 21 | |
f9b28ccb | 22 | #include <linux/export.h> |
fa0fe48f RK |
23 | #include <linux/init.h> |
24 | #include <linux/list.h> | |
fced80c7 | 25 | #include <linux/io.h> |
bc895b59 | 26 | #include <linux/irq.h> |
f9b28ccb JI |
27 | #include <linux/irqdomain.h> |
28 | #include <linux/of.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
328f5cc3 | 31 | #include <linux/syscore_ops.h> |
59fcf48f | 32 | #include <linux/device.h> |
f17a1f06 | 33 | #include <linux/amba/bus.h> |
9e47b8bf | 34 | #include <linux/irqchip/arm-vic.h> |
fa0fe48f | 35 | |
1558368e | 36 | #include <asm/exception.h> |
f36a3bb1 | 37 | #include <asm/irq.h> |
fa0fe48f | 38 | |
44430ec0 RH |
39 | #include "irqchip.h" |
40 | ||
cf21af54 RH |
41 | #define VIC_IRQ_STATUS 0x00 |
42 | #define VIC_FIQ_STATUS 0x04 | |
43 | #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ | |
44 | #define VIC_INT_SOFT 0x18 | |
45 | #define VIC_INT_SOFT_CLEAR 0x1c | |
46 | #define VIC_PROTECT 0x20 | |
47 | #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ | |
48 | #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ | |
49 | ||
50 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ | |
51 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ | |
52 | #define VIC_ITCR 0x300 /* VIC test control register */ | |
53 | ||
54 | #define VIC_VECT_CNTL_ENABLE (1 << 5) | |
55 | ||
56 | #define VIC_PL192_VECT_ADDR 0xF00 | |
57 | ||
c07f87f2 BD |
58 | /** |
59 | * struct vic_device - VIC PM device | |
c07f87f2 BD |
60 | * @irq: The IRQ number for the base of the VIC. |
61 | * @base: The register base for the VIC. | |
ce94df9c | 62 | * @valid_sources: A bitmask of valid interrupts |
c07f87f2 BD |
63 | * @resume_sources: A bitmask of interrupts for resume. |
64 | * @resume_irqs: The IRQs enabled for resume. | |
65 | * @int_select: Save for VIC_INT_SELECT. | |
66 | * @int_enable: Save for VIC_INT_ENABLE. | |
67 | * @soft_int: Save for VIC_INT_SOFT. | |
68 | * @protect: Save for VIC_PROTECT. | |
f9b28ccb | 69 | * @domain: The IRQ domain for the VIC. |
c07f87f2 BD |
70 | */ |
71 | struct vic_device { | |
c07f87f2 BD |
72 | void __iomem *base; |
73 | int irq; | |
ce94df9c | 74 | u32 valid_sources; |
c07f87f2 BD |
75 | u32 resume_sources; |
76 | u32 resume_irqs; | |
77 | u32 int_select; | |
78 | u32 int_enable; | |
79 | u32 soft_int; | |
80 | u32 protect; | |
75294957 | 81 | struct irq_domain *domain; |
c07f87f2 BD |
82 | }; |
83 | ||
84 | /* we cannot allocate memory when VICs are initially registered */ | |
85 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; | |
86 | ||
bb06b737 | 87 | static int vic_id; |
c07f87f2 | 88 | |
a0368029 RH |
89 | static void vic_handle_irq(struct pt_regs *regs); |
90 | ||
bb06b737 HS |
91 | /** |
92 | * vic_init2 - common initialisation code | |
93 | * @base: Base of the VIC. | |
94 | * | |
b595076a | 95 | * Common initialisation code for registration |
bb06b737 HS |
96 | * and resume. |
97 | */ | |
98 | static void vic_init2(void __iomem *base) | |
99 | { | |
100 | int i; | |
101 | ||
102 | for (i = 0; i < 16; i++) { | |
103 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
104 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | |
105 | } | |
106 | ||
107 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
108 | } | |
c07f87f2 | 109 | |
328f5cc3 RW |
110 | #ifdef CONFIG_PM |
111 | static void resume_one_vic(struct vic_device *vic) | |
c07f87f2 | 112 | { |
c07f87f2 BD |
113 | void __iomem *base = vic->base; |
114 | ||
115 | printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); | |
116 | ||
117 | /* re-initialise static settings */ | |
118 | vic_init2(base); | |
119 | ||
120 | writel(vic->int_select, base + VIC_INT_SELECT); | |
121 | writel(vic->protect, base + VIC_PROTECT); | |
122 | ||
123 | /* set the enabled ints and then clear the non-enabled */ | |
124 | writel(vic->int_enable, base + VIC_INT_ENABLE); | |
125 | writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); | |
126 | ||
127 | /* and the same for the soft-int register */ | |
128 | ||
129 | writel(vic->soft_int, base + VIC_INT_SOFT); | |
130 | writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); | |
328f5cc3 | 131 | } |
c07f87f2 | 132 | |
328f5cc3 RW |
133 | static void vic_resume(void) |
134 | { | |
135 | int id; | |
136 | ||
137 | for (id = vic_id - 1; id >= 0; id--) | |
138 | resume_one_vic(vic_devices + id); | |
c07f87f2 BD |
139 | } |
140 | ||
328f5cc3 | 141 | static void suspend_one_vic(struct vic_device *vic) |
c07f87f2 | 142 | { |
c07f87f2 BD |
143 | void __iomem *base = vic->base; |
144 | ||
145 | printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); | |
146 | ||
147 | vic->int_select = readl(base + VIC_INT_SELECT); | |
148 | vic->int_enable = readl(base + VIC_INT_ENABLE); | |
149 | vic->soft_int = readl(base + VIC_INT_SOFT); | |
150 | vic->protect = readl(base + VIC_PROTECT); | |
151 | ||
152 | /* set the interrupts (if any) that are used for | |
153 | * resuming the system */ | |
154 | ||
155 | writel(vic->resume_irqs, base + VIC_INT_ENABLE); | |
156 | writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); | |
328f5cc3 RW |
157 | } |
158 | ||
159 | static int vic_suspend(void) | |
160 | { | |
161 | int id; | |
162 | ||
163 | for (id = 0; id < vic_id; id++) | |
164 | suspend_one_vic(vic_devices + id); | |
c07f87f2 BD |
165 | |
166 | return 0; | |
167 | } | |
168 | ||
328f5cc3 RW |
169 | struct syscore_ops vic_syscore_ops = { |
170 | .suspend = vic_suspend, | |
171 | .resume = vic_resume, | |
c07f87f2 BD |
172 | }; |
173 | ||
c07f87f2 BD |
174 | /** |
175 | * vic_pm_init - initicall to register VIC pm | |
176 | * | |
177 | * This is called via late_initcall() to register | |
178 | * the resources for the VICs due to the early | |
179 | * nature of the VIC's registration. | |
180 | */ | |
181 | static int __init vic_pm_init(void) | |
182 | { | |
328f5cc3 RW |
183 | if (vic_id > 0) |
184 | register_syscore_ops(&vic_syscore_ops); | |
c07f87f2 BD |
185 | |
186 | return 0; | |
187 | } | |
c07f87f2 | 188 | late_initcall(vic_pm_init); |
f9b28ccb | 189 | #endif /* CONFIG_PM */ |
c07f87f2 | 190 | |
ce94df9c LW |
191 | static struct irq_chip vic_chip; |
192 | ||
193 | static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
194 | irq_hw_number_t hwirq) | |
195 | { | |
196 | struct vic_device *v = d->host_data; | |
197 | ||
198 | /* Skip invalid IRQs, only register handlers for the real ones */ | |
199 | if (!(v->valid_sources & (1 << hwirq))) | |
d94ea3f6 | 200 | return -EPERM; |
ce94df9c LW |
201 | irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); |
202 | irq_set_chip_data(irq, v->base); | |
203 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
204 | return 0; | |
205 | } | |
206 | ||
a0368029 RH |
207 | /* |
208 | * Handle each interrupt in a single VIC. Returns non-zero if we've | |
209 | * handled at least one interrupt. This reads the status register | |
210 | * before handling each interrupt, which is necessary given that | |
211 | * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. | |
212 | */ | |
213 | static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) | |
214 | { | |
215 | u32 stat, irq; | |
216 | int handled = 0; | |
217 | ||
218 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { | |
219 | irq = ffs(stat) - 1; | |
220 | handle_IRQ(irq_find_mapping(vic->domain, irq), regs); | |
221 | handled = 1; | |
222 | } | |
223 | ||
224 | return handled; | |
225 | } | |
226 | ||
227 | /* | |
228 | * Keep iterating over all registered VIC's until there are no pending | |
229 | * interrupts. | |
230 | */ | |
231 | static asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs) | |
232 | { | |
233 | int i, handled; | |
234 | ||
235 | do { | |
236 | for (i = 0, handled = 0; i < vic_id; ++i) | |
237 | handled |= handle_one_vic(&vic_devices[i], regs); | |
238 | } while (handled); | |
239 | } | |
240 | ||
ce94df9c LW |
241 | static struct irq_domain_ops vic_irqdomain_ops = { |
242 | .map = vic_irqdomain_map, | |
243 | .xlate = irq_domain_xlate_onetwocell, | |
244 | }; | |
245 | ||
bb06b737 | 246 | /** |
f9b28ccb | 247 | * vic_register() - Register a VIC. |
bb06b737 HS |
248 | * @base: The base address of the VIC. |
249 | * @irq: The base IRQ for the VIC. | |
fa943bed | 250 | * @valid_sources: bitmask of valid interrupts |
bb06b737 | 251 | * @resume_sources: bitmask of interrupts allowed for resume sources. |
f9b28ccb | 252 | * @node: The device tree node associated with the VIC. |
bb06b737 HS |
253 | * |
254 | * Register the VIC with the system device tree so that it can be notified | |
255 | * of suspend and resume requests and ensure that the correct actions are | |
256 | * taken to re-instate the settings on resume. | |
f9b28ccb JI |
257 | * |
258 | * This also configures the IRQ domain for the VIC. | |
bb06b737 | 259 | */ |
f9b28ccb | 260 | static void __init vic_register(void __iomem *base, unsigned int irq, |
fa943bed LW |
261 | u32 valid_sources, u32 resume_sources, |
262 | struct device_node *node) | |
bb06b737 HS |
263 | { |
264 | struct vic_device *v; | |
5ced33bc | 265 | int i; |
bb06b737 | 266 | |
f9b28ccb | 267 | if (vic_id >= ARRAY_SIZE(vic_devices)) { |
bb06b737 | 268 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); |
f9b28ccb | 269 | return; |
bb06b737 | 270 | } |
f9b28ccb JI |
271 | |
272 | v = &vic_devices[vic_id]; | |
273 | v->base = base; | |
ce94df9c | 274 | v->valid_sources = valid_sources; |
f9b28ccb | 275 | v->resume_sources = resume_sources; |
7fb7d8ae | 276 | set_handle_irq(vic_handle_irq); |
f9b28ccb | 277 | vic_id++; |
07c9249f | 278 | v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, |
fa943bed | 279 | &vic_irqdomain_ops, v); |
5ced33bc LW |
280 | /* create an IRQ mapping for each valid IRQ */ |
281 | for (i = 0; i < fls(valid_sources); i++) | |
282 | if (valid_sources & (1 << i)) | |
283 | irq_create_mapping(v->domain, i); | |
3b4df9db LW |
284 | /* If no base IRQ was passed, figure out our allocated base */ |
285 | if (irq) | |
286 | v->irq = irq; | |
287 | else | |
288 | v->irq = irq_find_mapping(v->domain, 0); | |
bb06b737 | 289 | } |
bb06b737 | 290 | |
f013c98d | 291 | static void vic_ack_irq(struct irq_data *d) |
bb06b737 | 292 | { |
f013c98d | 293 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 294 | unsigned int irq = d->hwirq; |
bb06b737 HS |
295 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
296 | /* moreover, clear the soft-triggered, in case it was the reason */ | |
297 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | |
298 | } | |
299 | ||
f013c98d | 300 | static void vic_mask_irq(struct irq_data *d) |
bb06b737 | 301 | { |
f013c98d | 302 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 303 | unsigned int irq = d->hwirq; |
bb06b737 HS |
304 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
305 | } | |
306 | ||
f013c98d | 307 | static void vic_unmask_irq(struct irq_data *d) |
bb06b737 | 308 | { |
f013c98d | 309 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 310 | unsigned int irq = d->hwirq; |
bb06b737 HS |
311 | writel(1 << irq, base + VIC_INT_ENABLE); |
312 | } | |
313 | ||
314 | #if defined(CONFIG_PM) | |
c07f87f2 BD |
315 | static struct vic_device *vic_from_irq(unsigned int irq) |
316 | { | |
317 | struct vic_device *v = vic_devices; | |
318 | unsigned int base_irq = irq & ~31; | |
319 | int id; | |
320 | ||
321 | for (id = 0; id < vic_id; id++, v++) { | |
322 | if (v->irq == base_irq) | |
323 | return v; | |
324 | } | |
325 | ||
326 | return NULL; | |
327 | } | |
328 | ||
f013c98d | 329 | static int vic_set_wake(struct irq_data *d, unsigned int on) |
c07f87f2 | 330 | { |
f013c98d | 331 | struct vic_device *v = vic_from_irq(d->irq); |
f9b28ccb | 332 | unsigned int off = d->hwirq; |
3f1a567d | 333 | u32 bit = 1 << off; |
c07f87f2 BD |
334 | |
335 | if (!v) | |
336 | return -EINVAL; | |
337 | ||
3f1a567d BD |
338 | if (!(bit & v->resume_sources)) |
339 | return -EINVAL; | |
340 | ||
c07f87f2 | 341 | if (on) |
3f1a567d | 342 | v->resume_irqs |= bit; |
c07f87f2 | 343 | else |
3f1a567d | 344 | v->resume_irqs &= ~bit; |
c07f87f2 BD |
345 | |
346 | return 0; | |
347 | } | |
c07f87f2 | 348 | #else |
c07f87f2 BD |
349 | #define vic_set_wake NULL |
350 | #endif /* CONFIG_PM */ | |
351 | ||
38c677cb | 352 | static struct irq_chip vic_chip = { |
b0c4c898 | 353 | .name = "VIC", |
f013c98d LB |
354 | .irq_ack = vic_ack_irq, |
355 | .irq_mask = vic_mask_irq, | |
356 | .irq_unmask = vic_unmask_irq, | |
357 | .irq_set_wake = vic_set_wake, | |
fa0fe48f RK |
358 | }; |
359 | ||
b0c4c898 HS |
360 | static void __init vic_disable(void __iomem *base) |
361 | { | |
362 | writel(0, base + VIC_INT_SELECT); | |
363 | writel(0, base + VIC_INT_ENABLE); | |
364 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | |
b0c4c898 HS |
365 | writel(0, base + VIC_ITCR); |
366 | writel(~0, base + VIC_INT_SOFT_CLEAR); | |
367 | } | |
368 | ||
369 | static void __init vic_clear_interrupts(void __iomem *base) | |
370 | { | |
371 | unsigned int i; | |
372 | ||
373 | writel(0, base + VIC_PL190_VECT_ADDR); | |
374 | for (i = 0; i < 19; i++) { | |
375 | unsigned int value; | |
376 | ||
377 | value = readl(base + VIC_PL190_VECT_ADDR); | |
378 | writel(value, base + VIC_PL190_VECT_ADDR); | |
379 | } | |
380 | } | |
381 | ||
bb06b737 HS |
382 | /* |
383 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | |
384 | * The original cell has 32 interrupts, while the modified one has 64, | |
385 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | |
386 | * the probe function is called twice, with base set to offset 000 | |
387 | * and 020 within the page. We call this "second block". | |
388 | */ | |
389 | static void __init vic_init_st(void __iomem *base, unsigned int irq_start, | |
ad622671 | 390 | u32 vic_sources, struct device_node *node) |
bb06b737 HS |
391 | { |
392 | unsigned int i; | |
393 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | |
394 | ||
395 | /* Disable all interrupts initially. */ | |
b0c4c898 | 396 | vic_disable(base); |
bb06b737 HS |
397 | |
398 | /* | |
399 | * Make sure we clear all existing interrupts. The vector registers | |
400 | * in this cell are after the second block of general registers, | |
401 | * so we can address them using standard offsets, but only from | |
402 | * the second base address, which is 0x20 in the page | |
403 | */ | |
404 | if (vic_2nd_block) { | |
b0c4c898 | 405 | vic_clear_interrupts(base); |
bb06b737 | 406 | |
bb06b737 HS |
407 | /* ST has 16 vectors as well, but we don't enable them by now */ |
408 | for (i = 0; i < 16; i++) { | |
409 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
410 | writel(0, reg); | |
411 | } | |
412 | ||
413 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
414 | } | |
415 | ||
fa943bed | 416 | vic_register(base, irq_start, vic_sources, 0, node); |
bb06b737 | 417 | } |
87e8824b | 418 | |
07c9249f | 419 | void __init __vic_init(void __iomem *base, int irq_start, |
f9b28ccb JI |
420 | u32 vic_sources, u32 resume_sources, |
421 | struct device_node *node) | |
fa0fe48f RK |
422 | { |
423 | unsigned int i; | |
87e8824b | 424 | u32 cellid = 0; |
f17a1f06 | 425 | enum amba_vendor vendor; |
87e8824b AR |
426 | |
427 | /* Identify which VIC cell this one is, by reading the ID */ | |
428 | for (i = 0; i < 4; i++) { | |
d4f3add2 AB |
429 | void __iomem *addr; |
430 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | |
87e8824b AR |
431 | cellid |= (readl(addr) & 0xff) << (8 * i); |
432 | } | |
433 | vendor = (cellid >> 12) & 0xff; | |
434 | printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", | |
435 | base, cellid, vendor); | |
436 | ||
437 | switch(vendor) { | |
f17a1f06 | 438 | case AMBA_VENDOR_ST: |
ad622671 | 439 | vic_init_st(base, irq_start, vic_sources, node); |
87e8824b AR |
440 | return; |
441 | default: | |
442 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); | |
443 | /* fall through */ | |
f17a1f06 | 444 | case AMBA_VENDOR_ARM: |
87e8824b AR |
445 | break; |
446 | } | |
fa0fe48f | 447 | |
fa0fe48f | 448 | /* Disable all interrupts initially. */ |
b0c4c898 | 449 | vic_disable(base); |
fa0fe48f | 450 | |
b0c4c898 HS |
451 | /* Make sure we clear all existing interrupts */ |
452 | vic_clear_interrupts(base); | |
fa0fe48f | 453 | |
c07f87f2 | 454 | vic_init2(base); |
fa0fe48f | 455 | |
fa943bed | 456 | vic_register(base, irq_start, vic_sources, resume_sources, node); |
f9b28ccb JI |
457 | } |
458 | ||
459 | /** | |
460 | * vic_init() - initialise a vectored interrupt controller | |
461 | * @base: iomem base address | |
462 | * @irq_start: starting interrupt number, must be muliple of 32 | |
463 | * @vic_sources: bitmask of interrupt sources to allow | |
464 | * @resume_sources: bitmask of interrupt sources to allow for resume | |
465 | */ | |
466 | void __init vic_init(void __iomem *base, unsigned int irq_start, | |
467 | u32 vic_sources, u32 resume_sources) | |
468 | { | |
469 | __vic_init(base, irq_start, vic_sources, resume_sources, NULL); | |
470 | } | |
471 | ||
472 | #ifdef CONFIG_OF | |
473 | int __init vic_of_init(struct device_node *node, struct device_node *parent) | |
474 | { | |
475 | void __iomem *regs; | |
81e9c179 TF |
476 | u32 interrupt_mask = ~0; |
477 | u32 wakeup_mask = ~0; | |
f9b28ccb JI |
478 | |
479 | if (WARN(parent, "non-root VICs are not supported")) | |
480 | return -EINVAL; | |
481 | ||
482 | regs = of_iomap(node, 0); | |
483 | if (WARN_ON(!regs)) | |
484 | return -EIO; | |
485 | ||
81e9c179 TF |
486 | of_property_read_u32(node, "valid-mask", &interrupt_mask); |
487 | of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask); | |
488 | ||
07c9249f | 489 | /* |
5ced33bc | 490 | * Passing 0 as first IRQ makes the simple domain allocate descriptors |
07c9249f | 491 | */ |
81e9c179 | 492 | __vic_init(regs, 0, interrupt_mask, wakeup_mask, node); |
f9b28ccb JI |
493 | |
494 | return 0; | |
fa0fe48f | 495 | } |
44430ec0 RH |
496 | IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init); |
497 | IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init); | |
498 | IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init); | |
f9b28ccb | 499 | #endif /* CONFIG OF */ |