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fa0fe48f RK |
1 | /* |
2 | * linux/arch/arm/common/vic.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
bb06b737 | 21 | |
f9b28ccb | 22 | #include <linux/export.h> |
fa0fe48f RK |
23 | #include <linux/init.h> |
24 | #include <linux/list.h> | |
fced80c7 | 25 | #include <linux/io.h> |
bc895b59 | 26 | #include <linux/irq.h> |
41a83e06 | 27 | #include <linux/irqchip.h> |
f6da9fe4 | 28 | #include <linux/irqchip/chained_irq.h> |
f9b28ccb JI |
29 | #include <linux/irqdomain.h> |
30 | #include <linux/of.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
328f5cc3 | 33 | #include <linux/syscore_ops.h> |
59fcf48f | 34 | #include <linux/device.h> |
f17a1f06 | 35 | #include <linux/amba/bus.h> |
9e47b8bf | 36 | #include <linux/irqchip/arm-vic.h> |
fa0fe48f | 37 | |
1558368e | 38 | #include <asm/exception.h> |
f36a3bb1 | 39 | #include <asm/irq.h> |
fa0fe48f | 40 | |
cf21af54 RH |
41 | #define VIC_IRQ_STATUS 0x00 |
42 | #define VIC_FIQ_STATUS 0x04 | |
43 | #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ | |
44 | #define VIC_INT_SOFT 0x18 | |
45 | #define VIC_INT_SOFT_CLEAR 0x1c | |
46 | #define VIC_PROTECT 0x20 | |
47 | #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ | |
48 | #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ | |
49 | ||
50 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ | |
51 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ | |
52 | #define VIC_ITCR 0x300 /* VIC test control register */ | |
53 | ||
54 | #define VIC_VECT_CNTL_ENABLE (1 << 5) | |
55 | ||
56 | #define VIC_PL192_VECT_ADDR 0xF00 | |
57 | ||
c07f87f2 BD |
58 | /** |
59 | * struct vic_device - VIC PM device | |
e641b987 | 60 | * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0. |
c07f87f2 BD |
61 | * @irq: The IRQ number for the base of the VIC. |
62 | * @base: The register base for the VIC. | |
ce94df9c | 63 | * @valid_sources: A bitmask of valid interrupts |
c07f87f2 BD |
64 | * @resume_sources: A bitmask of interrupts for resume. |
65 | * @resume_irqs: The IRQs enabled for resume. | |
66 | * @int_select: Save for VIC_INT_SELECT. | |
67 | * @int_enable: Save for VIC_INT_ENABLE. | |
68 | * @soft_int: Save for VIC_INT_SOFT. | |
69 | * @protect: Save for VIC_PROTECT. | |
f9b28ccb | 70 | * @domain: The IRQ domain for the VIC. |
c07f87f2 BD |
71 | */ |
72 | struct vic_device { | |
c07f87f2 BD |
73 | void __iomem *base; |
74 | int irq; | |
ce94df9c | 75 | u32 valid_sources; |
c07f87f2 BD |
76 | u32 resume_sources; |
77 | u32 resume_irqs; | |
78 | u32 int_select; | |
79 | u32 int_enable; | |
80 | u32 soft_int; | |
81 | u32 protect; | |
75294957 | 82 | struct irq_domain *domain; |
c07f87f2 BD |
83 | }; |
84 | ||
85 | /* we cannot allocate memory when VICs are initially registered */ | |
86 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; | |
87 | ||
bb06b737 | 88 | static int vic_id; |
c07f87f2 | 89 | |
a0368029 RH |
90 | static void vic_handle_irq(struct pt_regs *regs); |
91 | ||
bb06b737 HS |
92 | /** |
93 | * vic_init2 - common initialisation code | |
94 | * @base: Base of the VIC. | |
95 | * | |
b595076a | 96 | * Common initialisation code for registration |
bb06b737 HS |
97 | * and resume. |
98 | */ | |
99 | static void vic_init2(void __iomem *base) | |
100 | { | |
101 | int i; | |
102 | ||
103 | for (i = 0; i < 16; i++) { | |
104 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
105 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | |
106 | } | |
107 | ||
108 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
109 | } | |
c07f87f2 | 110 | |
328f5cc3 RW |
111 | #ifdef CONFIG_PM |
112 | static void resume_one_vic(struct vic_device *vic) | |
c07f87f2 | 113 | { |
c07f87f2 BD |
114 | void __iomem *base = vic->base; |
115 | ||
116 | printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); | |
117 | ||
118 | /* re-initialise static settings */ | |
119 | vic_init2(base); | |
120 | ||
121 | writel(vic->int_select, base + VIC_INT_SELECT); | |
122 | writel(vic->protect, base + VIC_PROTECT); | |
123 | ||
124 | /* set the enabled ints and then clear the non-enabled */ | |
125 | writel(vic->int_enable, base + VIC_INT_ENABLE); | |
126 | writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); | |
127 | ||
128 | /* and the same for the soft-int register */ | |
129 | ||
130 | writel(vic->soft_int, base + VIC_INT_SOFT); | |
131 | writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); | |
328f5cc3 | 132 | } |
c07f87f2 | 133 | |
328f5cc3 RW |
134 | static void vic_resume(void) |
135 | { | |
136 | int id; | |
137 | ||
138 | for (id = vic_id - 1; id >= 0; id--) | |
139 | resume_one_vic(vic_devices + id); | |
c07f87f2 BD |
140 | } |
141 | ||
328f5cc3 | 142 | static void suspend_one_vic(struct vic_device *vic) |
c07f87f2 | 143 | { |
c07f87f2 BD |
144 | void __iomem *base = vic->base; |
145 | ||
146 | printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); | |
147 | ||
148 | vic->int_select = readl(base + VIC_INT_SELECT); | |
149 | vic->int_enable = readl(base + VIC_INT_ENABLE); | |
150 | vic->soft_int = readl(base + VIC_INT_SOFT); | |
151 | vic->protect = readl(base + VIC_PROTECT); | |
152 | ||
153 | /* set the interrupts (if any) that are used for | |
154 | * resuming the system */ | |
155 | ||
156 | writel(vic->resume_irqs, base + VIC_INT_ENABLE); | |
157 | writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); | |
328f5cc3 RW |
158 | } |
159 | ||
160 | static int vic_suspend(void) | |
161 | { | |
162 | int id; | |
163 | ||
164 | for (id = 0; id < vic_id; id++) | |
165 | suspend_one_vic(vic_devices + id); | |
c07f87f2 BD |
166 | |
167 | return 0; | |
168 | } | |
169 | ||
328f5cc3 RW |
170 | struct syscore_ops vic_syscore_ops = { |
171 | .suspend = vic_suspend, | |
172 | .resume = vic_resume, | |
c07f87f2 BD |
173 | }; |
174 | ||
c07f87f2 BD |
175 | /** |
176 | * vic_pm_init - initicall to register VIC pm | |
177 | * | |
178 | * This is called via late_initcall() to register | |
179 | * the resources for the VICs due to the early | |
180 | * nature of the VIC's registration. | |
181 | */ | |
182 | static int __init vic_pm_init(void) | |
183 | { | |
328f5cc3 RW |
184 | if (vic_id > 0) |
185 | register_syscore_ops(&vic_syscore_ops); | |
c07f87f2 BD |
186 | |
187 | return 0; | |
188 | } | |
c07f87f2 | 189 | late_initcall(vic_pm_init); |
f9b28ccb | 190 | #endif /* CONFIG_PM */ |
c07f87f2 | 191 | |
ce94df9c LW |
192 | static struct irq_chip vic_chip; |
193 | ||
194 | static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
195 | irq_hw_number_t hwirq) | |
196 | { | |
197 | struct vic_device *v = d->host_data; | |
198 | ||
199 | /* Skip invalid IRQs, only register handlers for the real ones */ | |
200 | if (!(v->valid_sources & (1 << hwirq))) | |
d94ea3f6 | 201 | return -EPERM; |
ce94df9c LW |
202 | irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); |
203 | irq_set_chip_data(irq, v->base); | |
204 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
205 | return 0; | |
206 | } | |
207 | ||
a0368029 RH |
208 | /* |
209 | * Handle each interrupt in a single VIC. Returns non-zero if we've | |
210 | * handled at least one interrupt. This reads the status register | |
211 | * before handling each interrupt, which is necessary given that | |
212 | * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. | |
213 | */ | |
214 | static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) | |
215 | { | |
216 | u32 stat, irq; | |
217 | int handled = 0; | |
218 | ||
219 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { | |
220 | irq = ffs(stat) - 1; | |
0af83b3b | 221 | handle_domain_irq(vic->domain, irq, regs); |
a0368029 RH |
222 | handled = 1; |
223 | } | |
224 | ||
225 | return handled; | |
226 | } | |
227 | ||
e641b987 LW |
228 | static void vic_handle_irq_cascaded(unsigned int irq, struct irq_desc *desc) |
229 | { | |
230 | u32 stat, hwirq; | |
f6da9fe4 | 231 | struct irq_chip *host_chip = irq_desc_get_chip(desc); |
e641b987 LW |
232 | struct vic_device *vic = irq_desc_get_handler_data(desc); |
233 | ||
f6da9fe4 LW |
234 | chained_irq_enter(host_chip, desc); |
235 | ||
e641b987 LW |
236 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { |
237 | hwirq = ffs(stat) - 1; | |
238 | generic_handle_irq(irq_find_mapping(vic->domain, hwirq)); | |
239 | } | |
f6da9fe4 LW |
240 | |
241 | chained_irq_exit(host_chip, desc); | |
e641b987 LW |
242 | } |
243 | ||
a0368029 RH |
244 | /* |
245 | * Keep iterating over all registered VIC's until there are no pending | |
246 | * interrupts. | |
247 | */ | |
8783dd3a | 248 | static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs) |
a0368029 RH |
249 | { |
250 | int i, handled; | |
251 | ||
252 | do { | |
253 | for (i = 0, handled = 0; i < vic_id; ++i) | |
254 | handled |= handle_one_vic(&vic_devices[i], regs); | |
255 | } while (handled); | |
256 | } | |
257 | ||
96009736 | 258 | static const struct irq_domain_ops vic_irqdomain_ops = { |
ce94df9c LW |
259 | .map = vic_irqdomain_map, |
260 | .xlate = irq_domain_xlate_onetwocell, | |
261 | }; | |
262 | ||
bb06b737 | 263 | /** |
f9b28ccb | 264 | * vic_register() - Register a VIC. |
bb06b737 | 265 | * @base: The base address of the VIC. |
e641b987 | 266 | * @parent_irq: The parent IRQ if cascaded, else 0. |
bb06b737 | 267 | * @irq: The base IRQ for the VIC. |
fa943bed | 268 | * @valid_sources: bitmask of valid interrupts |
bb06b737 | 269 | * @resume_sources: bitmask of interrupts allowed for resume sources. |
f9b28ccb | 270 | * @node: The device tree node associated with the VIC. |
bb06b737 HS |
271 | * |
272 | * Register the VIC with the system device tree so that it can be notified | |
273 | * of suspend and resume requests and ensure that the correct actions are | |
274 | * taken to re-instate the settings on resume. | |
f9b28ccb JI |
275 | * |
276 | * This also configures the IRQ domain for the VIC. | |
bb06b737 | 277 | */ |
e641b987 LW |
278 | static void __init vic_register(void __iomem *base, unsigned int parent_irq, |
279 | unsigned int irq, | |
fa943bed LW |
280 | u32 valid_sources, u32 resume_sources, |
281 | struct device_node *node) | |
bb06b737 HS |
282 | { |
283 | struct vic_device *v; | |
5ced33bc | 284 | int i; |
bb06b737 | 285 | |
f9b28ccb | 286 | if (vic_id >= ARRAY_SIZE(vic_devices)) { |
bb06b737 | 287 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); |
f9b28ccb | 288 | return; |
bb06b737 | 289 | } |
f9b28ccb JI |
290 | |
291 | v = &vic_devices[vic_id]; | |
292 | v->base = base; | |
ce94df9c | 293 | v->valid_sources = valid_sources; |
f9b28ccb | 294 | v->resume_sources = resume_sources; |
7fb7d8ae | 295 | set_handle_irq(vic_handle_irq); |
f9b28ccb | 296 | vic_id++; |
e641b987 LW |
297 | |
298 | if (parent_irq) { | |
9f213541 TG |
299 | irq_set_chained_handler_and_data(parent_irq, |
300 | vic_handle_irq_cascaded, v); | |
e641b987 LW |
301 | } |
302 | ||
07c9249f | 303 | v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, |
fa943bed | 304 | &vic_irqdomain_ops, v); |
5ced33bc LW |
305 | /* create an IRQ mapping for each valid IRQ */ |
306 | for (i = 0; i < fls(valid_sources); i++) | |
307 | if (valid_sources & (1 << i)) | |
308 | irq_create_mapping(v->domain, i); | |
3b4df9db LW |
309 | /* If no base IRQ was passed, figure out our allocated base */ |
310 | if (irq) | |
311 | v->irq = irq; | |
312 | else | |
313 | v->irq = irq_find_mapping(v->domain, 0); | |
bb06b737 | 314 | } |
bb06b737 | 315 | |
f013c98d | 316 | static void vic_ack_irq(struct irq_data *d) |
bb06b737 | 317 | { |
f013c98d | 318 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 319 | unsigned int irq = d->hwirq; |
bb06b737 HS |
320 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
321 | /* moreover, clear the soft-triggered, in case it was the reason */ | |
322 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | |
323 | } | |
324 | ||
f013c98d | 325 | static void vic_mask_irq(struct irq_data *d) |
bb06b737 | 326 | { |
f013c98d | 327 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 328 | unsigned int irq = d->hwirq; |
bb06b737 HS |
329 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
330 | } | |
331 | ||
f013c98d | 332 | static void vic_unmask_irq(struct irq_data *d) |
bb06b737 | 333 | { |
f013c98d | 334 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 335 | unsigned int irq = d->hwirq; |
bb06b737 HS |
336 | writel(1 << irq, base + VIC_INT_ENABLE); |
337 | } | |
338 | ||
339 | #if defined(CONFIG_PM) | |
c07f87f2 BD |
340 | static struct vic_device *vic_from_irq(unsigned int irq) |
341 | { | |
342 | struct vic_device *v = vic_devices; | |
343 | unsigned int base_irq = irq & ~31; | |
344 | int id; | |
345 | ||
346 | for (id = 0; id < vic_id; id++, v++) { | |
347 | if (v->irq == base_irq) | |
348 | return v; | |
349 | } | |
350 | ||
351 | return NULL; | |
352 | } | |
353 | ||
f013c98d | 354 | static int vic_set_wake(struct irq_data *d, unsigned int on) |
c07f87f2 | 355 | { |
f013c98d | 356 | struct vic_device *v = vic_from_irq(d->irq); |
f9b28ccb | 357 | unsigned int off = d->hwirq; |
3f1a567d | 358 | u32 bit = 1 << off; |
c07f87f2 BD |
359 | |
360 | if (!v) | |
361 | return -EINVAL; | |
362 | ||
3f1a567d BD |
363 | if (!(bit & v->resume_sources)) |
364 | return -EINVAL; | |
365 | ||
c07f87f2 | 366 | if (on) |
3f1a567d | 367 | v->resume_irqs |= bit; |
c07f87f2 | 368 | else |
3f1a567d | 369 | v->resume_irqs &= ~bit; |
c07f87f2 BD |
370 | |
371 | return 0; | |
372 | } | |
c07f87f2 | 373 | #else |
c07f87f2 BD |
374 | #define vic_set_wake NULL |
375 | #endif /* CONFIG_PM */ | |
376 | ||
38c677cb | 377 | static struct irq_chip vic_chip = { |
b0c4c898 | 378 | .name = "VIC", |
f013c98d LB |
379 | .irq_ack = vic_ack_irq, |
380 | .irq_mask = vic_mask_irq, | |
381 | .irq_unmask = vic_unmask_irq, | |
382 | .irq_set_wake = vic_set_wake, | |
fa0fe48f RK |
383 | }; |
384 | ||
b0c4c898 HS |
385 | static void __init vic_disable(void __iomem *base) |
386 | { | |
387 | writel(0, base + VIC_INT_SELECT); | |
388 | writel(0, base + VIC_INT_ENABLE); | |
389 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | |
b0c4c898 HS |
390 | writel(0, base + VIC_ITCR); |
391 | writel(~0, base + VIC_INT_SOFT_CLEAR); | |
392 | } | |
393 | ||
394 | static void __init vic_clear_interrupts(void __iomem *base) | |
395 | { | |
396 | unsigned int i; | |
397 | ||
398 | writel(0, base + VIC_PL190_VECT_ADDR); | |
399 | for (i = 0; i < 19; i++) { | |
400 | unsigned int value; | |
401 | ||
402 | value = readl(base + VIC_PL190_VECT_ADDR); | |
403 | writel(value, base + VIC_PL190_VECT_ADDR); | |
404 | } | |
405 | } | |
406 | ||
bb06b737 HS |
407 | /* |
408 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | |
409 | * The original cell has 32 interrupts, while the modified one has 64, | |
410 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | |
411 | * the probe function is called twice, with base set to offset 000 | |
412 | * and 020 within the page. We call this "second block". | |
413 | */ | |
414 | static void __init vic_init_st(void __iomem *base, unsigned int irq_start, | |
ad622671 | 415 | u32 vic_sources, struct device_node *node) |
bb06b737 HS |
416 | { |
417 | unsigned int i; | |
418 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | |
419 | ||
420 | /* Disable all interrupts initially. */ | |
b0c4c898 | 421 | vic_disable(base); |
bb06b737 HS |
422 | |
423 | /* | |
424 | * Make sure we clear all existing interrupts. The vector registers | |
425 | * in this cell are after the second block of general registers, | |
426 | * so we can address them using standard offsets, but only from | |
427 | * the second base address, which is 0x20 in the page | |
428 | */ | |
429 | if (vic_2nd_block) { | |
b0c4c898 | 430 | vic_clear_interrupts(base); |
bb06b737 | 431 | |
bb06b737 HS |
432 | /* ST has 16 vectors as well, but we don't enable them by now */ |
433 | for (i = 0; i < 16; i++) { | |
434 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
435 | writel(0, reg); | |
436 | } | |
437 | ||
438 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
439 | } | |
440 | ||
e641b987 | 441 | vic_register(base, 0, irq_start, vic_sources, 0, node); |
bb06b737 | 442 | } |
87e8824b | 443 | |
e641b987 | 444 | void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, |
f9b28ccb JI |
445 | u32 vic_sources, u32 resume_sources, |
446 | struct device_node *node) | |
fa0fe48f RK |
447 | { |
448 | unsigned int i; | |
87e8824b | 449 | u32 cellid = 0; |
f17a1f06 | 450 | enum amba_vendor vendor; |
87e8824b AR |
451 | |
452 | /* Identify which VIC cell this one is, by reading the ID */ | |
453 | for (i = 0; i < 4; i++) { | |
d4f3add2 AB |
454 | void __iomem *addr; |
455 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | |
87e8824b AR |
456 | cellid |= (readl(addr) & 0xff) << (8 * i); |
457 | } | |
458 | vendor = (cellid >> 12) & 0xff; | |
459 | printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", | |
460 | base, cellid, vendor); | |
461 | ||
462 | switch(vendor) { | |
f17a1f06 | 463 | case AMBA_VENDOR_ST: |
ad622671 | 464 | vic_init_st(base, irq_start, vic_sources, node); |
87e8824b AR |
465 | return; |
466 | default: | |
467 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); | |
468 | /* fall through */ | |
f17a1f06 | 469 | case AMBA_VENDOR_ARM: |
87e8824b AR |
470 | break; |
471 | } | |
fa0fe48f | 472 | |
fa0fe48f | 473 | /* Disable all interrupts initially. */ |
b0c4c898 | 474 | vic_disable(base); |
fa0fe48f | 475 | |
b0c4c898 HS |
476 | /* Make sure we clear all existing interrupts */ |
477 | vic_clear_interrupts(base); | |
fa0fe48f | 478 | |
c07f87f2 | 479 | vic_init2(base); |
fa0fe48f | 480 | |
e641b987 | 481 | vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node); |
f9b28ccb JI |
482 | } |
483 | ||
484 | /** | |
485 | * vic_init() - initialise a vectored interrupt controller | |
486 | * @base: iomem base address | |
487 | * @irq_start: starting interrupt number, must be muliple of 32 | |
488 | * @vic_sources: bitmask of interrupt sources to allow | |
489 | * @resume_sources: bitmask of interrupt sources to allow for resume | |
490 | */ | |
491 | void __init vic_init(void __iomem *base, unsigned int irq_start, | |
492 | u32 vic_sources, u32 resume_sources) | |
493 | { | |
e641b987 LW |
494 | __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL); |
495 | } | |
496 | ||
497 | /** | |
498 | * vic_init_cascaded() - initialise a cascaded vectored interrupt controller | |
499 | * @base: iomem base address | |
500 | * @parent_irq: the parent IRQ we're cascaded off | |
501 | * @irq_start: starting interrupt number, must be muliple of 32 | |
502 | * @vic_sources: bitmask of interrupt sources to allow | |
503 | * @resume_sources: bitmask of interrupt sources to allow for resume | |
504 | * | |
505 | * This returns the base for the new interrupts or negative on error. | |
506 | */ | |
507 | int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq, | |
508 | u32 vic_sources, u32 resume_sources) | |
509 | { | |
510 | struct vic_device *v; | |
511 | ||
512 | v = &vic_devices[vic_id]; | |
513 | __vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL); | |
514 | /* Return out acquired base */ | |
515 | return v->irq; | |
f9b28ccb | 516 | } |
a3f4fdf2 | 517 | EXPORT_SYMBOL_GPL(vic_init_cascaded); |
f9b28ccb JI |
518 | |
519 | #ifdef CONFIG_OF | |
520 | int __init vic_of_init(struct device_node *node, struct device_node *parent) | |
521 | { | |
522 | void __iomem *regs; | |
81e9c179 TF |
523 | u32 interrupt_mask = ~0; |
524 | u32 wakeup_mask = ~0; | |
f9b28ccb JI |
525 | |
526 | if (WARN(parent, "non-root VICs are not supported")) | |
527 | return -EINVAL; | |
528 | ||
529 | regs = of_iomap(node, 0); | |
530 | if (WARN_ON(!regs)) | |
531 | return -EIO; | |
532 | ||
81e9c179 TF |
533 | of_property_read_u32(node, "valid-mask", &interrupt_mask); |
534 | of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask); | |
535 | ||
07c9249f | 536 | /* |
5ced33bc | 537 | * Passing 0 as first IRQ makes the simple domain allocate descriptors |
07c9249f | 538 | */ |
e641b987 | 539 | __vic_init(regs, 0, 0, interrupt_mask, wakeup_mask, node); |
f9b28ccb JI |
540 | |
541 | return 0; | |
fa0fe48f | 542 | } |
44430ec0 RH |
543 | IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init); |
544 | IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init); | |
545 | IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init); | |
f9b28ccb | 546 | #endif /* CONFIG OF */ |