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4c18e77f | 1 | /* |
4c18e77f | 2 | * SPEAr platform shared irq layer source file |
3 | * | |
df1590d9 | 4 | * Copyright (C) 2009-2012 ST Microelectronics |
10d8935f | 5 | * Viresh Kumar <viresh.linux@gmail.com> |
4c18e77f | 6 | * |
df1590d9 | 7 | * Copyright (C) 2012 ST Microelectronics |
9cc23682 | 8 | * Shiraz Hashim <shiraz.linux.kernel@gmail.com> |
df1590d9 | 9 | * |
4c18e77f | 10 | * This file is licensed under the terms of the GNU General Public |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
80515a5a | 14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
4c18e77f | 15 | |
16 | #include <linux/err.h> | |
80515a5a SH |
17 | #include <linux/export.h> |
18 | #include <linux/interrupt.h> | |
4c18e77f | 19 | #include <linux/io.h> |
20 | #include <linux/irq.h> | |
80515a5a SH |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
4c18e77f | 25 | #include <linux/spinlock.h> |
4c18e77f | 26 | |
e9c51558 RH |
27 | #include "irqchip.h" |
28 | ||
078bc005 TG |
29 | /* |
30 | * struct spear_shirq: shared irq structure | |
31 | * | |
c5d1d857 | 32 | * base: Base register address |
1b0a76c1 TG |
33 | * status_reg: Status register offset for chained interrupt handler |
34 | * mask_reg: Mask register offset for irq chip | |
4ecc832f | 35 | * mask: Mask to apply to the status register |
c5d1d857 TG |
36 | * virq_base: Base virtual interrupt number |
37 | * nr_irqs: Number of interrupts handled by this block | |
38 | * offset: Bit offset of the first interrupt | |
f07e42f9 TG |
39 | * irq_chip: Interrupt controller chip used for this instance, |
40 | * if NULL group is disabled, but accounted | |
078bc005 TG |
41 | */ |
42 | struct spear_shirq { | |
c5d1d857 | 43 | void __iomem *base; |
1b0a76c1 TG |
44 | u32 status_reg; |
45 | u32 mask_reg; | |
4ecc832f | 46 | u32 mask; |
c5d1d857 TG |
47 | u32 virq_base; |
48 | u32 nr_irqs; | |
49 | u32 offset; | |
f07e42f9 | 50 | struct irq_chip *irq_chip; |
078bc005 TG |
51 | }; |
52 | ||
80515a5a SH |
53 | /* spear300 shared irq registers offsets and masks */ |
54 | #define SPEAR300_INT_ENB_MASK_REG 0x54 | |
55 | #define SPEAR300_INT_STS_MASK_REG 0x58 | |
56 | ||
f07e42f9 TG |
57 | static DEFINE_RAW_SPINLOCK(shirq_lock); |
58 | ||
59 | static void shirq_irq_mask(struct irq_data *d) | |
60 | { | |
61 | struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); | |
62 | u32 val, shift = d->irq - shirq->virq_base + shirq->offset; | |
1b0a76c1 | 63 | u32 __iomem *reg = shirq->base + shirq->mask_reg; |
f07e42f9 TG |
64 | |
65 | raw_spin_lock(&shirq_lock); | |
66 | val = readl(reg) & ~(0x1 << shift); | |
67 | writel(val, reg); | |
68 | raw_spin_unlock(&shirq_lock); | |
69 | } | |
70 | ||
71 | static void shirq_irq_unmask(struct irq_data *d) | |
72 | { | |
73 | struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); | |
74 | u32 val, shift = d->irq - shirq->virq_base + shirq->offset; | |
1b0a76c1 | 75 | u32 __iomem *reg = shirq->base + shirq->mask_reg; |
f07e42f9 TG |
76 | |
77 | raw_spin_lock(&shirq_lock); | |
78 | val = readl(reg) | (0x1 << shift); | |
79 | writel(val, reg); | |
80 | raw_spin_unlock(&shirq_lock); | |
81 | } | |
82 | ||
83 | static struct irq_chip shirq_chip = { | |
84 | .name = "spear-shirq", | |
85 | .irq_mask = shirq_irq_mask, | |
86 | .irq_unmask = shirq_irq_unmask, | |
87 | }; | |
88 | ||
80515a5a | 89 | static struct spear_shirq spear300_shirq_ras1 = { |
c5d1d857 TG |
90 | .offset = 0, |
91 | .nr_irqs = 9, | |
4ecc832f | 92 | .mask = ((0x1 << 9) - 1) << 0, |
f07e42f9 | 93 | .irq_chip = &shirq_chip, |
1b0a76c1 TG |
94 | .status_reg = SPEAR300_INT_STS_MASK_REG, |
95 | .mask_reg = SPEAR300_INT_ENB_MASK_REG, | |
80515a5a SH |
96 | }; |
97 | ||
98 | static struct spear_shirq *spear300_shirq_blocks[] = { | |
99 | &spear300_shirq_ras1, | |
100 | }; | |
101 | ||
102 | /* spear310 shared irq registers offsets and masks */ | |
103 | #define SPEAR310_INT_STS_MASK_REG 0x04 | |
104 | ||
105 | static struct spear_shirq spear310_shirq_ras1 = { | |
c5d1d857 TG |
106 | .offset = 0, |
107 | .nr_irqs = 8, | |
4ecc832f | 108 | .mask = ((0x1 << 8) - 1) << 0, |
f07e42f9 | 109 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 110 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
80515a5a SH |
111 | }; |
112 | ||
113 | static struct spear_shirq spear310_shirq_ras2 = { | |
c5d1d857 TG |
114 | .offset = 8, |
115 | .nr_irqs = 5, | |
4ecc832f | 116 | .mask = ((0x1 << 5) - 1) << 8, |
f07e42f9 | 117 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 118 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
80515a5a SH |
119 | }; |
120 | ||
121 | static struct spear_shirq spear310_shirq_ras3 = { | |
c5d1d857 TG |
122 | .offset = 13, |
123 | .nr_irqs = 1, | |
4ecc832f | 124 | .mask = ((0x1 << 1) - 1) << 13, |
f07e42f9 | 125 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 126 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
80515a5a SH |
127 | }; |
128 | ||
129 | static struct spear_shirq spear310_shirq_intrcomm_ras = { | |
c5d1d857 TG |
130 | .offset = 14, |
131 | .nr_irqs = 3, | |
4ecc832f | 132 | .mask = ((0x1 << 3) - 1) << 14, |
f07e42f9 | 133 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 134 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
80515a5a SH |
135 | }; |
136 | ||
137 | static struct spear_shirq *spear310_shirq_blocks[] = { | |
138 | &spear310_shirq_ras1, | |
139 | &spear310_shirq_ras2, | |
140 | &spear310_shirq_ras3, | |
141 | &spear310_shirq_intrcomm_ras, | |
142 | }; | |
143 | ||
144 | /* spear320 shared irq registers offsets and masks */ | |
145 | #define SPEAR320_INT_STS_MASK_REG 0x04 | |
146 | #define SPEAR320_INT_CLR_MASK_REG 0x04 | |
147 | #define SPEAR320_INT_ENB_MASK_REG 0x08 | |
148 | ||
03319a1a TG |
149 | static struct spear_shirq spear320_shirq_ras3 = { |
150 | .offset = 0, | |
151 | .nr_irqs = 7, | |
4ecc832f | 152 | .mask = ((0x1 << 7) - 1) << 0, |
80515a5a SH |
153 | }; |
154 | ||
03319a1a TG |
155 | static struct spear_shirq spear320_shirq_ras1 = { |
156 | .offset = 7, | |
157 | .nr_irqs = 3, | |
4ecc832f | 158 | .mask = ((0x1 << 3) - 1) << 7, |
f07e42f9 | 159 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 160 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
80515a5a SH |
161 | }; |
162 | ||
03319a1a TG |
163 | static struct spear_shirq spear320_shirq_ras2 = { |
164 | .offset = 10, | |
165 | .nr_irqs = 1, | |
4ecc832f | 166 | .mask = ((0x1 << 1) - 1) << 10, |
f07e42f9 | 167 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 168 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
80515a5a SH |
169 | }; |
170 | ||
171 | static struct spear_shirq spear320_shirq_intrcomm_ras = { | |
c5d1d857 TG |
172 | .offset = 11, |
173 | .nr_irqs = 11, | |
4ecc832f | 174 | .mask = ((0x1 << 11) - 1) << 11, |
f07e42f9 | 175 | .irq_chip = &dummy_irq_chip, |
1b0a76c1 | 176 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
80515a5a SH |
177 | }; |
178 | ||
179 | static struct spear_shirq *spear320_shirq_blocks[] = { | |
180 | &spear320_shirq_ras3, | |
181 | &spear320_shirq_ras1, | |
182 | &spear320_shirq_ras2, | |
183 | &spear320_shirq_intrcomm_ras, | |
184 | }; | |
185 | ||
4c18e77f | 186 | static void shirq_handler(unsigned irq, struct irq_desc *desc) |
187 | { | |
6845664a | 188 | struct spear_shirq *shirq = irq_get_handler_data(irq); |
25dc49e3 | 189 | u32 pend; |
4c18e77f | 190 | |
1b0a76c1 | 191 | pend = readl(shirq->base + shirq->status_reg) & shirq->mask; |
25dc49e3 | 192 | pend >>= shirq->offset; |
80515a5a | 193 | |
25dc49e3 TG |
194 | while (pend) { |
195 | int irq = __ffs(pend); | |
80515a5a | 196 | |
25dc49e3 TG |
197 | pend &= ~(0x1 << irq); |
198 | generic_handle_irq(shirq->virq_base + irq); | |
4c18e77f | 199 | } |
4c18e77f | 200 | } |
201 | ||
f37ecbce TG |
202 | static void __init spear_shirq_register(struct spear_shirq *shirq, |
203 | int parent_irq) | |
4c18e77f | 204 | { |
205 | int i; | |
206 | ||
f07e42f9 | 207 | if (!shirq->irq_chip) |
80515a5a | 208 | return; |
4c18e77f | 209 | |
f37ecbce TG |
210 | irq_set_chained_handler(parent_irq, shirq_handler); |
211 | irq_set_handler_data(parent_irq, shirq); | |
212 | ||
c5d1d857 TG |
213 | for (i = 0; i < shirq->nr_irqs; i++) { |
214 | irq_set_chip_and_handler(shirq->virq_base + i, | |
f07e42f9 | 215 | shirq->irq_chip, handle_simple_irq); |
c5d1d857 TG |
216 | set_irq_flags(shirq->virq_base + i, IRQF_VALID); |
217 | irq_set_chip_data(shirq->virq_base + i, shirq); | |
4c18e77f | 218 | } |
80515a5a SH |
219 | } |
220 | ||
221 | static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr, | |
222 | struct device_node *np) | |
223 | { | |
c5d1d857 | 224 | int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0; |
a26c06f9 | 225 | struct irq_domain *shirq_domain; |
80515a5a SH |
226 | void __iomem *base; |
227 | ||
228 | base = of_iomap(np, 0); | |
229 | if (!base) { | |
230 | pr_err("%s: failed to map shirq registers\n", __func__); | |
231 | return -ENXIO; | |
232 | } | |
233 | ||
234 | for (i = 0; i < block_nr; i++) | |
c5d1d857 | 235 | nr_irqs += shirq_blocks[i]->nr_irqs; |
80515a5a | 236 | |
c5d1d857 TG |
237 | virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
238 | if (IS_ERR_VALUE(virq_base)) { | |
80515a5a SH |
239 | pr_err("%s: irq desc alloc failed\n", __func__); |
240 | goto err_unmap; | |
241 | } | |
242 | ||
c5d1d857 | 243 | shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0, |
80515a5a SH |
244 | &irq_domain_simple_ops, NULL); |
245 | if (WARN_ON(!shirq_domain)) { | |
246 | pr_warn("%s: irq domain init failed\n", __func__); | |
247 | goto err_free_desc; | |
248 | } | |
249 | ||
250 | for (i = 0; i < block_nr; i++) { | |
251 | shirq_blocks[i]->base = base; | |
c5d1d857 | 252 | shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain, |
80515a5a | 253 | hwirq); |
80515a5a | 254 | |
f37ecbce TG |
255 | parent_irq = irq_of_parse_and_map(np, i); |
256 | spear_shirq_register(shirq_blocks[i], parent_irq); | |
c5d1d857 | 257 | hwirq += shirq_blocks[i]->nr_irqs; |
80515a5a SH |
258 | } |
259 | ||
4c18e77f | 260 | return 0; |
80515a5a SH |
261 | |
262 | err_free_desc: | |
c5d1d857 | 263 | irq_free_descs(virq_base, nr_irqs); |
80515a5a SH |
264 | err_unmap: |
265 | iounmap(base); | |
266 | return -ENXIO; | |
267 | } | |
268 | ||
078bc005 TG |
269 | static int __init spear300_shirq_of_init(struct device_node *np, |
270 | struct device_node *parent) | |
80515a5a SH |
271 | { |
272 | return shirq_init(spear300_shirq_blocks, | |
273 | ARRAY_SIZE(spear300_shirq_blocks), np); | |
274 | } | |
e9c51558 | 275 | IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); |
80515a5a | 276 | |
078bc005 TG |
277 | static int __init spear310_shirq_of_init(struct device_node *np, |
278 | struct device_node *parent) | |
80515a5a SH |
279 | { |
280 | return shirq_init(spear310_shirq_blocks, | |
281 | ARRAY_SIZE(spear310_shirq_blocks), np); | |
282 | } | |
e9c51558 | 283 | IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); |
80515a5a | 284 | |
078bc005 TG |
285 | static int __init spear320_shirq_of_init(struct device_node *np, |
286 | struct device_node *parent) | |
80515a5a SH |
287 | { |
288 | return shirq_init(spear320_shirq_blocks, | |
289 | ARRAY_SIZE(spear320_shirq_blocks), np); | |
4c18e77f | 290 | } |
e9c51558 | 291 | IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init); |