Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * IPACX specific defines | |
4 | * | |
5 | * This software may be used and distributed according to the terms | |
6 | * of the GNU General Public License, incorporated herein by reference. | |
7 | * | |
8 | */ | |
9 | ||
10 | /* All Registers original Siemens Spec */ | |
11 | ||
12 | #ifndef INCLUDE_IPACX_H | |
13 | #define INCLUDE_IPACX_H | |
14 | ||
15 | /* D-channel registers */ | |
16 | #define IPACX_RFIFOD 0x00 /* RD */ | |
17 | #define IPACX_XFIFOD 0x00 /* WR */ | |
18 | #define IPACX_ISTAD 0x20 /* RD */ | |
19 | #define IPACX_MASKD 0x20 /* WR */ | |
20 | #define IPACX_STARD 0x21 /* RD */ | |
21 | #define IPACX_CMDRD 0x21 /* WR */ | |
22 | #define IPACX_MODED 0x22 /* RD/WR */ | |
23 | #define IPACX_EXMD1 0x23 /* RD/WR */ | |
24 | #define IPACX_TIMR1 0x24 /* RD/WR */ | |
25 | #define IPACX_SAP1 0x25 /* WR */ | |
26 | #define IPACX_SAP2 0x26 /* WR */ | |
27 | #define IPACX_RBCLD 0x26 /* RD */ | |
28 | #define IPACX_RBCHD 0x27 /* RD */ | |
29 | #define IPACX_TEI1 0x27 /* WR */ | |
30 | #define IPACX_TEI2 0x28 /* WR */ | |
31 | #define IPACX_RSTAD 0x28 /* RD */ | |
32 | #define IPACX_TMD 0x29 /* RD/WR */ | |
33 | #define IPACX_CIR0 0x2E /* RD */ | |
34 | #define IPACX_CIX0 0x2E /* WR */ | |
35 | #define IPACX_CIR1 0x2F /* RD */ | |
36 | #define IPACX_CIX1 0x2F /* WR */ | |
37 | ||
38 | /* Transceiver registers */ | |
39 | #define IPACX_TR_CONF0 0x30 /* RD/WR */ | |
40 | #define IPACX_TR_CONF1 0x31 /* RD/WR */ | |
41 | #define IPACX_TR_CONF2 0x32 /* RD/WR */ | |
42 | #define IPACX_TR_STA 0x33 /* RD */ | |
43 | #define IPACX_TR_CMD 0x34 /* RD/WR */ | |
44 | #define IPACX_SQRR1 0x35 /* RD */ | |
45 | #define IPACX_SQXR1 0x35 /* WR */ | |
46 | #define IPACX_SQRR2 0x36 /* RD */ | |
47 | #define IPACX_SQXR2 0x36 /* WR */ | |
48 | #define IPACX_SQRR3 0x37 /* RD */ | |
49 | #define IPACX_SQXR3 0x37 /* WR */ | |
50 | #define IPACX_ISTATR 0x38 /* RD */ | |
51 | #define IPACX_MASKTR 0x39 /* RD/WR */ | |
52 | #define IPACX_TR_MODE 0x3A /* RD/WR */ | |
53 | #define IPACX_ACFG1 0x3C /* RD/WR */ | |
54 | #define IPACX_ACFG2 0x3D /* RD/WR */ | |
55 | #define IPACX_AOE 0x3E /* RD/WR */ | |
56 | #define IPACX_ARX 0x3F /* RD */ | |
57 | #define IPACX_ATX 0x3F /* WR */ | |
58 | ||
59 | /* IOM: Timeslot, DPS, CDA */ | |
60 | #define IPACX_CDA10 0x40 /* RD/WR */ | |
61 | #define IPACX_CDA11 0x41 /* RD/WR */ | |
62 | #define IPACX_CDA20 0x42 /* RD/WR */ | |
63 | #define IPACX_CDA21 0x43 /* RD/WR */ | |
64 | #define IPACX_CDA_TSDP10 0x44 /* RD/WR */ | |
65 | #define IPACX_CDA_TSDP11 0x45 /* RD/WR */ | |
66 | #define IPACX_CDA_TSDP20 0x46 /* RD/WR */ | |
67 | #define IPACX_CDA_TSDP21 0x47 /* RD/WR */ | |
68 | #define IPACX_BCHA_TSDP_BC1 0x48 /* RD/WR */ | |
69 | #define IPACX_BCHA_TSDP_BC2 0x49 /* RD/WR */ | |
70 | #define IPACX_BCHB_TSDP_BC1 0x4A /* RD/WR */ | |
71 | #define IPACX_BCHB_TSDP_BC2 0x4B /* RD/WR */ | |
72 | #define IPACX_TR_TSDP_BC1 0x4C /* RD/WR */ | |
73 | #define IPACX_TR_TSDP_BC2 0x4D /* RD/WR */ | |
74 | #define IPACX_CDA1_CR 0x4E /* RD/WR */ | |
75 | #define IPACX_CDA2_CR 0x4F /* RD/WR */ | |
76 | ||
77 | /* IOM: Contol, Sync transfer, Monitor */ | |
78 | #define IPACX_TR_CR 0x50 /* RD/WR */ | |
79 | #define IPACX_TRC_CR 0x50 /* RD/WR */ | |
80 | #define IPACX_BCHA_CR 0x51 /* RD/WR */ | |
81 | #define IPACX_BCHB_CR 0x52 /* RD/WR */ | |
82 | #define IPACX_DCI_CR 0x53 /* RD/WR */ | |
83 | #define IPACX_DCIC_CR 0x53 /* RD/WR */ | |
84 | #define IPACX_MON_CR 0x54 /* RD/WR */ | |
85 | #define IPACX_SDS1_CR 0x55 /* RD/WR */ | |
86 | #define IPACX_SDS2_CR 0x56 /* RD/WR */ | |
87 | #define IPACX_IOM_CR 0x57 /* RD/WR */ | |
88 | #define IPACX_STI 0x58 /* RD */ | |
89 | #define IPACX_ASTI 0x58 /* WR */ | |
90 | #define IPACX_MSTI 0x59 /* RD/WR */ | |
91 | #define IPACX_SDS_CONF 0x5A /* RD/WR */ | |
92 | #define IPACX_MCDA 0x5B /* RD */ | |
93 | #define IPACX_MOR 0x5C /* RD */ | |
94 | #define IPACX_MOX 0x5C /* WR */ | |
95 | #define IPACX_MOSR 0x5D /* RD */ | |
96 | #define IPACX_MOCR 0x5E /* RD/WR */ | |
97 | #define IPACX_MSTA 0x5F /* RD */ | |
98 | #define IPACX_MCONF 0x5F /* WR */ | |
99 | ||
100 | /* Interrupt and general registers */ | |
101 | #define IPACX_ISTA 0x60 /* RD */ | |
102 | #define IPACX_MASK 0x60 /* WR */ | |
103 | #define IPACX_AUXI 0x61 /* RD */ | |
104 | #define IPACX_AUXM 0x61 /* WR */ | |
105 | #define IPACX_MODE1 0x62 /* RD/WR */ | |
106 | #define IPACX_MODE2 0x63 /* RD/WR */ | |
107 | #define IPACX_ID 0x64 /* RD */ | |
108 | #define IPACX_SRES 0x64 /* WR */ | |
109 | #define IPACX_TIMR2 0x65 /* RD/WR */ | |
110 | ||
111 | /* B-channel registers */ | |
112 | #define IPACX_OFF_B1 0x70 | |
113 | #define IPACX_OFF_B2 0x80 | |
114 | ||
115 | #define IPACX_ISTAB 0x00 /* RD */ | |
116 | #define IPACX_MASKB 0x00 /* WR */ | |
117 | #define IPACX_STARB 0x01 /* RD */ | |
118 | #define IPACX_CMDRB 0x01 /* WR */ | |
119 | #define IPACX_MODEB 0x02 /* RD/WR */ | |
120 | #define IPACX_EXMB 0x03 /* RD/WR */ | |
121 | #define IPACX_RAH1 0x05 /* WR */ | |
122 | #define IPACX_RAH2 0x06 /* WR */ | |
123 | #define IPACX_RBCLB 0x06 /* RD */ | |
124 | #define IPACX_RBCHB 0x07 /* RD */ | |
125 | #define IPACX_RAL1 0x07 /* WR */ | |
126 | #define IPACX_RAL2 0x08 /* WR */ | |
127 | #define IPACX_RSTAB 0x08 /* RD */ | |
128 | #define IPACX_TMB 0x09 /* RD/WR */ | |
129 | #define IPACX_RFIFOB 0x0A /*- RD */ | |
130 | #define IPACX_XFIFOB 0x0A /*- WR */ | |
131 | ||
132 | /* Layer 1 Commands */ | |
133 | #define IPACX_CMD_TIM 0x0 | |
134 | #define IPACX_CMD_RES 0x1 | |
135 | #define IPACX_CMD_SSP 0x2 | |
136 | #define IPACX_CMD_SCP 0x3 | |
137 | #define IPACX_CMD_AR8 0x8 | |
138 | #define IPACX_CMD_AR10 0x9 | |
139 | #define IPACX_CMD_ARL 0xa | |
140 | #define IPACX_CMD_DI 0xf | |
141 | ||
142 | /* Layer 1 Indications */ | |
143 | #define IPACX_IND_DR 0x0 | |
144 | #define IPACX_IND_RES 0x1 | |
145 | #define IPACX_IND_TMA 0x2 | |
146 | #define IPACX_IND_SLD 0x3 | |
147 | #define IPACX_IND_RSY 0x4 | |
148 | #define IPACX_IND_DR6 0x5 | |
149 | #define IPACX_IND_PU 0x7 | |
150 | #define IPACX_IND_AR 0x8 | |
151 | #define IPACX_IND_ARL 0xa | |
152 | #define IPACX_IND_CVR 0xb | |
153 | #define IPACX_IND_AI8 0xc | |
154 | #define IPACX_IND_AI10 0xd | |
155 | #define IPACX_IND_AIL 0xe | |
156 | #define IPACX_IND_DC 0xf | |
157 | ||
158 | extern void init_ipacx(struct IsdnCardState *, int); | |
159 | extern void interrupt_ipacx(struct IsdnCardState *); | |
160 | extern void setup_isac(struct IsdnCardState *); | |
161 | ||
162 | #endif |