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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
3 | * | |
4 | * MandrakeSoft S.A. | |
5 | * 43, rue d'Aboukir | |
6 | * 75002 Paris - France | |
7 | * http://www.linux-mandrake.com/ | |
8 | * http://www.mandrakesoft.com/ | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
25 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
26 | * Based on Xen 3.1 code. | |
27 | */ | |
28 | ||
29 | #include "kvm.h" | |
34c16eec ZX |
30 | #include "x86.h" |
31 | ||
1fd4f2a5 ED |
32 | #include <linux/kvm.h> |
33 | #include <linux/mm.h> | |
34 | #include <linux/highmem.h> | |
35 | #include <linux/smp.h> | |
36 | #include <linux/hrtimer.h> | |
37 | #include <linux/io.h> | |
38 | #include <asm/processor.h> | |
1fd4f2a5 ED |
39 | #include <asm/page.h> |
40 | #include <asm/current.h> | |
1fd4f2a5 | 41 | #include "irq.h" |
e25e3ed5 LV |
42 | #if 0 |
43 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
44 | #else | |
1fd4f2a5 | 45 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 46 | #endif |
1fd4f2a5 ED |
47 | static void ioapic_deliver(struct kvm_ioapic *vioapic, int irq); |
48 | ||
49 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
50 | unsigned long addr, | |
51 | unsigned long length) | |
52 | { | |
53 | unsigned long result = 0; | |
54 | ||
55 | switch (ioapic->ioregsel) { | |
56 | case IOAPIC_REG_VERSION: | |
57 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
58 | | (IOAPIC_VERSION_ID & 0xff)); | |
59 | break; | |
60 | ||
61 | case IOAPIC_REG_APIC_ID: | |
62 | case IOAPIC_REG_ARB_ID: | |
63 | result = ((ioapic->id & 0xf) << 24); | |
64 | break; | |
65 | ||
66 | default: | |
67 | { | |
68 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
69 | u64 redir_content; | |
70 | ||
71 | ASSERT(redir_index < IOAPIC_NUM_PINS); | |
72 | ||
73 | redir_content = ioapic->redirtbl[redir_index].bits; | |
74 | result = (ioapic->ioregsel & 0x1) ? | |
75 | (redir_content >> 32) & 0xffffffff : | |
76 | redir_content & 0xffffffff; | |
77 | break; | |
78 | } | |
79 | } | |
80 | ||
81 | return result; | |
82 | } | |
83 | ||
84 | static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx) | |
85 | { | |
86 | union ioapic_redir_entry *pent; | |
87 | ||
88 | pent = &ioapic->redirtbl[idx]; | |
89 | ||
90 | if (!pent->fields.mask) { | |
91 | ioapic_deliver(ioapic, idx); | |
92 | if (pent->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
93 | pent->fields.remote_irr = 1; | |
94 | } | |
95 | if (!pent->fields.trig_mode) | |
96 | ioapic->irr &= ~(1 << idx); | |
97 | } | |
98 | ||
99 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) | |
100 | { | |
101 | unsigned index; | |
102 | ||
103 | switch (ioapic->ioregsel) { | |
104 | case IOAPIC_REG_VERSION: | |
105 | /* Writes are ignored. */ | |
106 | break; | |
107 | ||
108 | case IOAPIC_REG_APIC_ID: | |
109 | ioapic->id = (val >> 24) & 0xf; | |
110 | break; | |
111 | ||
112 | case IOAPIC_REG_ARB_ID: | |
113 | break; | |
114 | ||
115 | default: | |
116 | index = (ioapic->ioregsel - 0x10) >> 1; | |
117 | ||
e25e3ed5 | 118 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
119 | if (index >= IOAPIC_NUM_PINS) |
120 | return; | |
121 | if (ioapic->ioregsel & 1) { | |
122 | ioapic->redirtbl[index].bits &= 0xffffffff; | |
123 | ioapic->redirtbl[index].bits |= (u64) val << 32; | |
124 | } else { | |
125 | ioapic->redirtbl[index].bits &= ~0xffffffffULL; | |
126 | ioapic->redirtbl[index].bits |= (u32) val; | |
127 | ioapic->redirtbl[index].fields.remote_irr = 0; | |
128 | } | |
129 | if (ioapic->irr & (1 << index)) | |
130 | ioapic_service(ioapic, index); | |
131 | break; | |
132 | } | |
133 | } | |
134 | ||
135 | static void ioapic_inj_irq(struct kvm_ioapic *ioapic, | |
8be5453f | 136 | struct kvm_vcpu *vcpu, |
1fd4f2a5 ED |
137 | u8 vector, u8 trig_mode, u8 delivery_mode) |
138 | { | |
e25e3ed5 | 139 | ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode, |
1fd4f2a5 ED |
140 | delivery_mode); |
141 | ||
0c7ac28d ZX |
142 | ASSERT((delivery_mode == IOAPIC_FIXED) || |
143 | (delivery_mode == IOAPIC_LOWEST_PRIORITY)); | |
1fd4f2a5 | 144 | |
8be5453f | 145 | kvm_apic_set_irq(vcpu, vector, trig_mode); |
1fd4f2a5 ED |
146 | } |
147 | ||
148 | static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest, | |
149 | u8 dest_mode) | |
150 | { | |
151 | u32 mask = 0; | |
152 | int i; | |
153 | struct kvm *kvm = ioapic->kvm; | |
154 | struct kvm_vcpu *vcpu; | |
155 | ||
e25e3ed5 | 156 | ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode); |
1fd4f2a5 ED |
157 | |
158 | if (dest_mode == 0) { /* Physical mode. */ | |
159 | if (dest == 0xFF) { /* Broadcast. */ | |
160 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
161 | if (kvm->vcpus[i] && kvm->vcpus[i]->apic) | |
162 | mask |= 1 << i; | |
163 | return mask; | |
164 | } | |
165 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
166 | vcpu = kvm->vcpus[i]; | |
167 | if (!vcpu) | |
168 | continue; | |
169 | if (kvm_apic_match_physical_addr(vcpu->apic, dest)) { | |
170 | if (vcpu->apic) | |
171 | mask = 1 << i; | |
172 | break; | |
173 | } | |
174 | } | |
175 | } else if (dest != 0) /* Logical mode, MDA non-zero. */ | |
176 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
177 | vcpu = kvm->vcpus[i]; | |
178 | if (!vcpu) | |
179 | continue; | |
180 | if (vcpu->apic && | |
181 | kvm_apic_match_logical_addr(vcpu->apic, dest)) | |
182 | mask |= 1 << vcpu->vcpu_id; | |
183 | } | |
e25e3ed5 | 184 | ioapic_debug("mask %x\n", mask); |
1fd4f2a5 ED |
185 | return mask; |
186 | } | |
187 | ||
188 | static void ioapic_deliver(struct kvm_ioapic *ioapic, int irq) | |
189 | { | |
190 | u8 dest = ioapic->redirtbl[irq].fields.dest_id; | |
191 | u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode; | |
192 | u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode; | |
193 | u8 vector = ioapic->redirtbl[irq].fields.vector; | |
194 | u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode; | |
195 | u32 deliver_bitmask; | |
1fd4f2a5 ED |
196 | struct kvm_vcpu *vcpu; |
197 | int vcpu_id; | |
198 | ||
199 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " | |
e25e3ed5 | 200 | "vector=%x trig_mode=%x\n", |
1fd4f2a5 ED |
201 | dest, dest_mode, delivery_mode, vector, trig_mode); |
202 | ||
203 | deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode); | |
204 | if (!deliver_bitmask) { | |
e25e3ed5 | 205 | ioapic_debug("no target on destination\n"); |
1fd4f2a5 ED |
206 | return; |
207 | } | |
208 | ||
209 | switch (delivery_mode) { | |
0c7ac28d | 210 | case IOAPIC_LOWEST_PRIORITY: |
8be5453f ZX |
211 | vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector, |
212 | deliver_bitmask); | |
213 | if (vcpu != NULL) | |
214 | ioapic_inj_irq(ioapic, vcpu, vector, | |
1fd4f2a5 ED |
215 | trig_mode, delivery_mode); |
216 | else | |
8be5453f | 217 | ioapic_debug("null lowest prio vcpu: " |
e25e3ed5 | 218 | "mask=%x vector=%x delivery_mode=%x\n", |
0c7ac28d | 219 | deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY); |
1fd4f2a5 | 220 | break; |
0c7ac28d | 221 | case IOAPIC_FIXED: |
1fd4f2a5 ED |
222 | for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) { |
223 | if (!(deliver_bitmask & (1 << vcpu_id))) | |
224 | continue; | |
225 | deliver_bitmask &= ~(1 << vcpu_id); | |
226 | vcpu = ioapic->kvm->vcpus[vcpu_id]; | |
227 | if (vcpu) { | |
8be5453f | 228 | ioapic_inj_irq(ioapic, vcpu, vector, |
1fd4f2a5 ED |
229 | trig_mode, delivery_mode); |
230 | } | |
231 | } | |
232 | break; | |
233 | ||
234 | /* TODO: NMI */ | |
235 | default: | |
236 | printk(KERN_WARNING "Unsupported delivery mode %d\n", | |
237 | delivery_mode); | |
238 | break; | |
239 | } | |
240 | } | |
241 | ||
242 | void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) | |
243 | { | |
244 | u32 old_irr = ioapic->irr; | |
245 | u32 mask = 1 << irq; | |
246 | union ioapic_redir_entry entry; | |
247 | ||
248 | if (irq >= 0 && irq < IOAPIC_NUM_PINS) { | |
249 | entry = ioapic->redirtbl[irq]; | |
250 | level ^= entry.fields.polarity; | |
251 | if (!level) | |
252 | ioapic->irr &= ~mask; | |
253 | else { | |
254 | ioapic->irr |= mask; | |
255 | if ((!entry.fields.trig_mode && old_irr != ioapic->irr) | |
256 | || !entry.fields.remote_irr) | |
257 | ioapic_service(ioapic, irq); | |
258 | } | |
259 | } | |
260 | } | |
261 | ||
262 | static int get_eoi_gsi(struct kvm_ioapic *ioapic, int vector) | |
263 | { | |
264 | int i; | |
265 | ||
266 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
267 | if (ioapic->redirtbl[i].fields.vector == vector) | |
268 | return i; | |
269 | return -1; | |
270 | } | |
271 | ||
272 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector) | |
273 | { | |
274 | struct kvm_ioapic *ioapic = kvm->vioapic; | |
275 | union ioapic_redir_entry *ent; | |
276 | int gsi; | |
277 | ||
278 | gsi = get_eoi_gsi(ioapic, vector); | |
279 | if (gsi == -1) { | |
280 | printk(KERN_WARNING "Can't find redir item for %d EOI\n", | |
281 | vector); | |
282 | return; | |
283 | } | |
284 | ||
285 | ent = &ioapic->redirtbl[gsi]; | |
286 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); | |
287 | ||
288 | ent->fields.remote_irr = 0; | |
289 | if (!ent->fields.mask && (ioapic->irr & (1 << gsi))) | |
290 | ioapic_deliver(ioapic, gsi); | |
291 | } | |
292 | ||
293 | static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr) | |
294 | { | |
295 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
296 | ||
297 | return ((addr >= ioapic->base_address && | |
298 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
299 | } | |
300 | ||
301 | static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, | |
302 | void *val) | |
303 | { | |
304 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
305 | u32 result; | |
306 | ||
e25e3ed5 | 307 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
308 | ASSERT(!(addr & 0xf)); /* check alignment */ |
309 | ||
310 | addr &= 0xff; | |
311 | switch (addr) { | |
312 | case IOAPIC_REG_SELECT: | |
313 | result = ioapic->ioregsel; | |
314 | break; | |
315 | ||
316 | case IOAPIC_REG_WINDOW: | |
317 | result = ioapic_read_indirect(ioapic, addr, len); | |
318 | break; | |
319 | ||
320 | default: | |
321 | result = 0; | |
322 | break; | |
323 | } | |
324 | switch (len) { | |
325 | case 8: | |
326 | *(u64 *) val = result; | |
327 | break; | |
328 | case 1: | |
329 | case 2: | |
330 | case 4: | |
331 | memcpy(val, (char *)&result, len); | |
332 | break; | |
333 | default: | |
334 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
335 | } | |
336 | } | |
337 | ||
338 | static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, | |
339 | const void *val) | |
340 | { | |
341 | struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private; | |
342 | u32 data; | |
343 | ||
e25e3ed5 LV |
344 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
345 | (void*)addr, len, val); | |
1fd4f2a5 ED |
346 | ASSERT(!(addr & 0xf)); /* check alignment */ |
347 | if (len == 4 || len == 8) | |
348 | data = *(u32 *) val; | |
349 | else { | |
350 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); | |
351 | return; | |
352 | } | |
353 | ||
354 | addr &= 0xff; | |
355 | switch (addr) { | |
356 | case IOAPIC_REG_SELECT: | |
357 | ioapic->ioregsel = data; | |
358 | break; | |
359 | ||
360 | case IOAPIC_REG_WINDOW: | |
361 | ioapic_write_indirect(ioapic, data); | |
362 | break; | |
b1fd3d30 ZX |
363 | #ifdef CONFIG_IA64 |
364 | case IOAPIC_REG_EOI: | |
365 | kvm_ioapic_update_eoi(ioapic, data); | |
366 | break; | |
367 | #endif | |
1fd4f2a5 ED |
368 | |
369 | default: | |
370 | break; | |
371 | } | |
372 | } | |
373 | ||
8c392696 ED |
374 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
375 | { | |
376 | int i; | |
377 | ||
378 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
379 | ioapic->redirtbl[i].fields.mask = 1; | |
380 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
381 | ioapic->ioregsel = 0; | |
382 | ioapic->irr = 0; | |
383 | ioapic->id = 0; | |
384 | } | |
385 | ||
1fd4f2a5 ED |
386 | int kvm_ioapic_init(struct kvm *kvm) |
387 | { | |
388 | struct kvm_ioapic *ioapic; | |
1fd4f2a5 ED |
389 | |
390 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
391 | if (!ioapic) | |
392 | return -ENOMEM; | |
393 | kvm->vioapic = ioapic; | |
8c392696 | 394 | kvm_ioapic_reset(ioapic); |
1fd4f2a5 ED |
395 | ioapic->dev.read = ioapic_mmio_read; |
396 | ioapic->dev.write = ioapic_mmio_write; | |
397 | ioapic->dev.in_range = ioapic_in_range; | |
398 | ioapic->dev.private = ioapic; | |
399 | ioapic->kvm = kvm; | |
400 | kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev); | |
401 | return 0; | |
402 | } |