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KVM: Allocate userspace memory for older userspace
[deliverable/linux.git] / drivers / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20#include "kvm.h"
21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <asm/processor.h>
29#include <asm/msr.h>
30#include <asm/page.h>
31#include <asm/current.h>
32#include <asm/apicdef.h>
33#include <asm/atomic.h>
34#include <asm/div64.h>
35#include "irq.h"
36
37#define PRId64 "d"
38#define PRIx64 "llx"
39#define PRIu64 "u"
40#define PRIo64 "o"
41
42#define APIC_BUS_CYCLE_NS 1
43
44/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
45#define apic_debug(fmt, arg...)
46
47#define APIC_LVT_NUM 6
48/* 14 is the version for Xeon and Pentium 8.4.8*/
49#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
50#define LAPIC_MMIO_LENGTH (1 << 12)
51/* followed define is not in apicdef.h */
52#define APIC_SHORT_MASK 0xc0000
53#define APIC_DEST_NOSHORT 0x0
54#define APIC_DEST_MASK 0x800
55#define MAX_APIC_VECTOR 256
56
57#define VEC_POS(v) ((v) & (32 - 1))
58#define REG_POS(v) (((v) >> 5) << 4)
59static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
60{
61 return *((u32 *) (apic->regs + reg_off));
62}
63
64static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
65{
66 *((u32 *) (apic->regs + reg_off)) = val;
67}
68
69static inline int apic_test_and_set_vector(int vec, void *bitmap)
70{
71 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
72}
73
74static inline int apic_test_and_clear_vector(int vec, void *bitmap)
75{
76 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
77}
78
79static inline void apic_set_vector(int vec, void *bitmap)
80{
81 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82}
83
84static inline void apic_clear_vector(int vec, void *bitmap)
85{
86 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline int apic_hw_enabled(struct kvm_lapic *apic)
90{
91 return (apic)->vcpu->apic_base & MSR_IA32_APICBASE_ENABLE;
92}
93
94static inline int apic_sw_enabled(struct kvm_lapic *apic)
95{
96 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
97}
98
99static inline int apic_enabled(struct kvm_lapic *apic)
100{
101 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
102}
103
104#define LVT_MASK \
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106
107#define LINT_MASK \
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
110
111static inline int kvm_apic_id(struct kvm_lapic *apic)
112{
113 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
114}
115
116static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
117{
118 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
119}
120
121static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
122{
123 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
124}
125
126static inline int apic_lvtt_period(struct kvm_lapic *apic)
127{
128 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
129}
130
131static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
132 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
133 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
134 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
135 LINT_MASK, LINT_MASK, /* LVT0-1 */
136 LVT_MASK /* LVTERR */
137};
138
139static int find_highest_vector(void *bitmap)
140{
141 u32 *word = bitmap;
142 int word_offset = MAX_APIC_VECTOR >> 5;
143
144 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
145 continue;
146
147 if (likely(!word_offset && !word[0]))
148 return -1;
149 else
150 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
151}
152
153static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
154{
155 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
156}
157
158static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
159{
160 apic_clear_vector(vec, apic->regs + APIC_IRR);
161}
162
163static inline int apic_find_highest_irr(struct kvm_lapic *apic)
164{
165 int result;
166
167 result = find_highest_vector(apic->regs + APIC_IRR);
168 ASSERT(result == -1 || result >= 16);
169
170 return result;
171}
172
6e5d865c
YS		 173int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
174{
7e620d16 175 struct kvm_lapic *apic = vcpu->apic;
6e5d865c
YS		 176 int highest_irr;
177
178 if (!apic)
179 return 0;
180 highest_irr = apic_find_highest_irr(apic);
181
182 return highest_irr;
183}
184EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
185
97222cc8
ED		 186int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig)
187{
188 if (!apic_test_and_set_irr(vec, apic)) {
189 /* a new pending irq is set in IRR */
190 if (trig)
191 apic_set_vector(vec, apic->regs + APIC_TMR);
192 else
193 apic_clear_vector(vec, apic->regs + APIC_TMR);
194 kvm_vcpu_kick(apic->vcpu);
195 return 1;
196 }
197 return 0;
198}
199
200static inline int apic_find_highest_isr(struct kvm_lapic *apic)
201{
202 int result;
203
204 result = find_highest_vector(apic->regs + APIC_ISR);
205 ASSERT(result == -1 || result >= 16);
206
207 return result;
208}
209
210static void apic_update_ppr(struct kvm_lapic *apic)
211{
212 u32 tpr, isrv, ppr;
213 int isr;
214
215 tpr = apic_get_reg(apic, APIC_TASKPRI);
216 isr = apic_find_highest_isr(apic);
217 isrv = (isr != -1) ? isr : 0;
218
219 if ((tpr & 0xf0) >= (isrv & 0xf0))
220 ppr = tpr & 0xff;
221 else
222 ppr = isrv & 0xf0;
223
224 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
225 apic, ppr, isr, isrv);
226
227 apic_set_reg(apic, APIC_PROCPRI, ppr);
228}
229
230static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
231{
232 apic_set_reg(apic, APIC_TASKPRI, tpr);
233 apic_update_ppr(apic);
234}
235
236int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
237{
238 return kvm_apic_id(apic) == dest;
239}
240
241int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
242{
243 int result = 0;
244 u8 logical_id;
245
246 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
247
248 switch (apic_get_reg(apic, APIC_DFR)) {
249 case APIC_DFR_FLAT:
250 if (logical_id & mda)
251 result = 1;
252 break;
253 case APIC_DFR_CLUSTER:
254 if (((logical_id >> 4) == (mda >> 0x4))
255 && (logical_id & mda & 0xf))
256 result = 1;
257 break;
258 default:
259 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
260 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
261 break;
262 }
263
264 return result;
265}
266
267static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
268 int short_hand, int dest, int dest_mode)
269{
270 int result = 0;
271 struct kvm_lapic *target = vcpu->apic;
272
273 apic_debug("target %p, source %p, dest 0x%x, "
274 "dest_mode 0x%x, short_hand 0x%x",
275 target, source, dest, dest_mode, short_hand);
276
277 ASSERT(!target);
278 switch (short_hand) {
279 case APIC_DEST_NOSHORT:
280 if (dest_mode == 0) {
281 /* Physical mode. */
282 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
283 result = 1;
284 } else
285 /* Logical mode. */
286 result = kvm_apic_match_logical_addr(target, dest);
287 break;
288 case APIC_DEST_SELF:
289 if (target == source)
290 result = 1;
291 break;
292 case APIC_DEST_ALLINC:
293 result = 1;
294 break;
295 case APIC_DEST_ALLBUT:
296 if (target != source)
297 result = 1;
298 break;
299 default:
300 printk(KERN_WARNING "Bad dest shorthand value %x\n",
301 short_hand);
302 break;
303 }
304
305 return result;
306}
307
308/*
309 * Add a pending IRQ into lapic.
310 * Return 1 if successfully added and 0 if discarded.
311 */
312static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
313 int vector, int level, int trig_mode)
314{
c5ec1534
HQ		 315 int orig_irr, result = 0;
316 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 317
318 switch (delivery_mode) {
319 case APIC_DM_FIXED:
320 case APIC_DM_LOWEST:
321 /* FIXME add logic for vcpu on reset */
322 if (unlikely(!apic_enabled(apic)))
323 break;
324
1b9778da
ED		 325 orig_irr = apic_test_and_set_irr(vector, apic);
326 if (orig_irr && trig_mode) {
97222cc8
ED		 327 apic_debug("level trig mode repeatedly for vector %d",
328 vector);
329 break;
330 }
331
332 if (trig_mode) {
333 apic_debug("level trig mode for vector %d", vector);
334 apic_set_vector(vector, apic->regs + APIC_TMR);
335 } else
336 apic_clear_vector(vector, apic->regs + APIC_TMR);
337
c5ec1534
HQ		 338 if (vcpu->mp_state == VCPU_MP_STATE_RUNNABLE)
339 kvm_vcpu_kick(vcpu);
340 else if (vcpu->mp_state == VCPU_MP_STATE_HALTED) {
341 vcpu->mp_state = VCPU_MP_STATE_RUNNABLE;
342 if (waitqueue_active(&vcpu->wq))
343 wake_up_interruptible(&vcpu->wq);
344 }
97222cc8 345
1b9778da 346 result = (orig_irr == 0);
97222cc8
ED		 347 break;
348
349 case APIC_DM_REMRD:
350 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
351 break;
352
353 case APIC_DM_SMI:
354 printk(KERN_DEBUG "Ignoring guest SMI\n");
355 break;
356 case APIC_DM_NMI:
357 printk(KERN_DEBUG "Ignoring guest NMI\n");
358 break;
359
360 case APIC_DM_INIT:
c5ec1534
HQ		 361 if (level) {
362 if (vcpu->mp_state == VCPU_MP_STATE_RUNNABLE)
363 printk(KERN_DEBUG
364 "INIT on a runnable vcpu %d\n",
365 vcpu->vcpu_id);
366 vcpu->mp_state = VCPU_MP_STATE_INIT_RECEIVED;
367 kvm_vcpu_kick(vcpu);
368 } else {
369 printk(KERN_DEBUG
370 "Ignoring de-assert INIT to vcpu %d\n",
371 vcpu->vcpu_id);
372 }
373
97222cc8
ED		 374 break;
375
376 case APIC_DM_STARTUP:
c5ec1534
HQ		 377 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
378 vcpu->vcpu_id, vector);
379 if (vcpu->mp_state == VCPU_MP_STATE_INIT_RECEIVED) {
380 vcpu->sipi_vector = vector;
381 vcpu->mp_state = VCPU_MP_STATE_SIPI_RECEIVED;
382 if (waitqueue_active(&vcpu->wq))
383 wake_up_interruptible(&vcpu->wq);
384 }
97222cc8
ED		 385 break;
386
387 default:
388 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
389 delivery_mode);
390 break;
391 }
392 return result;
393}
394
395struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
396 unsigned long bitmap)
397{
932f72ad
HQ		 398 int last;
399 int next;
e4d47f40 400 struct kvm_lapic *apic = NULL;
932f72ad
HQ		 401
402 last = kvm->round_robin_prev_vcpu;
403 next = last;
404
405 do {
406 if (++next == KVM_MAX_VCPUS)
407 next = 0;
408 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
409 continue;
410 apic = kvm->vcpus[next]->apic;
411 if (apic && apic_enabled(apic))
412 break;
413 apic = NULL;
414 } while (next != last);
415 kvm->round_robin_prev_vcpu = next;
416
e4d47f40
QH		 417 if (!apic)
418 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
97222cc8 419
932f72ad 420 return apic;
97222cc8
ED		 421}
422
423static void apic_set_eoi(struct kvm_lapic *apic)
424{
425 int vector = apic_find_highest_isr(apic);
426
427 /*
428 * Not every write EOI will has corresponding ISR,
429 * one example is when Kernel check timer on setup_IO_APIC
430 */
431 if (vector == -1)
432 return;
433
434 apic_clear_vector(vector, apic->regs + APIC_ISR);
435 apic_update_ppr(apic);
436
437 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
438 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
439}
440
441static void apic_send_ipi(struct kvm_lapic *apic)
442{
443 u32 icr_low = apic_get_reg(apic, APIC_ICR);
444 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
445
446 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
447 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
448 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
449 unsigned int level = icr_low & APIC_INT_ASSERT;
450 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
451 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
452 unsigned int vector = icr_low & APIC_VECTOR_MASK;
453
454 struct kvm_lapic *target;
455 struct kvm_vcpu *vcpu;
456 unsigned long lpr_map = 0;
457 int i;
458
459 apic_debug("icr_high 0x%x, icr_low 0x%x, "
460 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
461 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
462 icr_high, icr_low, short_hand, dest,
463 trig_mode, level, dest_mode, delivery_mode, vector);
464
465 for (i = 0; i < KVM_MAX_VCPUS; i++) {
466 vcpu = apic->vcpu->kvm->vcpus[i];
467 if (!vcpu)
468 continue;
469
470 if (vcpu->apic &&
471 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
472 if (delivery_mode == APIC_DM_LOWEST)
473 set_bit(vcpu->vcpu_id, &lpr_map);
474 else
475 __apic_accept_irq(vcpu->apic, delivery_mode,
476 vector, level, trig_mode);
477 }
478 }
479
480 if (delivery_mode == APIC_DM_LOWEST) {
481 target = kvm_apic_round_robin(vcpu->kvm, vector, lpr_map);
482 if (target != NULL)
483 __apic_accept_irq(target, delivery_mode,
484 vector, level, trig_mode);
485 }
486}
487
488static u32 apic_get_tmcct(struct kvm_lapic *apic)
489{
9da8f4e8
KP		 490 u64 counter_passed;
491 ktime_t passed, now;
492 u32 tmcct;
97222cc8
ED		 493
494 ASSERT(apic != NULL);
495
9da8f4e8
KP		 496 now = apic->timer.dev.base->get_time();
497 tmcct = apic_get_reg(apic, APIC_TMICT);
498
499 /* if initial count is 0, current count should also be 0 */
500 if (tmcct == 0)
501 return 0;
502
97222cc8
ED		 503 if (unlikely(ktime_to_ns(now) <=
504 ktime_to_ns(apic->timer.last_update))) {
505 /* Wrap around */
506 passed = ktime_add(( {
507 (ktime_t) {
508 .tv64 = KTIME_MAX -
509 (apic->timer.last_update).tv64}; }
510 ), now);
511 apic_debug("time elapsed\n");
512 } else
513 passed = ktime_sub(now, apic->timer.last_update);
514
515 counter_passed = div64_64(ktime_to_ns(passed),
516 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
97222cc8 517
9da8f4e8
KP		 518 if (counter_passed > tmcct) {
519 if (unlikely(!apic_lvtt_period(apic))) {
520 /* one-shot timers stick at 0 until reset */
97222cc8 521 tmcct = 0;
9da8f4e8
KP		 522 } else {
523 /*
524 * periodic timers reset to APIC_TMICT when they
525 * hit 0. The while loop simulates this happening N
526 * times. (counter_passed %= tmcct) would also work,
527 * but might be slower or not work on 32-bit??
528 */
529 while (counter_passed > tmcct)
530 counter_passed -= tmcct;
531 tmcct -= counter_passed;
532 }
533 } else {
534 tmcct -= counter_passed;
97222cc8
ED		 535 }
536
537 return tmcct;
538}
539
540static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
541{
542 u32 val = 0;
543
544 if (offset >= LAPIC_MMIO_LENGTH)
545 return 0;
546
547 switch (offset) {
548 case APIC_ARBPRI:
549 printk(KERN_WARNING "Access APIC ARBPRI register "
550 "which is for P6\n");
551 break;
552
553 case APIC_TMCCT: /* Timer CCR */
554 val = apic_get_tmcct(apic);
555 break;
556
557 default:
6e5d865c 558 apic_update_ppr(apic);
97222cc8
ED		 559 val = apic_get_reg(apic, offset);
560 break;
561 }
562
563 return val;
564}
565
566static void apic_mmio_read(struct kvm_io_device *this,
567 gpa_t address, int len, void *data)
568{
569 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
570 unsigned int offset = address - apic->base_address;
571 unsigned char alignment = offset & 0xf;
572 u32 result;
573
574 if ((alignment + len) > 4) {
575 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
576 (unsigned long)address, len);
577 return;
578 }
579 result = __apic_read(apic, offset & ~0xf);
580
581 switch (len) {
582 case 1:
583 case 2:
584 case 4:
585 memcpy(data, (char *)&result + alignment, len);
586 break;
587 default:
588 printk(KERN_ERR "Local APIC read with len = %x, "
589 "should be 1,2, or 4 instead\n", len);
590 break;
591 }
592}
593
594static void update_divide_count(struct kvm_lapic *apic)
595{
596 u32 tmp1, tmp2, tdcr;
597
598 tdcr = apic_get_reg(apic, APIC_TDCR);
599 tmp1 = tdcr & 0xf;
600 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
601 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
602
603 apic_debug("timer divide count is 0x%x\n",
604 apic->timer.divide_count);
605}
606
607static void start_apic_timer(struct kvm_lapic *apic)
608{
609 ktime_t now = apic->timer.dev.base->get_time();
610
611 apic->timer.last_update = now;
612
613 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
614 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
615 atomic_set(&apic->timer.pending, 0);
616 hrtimer_start(&apic->timer.dev,
617 ktime_add_ns(now, apic->timer.period),
618 HRTIMER_MODE_ABS);
619
620 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
621 PRIx64 ", "
622 "timer initial count 0x%x, period %lldns, "
623 "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
624 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
625 apic_get_reg(apic, APIC_TMICT),
626 apic->timer.period,
627 ktime_to_ns(ktime_add_ns(now,
628 apic->timer.period)));
629}
630
631static void apic_mmio_write(struct kvm_io_device *this,
632 gpa_t address, int len, const void *data)
633{
634 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
635 unsigned int offset = address - apic->base_address;
636 unsigned char alignment = offset & 0xf;
637 u32 val;
638
639 /*
640 * APIC register must be aligned on 128-bits boundary.
641 * 32/64/128 bits registers must be accessed thru 32 bits.
642 * Refer SDM 8.4.1
643 */
644 if (len != 4 || alignment) {
645 if (printk_ratelimit())
646 printk(KERN_ERR "apic write: bad size=%d %lx\n",
647 len, (long)address);
648 return;
649 }
650
651 val = *(u32 *) data;
652
653 /* too common printing */
654 if (offset != APIC_EOI)
655 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
656 "0x%x\n", __FUNCTION__, offset, len, val);
657
658 offset &= 0xff0;
659
660 switch (offset) {
661 case APIC_ID: /* Local APIC ID */
662 apic_set_reg(apic, APIC_ID, val);
663 break;
664
665 case APIC_TASKPRI:
666 apic_set_tpr(apic, val & 0xff);
667 break;
668
669 case APIC_EOI:
670 apic_set_eoi(apic);
671 break;
672
673 case APIC_LDR:
674 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
675 break;
676
677 case APIC_DFR:
678 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
679 break;
680
681 case APIC_SPIV:
682 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
683 if (!(val & APIC_SPIV_APIC_ENABLED)) {
684 int i;
685 u32 lvt_val;
686
687 for (i = 0; i < APIC_LVT_NUM; i++) {
688 lvt_val = apic_get_reg(apic,
689 APIC_LVTT + 0x10 * i);
690 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
691 lvt_val | APIC_LVT_MASKED);
692 }
693 atomic_set(&apic->timer.pending, 0);
694
695 }
696 break;
697
698 case APIC_ICR:
699 /* No delay here, so we always clear the pending bit */
700 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
701 apic_send_ipi(apic);
702 break;
703
704 case APIC_ICR2:
705 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
706 break;
707
708 case APIC_LVTT:
709 case APIC_LVTTHMR:
710 case APIC_LVTPC:
711 case APIC_LVT0:
712 case APIC_LVT1:
713 case APIC_LVTERR:
714 /* TODO: Check vector */
715 if (!apic_sw_enabled(apic))
716 val |= APIC_LVT_MASKED;
717
718 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
719 apic_set_reg(apic, offset, val);
720
721 break;
722
723 case APIC_TMICT:
724 hrtimer_cancel(&apic->timer.dev);
725 apic_set_reg(apic, APIC_TMICT, val);
726 start_apic_timer(apic);
727 return;
728
729 case APIC_TDCR:
730 if (val & 4)
731 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
732 apic_set_reg(apic, APIC_TDCR, val);
733 update_divide_count(apic);
734 break;
735
736 default:
737 apic_debug("Local APIC Write to read-only register %x\n",
738 offset);
739 break;
740 }
741
742}
743
744static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
745{
746 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
747 int ret = 0;
748
749
750 if (apic_hw_enabled(apic) &&
751 (addr >= apic->base_address) &&
752 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
753 ret = 1;
754
755 return ret;
756}
757
d589444e 758void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 759{
d589444e 760 if (!vcpu->apic)
97222cc8
ED		 761 return;
762
d589444e 763 hrtimer_cancel(&vcpu->apic->timer.dev);
97222cc8 764
d589444e
RR		 765 if (vcpu->apic->regs_page)
766 __free_page(vcpu->apic->regs_page);
97222cc8 767
d589444e 768 kfree(vcpu->apic);
97222cc8
ED		 769}
770
771/*
772 *----------------------------------------------------------------------
773 * LAPIC interface
774 *----------------------------------------------------------------------
775 */
776
777void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
778{
7e620d16 779 struct kvm_lapic *apic = vcpu->apic;
97222cc8
ED		 780
781 if (!apic)
782 return;
783 apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
784}
785
786u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
787{
7e620d16 788 struct kvm_lapic *apic = vcpu->apic;
97222cc8
ED		 789 u64 tpr;
790
791 if (!apic)
792 return 0;
793 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
794
795 return (tpr & 0xf0) >> 4;
796}
6e5d865c 797EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
97222cc8
ED		 798
799void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
800{
7e620d16 801 struct kvm_lapic *apic = vcpu->apic;
97222cc8
ED		 802
803 if (!apic) {
804 value |= MSR_IA32_APICBASE_BSP;
805 vcpu->apic_base = value;
806 return;
807 }
808 if (apic->vcpu->vcpu_id)
809 value &= ~MSR_IA32_APICBASE_BSP;
810
811 vcpu->apic_base = value;
812 apic->base_address = apic->vcpu->apic_base &
813 MSR_IA32_APICBASE_BASE;
814
815 /* with FSB delivery interrupt, we can restart APIC functionality */
816 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
817 "0x%lx.\n", apic->apic_base, apic->base_address);
818
819}
820
821u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
822{
823 return vcpu->apic_base;
824}
825EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
826
c5ec1534 827void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 828{
829 struct kvm_lapic *apic;
830 int i;
831
832 apic_debug("%s\n", __FUNCTION__);
833
834 ASSERT(vcpu);
835 apic = vcpu->apic;
836 ASSERT(apic != NULL);
837
838 /* Stop the timer in case it's a reset to an active apic */
839 hrtimer_cancel(&apic->timer.dev);
840
841 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
842 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
843
844 for (i = 0; i < APIC_LVT_NUM; i++)
845 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 846 apic_set_reg(apic, APIC_LVT0,
847 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 848
849 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
850 apic_set_reg(apic, APIC_SPIV, 0xff);
851 apic_set_reg(apic, APIC_TASKPRI, 0);
852 apic_set_reg(apic, APIC_LDR, 0);
853 apic_set_reg(apic, APIC_ESR, 0);
854 apic_set_reg(apic, APIC_ICR, 0);
855 apic_set_reg(apic, APIC_ICR2, 0);
856 apic_set_reg(apic, APIC_TDCR, 0);
857 apic_set_reg(apic, APIC_TMICT, 0);
858 for (i = 0; i < 8; i++) {
859 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
860 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
861 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
862 }
b33ac88b 863 update_divide_count(apic);
97222cc8
ED		 864 atomic_set(&apic->timer.pending, 0);
865 if (vcpu->vcpu_id == 0)
866 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
867 apic_update_ppr(apic);
868
869 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
870 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
871 vcpu, kvm_apic_id(apic),
872 vcpu->apic_base, apic->base_address);
873}
c5ec1534 874EXPORT_SYMBOL_GPL(kvm_lapic_reset);
97222cc8
ED		 875
876int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
877{
7e620d16 878 struct kvm_lapic *apic = vcpu->apic;
97222cc8
ED		 879 int ret = 0;
880
881 if (!apic)
882 return 0;
883 ret = apic_enabled(apic);
884
885 return ret;
886}
6e5d865c 887EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
97222cc8
ED		 888
889/*
890 *----------------------------------------------------------------------
891 * timer interface
892 *----------------------------------------------------------------------
893 */
1b9778da
ED		 894
895/* TODO: make sure __apic_timer_fn runs in current pCPU */
97222cc8
ED		 896static int __apic_timer_fn(struct kvm_lapic *apic)
897{
97222cc8 898 int result = 0;
1b9778da 899 wait_queue_head_t *q = &apic->vcpu->wq;
97222cc8 900
97222cc8 901 atomic_inc(&apic->timer.pending);
d77c26fc 902 if (waitqueue_active(q)) {
c5ec1534 903 apic->vcpu->mp_state = VCPU_MP_STATE_RUNNABLE;
1b9778da 904 wake_up_interruptible(q);
c5ec1534 905 }
97222cc8 906 if (apic_lvtt_period(apic)) {
97222cc8
ED		 907 result = 1;
908 apic->timer.dev.expires = ktime_add_ns(
909 apic->timer.dev.expires,
910 apic->timer.period);
911 }
97222cc8
ED		 912 return result;
913}
914
1b9778da
ED		 915static int __inject_apic_timer_irq(struct kvm_lapic *apic)
916{
917 int vector;
918
919 vector = apic_lvt_vector(apic, APIC_LVTT);
920 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
921}
922
97222cc8
ED		 923static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
924{
925 struct kvm_lapic *apic;
926 int restart_timer = 0;
927
928 apic = container_of(data, struct kvm_lapic, timer.dev);
929
930 restart_timer = __apic_timer_fn(apic);
931
932 if (restart_timer)
933 return HRTIMER_RESTART;
934 else
935 return HRTIMER_NORESTART;
936}
937
938int kvm_create_lapic(struct kvm_vcpu *vcpu)
939{
940 struct kvm_lapic *apic;
941
942 ASSERT(vcpu != NULL);
943 apic_debug("apic_init %d\n", vcpu->vcpu_id);
944
945 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
946 if (!apic)
947 goto nomem;
948
949 vcpu->apic = apic;
950
951 apic->regs_page = alloc_page(GFP_KERNEL);
952 if (apic->regs_page == NULL) {
953 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
954 vcpu->vcpu_id);
d589444e 955 goto nomem_free_apic;
97222cc8
ED		 956 }
957 apic->regs = page_address(apic->regs_page);
958 memset(apic->regs, 0, PAGE_SIZE);
959 apic->vcpu = vcpu;
960
961 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
962 apic->timer.dev.function = apic_timer_fn;
963 apic->base_address = APIC_DEFAULT_PHYS_BASE;
964 vcpu->apic_base = APIC_DEFAULT_PHYS_BASE;
965
c5ec1534 966 kvm_lapic_reset(vcpu);
97222cc8
ED		 967 apic->dev.read = apic_mmio_read;
968 apic->dev.write = apic_mmio_write;
969 apic->dev.in_range = apic_mmio_range;
970 apic->dev.private = apic;
971
972 return 0;
d589444e
RR		 973nomem_free_apic:
974 kfree(apic);
97222cc8 975nomem:
97222cc8
ED		 976 return -ENOMEM;
977}
978EXPORT_SYMBOL_GPL(kvm_create_lapic);
979
980int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
981{
982 struct kvm_lapic *apic = vcpu->apic;
983 int highest_irr;
984
985 if (!apic || !apic_enabled(apic))
986 return -1;
987
6e5d865c 988 apic_update_ppr(apic);
97222cc8
ED		 989 highest_irr = apic_find_highest_irr(apic);
990 if ((highest_irr == -1) ||
991 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
992 return -1;
993 return highest_irr;
994}
995
40487c68
QH		 996int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
997{
998 u32 lvt0 = apic_get_reg(vcpu->apic, APIC_LVT0);
999 int r = 0;
1000
1001 if (vcpu->vcpu_id == 0) {
1002 if (!apic_hw_enabled(vcpu->apic))
1003 r = 1;
1004 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1005 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1006 r = 1;
1007 }
1008 return r;
1009}
1010
1b9778da
ED		 1011void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1012{
1013 struct kvm_lapic *apic = vcpu->apic;
1014
1015 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1016 atomic_read(&apic->timer.pending) > 0) {
1017 if (__inject_apic_timer_irq(apic))
1018 atomic_dec(&apic->timer.pending);
1019 }
1020}
1021
1022void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1023{
1024 struct kvm_lapic *apic = vcpu->apic;
1025
1026 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1027 apic->timer.last_update = ktime_add_ns(
1028 apic->timer.last_update,
1029 apic->timer.period);
1030}
1031
97222cc8
ED		 1032int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1033{
1034 int vector = kvm_apic_has_interrupt(vcpu);
1035 struct kvm_lapic *apic = vcpu->apic;
1036
1037 if (vector == -1)
1038 return -1;
1039
1040 apic_set_vector(vector, apic->regs + APIC_ISR);
1041 apic_update_ppr(apic);
1042 apic_clear_irr(vector, apic);
1043 return vector;
1044}
96ad2cc6
ED		 1045
1046void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1047{
1048 struct kvm_lapic *apic = vcpu->apic;
1049
1050 apic->base_address = vcpu->apic_base &
1051 MSR_IA32_APICBASE_BASE;
1052 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1053 apic_update_ppr(apic);
1054 hrtimer_cancel(&apic->timer.dev);
1055 update_divide_count(apic);
1056 start_apic_timer(apic);
1057}
a3d7f85f
ED		 1058
1059void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1060{
1061 struct kvm_lapic *apic = vcpu->apic;
1062 struct hrtimer *timer;
1063
1064 if (!apic)
1065 return;
1066
1067 timer = &apic->timer.dev;
1068 if (hrtimer_cancel(timer))
1069 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1070}
1071EXPORT_SYMBOL_GPL(kvm_migrate_apic_timer);
Linux kernel - Deliverables
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